A power semiconductor chip packaging structure

Abstract

The present invention provides a power semiconductor chip packaging structure, comprising: a first substrate electrode; a power semiconductor chip located on a portion of the first substrate electrode and electrically connected to the first substrate electrode; a coil shielding structure surrounding the power semiconductor chip, the coil shielding structure comprising a conductive coil and an insulator covering the conductive coil. The power semiconductor chip packaging structure has high pressure resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a power semiconductor chip packaging structure. Background Art

[0002] At present, most of the high-power power electronic devices in the power system use silicon power electronic devices, such as IGBT (Insulated Gate Bipolar Transistor) chip devices, thyristor chip devices, GTO (Gate Turn-Off thyristor) chip devices, etc., to achieve the control and conversion of electric energy. Since silicon power electronic devices are subject to the limitations of the material itself in terms of physical properties such as voltage resistance and operating temperature, in order to fundamentally improve the reliability and stability of high-power power electronic equipment, reduce the overall loss of the system, and improve the control and conversion efficiency of energy, it is necessary to research and develop new power electronic devices with higher voltage resistance, lower power consumption and high temperature resistance. Silicon Carbide (SiC) devices are one of the most mature and widely used third-generation semiconductor power electronic devices so far. They can break the physical limits of traditional silicon-based devices and have the advantages of high voltage level, large current capacity, low loss, and fast heat dissipation. They can be widely used in new power electronic equipment such as solid-state transformers and solid-state circuit breakers, as well as traditional FACTS and DC transmission equipment. They will have an important impact on the economic and safe operation of power systems and realize the innovation of power grid technology.

[0003] However, most of the current packaging structures for SiC chips still use the welding packaging type of silicon-based chips. The pressure resistance of the power semiconductor chip packaging structure in the existing technology is low, and its packaging parameters are obviously not suitable for the high shutdown speed and low loss characteristics of SiC chips. Therefore, it is necessary to develop a new packaging structure for high-voltage power chips. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the low pressure resistance of the existing power semiconductor chip packaging structure, thereby providing a power semiconductor chip packaging structure.

[0005] The present invention provides a power semiconductor chip packaging structure, comprising: a first substrate electrode; a power semiconductor chip located on a portion of the first substrate electrode and electrically connected to the first substrate electrode; a coil shielding structure surrounding the power semiconductor chip, the coil shielding structure comprising a conductive coil and an insulator covering the conductive coil.

[0006] Optionally, the insulator comprises ceramic.

[0007] Optionally, the distance between the insulator and the power semiconductor chip is 1 mm-10 mm.

[0008] Optionally, the coil shielding structure is a circular ring structure.

[0009] Optionally, the power semiconductor chip has an emitter on a side surface facing away from the first substrate electrode; the power semiconductor chip packaging structure also includes: a conductive connector located on the emitter, the conductive connector including a first sub-conductive connection part, a second sub-conductive connection part, and an insulating part located between the first sub-conductive connection part and the second sub-conductive connection part, the first sub-conductive connection part, the insulating part and the second sub-conductive connection part are arranged in a direction parallel to the surface of the first substrate electrode, the height of the first sub-conductive connection part is greater than the height of the second sub-conductive connection part, and the first sub-conductive connection part and the second sub-conductive connection part are both connected to the emitter; a second substrate electrode arranged opposite to the first substrate electrode; an auxiliary emitter circuit board located between the second substrate electrode and the first substrate electrode; the first sub-conductive connection part passes through the auxiliary emitter circuit board and is electrically connected to the second substrate electrode, the first sub-conductive connection part is electrically insulated from the auxiliary emitter circuit board; the second sub-conductive connection part is electrically connected to the auxiliary emitter circuit board.

[0010] Optionally, the first sub-conductive connection portion includes a first sub-bottom layer connection layer, and one or more first sub-top layer connection layers located above the first sub-bottom layer connection layer, the first sub-bottom layer connection layer is a full-surface structure, and the first sub-top layer connection layer has a plurality of first micropores; the second sub-conductive connection portion includes a second sub-bottom layer connection layer, and one or more second sub-top layer connection layers located above the second sub-bottom layer connection layer, the second sub-bottom layer connection layer is a full-surface structure, and the second sub-top layer connection layer has a plurality of second micropores.

[0011] Optionally, there are several auxiliary emitter circuit boards, including a first auxiliary emitter circuit board and a second auxiliary emitter circuit board located on the side of the first auxiliary emitter circuit board away from the first substrate electrode; the emitters of some power semiconductor chips are electrically connected to the first auxiliary emitter circuit board through the second sub-conductive connection part, and the emitters of some power semiconductor chips are electrically connected to the second auxiliary emitter circuit board through the second sub-conductive connection part; the projections of the first interconnection line in the first auxiliary emitter circuit board and the second interconnection line in the second auxiliary emitter circuit board on the surface of the first substrate electrode at least partially overlap, and for the first interconnection line and the second interconnection line whose projections on the surface of the first substrate electrode overlap, the current direction in the first interconnection line is opposite to the current direction in the second interconnection line.

[0012] Optionally, the power semiconductor chip has a gate on one side facing away from the first substrate electrode; the power semiconductor chip packaging structure also includes: a lining plate located on the first substrate electrode and on the side of the power semiconductor chip, the lining plate having a conductive column on a surface facing away from the first substrate electrode; a bonding wire connecting the gate and the conductive column; a gate circuit board arranged opposite to the first substrate electrode, the power semiconductor chip, the conductive column and the lining plate are all located between the gate circuit board and the first substrate electrode, and the conductive column is electrically connected to the gate circuit board.

[0013] Optionally, it also includes: a support column, located between the liner and the gate circuit board and located on the side of the conductive column.

[0014] Optionally, there are several gate circuit boards, including a first gate circuit board and a second gate circuit board located on the side of the first gate circuit board away from the first substrate electrode; the gates of some power semiconductor chips are electrically connected to the first gate circuit board through the bonding wires and the conductive pillars, and the gates of some power semiconductor chips are electrically connected to the second gate circuit board through the bonding wires and the conductive pillars; the third interconnection line in the first gate circuit board and the fourth interconnection line in the second gate circuit board have at least partially overlapped projections on the surface of the first substrate electrode, and for the third interconnection line and the fourth interconnection line whose projections on the surface of the first substrate electrode overlap, the current direction in the third interconnection line is opposite to the current direction in the fourth interconnection line.

[0015] Optionally, it further includes: a tube shell, wherein the tube shell surrounds the first substrate electrode and the second substrate electrode.

[0016] The technical solution of the present invention has the following advantages:

[0017] The power semiconductor chip packaging structure provided by the present invention has a coil shielding structure surrounding the power semiconductor chip. The coil shielding structure includes a conductive coil and an insulator covering the conductive coil. The coil shielding structure can balance the electric field concentration around the power semiconductor chip and reduce the risk of breakdown of the power semiconductor chip, so that the power semiconductor chip packaging structure has higher pressure resistance.

[0018] Furthermore, the conductive connector located on the emitter of the power semiconductor chip includes a first sub-conductive connection part, a second sub-conductive connection part, and an insulating part located between the first sub-conductive connection part and the second sub-conductive connection part; the first sub-conductive connection part passes through the auxiliary emitter circuit board and is electrically connected to the second substrate electrode, and the first sub-conductive connection part is electrically insulated from the auxiliary emitter circuit board; the second sub-conductive connection part is electrically connected to the auxiliary emitter circuit board, so that the emitter current can be drawn from the second substrate electrode and the auxiliary emitter circuit board respectively. Secondly, the bottom surface of the power semiconductor chip can dissipate heat through the first substrate electrode, and the emitter of the power semiconductor chip can dissipate heat through the first sub-conductive connection part and the second sub-conductive connection part, so the conductive connector has double-sided heat dissipation capability.

[0019] Furthermore, the first sub-conductive connection part includes a first sub-bottom layer connection layer, and one or more first sub-top layer connection layers located above the first sub-bottom layer connection layer, the first sub-bottom layer connection layer is a whole surface structure, and the first sub-top layer connection layer has a plurality of first micropores; the second sub-conductive connection part includes a second sub-bottom layer connection layer, and one or more second sub-top layer connection layers located above the second sub-bottom layer connection layer, the second sub-bottom layer connection layer is a whole surface structure, and the second sub-top layer connection layer has a plurality of second micropores. Since the first sub-top layer connection layer has a plurality of first micropores, and the second sub-top layer connection layer has a plurality of second micropores, the gaps in the first micropores and the second micropores cause the conductive connection part to produce a slight deformation when the power semiconductor chip packaging structure is subjected to pressure, and the pressure on the power semiconductor chip can be uniformed.

[0020] Furthermore, the projections of the first interconnection line in the first auxiliary emitter circuit board and the second interconnection line in the second auxiliary emitter circuit board on the surface of the first substrate electrode at least partially overlap, which can maximize the guarantee that each power semiconductor chip receives the driving signal at the same time; for the first interconnection line and the second interconnection line whose projections overlap on the surface of the first substrate electrode, the current direction in the first interconnection line is opposite to the current direction in the second interconnection line, which can eliminate the parasitic inductance of part of the emitter loop caused by the power semiconductor chip packaging structure, and reduce the emitter voltage overshoot and oscillation during testing.

[0021] Furthermore, the projections of the third interconnection line in the first gate circuit board and the fourth interconnection line in the second gate circuit board on the surface of the first substrate electrode at least partially overlap, which can maximize the guarantee that each power semiconductor chip receives the driving signal at the same time; for the third interconnection line and the fourth interconnection line whose projections on the surface of the first substrate electrode overlap, the current direction in the third interconnection line is opposite to the current direction in the fourth interconnection line, which can eliminate the parasitic inductance of part of the gate loop caused by the power semiconductor chip packaging structure, and reduce the emitter voltage overshoot and oscillation during testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the connection of the power semiconductor chip provided by the present invention;

[0024] Figure 2 A schematic diagram of the structure of a partial coil shielding structure provided by the present invention;

[0025] Figure 3 A schematic diagram of the structure of the conductive connecting member provided by the present invention;

[0026] Figure 4 A schematic structural diagram of a first auxiliary emitter circuit board provided by the present invention;

[0027] Figure 5 A schematic diagram of the structure of a second auxiliary emitter circuit board provided by the present invention;

[0028] Figure 6 A schematic structural diagram of a first insulating pad provided by the present invention;

[0029] Figure 7 A schematic structural diagram of a first grid circuit board provided by the present invention;

[0030] Figure 8 A schematic diagram of the structure of a second grid circuit board provided by the present invention;

[0031] Fig. 9 A schematic structural diagram of a second insulating pad provided by the present invention;

[0032] Fig.10 A schematic diagram of the structure of the tube shell provided by the present invention;

[0033] Fig.11This is a cross-sectional view of the power semiconductor chip packaging structure provided by the present invention.

[0034] Description of reference numerals:

[0035] 1-first substrate electrode; 2-power semiconductor chip; 201-emitter; 202-gate; 3-coil shielding structure; 4-conductive coil; 5-insulator; 6-conductive connecting member; 7-first sub-conductive connecting portion; 8-second sub-conductive connecting portion; 9-insulating portion; 71-first sub-bottom connecting layer; 72-first sub-top connecting layer; 73-first micro-hole; 81-second sub-bottom connecting layer; 82-second sub-top connecting layer; 83-second micro-hole; 10-second substrate electrode; 11 -auxiliary emitter circuit board; 111-first auxiliary emitter circuit board; 112-second auxiliary emitter circuit board; 113-first interconnection line; 114-second interconnection line; 115-first insulating pad; 12-liner; 13-conductive column; 14-bonding lead; 15-gate circuit board; 16-support column; 151-first gate circuit board; 152-second gate circuit board; 153-third interconnection line; 154-fourth interconnection line; 155-second insulating pad; 17-tube shell. DETAILED DESCRIPTION

[0036] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] The present invention provides a power semiconductor chip packaging structure, combined with reference Figure 1 and Figure 2 ,include:

[0041] A first substrate electrode 1;

[0042] a power semiconductor chip 2 located on a portion of the first substrate electrode 1 and electrically connected to the first substrate electrode 1;

[0043] The coil shielding structure 3 surrounds the power semiconductor chip 2 , and the coil shielding structure 3 includes a conductive coil 4 and an insulator 5 covering the conductive coil 4 .

[0044] In one embodiment, a collector is provided on one side surface of the power semiconductor chip 2, and the collector of the power semiconductor chip 2 is connected to the first substrate electrode 1 by a sintering process, such as a nanosilver sintering process; in other embodiments, the power semiconductor chip 2 and the first substrate electrode 1 may also be connected by other processes.

[0045] The collector electrode of the power semiconductor chip 2 is connected to the first substrate electrode 1 by a sintering process, which can reduce the contact resistance and thermal resistance of the power semiconductor chip 2 and further reduce the loss of the power semiconductor chip packaging structure.

[0046] In one embodiment, the material of the insulator 5 includes ceramics; in other embodiments, the material of the insulator 5 may also include other insulating materials.

[0047] In one embodiment, the insulator 5 is fixed around the power semiconductor chip 2 using a high-temperature resistant and high-insulation glue. For example, the material of the high-temperature resistant and high-insulation glue includes silicone rubber, epoxy glue and other materials that have both high insulation strength and good bonding strength. In other embodiments, the insulator 5 can also be fixed around the power semiconductor chip 2 using other methods.

[0048] The coil shielding structure 3 can make the electric field strength around the power semiconductor chip 2 uniform and improve the reliability of the power semiconductor chip 2. In one embodiment, the coil shielding structure 3 is in the shape of a circular ring structure, and the coil shielding structure 3 in the circular ring structure can better make the electric field strength around the power semiconductor chip 2 uniform.

[0049] In other embodiments, the coil shielding structure 3 may also be in other shapes.

[0050] In one embodiment, the distance between the insulator 5 and the power semiconductor chip 2 is 1mm-10mm, for example: 2mm; if the distance between the insulator 5 and the power semiconductor chip 2 is less than 1mm, it is not conducive to the filling of the insulating potting material, which makes the power semiconductor chip packaging structure prone to defects, resulting in partial discharge of the power semiconductor chip packaging structure during the test process, making the insulation performance of the power semiconductor chip packaging structure not obvious; if the distance between the insulator 5 and the power semiconductor chip 2 is greater than 10mm; the size of the power semiconductor chip packaging structure is too large, resulting in space waste, so that the power density of the power semiconductor chip packaging structure cannot achieve a better effect.

[0051] In one embodiment, the conductive coil 4 includes a metal wire, such as a copper wire; in other embodiments, the conductive coil 4 may also include other metals.

[0052] The surface of the power semiconductor chip 2 facing away from the first substrate electrode 1 has an emitter 201 and a gate 202 , and the gate 202 is separate from the emitter 201 .

[0053] In one embodiment, the power semiconductor chip packaging structure further includes: a conductive connecting member 6 located on the emitter 201, Figure 3 The conductive connection member 6 includes a first sub-conductive connection portion 7, a second sub-conductive connection portion 8, and an insulating portion 9 located between the first sub-conductive connection portion 7 and the second sub-conductive connection portion 8. The first sub-conductive connection portion 7, the insulating portion 9, and the second sub-conductive connection portion 8 are arranged in a direction parallel to the surface of the first substrate electrode 1. The height of the first sub-conductive connection portion 7 is greater than the height of the second sub-conductive connection portion 8. The first sub-conductive connection portion 7 and the second sub-conductive connection portion 8 are both connected to the emitter 201.

[0054] In one embodiment, the height of the conductive coil 4 is smaller than the height of the second sub-conductive connecting portion 8 .

[0055] In one embodiment, the emitter of the power semiconductor chip 2 is connected to the conductive connector 6 by a sintering process, such as a nanosilver sintering process; in other embodiments, the emitter of the power semiconductor chip 2 is connected to the conductive connector 6 by other processes.

[0056] The emitter of the power semiconductor chip 2 is connected to the conductive connector 6 by adopting a sintering process, which can reduce the contact resistance and thermal resistance of the power semiconductor chip 2 and further reduce the loss of the power semiconductor chip packaging structure.

[0057] The first sub-conductive connection part 7 penetrates the auxiliary emitter circuit board 11 and is electrically connected to the second substrate electrode 10. The first sub-conductive connection part 7 is electrically insulated from the auxiliary emitter circuit board 11; the second sub-conductive connection part 8 is electrically connected to the auxiliary emitter circuit board 11, so that the emitter current can be drawn from the second substrate electrode 10 and the auxiliary emitter circuit board 11 respectively. Secondly, the bottom surface of the power semiconductor chip 2 can dissipate heat through the first substrate electrode 1, and the emitter 201 of the power semiconductor chip 2 can dissipate heat through the first sub-conductive connection part 7 and the second sub-conductive connection part 8, so the conductive connection part 6 has a double-sided heat dissipation capability. In one embodiment, the first sub-conductive connection part 7 includes a first sub-bottom layer connection layer 71, and one or more first sub-top layer connection layers 72 located above the first sub-bottom layer connection layer 71. The first sub-bottom layer connection layer 71 is a whole surface structure, and the first sub-top layer connection layer 72 has a plurality of first microholes 73.

[0058] In this embodiment, the first micropores 73 are evenly arranged; in other embodiments, the first micropores 73 may also be unevenly arranged.

[0059] In this embodiment, the first micropores 73 penetrate the first sub-top layer connecting layer 72, and the first micropores of the first sub-top layer connecting layer 72 of each layer are connected; in other embodiments, the first micropores 73 may not penetrate the first sub-top layer connecting layer 72, and the first micropores 73 of the first sub-top layer connecting layer 72 of each layer may not be connected.

[0060] In one embodiment, the number of layers of the first sub-top layer connection layer 72 is determined according to insulation requirements and crimping requirements.

[0061] In one embodiment, the thickness of the first sub-bottom layer 71 is 0.8 mm-1.2 mm, for example, 1 mm.

[0062] In one embodiment, the thickness of each first sub-top layer connecting layer 72 is 0.8 mm-1.2 mm, for example, 1 mm.

[0063] In one embodiment, the number of layers of the first sub-top layer connection layer 72 is 16-18.

[0064] In one embodiment, the second sub-conductive connection part 8 includes a second sub-bottom layer connection layer 81 and one or more second sub-top layer connection layers 82 located above the second sub-bottom layer connection layer 81. The second sub-bottom layer connection layer 81 is a full-surface structure, and the second sub-top layer connection layer 82 has a plurality of second microholes 83.

[0065] In this embodiment, the second micropores 83 are evenly arranged; in other embodiments, the second micropores 83 may also be unevenly arranged.

[0066] In this embodiment, the second micropores 83 may penetrate the second sub-top layer connecting layer 82, and the second micropores 83 of the second sub-top layer connecting layer 82 of each layer may be connected; in other embodiments, the second micropores 83 may not penetrate the second sub-top layer connecting layer 82, and the second micropores 83 of the second sub-top layer connecting layer 82 of each layer may not be connected.

[0067] The insulating portion 9 is used to isolate the first sub-conductive connecting portion 7 from the second sub-conductive connecting portion 8 .

[0068] In one embodiment, the material of the insulating portion 9 includes elastic insulating materials such as rubber. In other embodiments, the material of the insulating portion 9 may also include other elastic insulating materials.

[0069] In one embodiment, the number of layers of the second sub-top layer 82 is determined according to insulation requirements and crimping requirements.

[0070] In one embodiment, the thickness of the second sub-bottom layer 81 is 0.8 mm-1.2 mm, for example, 1 mm.

[0071] In one embodiment, the thickness of each second sub-top layer connecting layer 82 is 0.8 mm-1.2 mm, for example, 1 mm.

[0072] In one embodiment, the number of layers of the second sub-top layer connection layer 82 is 14-16.

[0073] In one embodiment, the power semiconductor chip packaging structure further includes: a second substrate electrode 10 disposed opposite to the first substrate electrode 1 .

[0074] In one embodiment, the power semiconductor chip packaging structure further includes: an auxiliary emitter circuit board 11 located between the second substrate electrode 10 and the first substrate electrode 1 .

[0075] In one embodiment, the first sub-conductive connection portion 7 passes through the auxiliary emitter circuit board 11 and is electrically connected to the second substrate electrode 10 , and the first sub-conductive connection portion 7 is electrically insulated from the auxiliary emitter circuit board 11 ; the second sub-conductive connection portion 8 is electrically connected to the auxiliary emitter circuit board 11 .

[0076] In one embodiment, the number of the auxiliary emitter circuit boards 11 is several, referring to Figures 4 to 5 The plurality of auxiliary emitter circuit boards 11 include a first auxiliary emitter circuit board 111 and a second auxiliary emitter circuit board 112 located on a side of the first auxiliary emitter circuit board 111 away from the first substrate electrode 1 .

[0077] In one embodiment, the emitters of some power semiconductor chips 2 are electrically connected to the first auxiliary emitter circuit board 111 through the second sub-conductive connecting portion 8, and the emitters 201 of some power semiconductor chips are electrically connected to the second auxiliary emitter circuit board 112 through the second sub-conductive connecting portion 8; the projections of the first interconnection line 113 in the first auxiliary emitter circuit board 111 and the second interconnection line 114 in the second auxiliary emitter circuit board 112 at least partially overlap on the surface of the first substrate electrode 1, and for the first interconnection line 113 and the second interconnection line 114 whose projections overlap on the surface of the first substrate electrode 1, the current direction in the first interconnection line 113 is opposite to the current direction in the second interconnection line 114, and the current direction in the first interconnection line 113 is opposite to the current direction in the second interconnection line 114, which can eliminate the parasitic inductance of part of the emitter loop caused by the power semiconductor chip packaging structure, and reduce the emitter voltage overshoot and oscillation during testing.

[0078] The first interconnection line 113 and the second interconnection line 114 face away from the first substrate electrode 1 .

[0079] The projections of the first interconnection line 113 in the first auxiliary emitter circuit board 111 and the second interconnection line 114 in the second auxiliary emitter circuit board 112 on the surface of the first substrate electrode 1 at least partially overlap, which can eliminate the parasitic inductance of the overlapping part, thereby reducing the parasitic inductance of the power semiconductor chip packaging structure.

[0080] In one embodiment, reference Figure 6 The auxiliary emitter circuit board 11 further includes a first insulating pad 115 ; the first insulating pad 115 is located between the first auxiliary emitter circuit board 111 and the second auxiliary emitter circuit board 112 .

[0081] In one embodiment, the emitter 201 of some power semiconductor chips 2 is electrically connected to the first auxiliary emitter circuit board 111 through the second sub-conductive connection part 8, and the emitter 201 of some power semiconductor chips 2 is electrically connected to the second auxiliary emitter circuit board 112 through the second sub-conductive connection part 8, and the first insulating pad 115 is used to isolate the first auxiliary emitter circuit board 111 from the second auxiliary emitter circuit board 112.

[0082] In one embodiment, the power semiconductor chip 2 has a gate 202 on a side facing away from the first substrate electrode 1 .

[0083] In one embodiment, the power semiconductor chip packaging structure further includes: a liner 12 located on the first substrate electrode 1 and on the side of the power semiconductor chip 2, and a surface of the liner 12 on one side away from the first substrate electrode 1 has a conductive column 13. The material of the liner 12 includes: aluminum nitride or aluminum silicon carbide or ceramic copper clad plate or ceramic aluminum clad plate.

[0084] In one embodiment, the power semiconductor chip packaging structure further includes: a bonding wire 14 connecting the gate 202 and the conductive pillar 13 .

[0085] In one embodiment, the power semiconductor chip packaging structure also includes: a gate circuit board 15 arranged opposite to the first substrate electrode 1, the power semiconductor chip 2, the conductive column 13, and the backing plate 12 are all located between the gate circuit board 15 and the first substrate electrode 1, and the conductive column 13 is electrically connected to the gate circuit board 15.

[0086] The gate circuit board 15 is located between the auxiliary emitter circuit board 11 and the first substrate electrode 1 .

[0087] In one embodiment, the power semiconductor chip packaging structure further includes: a support column 16 , wherein the support column 16 is located between the backing plate 12 and the gate circuit board 15 and is located on a side of the conductive column 13 .

[0088] In one embodiment, the number of the gate circuit boards 15 is several, referring to Figures 7 and 8 , a plurality of gate circuit boards include a first gate circuit board 151 and a second gate circuit board 152 located on a side of the first gate circuit board 151 away from the first substrate electrode 1; the gates of some power semiconductor chips 2 are electrically connected to the first gate circuit board 151 through the bonding wires 14 and the conductive pillars 13, and the gates of some power semiconductor chips 2 are electrically connected to the second gate circuit board 152 through the bonding wires 14 and the conductive pillars 13; the projections of the third interconnection lines 153 in the first gate circuit board 151 and the fourth interconnection lines 154 in the second gate circuit board 152 on the surface of the first substrate electrode 1 at least partially overlap, and for the third interconnection lines 153 and the fourth interconnection lines 154 whose projections on the surface of the first substrate electrode 1 overlap, the current direction in the third interconnection lines 153 is opposite to the current direction in the fourth interconnection lines 154, and the current direction in the third interconnection lines 153 is opposite to the current direction in the fourth interconnection lines 154, which can eliminate the parasitic inductance of some gate loops caused by the power semiconductor chip packaging structure, and reduce the gate voltage overshoot and oscillation during testing.

[0089] The third interconnection line 153 and the fourth interconnection line 154 are oriented toward the first substrate electrode 1. In one embodiment, the gate circuit board 15 further includes a second insulating pad 155, referring to Fig. 9 The second insulating pad 155 is located between the first gate circuit board 151 and the second gate circuit board 152 .

[0090] In one embodiment, the gate circuit board 15 has a first hole penetrating the gate circuit board 15, and the first hole is located above the emitter of the power semiconductor chip 2. The auxiliary emitter circuit board 11 has a second hole penetrating the auxiliary emitter circuit board 11, and the second hole is at least connected to a portion of the first hole.

[0091] The first sub-conductive connecting portion 7 passes through the first hole and the second hole and is electrically connected to the second substrate electrode 10 .

[0092] The first sub-conductive connection portion 7 on the power semiconductor chip 2 passes through the first hole and the second hole to be electrically connected to the second substrate electrode 10, and the second sub-conductive connection portion 8 on part of the power semiconductor chip 2 passes through the first hole and the second hole to be electrically connected to the second interconnection line 114 on the second auxiliary emitter circuit board 112; the second sub-conductive connection portion 8 on part of the power semiconductor chip 2 passes through the first hole and the second hole of the first auxiliary emitter circuit board 111 to be electrically connected to the first interconnection line 113 on the first auxiliary emitter circuit board 111.

[0093] For the convenience of description, the plurality of conductive pillars are divided into first conductive pillars and second conductive pillars.

[0094] The gates 202 of some power semiconductor chips 2 are electrically connected to the third interconnection line 153 on the first gate circuit board 151 through the bonding wire 14 and the first conductive column, and the first conductive column does not penetrate the first gate circuit board 151; the gates 202 of some power semiconductor chips 2 are electrically connected to the fourth interconnection line 154 on the second gate circuit board 152 through the bonding wire 14 and the second conductive column, and the second conductive column penetrates the first gate circuit board 151 and is electrically insulated from the first gate circuit board 151.

[0095] The second sub-conductive connecting portion 8 passes through the first hole and is connected to the auxiliary emitter circuit board 11 .

[0096] In one embodiment, the first gate circuit board 151 and the second gate circuit board 152 are electrically connected through a through hole using the gate opening position of the power semiconductor chip 2 .

[0097] In one embodiment, the power semiconductor chip packaging structure further includes: a tube shell 17, referring to Fig.10 The tube shell 17 surrounds the first substrate electrode 1 and the second substrate electrode 10 .

[0098] In one embodiment, the tube shell 17 is made of a material with high insulation strength and high temperature resistance.

[0099] In one embodiment, the power semiconductor chip packaging structure further includes: an insulating potting material, wherein the insulating potting material includes silicone gel and epoxy glue; in other embodiments, the insulating potting material may further include other insulating materials.

[0100] The first micropores 73 and the second micropores 83 in the conductive connector 6 in the power semiconductor chip packaging structure provided by the present invention are combined with the insulating potting material and the sintering process technology in the power semiconductor chip packaging structure. While ensuring the flow capacity of the power semiconductor chip packaging structure, the mechanical stress on the surface of the power semiconductor chip 2 can be released, so that the first substrate electrode 1 and the second substrate electrode 10 have a certain elasticity, which can improve the reliability of the power semiconductor chip packaging structure and reduce the influence of the drive circuit on the power circuit.

[0101] In one embodiment, the insulating potting material surrounds the conductive connection 6 .

[0102] refer to Fig.11 , Fig.11 It is a plan cross-sectional view of the power semiconductor chip packaging structure.

[0103] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A power semiconductor chip packaging structure, characterized in that: include: a first substrate electrode; A power semiconductor chip located on a portion of the first substrate electrode and electrically connected to the first substrate electrode; a surface of the power semiconductor chip facing away from the first substrate electrode has an emitter; A coil shielding structure surrounding the power semiconductor chip, the coil shielding structure comprising a conductive coil and an insulator covering the conductive coil; The power semiconductor chip packaging structure further includes: A conductive connection member located on the emitter, the conductive connection member comprising a first sub-conductive connection portion, a second sub-conductive connection portion, and an insulating portion located between the first sub-conductive connection portion and the second sub-conductive connection portion, the first sub-conductive connection portion, the insulating portion, and the second sub-conductive connection portion are arranged in a direction parallel to the surface of the first substrate electrode, the height of the first sub-conductive connection portion is greater than the height of the second sub-conductive connection portion, and the first sub-conductive connection portion and the second sub-conductive connection portion are both connected to the emitter; a second substrate electrode disposed opposite to the first substrate electrode; an auxiliary emitter circuit board located between the second substrate electrode and the first substrate electrode; The first sub-conductive connection portion passes through the auxiliary emitter circuit board and is electrically connected to the second substrate electrode, the first sub-conductive connection portion is electrically insulated from the auxiliary emitter circuit board; the second sub-conductive connection portion is electrically connected to the auxiliary emitter circuit board; The first sub-conductive connection portion includes a first sub-bottom layer connection layer and one or more first sub-top layer connection layers located above the first sub-bottom layer connection layer, the first sub-bottom layer connection layer is a full-surface structure, and the first sub-top layer connection layer has a plurality of first micro-holes; The second sub-conductive connection part includes a second sub-bottom layer connection layer and one or more second sub-top layer connection layers located above the second sub-bottom layer connection layer. The second sub-bottom layer connection layer is a full-surface structure and has a plurality of second micro-holes in the second sub-top layer connection layer.

2. The power semiconductor chip packaging structure according to claim 1, characterized in that: The insulator comprises ceramic; The distance between the insulator and the power semiconductor chip is 1 mm-10 mm.

3. The power semiconductor chip packaging structure according to claim 1, characterized in that: The coil shielding structure is a circular ring structure.

4. The power semiconductor chip packaging structure according to claim 1, characterized in that: The number of the auxiliary emitter circuit boards is several, and the several auxiliary emitter circuit boards include a first auxiliary emitter circuit board and a second auxiliary emitter circuit board located on a side of the first auxiliary emitter circuit board away from the first substrate electrode; The emitters of some power semiconductor chips are electrically connected to the first auxiliary emitter circuit board through the second sub-conductive connection part, and the emitters of some power semiconductor chips are electrically connected to the second auxiliary emitter circuit board through the second sub-conductive connection part; the projections of the first interconnection line in the first auxiliary emitter circuit board and the second interconnection line in the second auxiliary emitter circuit board on the surface of the first substrate electrode at least partially overlap, and for the first interconnection line and the second interconnection line whose projections on the surface of the first substrate electrode overlap, the current direction in the first interconnection line is opposite to the current direction in the second interconnection line.

5. The power semiconductor chip packaging structure according to claim 1, characterized in that: The power semiconductor chip has a gate on a side facing away from the first substrate electrode; The power semiconductor chip packaging structure further includes: a liner located on the first substrate electrode and on the side of the power semiconductor chip, wherein a surface of the liner facing away from the first substrate electrode has a conductive column; A bonding wire connecting the gate and the conductive pillar; A gate circuit board is arranged opposite to the first substrate electrode, the power semiconductor chip, the conductive column and the liner are all located between the gate circuit board and the first substrate electrode, and the conductive column is electrically connected to the gate circuit board.

6. The power semiconductor chip packaging structure according to claim 5, characterized in that: Also includes: The support column is located between the liner and the gate circuit board and on the side of the conductive column.

7. The power semiconductor chip packaging structure according to claim 5, characterized in that: The number of the gate circuit boards is several, and the several gate circuit boards include a first gate circuit board and a second gate circuit board located on a side of the first gate circuit board away from the first substrate electrode; The gates of some power semiconductor chips are electrically connected to the first gate circuit board through the bonding wires and the conductive pillars, and the gates of some power semiconductor chips are electrically connected to the second gate circuit board through the bonding wires and the conductive pillars; the projections of the third interconnection line in the first gate circuit board and the fourth interconnection line in the second gate circuit board at least partially overlap on the surface of the first substrate electrode, and for the third interconnection line and the fourth interconnection line whose projections on the surface of the first substrate electrode overlap, the current direction in the third interconnection line is opposite to the current direction in the fourth interconnection line.

8. The power semiconductor chip packaging structure according to claim 1, characterized in that: Also includes: A tube shell surrounds the first substrate electrode and the second substrate electrode.

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