Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: forming a first dielectric material layer and a first sidewall material layer located on the first dielectric material layer on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on a substrate; etching back the first sidewall material layer until the surface of the first dielectric material layer is exposed, and forming a first sidewall on the sidewall of the first opening and the sidewall of the third gate; using the first sidewall as a mask, forming a storage drain region in a storage region below the first opening; after forming the storage drain region, removing the first sidewall in the first opening; after removing the first sidewall in the first opening, forming a second sidewall on the sidewall of the first opening and the sidewall of the third gate, wherein the thickness of the second sidewall is less than that of the first sidewall, so as to facilitate the filling of an interlayer dielectric layer between the first gate and the second gate, thereby improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Flash memory is a non-volatile memory that can retain data for a long time even without current supply, that is, data will not be lost even if power is off. Flash memory is mainly divided into two types: NOR and NAND, usually called NOR Flash and NAND Flash. Among them, NOR Flash is also called coded flash memory. Because it has the characteristics of direct code execution, high reliability, and fast reading speed, it has become the mainstream non-volatile memory in flash memory technology.

[0003] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, integrated circuit chips are developing towards higher device density and higher integration. The performance of existing flash memory structures needs to be further improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a first gate and a plurality of second gates on the storage area, and a plurality of third gates on the peripheral area, wherein a first opening is provided between the first gate and the adjacent second gates; forming a first dielectric material layer and a first sidewall material layer located on the first dielectric material layer on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on the substrate, wherein the material of the first dielectric material layer is different from that of the first sidewall material layer; etching back the first sidewall material layer until the surface of the first dielectric material layer is exposed, and forming a first sidewall on the sidewall of the first opening and the sidewall of the third gate; using the first sidewall as a mask, forming a storage drain area in the storage area below the first opening; after forming the storage drain area, removing the first sidewall in the first opening; after removing the first sidewall in the first opening, forming a second sidewall on the sidewall of the first opening and the sidewall of the third gate, wherein the thickness of the second sidewall is less than that of the first sidewall.

[0006] Optionally, a second opening is provided between two adjacent second gates, and a storage source region is provided in the storage region below the second opening.

[0007] Optionally, the process for forming the storage source region includes a process for forming a self-aligned source region.

[0008] Optionally, the first dielectric material layer and the first spacer material layer are formed on the side walls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on the substrate so as to fill up the second opening.

[0009] Optionally, the width of the second opening is smaller than the width of the first opening.

[0010] Optionally, before forming the first dielectric material layer, a second dielectric material layer is further formed on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates, and on the substrate.

[0011] Optionally, along the normal direction of the substrate surface, the total thickness of the first dielectric material layer and the second dielectric material layer has a first value, the thickness of the first sidewall material layer has a second value, and the ratio of the first value to the second value ranges from 1:1 to 1:3.

[0012] Optionally, the material of the first dielectric material layer includes silicon nitride; the material of the second dielectric material layer includes silicon oxide; the material of the first spacer material layer includes silicon oxide; and the material of the second spacer includes silicon oxide.

[0013] Optionally, the formation process of the second dielectric material layer includes a high-temperature thermal oxidation process; the formation process of the first sidewall material layer includes a furnace tube tetraethyl orthosilicate process; and the formation process of the second sidewall includes a furnace tube tetraethyl orthosilicate process.

[0014] Optionally, the method for forming the storage drain region further includes: forming a first mask layer on the surface of the storage region and the third gate; and forming the storage drain region using the first mask layer and the first sidewall as masks.

[0015] Optionally, the method for removing the first sidewall in the first opening further includes: after forming the storage drain region, etching the first sidewall using the first mask layer as a mask; and after removing the first sidewall, removing the first mask layer.

[0016] Optionally, after forming the second sidewall, it also includes: forming a second mask layer on the surface of the storage area, the first gate and the second gate; using the second mask layer and the second sidewall as masks, forming a peripheral source and drain layer in the peripheral area on both sides of the third gate.

[0017] Optionally, the thickness of the first sidewall spacer is in a range of 20 nm to 40 nm, and the thickness of the second sidewall spacer is in a range of 20 nm to 35 nm.

[0018] Optionally, the aspect ratio of the first opening ranges from 1:1 to 4:1.

[0019] Optionally, the material of the first side wall material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and carbon silicon oxynitride; the material of the second side wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and carbon silicon oxynitride.

[0020] Optionally, a shallowly doped ion implantation region is provided in the storage region below the first opening.

[0021] Optionally, the storage area comprises a first double deep well region, a heavily doped well region located on the first double deep well region, and an adjustment threshold voltage region located on the heavily doped well region, and the conductivity type of the first double deep well region is different from that of the heavily doped well region.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, after forming the storage drain region, the first sidewall in the first opening is removed, and after removing the first sidewall in the first opening, a second sidewall is formed on the sidewall of the first opening and the sidewall of the third gate, and the thickness of the second sidewall is less than the thickness of the first sidewall. The storage region uses the first sidewall as a mask to form a storage drain region, and the peripheral region uses the second sidewall as a mask to form a source and drain layer of the peripheral region. Under the premise of not changing the channel length of the storage region and the peripheral region, in the final structure, due to the removal of the first sidewall of the first opening sidewall, the opening between the first gate of the storage region and the adjacent second gate becomes larger, which is conducive to the subsequent filling of the interlayer dielectric layer between the first gate and the second gate, thereby improving the performance of the device; in addition, the first dielectric material layer serves as an etching stop layer in the process of forming the first sidewall, and in the process of removing the first sidewall in the first opening, the first dielectric material layer also protects the storage region, the first gate and the second gate.

[0024] Furthermore, the process of removing the first sidewall in the first opening and the process of forming the storage drain region use the same first mask layer as a mask, which helps to save mask costs.

[0025] Further, along the normal direction of the substrate surface, the total thickness of the first dielectric material layer and the second dielectric material layer has a first value, the thickness of the first spacer material layer has a second value, the ratio of the first value to the second value ranges from 1:1 to 1:3, and the total thickness of the first dielectric material layer, the second dielectric material layer and the first spacer material layer determines the position of the drain area of ​​the storage area. Under the premise of not changing the channel length of the storage area, the thickness of the first spacer material layer is increased, so that after removing the first spacer in the first opening, the aspect ratio between the first gate and the second gate is reduced when the interlayer dielectric layer is filled, thereby improving the filling capacity of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 to Figure 2 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0027] Figures 3 to 9 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0029] As described in the background art, the performance of existing flash memory structures needs to be further improved. Now, a method for forming a semiconductor structure is described and analyzed.

[0030] Figure 1 to Figure 2 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0031] Please refer to Figure 1, providing a substrate, the substrate comprising a base 100, the base 100 comprising a storage area I and a peripheral area II, the substrate further comprising a first gate 101, a second gate 102, and a third gate 103 arranged along a first direction X on the storage area I, and a plurality of fourth gates 201 arranged along the first direction X on the peripheral area II, a first opening 104 being provided between the first gate 101 and the second gate 102, a second opening (not shown in the figure) being provided between the second gate 102 and the third gate 103, a source area 106 being provided in the storage area I under the second opening, a width of the first opening 104 being greater than a width of the second opening along the first direction X, and a width n of the first opening 104 being less than a distance between two adjacent fourth gates 201; A first sidewall material layer is formed on the substrate, wherein the first sidewall material layer includes a first oxide material layer 107, a first silicon nitride material layer 108 located on the first oxide material layer 107, and a second oxide material layer 109 located on the first silicon nitride material layer 108, wherein the first sidewall material layer fills the second opening; the first sidewall material layer is etched until the first oxide material layer 107 is exposed, and the first sidewall material layer is used to form a first sidewall at the sidewalls of the first gate 101 and the second gate 102 exposed at the first opening 104; after forming the first sidewall, a mask layer (not shown in the figure) is formed in the peripheral region II, and a source region 110 is formed in the substrate under the first opening 104 using the first sidewall and the first mask layer as masks; after forming the source region 110, the first mask layer is removed.

[0032] Please refer to Figure 2 After removing the mask layer, depositing a second silicon nitride material layer 202 on the substrate; etching the second silicon nitride material layer 202 until the first oxide material layer 107 is exposed, and forming a second sidewall with the first oxide material layer 107, the first silicon nitride material layer 108, the first silicon nitride material layer 109 and the second silicon nitride material layer 202 of the fourth gate 201; after forming the second sidewall, forming a second mask layer in the storage area I; using the second mask layer and the second sidewall as masks, forming a source and drain region 203 in the peripheral area II on both sides of the fourth gate 201.

[0033] In the above method, since the material of the first sidewall of the storage area and the material of the second sidewall of the peripheral area are deposited simultaneously, the width n of the first opening 104 is smaller than the distance between the two adjacent fourth gates 201. After the second sidewall is formed, the first opening 104 is filled with the first sidewall material and the second sidewall material, and has a high aspect ratio, which is not conducive to the subsequent filling of the interlayer dielectric layer material. During the filling process, defects such as gaps are prone to occur, thereby affecting the performance of the device. In order to improve the filling problem of the interlayer dielectric layer material in the storage area, in another embodiment, the filling capacity of the interlayer dielectric layer between the first gate 101 and the second gate 102 is improved by thinning the thickness of the first sidewall material layer. However, the thinning of the thickness of the first sidewall material layer will shorten the channel length of the peripheral device, thereby affecting the reliability of the device.

[0034] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, wherein after forming the storage drain region, the first sidewall in the first opening is removed, and after removing the first sidewall in the first opening, a second sidewall is formed on the sidewall of the first opening and the sidewall of the third gate, and the thickness of the second sidewall is less than the thickness of the first sidewall. The storage region uses the first sidewall as a mask to form a storage drain region, and the peripheral region uses the second sidewall as a mask to form a source and drain layer of the peripheral region. Under the premise of not changing the channel length of the device in the storage region and the peripheral region, in the final structure, due to the removal of the first sidewall of the first opening sidewall, the opening between the first gate of the storage region and the adjacent second gate becomes larger, which is beneficial to the subsequent filling of the interlayer dielectric layer between the first gate and the second gate, thereby improving the performance of the device; in addition, the first dielectric material layer serves as an etching stop layer in the process of forming the first sidewall, and in the process of removing the first sidewall in the first opening, the first dielectric material layer also plays a role of protecting the substrate for the storage region, the first gate and the second gate.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 9 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0037] Please refer to Figure 3 , providing a substrate, wherein the substrate includes a storage area A and a peripheral area B;

[0038] In this embodiment, the material of the substrate is single crystal silicon. In other embodiments, the material of the substrate can be polycrystalline silicon or amorphous silicon, or can be semiconductor materials such as germanium, silicon germanium, gallium arsenide, or can be a semiconductor-on-insulator structure.

[0039] The storage area A is used to form a storage device, and the peripheral area B is used to form a peripheral device. A channel length of the storage device is smaller than a channel length of the peripheral device.

[0040] In this embodiment, the storage area A includes a first double deep well region 200a, a heavily doped well region 200b located on the first double deep well region 200a, and an adjustment threshold voltage region 200c located on the heavily doped well region 200b, and the conductivity type of the first double deep well region 200a is different from the conductivity type of the heavily doped well region 200b. Specifically, the conductivity type of the first double deep well region 200a is N-type, and the conductivity type of the heavily doped well region 200b is P-type.

[0041] In this embodiment, a second deep well region 200d is defined in the peripheral region B, and the conductivity type of the second deep well region 200d is N type.

[0042] Please refer to Figure 4 , forming a first gate 201 and a plurality of second gates 202 on the storage area A, and a plurality of third gates 203 on the peripheral area B, wherein a first opening 204 is provided between the first gate 201 and the adjacent second gate 202 .

[0043] The first gate 201 includes a first gate oxide layer (not shown in the figure) located on the surface of the storage area A, a first floating gate (not shown in the figure) located on a portion of the surface of the first gate oxide layer, a first gate dielectric layer (not shown in the figure) located on the first floating gate, and a control gate (not shown in the figure) located on the first gate dielectric layer; the second gate 202 includes a first gate oxide layer (not shown in the figure) located on the surface of the peripheral area B, a second floating gate (not shown in the figure) located on a portion of the surface of the second gate oxide layer, a second gate dielectric layer (not shown in the figure) located on the second floating gate, and a second control gate (not shown in the figure) located on the second gate dielectric layer.

[0044] In this embodiment, there is a second opening 205 between two adjacent second gates 202, and a storage source region is provided in the storage region B under the second opening 205. The storage source region is shared by two adjacent second gates 202. Specifically, the storage source region includes a P-type injection region 206 and an N-type injection region 207 located on the P-type injection region 206.

[0045] The width of the second opening 205 is smaller than that of the first opening 204. The width refers to a dimension along a direction parallel to the surface of the substrate.

[0046] The storage source region forming process includes a self-aligned source region forming process.

[0047] In this embodiment, the method for forming the storage source region includes: using a plurality of second gates 202 as masks, respectively injecting P-type ions and N-type ions into the storage region A under the second opening 205 to form the P-type injection region 206 and the N-type injection region 207, wherein the position of the P-type injection region 206 is lower than the position of the N-type injection region 207, and the P-type injection region 206 and the N-type injection region 207 are in contact with each other.

[0048] In this embodiment, the storage area A below the first opening 204 further includes a shallowly doped ion implantation area 208 .

[0049] The aspect ratio of the first opening 204 is in a range of 1:1 to 4:1. After the spacer material layer is filled in the first opening 204, the aspect ratio of the first opening 204 will be increased.

[0050] Please refer to Figure 5 A first dielectric material layer 209 and a first spacer material layer 210 located on the first dielectric material layer 209 are formed on the side walls and top surfaces of the first gate 201, the plurality of second gates 202 and the plurality of third gates 203 and on the substrate, and the material of the first dielectric material layer 209 is different from that of the first spacer material layer 210.

[0051] The first dielectric material layer 209 and the first spacer material layer 210 are formed on the sidewalls and top surfaces of the first gate 201 , the plurality of second gates 202 , and the plurality of third gates 203 and on the substrate, so as to fill up the second opening 205 .

[0052] In this embodiment, before forming the first dielectric material layer 209 , a second dielectric material layer 211 is further formed on the sidewalls and top surfaces of the first gate 201 , the plurality of second gates 202 , and the plurality of third gates 203 , as well as on the substrate.

[0053] The material of the first spacer material layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0054] Specifically, the material of the first dielectric material layer 209 includes silicon nitride; the material of the second dielectric material layer 211 includes silicon oxide; and the material of the first spacer material layer 210 includes silicon oxide.

[0055] The formation process of the second dielectric material layer 211 includes a high-temperature thermal oxidation process; the formation process of the first sidewall material layer 211 includes a furnace tube tetraethyl orthosilicate process. In this embodiment, in the ONO (Oxide-Nitride-Oxide) sidewall structure formed by the sidewalls of the first gate, the second gate and the third gate: the material of the second dielectric material layer 211 is silicon oxide, formed by a high-temperature thermal oxidation process, and the second dielectric material layer 211 is used as a buffer layer to reduce the stress of the first dielectric material layer 209 on the substrate and the first gate 201, the second gate 202 and the third gate 203; the material of the first dielectric material layer 209 is silicon nitride, and the first dielectric material layer 209 has a high density and strength, which can effectively prevent the diffusion of water vapor and sodium ions; the first sidewall material layer 210 is silicon oxide formed by the furnace tube tetraethyl orthosilicate process.

[0056] Subsequently, the first spacer material layer 210 is used to form a first spacer.

[0057] In this embodiment, along the normal direction of the substrate surface, the total thickness of the first dielectric material layer 209 and the second dielectric material layer 211 has a first value, the thickness of the first spacer material layer 210 has a second value, and the ratio of the first value to the second value ranges from 1:1 to 1:3. The total thickness of the first dielectric material layer 209, the second dielectric material layer 211, and the first spacer material layer 210 determines the position of the drain region of the storage area. Under the premise of not changing the channel length of the storage area A, the thickness of the first spacer material layer 210 is increased, so that after removing the first spacer in the first opening 204, it is beneficial to reduce the aspect ratio between the first gate 201 and the second gate 202 when the interlayer dielectric layer is filled, thereby improving the filling capacity of the interlayer dielectric layer.

[0058] In this embodiment, the thickness of the first dielectric material layer 209 is 10 nm to 20 nm, the thickness of the second dielectric material layer 211 is 8 nm to 15 nm, and the thickness of the first spacer material layer 210 is 30 nm to 50 nm.

[0059] Please refer to Figure 6 , the first spacer material layer 210 is etched back until the surface of the first dielectric material layer 209 is exposed, and a first spacer 212 is formed on the sidewalls of the first opening 204 and the sidewalls of the third gate 203 .

[0060] The first dielectric material layer 209 is used as an etching stop layer during the formation of the first sidewall spacer 212 .

[0061] Subsequently, the first sidewall 212 is used as a mask to form a storage drain region in the storage region A below the first opening 204. For a method of forming the storage drain region, please refer to Figure 7 .

[0062] Please refer to Figure 7 , forming a first mask layer 213 on the surface of the storage area A and the third gate 203; using the first mask layer 213 and the first sidewall 212 as masks, forming the storage drain area 214.

[0063] The thickness d1 of the first sidewall spacer 212 is in a range of 20 nm to 40 nm. The thickness refers to a dimension in a direction perpendicular to the sidewall surface of the first gate 201 .

[0064] Subsequently, after forming the storage drain region, the first sidewall in the first opening 204 is removed; for a method of removing the first sidewall 212 in the first opening 204, please refer to Figure 8 .

[0065] Please refer to Figure 8 After forming the storage drain region 214, the first mask layer 213 is used as a mask to etch the first sidewall 212; after removing the first sidewall 212, the first mask layer 213 is removed.

[0066] The process of etching the first sidewall spacer 212 includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the process of etching the first sidewall spacer 212 is a wet etching process.

[0067] In this embodiment, since the second opening 205 has a high aspect ratio, the first spacer material layer 210 in the second opening 205 is retained during the process of etching the first spacer 212 .

[0068] In the process of removing the first sidewall 212 in the first opening 204, the first dielectric material layer 209 also protects the storage area A, the first gate 201 and the second gate 202. In addition, the process of removing the first sidewall 212 in the first opening 204 and the process of forming the storage drain area A use the same first mask layer 213 as a mask, which helps to save mask costs.

[0069] Please refer to Fig. 9 After removing the first sidewall 212 in the first opening 204 , a second sidewall 215 is formed on the sidewalls of the first opening 204 and the third gate 203 , and a thickness d2 of the second sidewall 215 is less than a thickness d1 of the first sidewall 212 .

[0070] The method for forming the second spacer 215 includes: forming a second spacer material layer (not shown in the figure) on the sidewalls and top surfaces of the first gate 201, the plurality of second gates 202 and the plurality of third gates 203 and the substrate; and etching back the second spacer material layer until the first dielectric material layer 209 is exposed. In this embodiment, the thickness of the second spacer material layer is 25nm to 40nm.

[0071] The thickness d2 of the second spacer 215 is in a range of 20 nm to 35 nm. The thickness refers to the dimension in a direction perpendicular to the sidewall surface of the third gate 203 .

[0072] The material of the second spacer 215 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0073] The material of the second sidewall spacer includes silicon oxide. In this embodiment, the material of the second sidewall spacer is silicon oxide.

[0074] The second spacer 215 is formed by a furnace tube ethyl orthosilicate process. Specifically, the second spacer material layer is formed by a furnace tube ethyl orthosilicate process.

[0075] Subsequently, after the second side wall 215 is formed, it also includes: forming a second mask layer (not shown in the figure) on the surface of the storage area A, the first gate and the second gate; using the second mask layer and the second side wall 215 as masks, forming a peripheral source and drain layer (not shown in the figure) of the peripheral B in the peripheral area on both sides of the third gate.

[0076] The peripheral region uses the second sidewall 215 as a mask to form the source and drain layer of the peripheral region B. Under the premise of not changing the channel length of the devices in the storage region A and the peripheral region B, in the finally formed structure, due to the removal of the first sidewall 212 on the sidewall of the first opening 204, the opening between the first gate 201 of the storage region A and the adjacent second gate 202 becomes larger, which is beneficial to the subsequent filling of the interlayer dielectric layer between the first gate 201 and the second gate 202, thereby improving the performance of the device.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a first gate and a plurality of second gates on the storage area, and a plurality of third gates on the peripheral area, wherein a first opening is provided between the first gate and the adjacent second gates; Forming a first dielectric material layer and a first spacer material layer on the first dielectric material layer on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on the substrate, wherein the material of the first dielectric material layer is different from that of the first spacer material layer; Etching back the first spacer material layer until the surface of the first dielectric material layer is exposed, and forming a first spacer on the sidewall of the first opening and the sidewall of the third gate; Using the first sidewall as a mask, forming a storage drain region in the storage region below the first opening; After forming the storage drain region, removing the first sidewall in the first opening; After removing the first sidewall spacer in the first opening, a second sidewall spacer is formed on the sidewall of the first opening and the sidewall of the third gate, and the thickness of the second sidewall spacer is smaller than the thickness of the first sidewall spacer.

2. The method for forming a semiconductor structure according to claim 1, wherein: A second opening is provided between two adjacent second gates, and a storage source region is provided in the storage region below the second opening.

3. The method for forming a semiconductor structure according to claim 2, wherein: The storage source region forming process includes a self-aligned source region forming process.

4. The method for forming a semiconductor structure according to claim 2, wherein: The first dielectric material layer and the first spacer material layer are formed on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on the substrate, so as to fill up the second opening.

5. The method for forming a semiconductor structure according to claim 2, wherein: A width of the second opening is smaller than a width of the first opening.

6. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first dielectric material layer, a second dielectric material layer is further formed on the sidewalls and top surfaces of the first gate, the plurality of second gates and the plurality of third gates and on the substrate.

7. The method for forming a semiconductor structure according to claim 6, wherein: Along the normal direction of the substrate surface, the total thickness of the first dielectric material layer and the second dielectric material layer has a first value, the thickness of the first sidewall material layer has a second value, and the ratio of the first value to the second value ranges from 1:1 to 1:

3.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first dielectric material layer includes silicon nitride; the material of the second dielectric material layer includes silicon oxide; the material of the first spacer material layer includes silicon oxide; and the material of the second spacer includes silicon oxide.

9. The method for forming a semiconductor structure according to claim 8, wherein: The forming process of the second dielectric material layer includes a high-temperature thermal oxidation process; the forming process of the first sidewall material layer includes a furnace tube tetraethyl orthosilicate process; and the forming process of the second sidewall includes a furnace tube tetraethyl orthosilicate process.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the storage drain region further includes: forming a first mask layer on the surface of the storage region and the third gate; and forming the storage drain region using the first mask layer and the first sidewall as masks.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for removing the first sidewall in the first opening further includes: after forming the storage drain region, etching the first sidewall using the first mask layer as a mask; and after removing the first sidewall, removing the first mask layer.

12. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second sidewall, it also includes: forming a second mask layer on the surface of the storage area, the first gate and the second gate; using the second mask layer and the second sidewall as masks, forming a peripheral source and drain layer in the peripheral area on both sides of the third gate.

13. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first spacer is in a range of 20 nm to 40 nm, and the thickness of the second spacer is in a range of 20 nm to 35 nm.

14. The method for forming a semiconductor structure according to claim 1, wherein: The first opening has a depth-to-width ratio ranging from 1:1 to 4:

1.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first side wall material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and carbon silicon oxynitride; the material of the second side wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and carbon silicon oxynitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The storage area under the first opening has a shallow doped ion implantation area.

17. The method for forming a semiconductor structure according to claim 1, wherein: The storage area comprises a first double deep well region, a heavily doped well region located on the first double deep well region, and a threshold voltage adjustment region located on the heavily doped well region. The first double deep well region and the heavily doped well region have different conductivity types.

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