Power semiconductor devices

Abstract

The present application provides a power semiconductor device, including a wafer, and a plurality of first cathode combs and gates arranged on the surface of the wafer; wherein the surface of the wafer is divided into a plurality of concentric circular ring areas and a plurality of concentric fan-shaped areas with the same center, the plurality of concentric circular ring areas and the plurality of concentric fan-shaped areas overlap to define a plurality of graphic areas, the plurality of first cathode combs are arranged at intervals in the plurality of graphic areas; each of the first cathode combs arranged in the same graphic area is parallel to the radial symmetry axis of the graphic area, and is arranged along the inner ring of the circular ring area where it is located; the arrangement spacing of the first cathode combs in each of the graphic areas first decreases and then increases in the direction of increasing radial distance from the gate. The spacing of the cathode combs in the graphic area is designed to change with the change of the radial distance from the gate, which improves the dynamic switching uniformity of the cathode combs, and is conducive to improving the shutdown capability of large-area chips.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] Gate Commutated Thyristors (GCT) are a current-controlled, high-power semiconductor device in the field of power electronics. Their turn-on characteristics are similar to those of thyristors, with low conduction losses, and their turn-off characteristics are similar to those of transistors, so they have the characteristics of low conduction losses, large surge currents, fast turn-off speeds, and large power capacity. GCTs are usually used in some power devices with ultra-large power capacity, such as metallurgical rolling mill transmission systems, ship drive systems, power grid energy quality control devices, and other heavy industry core equipment.

[0003] The GCT chip structure is similar to the Gate Turn Off Thyristor (GTO), with three terminals (cathode, anode and gate) and a four-layer PNPN structure. The cathode surface is formed by thousands of GCT basic units (called "cathode combs") in parallel, surrounded by an integrally connected gate region, and the gate region is led out from the gate. Among them, the cathode combs are usually arranged in concentric circles, in a rectangular array, a circular array, or evenly arranged radially on a wafer surface. However, in the existing arrangement method, the cathode combs are staggered to a large extent, resulting in difficult process molding, and the gate fast channel sizes are different, resulting in poor chip shutdown uniformity. Summary of the invention

[0004] In view of the above problems, the present application provides a power semiconductor device, which solves the technical problem in the prior art that the arrangement of cathode comb bars of gate-commutated thyristor power semiconductor devices leads to poor chip shutdown uniformity.

[0005] The present application provides a power semiconductor device, comprising a wafer, and a plurality of first cathode comb bars and gate electrodes arranged on a surface of the wafer;

[0006] The wafer surface is divided into a plurality of concentric circular ring areas and a plurality of concentric fan-shaped areas having the same center, the plurality of concentric circular ring areas and the plurality of concentric fan-shaped areas overlap to define a plurality of graphic areas, and the plurality of first cathode comb bars are arranged at intervals in the plurality of graphic areas;

[0007] Each of the first cathode comb bars disposed in the same graphic area is parallel to the radial symmetry axis of the graphic area, and is arranged along the inner ring of the annular area where it is located;

[0008] The arrangement spacing of the first cathode comb bars in each of the graphic areas first decreases and then increases in the direction of increasing radial distance from the gate.

[0009] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the length and / or width of each of the first cathode comb bars gradually decreases in a direction of increasing radial distance from the gate.

[0010] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, among the plurality of the first cathode comb bars arranged in the same the graphic area, the spacing between any two adjacent first cathode comb bars is the same.

[0011] According to an embodiment of the present application, optionally, the power semiconductor device further comprises: a second cathode comb bar disposed at the junction of any two adjacent graphic areas in the annular area;

[0012] Wherein, the extension line of the second cathode comb bar intersects with the center of the circle.

[0013] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the second cathode comb bars are arranged along the inner ring of the circular area where they are located.

[0014] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the arrangement spacing of the first cathode comb bars arranged in the same graphic area is a first distance;

[0015] The distance between one end of the second cathode comb bar close to the center of the circle and the adjacent first cathode comb bar is a second distance;

[0016] The first distance and the second distance corresponding to the same graphic area are equal.

[0017] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, a channel region is formed between the second cathode comb bar and the adjacent first cathode comb bar.

[0018] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the number of the second cathode comb bars at the junction of any two adjacent graphic areas is 1.

[0019] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the gate is arranged in the annular area at the edge, center or middle position of the wafer.

[0020] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, radial spacing distances between each of the first cathode comb bars arranged in the same graphic area and the inner ring of the annular area in which they are located are the same.

[0021] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the lengths of the first cathode comb bars arranged in the same graphic area are the same; and / or,

[0022] The widths of the first cathode comb bars arranged in the same graphic area are the same.

[0023] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the multiple concentric sector-shaped areas have the same size.

[0024] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, radial widths of the respective annular regions where the first cathode comb bars are arranged are the same.

[0025] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, both ends of the cathode comb bar are semicircular arc-shaped.

[0026] By adopting the above technical solution, at least the following technical effects can be achieved:

[0027] (1) The comb strips are evenly arranged in a sector arc, and the comb strips can be arranged in an array. The cathode comb strips in different circles are less staggered, and the chip shutdown / opening delay time is shorter. While improving the cathode area utilization and flow capacity of the chip, it also reduces the process difficulty of cathode comb strip molding, improves the process yield and reduces the chip production cost.

[0028] (2) The spacing of the cathode comb bars in the graphic area is designed to change with the radial distance between the cathode comb bars and the gate electrode, which offsets the influence of parasitic inductance and improves the dynamic switching uniformity of the cathode comb bars. This is particularly beneficial for improving the turn-off capability of large-area chips and can simplify the irradiation process.

[0029] (3) The spacing of the cathode comb bars in the graphic area is designed to change with the radial distance between the cathode comb bars and the gate electrode, which reduces the influence of stray inductance introduced by the lateral structure of the chip and is conducive to expanding the chip diameter design, especially suitable for large diameter edge gate chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0031] Figure 1a It is a schematic diagram of cathode comb arrangement of a power semiconductor device;

[0032] Figure 1b yes Figure 1a A magnified view of a one-sixteenth portion of a medium-power semiconductor device;

[0033] Figure 2a This is a schematic diagram of cathode comb arrangement of another power semiconductor device;

[0034] Figure 2b yes Figure 2a An enlarged schematic diagram of a one-sixteenth portion of a medium-power semiconductor device;

[0035] Figure 3a This is a schematic diagram of cathode comb arrangement of another power semiconductor device;

[0036] Figure 3b yes Figure 3a An enlarged schematic diagram of a one-sixteenth portion of a medium-power semiconductor device;

[0037] Figure 4 It is a schematic diagram of dividing the surface of a wafer in a power semiconductor device shown in an exemplary embodiment of the present application;

[0038] Figure 5a It is a schematic diagram of cathode comb arrangement of a power semiconductor device shown in an exemplary embodiment of the present application;

[0039] Figure 5b yes Figure 5a An enlarged schematic diagram of a one-sixteenth portion of a medium-power semiconductor device;

[0040] Figure 6 yes Figure 5a and 5b An enlarged schematic diagram of the middle cathode comb bar;

[0041] Figure 7a is a schematic diagram of cathode comb arrangement of another power semiconductor device shown in an exemplary embodiment of the present application;

[0042] Figure 7b yes Figure 7a A magnified schematic diagram of a quarter of a medium power semiconductor device;

[0043] Figure 7c yes Figure 7a An enlarged schematic diagram of one thirty-second portion of a medium power semiconductor device;

[0044] Figure 8a is a schematic diagram of cathode comb arrangement of another power semiconductor device shown in an exemplary embodiment of the present application;

[0045] Figure 8b yes Figure 8a A magnified schematic diagram of a quarter of a medium power semiconductor device;

[0046] Figure 8c yes Figure 8a An enlarged schematic diagram of a sixty-fourth portion of a medium-power semiconductor device;

[0047] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0048] The following will describe the implementation methods of the present application in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0049] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0050] It will be appreciated that spatially relative terms, such as "above", "above", "below", "under", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below other elements" would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the present application are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0053] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0054] A cathode comb arrangement method of a power semiconductor device 10, such as Figure 1a and Figure 1b As shown, each cathode comb bar 12 is the same size and is arranged radially along the wafer 11. The direction of each cathode comb bar 12 points to the center of the wafer and is arranged in concentric circles. The overall pattern is uniform, the structure is simple, and the distribution is regular, so it is widely used. However, the cathode comb bars 12 are distributed radially, and the circumferences of the concentric circles are not equal. The cathode comb bars 12 cannot correspond one to one, and as the radius of the circle increases, the radial angle margin continues to increase. The gap between the cathode comb bars 12 is approximately trapezoidal, and the shape and area of ​​the gap between the cathode comb bars 12 in each circle are different, and the chip area utilization rate is not high. On the other hand, the cathode comb bars 12 in different circles are staggered with each other, which has a greater impact on the lateral commutation of current during the switching process.

[0055] Another cathode comb arrangement of the power semiconductor device 20 is as follows: Figure 2a and Figure 2b As shown, the wafer 21 is divided into sixteen sector-shaped partitions with the center of the circle as the axis. The sector-shaped partitions overlap with the concentric ring areas to form multiple partitions. The cathode comb bars 22 in the partitions are arranged in a rectangular array, and the cathode comb bars 22 between the partitions are still arranged in a circular manner. The overall pattern is relatively regular, and the gates around the cathode comb bars 22 in the partitions are uniform. However, each partition has an irregular area at the junction of the rectangle and the arc, which reduces the utilization rate of the chip area, and the waste is greater as the radius of the pattern increases, which is not suitable for large-diameter fully controlled devices.

[0056] Another cathode comb arrangement of the power semiconductor device 30 is as follows: Figure 3a and Figure 3b As shown, the wafer 31 is divided into sixteen sector-shaped partitions with the center of the circle as the axis. The sector-shaped partitions overlap with the concentric ring areas to form multiple partitions. The cathode comb bars 32 in the partitions are arranged in an arc array, and the cathode comb bars 32 between each partition are still arranged in a circle. The cathode comb bars 32 in the partition are parallel to the radial symmetry axis of the partition, and in each partition, the arrangement spacing (perpendicular to the extension direction of the cathode comb bars 32) between the cathode comb bars 32 is the same (including the cathode comb bars 32 in the inner and outer circles), so that the gate area between the cathode comb bars 32 in the sector is completely consistent. A single radial comb bar of another type is inserted between the sectors according to the size of the area. A gate current shortcut channel (the area between the cathode comb bar 32 and the another radial comb bar) is formed between the sectors. As the chip develops to 6 inches, the gate current shortcut channel area between the sectors on the outer circle of the chip and the gate area between the cathode comb bars 32 in the sector are quite different, which makes the comb bar molding process more difficult and affects the device turn-off uniformity.

[0057] In the above three structures, the gate can be arranged in any of the following ways:

[0058] (1) Center gate: An area is designed at the center of the wafer to lead out the gate electrode. Generally, chips with smaller diameters use center gates.

[0059] (2) Ring gate type: A circular ring area is designed in the middle of the cathode pattern to lead out the gate electrode. Generally, larger diameter chips use ring gates.

[0060] (3) Edge gate type: A circular ring area is designed at the edge of the chip cathode pattern to lead out the gate electrode. It can be applied to chips with smaller diameters and has been rarely used before.

[0061] Embodiment 1

[0062] The embodiment of the present application provides a power semiconductor device 40 , including a wafer 41 and a plurality of first cathode comb bars 42 and a gate 45 disposed on a surface of the wafer 41 .

[0063] Among them, Figure 4 As shown, the surface of the wafer 41 is divided into a plurality of concentric circular ring areas 411 and a plurality of concentric fan-shaped areas 412 having the same center O. The plurality of concentric circular ring areas 411 and the plurality of concentric fan-shaped areas 412 overlap to define a plurality of graphic areas 413, that is, the area where the plurality of concentric circular ring areas 411 and the plurality of concentric fan-shaped areas 412 overlap is the basic graphic unit.

[0064] The number of the annular areas 411 may be between 1 and 18, and the number of the fan-shaped areas 412 may be between 30 and 144, wherein the number of the annular areas 411 is related to the diameter of the wafer 41 and the size of the first cathode comb bar 42. The radial widths of the annular areas 411 provided with the first cathode comb bar 42 are the same, and the fan-shaped areas 412 are equally divided, that is, the sizes of the multiple concentric fan-shaped areas 412 are the same.

[0065] A plurality of first cathode comb bars 42 are arranged at intervals in a plurality of graphic areas 413, such as Figure 5a and 5b Each first cathode comb bar 42 is surrounded by a gate region (not shown), and the gate region is led out through a gate 45 .

[0066] Each of the first cathode comb bars 42 disposed in the same graphic area 413 is parallel to the radial symmetry axis of the graphic area 413 and is arranged along the inner ring of the annular area 411 where it is located.

[0067] The arrangement of the first cathode bars 42 can be similar to an array arrangement, the first cathode bars 42 in different circles are less staggered, and the chip shutdown / opening delay time is shorter. Compared with other existing arrangements, the spacing between the first cathode bars 42 can be designed to be smaller, which is conducive to improving the cathode area utilization of the chip.

[0068] It can be understood that the radial spacing distance between each first cathode comb bar 42 arranged in the same graphic area 413 and the inner ring of the annular area 411 where it is located is the same.

[0069] Furthermore, the radial spacing distance between each first cathode comb bar 42 arranged in the same annular area 411 and the inner ring of the annular area 411 where the first cathode comb bar 42 is located is the same.

[0070] Furthermore, one end of each first cathode comb bar 42 disposed in the same annular region 411 close to the circle center O is in contact with the inner ring of the annular region 411 where it is located.

[0071] It can be understood that the line connecting the ends of the first cathode comb bars 42 arranged in the same annular area 411 that are close to or far from the center O is also a circle with the center O as the center.

[0072] The arrangement spacing of the first cathode comb bars 42 in each graphic area 413 first decreases and then increases along the direction of increasing radial distance from the gate 45. The arrangement spacing refers to the spacing between two adjacent first cathode comb bars 42 in the graphic area 413 in a direction perpendicular to their extension direction (radial symmetry axis).

[0073] It can be understood that at positions far away from and close to the gate 45 in radial direction, the arrangement spacing of the first cathode comb bars 42 in the graphic area 413 is larger, the arrangement density is smaller, and the arrangement is sparse. In the middle position, the arrangement spacing of the first cathode comb bars 42 in the graphic area 413 is smaller, the arrangement density is larger, and the arrangement is denser.

[0074] The spacing of the first cathode comb bars 42 in the graphic area 413 is designed to change with the radial distance between the cathode comb bars and the gate 45, which improves the dynamic switching uniformity of the cathode comb bars, is conducive to improving the shutdown capability of large-area chips, and is also conducive to improving the cathode area utilization rate of the chip and improving the chip current capacity. On the other hand, it can reduce the process difficulty, simplify the irradiation process, improve the chip production yield, and reduce the chip production cost.

[0075] In this embodiment, the gate 45 can be set in the circular ring area 411 at the edge, center or middle position of the wafer 41. It can be understood that the gate 45 is set in the circular ring area 411 of the outermost circle or the middle inner circle of the wafer 41, and the radial width of the gate 45 can be 4mm to 6mm.

[0076] That is to say, the arrangement spacing of the first cathode comb bars 42 in the circular areas 411 close to the edge and the center O of the multiple concentric circular areas 411 is larger, the arrangement density is smaller, and the arrangement is sparser.

[0077] Among them, in the 1st to 4th ring area 411 which is farthest from the gate 45 in radial direction (close to the center O), the arrangement spacing of the first cathode comb bars 42 in the graphic area 413 is 0.3mm to 0.8mm, and the arrangement is more sparse. The arrangement spacing between the first cathode comb bars 42 at other positions can be 0.15mm to 0.5mm.

[0078] The difference in arrangement spacing of the first cathode comb bars 42 in two adjacent circular areas 411 is 5μm to 60μm. The difference in arrangement spacing of the first cathode comb bars 42 in two adjacent circular areas 411 is very small, the misalignment degree of the first cathode comb bars 42 is very small, and the chip shutdown / turn-on delay time is short.

[0079] Furthermore, among the multiple first cathode comb bars 42 arranged in the same graphic area 413, the distance between any two adjacent first cathode comb bars 42 is the same, that is, the first cathode comb bars 42 in any graphic area 413 are arranged at equal intervals.

[0080] Furthermore, the arrangement intervals of the first cathode comb bars 42 in each graphic area 413 within the same annular area 411 are the same, further realizing the array arrangement of the first cathode comb bars 42 .

[0081] Furthermore, the power semiconductor device 40 further includes a second cathode comb bar 43. The second cathode comb bar 43 is arranged at the junction of any two adjacent graphic areas 413 in the annular area 411 (i.e., the junction of adjacent sector areas 412), and the extension line of the second cathode comb bar 43 intersects with the center O, i.e., the second cathode comb bar 43 extends in the radial direction.

[0082] The second cathode comb bars 43 are arranged along the inner ring of the annular area 411 where they are located. It can be understood that the radial spacing distance between the second cathode comb bars 43 and each first cathode comb bar 42 in the corresponding annular area 411 and the inner ring of the annular area 411 is the same.

[0083] The arrangement spacing (in a direction perpendicular to the extension direction of the cathode comb bars 42 ) of the first cathode comb bars 42 arranged in the same graphic area 413 is a first distance D1 .

[0084] The distance between the end of the second cathode comb bar 43 close to the center O and the adjacent first cathode comb bar 42 is the second distance D2. The second distance D2 can also be regarded as the width of the end of the channel region 44 close to the center O (ie, the minimum width).

[0085] The first distance D1 and the second distance D2 corresponding to the same graphic area 413 are equal.

[0086] That is to say, during the design, the inner ring of the graphic area 413 can be divided into arcs according to the preset number of first cathode comb bars 42 plus 1, with second cathode comb bars 43 arranged on both sides and first cathode comb bars 42 arranged at equal arc spacing in the middle.

[0087] This structural design greatly reduces the size difference between the gate area and the channel area 44 between the cathode combs 32, making them relatively uniform. On the one hand, it is beneficial to improve the cathode area utilization of the chip and improve the chip's current capacity. On the other hand, it reduces the process difficulty of cathode comb molding, improves the process yield and reduces the chip production cost. In addition, this structure facilitates the uniformity of the cathode comb molding process, improves the non-uniformity of the fast channel area, and solves the non-uniformity of the cathode comb molding process, such as local non-uniformity in the process of trenching depth, aluminum etching, etc., thereby ensuring the uniformity of the cathode comb shutoff and improving the chip's shutoff current capacity.

[0088] Furthermore, the number of the second cathode comb bars 43 at the boundary between any two adjacent graphic areas 413 is one.

[0089] A channel region 44 is formed between the second cathode comb bar 43 and the adjacent first cathode comb bar 42, that is, an angle region formed between the second cathode comb bar 43 and the adjacent first cathode comb bar 42, forming a fast channel for the gate 45. The channel region 44 is approximately trapezoidal, with a narrower end near the center O and a wider end away from the center O.

[0090] In the above structure, the width of the two channel areas 44 on both sides of the same graphic area 413 at one end close to the center O (i.e. the minimum width) and the width of the end away from the center O (i.e. the maximum width) are the same, and even the width of the channel area 44 in the same annular area 411 is the same, and the minimum width of the channel area 44 is the same as the arrangement spacing of the first cathode comb bar 42 in the corresponding graphic area 413. This structural design further reduces the size difference between the gate area size and the channel area 44 between the cathode comb bars 32, is more uniform, and is more conducive to the uniformity of the cathode comb bar forming process, improves the unevenness of the quick channel area, and solves the unevenness in the cathode comb bar forming process, such as local unevenness in the groove depth, aluminum etching and other processes, thereby ensuring the shutdown uniformity of the cathode comb bar, and then improving the shutdown current capability of the chip.

[0091] In the above structure, the width of the channel region 44 (the end close to the center O) can be controlled by the number of the first cathode comb bars 42 .

[0092] The structure of the first cathode comb bar 42 is as follows Figure 6 As shown, its length L is the dimension along its extension direction, and its width W is the dimension perpendicular to its extension direction. The length L of the first cathode comb bar 42 can be 1mm to 6mm, and the width W of the first cathode comb bar 42 can be 0.05mm to 0.4mm, that is, 50μm to 400μm.

[0093] Both ends of the first cathode comb bar 42 are semicircular arc-shaped, and the diameter d of the semicircle is equal to the width W.

[0094] The lengths of the first cathode comb bars 42 arranged in the same graphic area 413 are the same; and / or the widths of the first cathode comb bars 42 arranged in the same graphic area 413 are the same.

[0095] Furthermore, the first cathode comb bars 42 arranged in the same annular area 411 have the same length and width.

[0096] Furthermore, the length and / or width of each first cathode comb bar 42 gradually decreases along the direction of increasing radial distance from the gate 45. In this embodiment, the design of changing the size of the cathode comb bar can further improve the dynamic switching uniformity of the cathode comb bar, which is beneficial to improving the shutdown capability of large-area chips and can simplify the electron irradiation process.

[0097] It can be understood that at a position with a smaller radial distance from the gate 45 (closer to the outer circle in the edge gate structure), the length and / or width of each first cathode comb bar 42 is larger.

[0098] At a position with a greater radial distance from the gate 45 (inner circle in the edge gate structure), the length and / or width of each first cathode comb bar 42 is smaller.

[0099] Furthermore, the length and / or width of each first cathode comb bar 42 may decrease gradually in a step-like manner along the direction of increasing radial distance from the gate electrode 45 .

[0100] The length difference of the first cathode comb bars 42 in two adjacent annular areas 411 is 0 to 1 mm, and the width difference of the first cathode comb bars 42 in two adjacent annular areas 411 is 5 μm to 60 μm, ensuring the shutoff uniformity of the cathode comb bars on the chip.

[0101] The radial spacing between the first cathode comb bars 42 respectively located in two adjacent annular areas 411 is 0.1 to 0.5 mm.

[0102] In this embodiment, the power semiconductor device 40 may be a GCT chip. Correspondingly, the wafer is also provided with p+ emitter, n+ buffer layer, n base region and other required doping structures constituting the GCT chip.

[0103] In this embodiment, the arrangement of the cathode comb strips is suitable for GCT chips with large-diameter edge gate, center gate or intermediate ring gate structures, which is helpful to reduce the influence of parasitic stray inductance of the device.

[0104] The present application provides a power semiconductor device 40, including a wafer 41, and a plurality of first cathode comb bars 42 and a gate 45 arranged on the surface of the wafer 41; wherein the surface of the wafer 41 is divided into a plurality of concentric circular ring areas 411 and a plurality of concentric fan-shaped areas 412 having the same center O, the plurality of concentric circular ring areas 411 and the plurality of concentric fan-shaped areas 412 overlap to define a plurality of graphic areas 413, and the plurality of first cathode comb bars 42 are arranged at intervals in the plurality of graphic areas 413; each of the first cathode comb bars 42 arranged in the same graphic area 413 is parallel to the radial symmetry axis of the graphic area 413, and is arranged along the inner ring of the circular ring area 411 where it is located; the arrangement spacing of the first cathode comb bars 42 in each of the graphic areas 413 first decreases and then increases in the direction of increasing radial distance from the gate 45. The sector arc arrangement, the comb strips can form an approximate array arrangement, the cathode comb strips in different circles are less staggered, and the chip shutdown / opening delay time is shorter. The spacing of the cathode comb strips in the graphic area 413 is designed to change with the radial distance between the cathode comb strips and the gate 45, which improves the dynamic switching uniformity of the cathode comb strips, is conducive to improving the shutdown capability of large-area chips, and can simplify the irradiation process.

[0105] Embodiment 2

[0106] Based on the first embodiment, this embodiment provides a specific application example of a power semiconductor device.

[0107] The power semiconductor device in this embodiment is a 4-inch GCT chip. The first cathode comb 42 is arranged in 32 sectors (the central angle of each sector is 11.25°) and matched with the edge gate 45 design scheme. The design effect diagram is shown in FIG. Figure 7a , Figure 7b and Figure 7c As shown. A central isolation comb bar 46 is also provided at the center of the surface of the wafer. The radial width of the edge gate 45 is designed to be 4.23 mm, the radial spacing between the side of the edge gate 45 away from the circle and the cut circle edge of the wafer is 3.00 mm, and the radial spacing between the first cathode comb bars 42 located in two adjacent annular areas is 0.28 mm. The various parameters of the cathode comb bar arrangement design are shown in Table 1.

[0108] Table 1 4-inch GCT32 sector cathode strip arrangement design parameters

[0109]

[0110] That is to say, in this embodiment, in the same graphic area, the arrangement spacing of the first cathode comb bars 42 is the same as the channel area width (the channel area width refers to the minimum width, that is, the width of the end close to the center of the circle). And the arrangement spacing of the first cathode comb bars 42 first decreases and then increases in the direction of increasing radial distance from the gate.

[0111] The arrangement spacing of the first cathode comb bars 42 in the annular areas near the inner and outer circles is relatively large and sparse, while the arrangement spacing of the first cathode comb bars 42 in the annular area near the middle position is relatively small and dense.

[0112] The length of each first cathode comb bar 42 decreases in a step-like manner along the direction of increasing radial distance from the gate electrode 45 .

[0113] The width of each first cathode comb bar 42 gradually decreases along the direction of increasing radial distance from the gate electrode 45 .

[0114] Embodiment 3

[0115] Based on the first embodiment, this embodiment provides another specific application example of a power semiconductor device.

[0116] In this embodiment, the power semiconductor device is a 6-inch RC-GCT (reverse-conducting gate-commutated thyristor) chip. The first cathode comb 42 is arranged in 64 sectors (the central angle of each sector is 5.625°) and matched with the edge gate 45 design scheme. The design effect diagram is shown in FIG. Figure 8a , Figure 8b and Figure 8c As shown. A fast recovery diode FRD with a radius of 40 mm is also arranged at the center of the surface of the wafer. The radial width of the edge gate 45 is designed to be 4.6 mm, and the radial spacing of the first cathode comb bars 42 located in two adjacent annular areas is 0.28 mm. The various parameters of the cathode comb bar arrangement design are shown in Table 2.

[0117] Table 2 Design parameters of cathode strip arrangement for 6-inch RC_GCT 64 sectors

[0118]

[0119] That is to say, in this embodiment, in the same graphic area, the arrangement spacing of the first cathode comb bars 42 is approximately the same as the channel area width (the channel area width refers to the minimum width, that is, the width of the end close to the center of the circle), and the gate fast channel is relatively uniform. And the arrangement spacing of the first cathode comb bars 42, along the direction of increasing radial distance from the gate 45, approximately shows a trend of first decreasing and then increasing.

[0120] The arrangement spacing of the first cathode comb bars 42 in the annular areas near the inner and outer circles is relatively large and sparse, while the arrangement spacing of the first cathode comb bars 42 in the annular area near the middle position (No. 3 circular area) is relatively small and dense.

[0121] The length of each first cathode comb bar 42 gradually decreases along the direction of increasing radial distance from the gate electrode 45 .

[0122] The width of each first cathode comb bar 42 gradually decreases along the direction of increasing radial distance from the gate electrode 45 .

[0123] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. Although the implementation methods disclosed in the present application are as above, the content is only an implementation method adopted to facilitate the understanding of the present application and is not intended to limit the present application. Any technician in the technical field to which the present application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application, but the protection scope of the present application shall still be subject to the scope defined by the attached claims.

Claims

1. A power semiconductor device, characterized in that: It comprises a wafer, and a plurality of first cathode comb bars and gate electrodes arranged on the surface of the wafer; The wafer surface is divided into a plurality of concentric circular ring areas and a plurality of concentric fan-shaped areas having the same center, the plurality of concentric circular ring areas and the plurality of concentric fan-shaped areas overlap to define a plurality of graphic areas, and the plurality of first cathode comb bars are arranged at intervals in the plurality of graphic areas; Each of the first cathode comb bars disposed in the same graphic area is parallel to the radial symmetry axis of the graphic area, and is arranged along the inner ring of the annular area where it is located; The arrangement spacing of the first cathode comb bars in each of the graphic areas first decreases and then increases in the direction of increasing radial distance from the gate.

2. The power semiconductor device according to claim 1, characterized in that: The length and / or width of each of the first cathode comb bars gradually decreases along the direction of increasing radial distance from the gate.

3. The power semiconductor device according to claim 1, characterized in that: Among the plurality of the first cathode comb bars arranged in the same graphic area, the distance between any two adjacent first cathode comb bars is the same.

4. The power semiconductor device according to claim 3, characterized in that: Also includes: A second cathode comb bar disposed at the junction of any two adjacent graphic areas in the annular area; Wherein, the extension line of the second cathode comb bar intersects with the center of the circle.

5. The power semiconductor device according to claim 4, characterized in that: The second cathode comb bars are arranged along the inner ring of the annular area where they are located.

6. The power semiconductor device according to claim 5, characterized in that: The arrangement spacing of the first cathode comb bars arranged in the same graphic area is a first distance; The distance between one end of the second cathode comb bar close to the center of the circle and the adjacent first cathode comb bar is a second distance; The first distance and the second distance corresponding to the same graphic area are equal.

7. The power semiconductor device according to claim 4, characterized in that: A channel region is formed between the second cathode comb bar and the adjacent first cathode comb bar.

8. The power semiconductor device according to claim 4, characterized in that: The number of the second cathode comb bars at the boundary between any two adjacent graphic areas is 1.

9. The power semiconductor device according to claim 1, characterized in that: The gate is arranged in the annular area at the edge, center or middle position of the wafer.

10. The power semiconductor device according to claim 1, characterized in that: The radial spacing distances between each of the first cathode comb bars arranged in the same graphic area and the inner ring of the annular area where it is located are the same.

11. The power semiconductor device according to claim 1, characterized in that: The lengths of the first cathode comb bars arranged in the same graphic area are the same; and / or, The widths of the first cathode comb bars arranged in the same graphic area are the same.

12. The power semiconductor device according to claim 1, characterized in that: The multiple concentric sector-shaped areas have the same size.

13. The power semiconductor device according to claim 1, characterized in that: The radial widths of the annular areas where the first cathode comb bars are arranged are the same.

14. The power semiconductor device according to claim 1, characterized in that: The two ends of the cathode comb bar are in semicircular arc shape.

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