Cell structure of power semiconductor device and power semiconductor device

Abstract

The present application provides a cell structure of a power semiconductor device and a power semiconductor device, wherein the cell structure includes a substrate, wherein the substrate includes a first surface and a second surface arranged opposite to each other; a first base region of a first conductivity type located in the substrate; wherein the first base region is provided with a first boss extending toward the second surface at the center of the cell structure; an anode region located between the first base region and the second surface; wherein a concave portion is formed at a position corresponding to the first boss on one side of the anode region close to the first base region. The junction depth of the anode region at the concave portion is smaller than that of other regions, which can reduce the reverse resistance anode emission efficiency at the location, and form a carrier rapid extraction channel at the location when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a cell structure of a power semiconductor device and a power semiconductor device. Background Art

[0002] With the development of flexible direct current grid technology, a reverse-resistance fully-controlled power semiconductor device is needed in core devices such as current-type converter valves and DC circuit breakers. The device is required to have the characteristics of low device loss, high shutdown capability, and strong reverse recovery capability. Among them, the reverse-resistance gate-commutated thyristors (GCT) are a current-controlled, high-power semiconductor device in the field of power electronics. The turn-on characteristics are like thyristors, with low conduction losses, and the turn-off characteristics are like transistors. Therefore, it has the characteristics of low conduction losses, large surge currents, fast turn-off speeds, and large power capacity.

[0003] Among them, the main structure of the reverse resistance GCT chip 10 in the longitudinal direction is as follows Figure 1 As shown, it includes an anode 13, a P+ anode region 12, an N-base region 11, a P base region 14, a P+ base region 15, an N+ emitter region 16 (also called a cathode comb), a cathode 17 and a gate 18. It is a PNPN four-layer structure. There are three PN junctions inside the device, from the anode 13 to the cathode 17, which are J1 junction (anode transparent junction), J2 junction (blocking voltage main junction) and J3 junction (gate cathode junction). Figure 2 As shown, from the lateral direction of the GCT chip, the N+ emitter region 16 (cathode comb, i.e. Figure 2 The stripe pattern in the figure) is evenly arranged in a wafer using sector arcs or circles, and is usually arranged in a concentric radial state when viewed horizontally.

[0004] For conventional reverse-resistance GCT, on the one hand, due to the large concentration gradient and deep junction depth of the P+ anode region, it is difficult for process carriers to pass through during the shutdown and reverse recovery process, resulting in high shutdown losses, which is not conducive to the frequency application of the device. On the other hand, as the diameter of the reverse-resistance GCT chip increases, its safe operating area does not increase significantly with the increase in its area. Since current crowding is easily caused in the area far away from the gate contact, the improvement of the chip's safe operating area is limited.

[0005] In order to reduce the turn-off loss of the reverse resistance GCT device, the commonly used method is irradiation technology, but it is easy to cause high on-state loss of the device and easily reduce the blocking characteristics of the device. Summary of the invention

[0006] In response to the above problems, the present application provides a cellular structure of a power semiconductor device and a power semiconductor device, which solves the technical problems of high turn-off loss and poor turn-off capability in power semiconductor devices such as reverse resistance GCT in the prior art.

[0007] In a first aspect, the present application provides a cell structure of a power semiconductor device, comprising:

[0008] A substrate, wherein the substrate comprises a first surface and a second surface arranged opposite to each other;

[0009] A first base region of the first conductivity type located in the substrate; wherein the first base region is provided with a first boss extending toward the second surface at the center of the cell structure;

[0010] An anode region is located between the first base region and the second surface; wherein a concave portion is formed at a position corresponding to the first boss on a side of the anode region close to the first base region, and a side of the anode region away from the first base region is flush with the second surface.

[0011] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, the anode region includes a first sub-anode region of a second conductivity type and a second sub-anode region of a second conductivity type stacked in sequence from the first base region to the second surface;

[0012] The ion doping concentration of the first sub-anode region is less than or equal to the ion doping concentration of the second sub-anode region.

[0013] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, a second boss extending toward the second surface is formed at a position corresponding to the first boss on a side of the first sub-anode region away from the first base region;

[0014] The first sub-anode region includes a first portion disposed around the first boss.

[0015] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, the second sub-anode region includes a third portion disposed around the second boss, and a fourth portion located between the top of the second boss and the second surface;

[0016] The junction depth of the fourth portion is smaller than the junction depth of the third portion.

[0017] According to an embodiment of the present application, optionally, in the cell structure of the above-mentioned power semiconductor device, the ion doping concentration of the fourth part is less than or equal to the ion doping concentration of the third part.

[0018] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, the top of the second boss is located on a side of the top of the first boss close to the second surface;

[0019] The first sub-anode region further includes a second portion located between the top of the first boss and the top of the second boss;

[0020] The junction depth of the second portion is smaller than the junction depth of the first portion, and the first portion is in contact with the second portion.

[0021] According to an embodiment of the present application, optionally, in the cell structure of the above-mentioned power semiconductor device, the ion doping concentration of the second part is less than or equal to the ion doping concentration of the first part.

[0022] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, the top of the first boss is flush with the top of the second boss.

[0023] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, the top of the first boss is flush with the second surface.

[0024] According to an embodiment of the present application, optionally, in the cell structure of the power semiconductor device, a first conductive type short-circuit region is provided on the top of the first boss at a side away from the second surface;

[0025] Wherein, the ion doping concentration of the short-circuit region is greater than the ion doping concentration of the first base region.

[0026] According to an embodiment of the present application, optionally, the cell structure of the power semiconductor device further includes:

[0027] A second conductive type second base region, a second conductive type third base region, and a first conductive type emitter region are located between the first base region and the first surface and are sequentially stacked in a direction from the first base region to the first surface;

[0028] The orthographic projection of the emission area on the second surface at least covers a portion of the orthographic projection of the recess on the second surface.

[0029] According to an embodiment of the present application, optionally, in the cell structure of the above-mentioned power semiconductor device, the ion doping concentration of the third base region is greater than the ion doping concentration of the second base region, and the ion doping concentration of the emitter region is greater than the ion doping concentration of the first base region.

[0030] According to an embodiment of the present application, optionally, the cell structure of the power semiconductor device further includes:

[0031] a cathode located on the first surface and electrically connected to the emitting region;

[0032] a gate electrode located on the first surface and electrically connected to the third base region;

[0033] An anode is located on the second surface and is electrically connected to the anode region.

[0034] In a second aspect, the present application provides a power semiconductor device, comprising a plurality of cellular structures of the power semiconductor device as described in any one of the first aspects, and a gate lead electrode arranged on a first surface of at least one of the cellular structures.

[0035] According to an embodiment of the present application, optionally, in the above-mentioned power semiconductor device, the width of the fourth portion of the anode region in each of the cellular structures gradually increases in a direction away from the gate lead-out electrode.

[0036] By adopting the above technical solution, at least the following technical effects can be achieved:

[0037] (1) A first boss extending toward the second surface is provided at the center of the cell structure in the first base region, so that a concave portion is formed at a position corresponding to the first boss portion on the side of the anode region close to the first base region. The junction depth of the anode region at the concave portion is smaller than that of other regions, which can reduce the reverse resistance anode emission efficiency at the location and form a carrier rapid extraction channel at the location when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss;

[0038] (2) The formation of the concave portion in the anode region, and the reverse blocking rated voltage of the device can be adjusted by adjusting the width of the concave portion;

[0039] (3) By designing the width of the low-emission-efficiency anode region, the uniformity of chip shutdown can be adjusted, thereby improving the shutdown capability of large-area power devices;

[0040] (4) The low emission efficiency anode area structure design is conducive to reducing the radiation dose and continuously maintaining the low on-state loss device characteristics of the reverse resistance type device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0042] Figure 1 It is a schematic diagram of the cross-sectional structure of an existing reverse resistance type GCT chip;

[0043] Figure 2It is a front top view schematic diagram of an existing reverse resistance type GCT chip;

[0044] Figure 3 is a schematic cross-sectional structure diagram of a cellular structure of a power semiconductor device shown in an exemplary embodiment of the present application;

[0045] Figure 4 is a schematic cross-sectional structure diagram of a cell structure of another power semiconductor device shown in an exemplary embodiment of the present application;

[0046] Figure 5 is a schematic cross-sectional structure diagram of a cell structure of another power semiconductor device shown in an exemplary embodiment of the present application;

[0047] Figure 6 is a schematic cross-sectional structure diagram of a cell structure of another power semiconductor device shown in an exemplary embodiment of the present application;

[0048] Figure 7a is a schematic diagram of a front top view of a power semiconductor device shown in an exemplary embodiment of the present application;

[0049] Figure 7b yes Figure 7a A magnified view of a quarter of a medium-power semiconductor device;

[0050] Figure 8 yes Figure 7a Schematic diagram of the cross-sectional structure of a medium power semiconductor device;

[0051] Fig. 9 is a partial front plan view of another power semiconductor device shown in an exemplary embodiment of the present application;

[0052] Fig.10 is a schematic cross-sectional structure diagram of a cell structure of another power semiconductor device shown in an exemplary embodiment of the present application;

[0053] Fig.11 yes Fig.10 A schematic diagram of the cross-sectional structure of a power semiconductor device composed of a cellular structure of a medium-power semiconductor device;

[0054] Fig.12 yes Fig.11 Schematic diagram of the width design of the transparent anode region of a medium power semiconductor device;

[0055] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale;

[0056] The accompanying drawings are marked as follows:

[0057] 10-cell structure of power semiconductor device; 11-N-base region; 12-P+ anode region; 13-anode; 14-P base region; 15-P+ third base region; 16-N+ emitter region (also called cathode comb); 17-cathode; 18-gate; J1-anode transparent junction; J2-blocking voltage main junction; J3-gate cathode junction;

[0058] 20-cell structure of power semiconductor device; 20A-first surface; 20B-second surface; 21-first base region; 21a-first boss; W1-width of first boss; 22-anode region; 221-first sub-anode region; 221a-second boss; 2211-first part; 2212-second part; 222-second sub-anode region; 2221-third part; 2222-fourth part; W2-width of "transparent" anode region; 23-anode; 24-second base region; 25-third base region; 26-emitter region (also called cathode comb); 27-cathode; 28-gate;

[0059] 30-cell structure of power semiconductor device; 30A-first surface; 30B-second surface; 31-first base region; 31a-first boss; W1-width of first boss; 32-anode region; 321-first sub-anode region; 321a-second boss; 3211-first part; 322-second sub-anode region; 3221-third part; 3222-fourth part; W2-width of "transparent" anode region; 33-anode; 34-second base region; 35-third base region; 36-emitter region (also called cathode comb); 37-cathode; 38-gate;

[0060] 40-cell structure of power semiconductor device; 40A-first surface; 40B-second surface; 41-first base region; 41a-first boss; 411-short-circuit region; W1-width of first boss; 42-anode region; 421-first sub-anode region; 421a-second boss; 4211-first part; 422-second sub-anode region; 4221-third part; 4222-fourth part; W2-width of "transparent" anode region; 43-anode; 44-second base region; 45-third base region; 46-emitter region (also called cathode comb); 47-cathode; 48-gate;

[0061] 50-cell structure of power semiconductor device; 50A-first surface; 50B-second surface; 51-first base region; 51a-first boss; 511-short-circuit region; W1-width of first boss; 52-anode region; 521-first sub-anode region; 521a-second boss; 5211-first part; 522-second sub-anode region; 5221-third part; 5222-fourth part; W2-width of "transparent" anode region; 53-anode; 54-second base region; 55-third base region; 56-emitter region (also called cathode comb); 57-cathode; 58-gate;

[0062] 60- Gate lead electrode. DETAILED DESCRIPTION

[0063] The following will describe the implementation methods of the present application in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0064] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0065] It will be appreciated that spatially relative terms, such as "above", "above", "below", "under", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below other elements" would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] Embodiments of the present application are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0068] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0069] Embodiment 1

[0070] like Figure 3 As shown, an embodiment of the present application provides a cell structure 20 of a power semiconductor device, including a substrate (not marked in the figure), a first base region 21, an anode region 22, a second base region 24, a third base region 25, an emitter region 26, a cathode 27, an anode 23 and a gate 28.

[0071] Exemplarily, the substrate is a single crystal silicon substrate, and the substrate includes a first surface 20A and a second surface 20B arranged opposite to each other, wherein the first surface 20A is provided with side grooves (not marked in the figure) downwardly on both sides of the cell structure 20. The formation of the side grooves on the first surface 20A forms a certain height difference between the gate 28 and the cathode 27, shortening the longitudinal commutation path of the power semiconductor device, which is conducive to improving the turn-off speed and turn-off capability.

[0072] The first base region 21 is a doped region of the first conductivity type and is located in the substrate. In this embodiment, the first base region 21 is spaced a certain distance from both the first surface 20A and the second surface 20B. The ion doping concentration and junction depth of the first base region 21 are mainly selected based on the blocking voltage, on-state voltage drop and other parameter requirements of the power device.

[0073] In this embodiment, the first base region 21 is provided with a first protrusion 21 a at the center of the cell structure 20 and extending toward the second surface 20B.

[0074] The anode region 22 is a doped region of the second conductivity type, and is located between the first base region 21 and the second surface 20B. The side of the anode region 22 close to the first base region 21 contacts the side of the first base region 21 close to the second surface 20B. The side of the anode region 22 close to the first base region 21 forms a recess (not marked in the figure) at a position corresponding to the first protrusion 21a, which is used to match the first protrusion 21a. The side of the anode region 22 away from the first base region 21 is flush with the second surface 20B.

[0075] In this embodiment, the junction depth of the anode region 22 at the above-mentioned concave portion is smaller than that of other regions, which can not only reduce the emission efficiency of the reverse resistance anode 23 at this position, but also form a carrier rapid extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. In addition, the width of the concave portion can be adjusted, and the reverse blocking rated voltage of the device can be adjusted. The low emission efficiency anode region 22 structural design is conducive to reducing the irradiation dose and continuously maintaining the low on-state loss device characteristics of the reverse resistance type device.

[0076] The width W1 of the concave portion is determined by the rated voltage design value of the anode transparent junction (the PN junction between the first base region 21 and the anode region 22). By adjusting the width W1 of the concave portion, the reverse blocking rated voltage can be adjusted. Usually, the design width of the width W1 is 10 μm to 80 μm, and does not affect the design voltage of the anode transparent junction in the longitudinal direction.

[0077] The anode region 22 includes a second conductivity type first sub-anode region 221 and a second conductivity type second sub-anode region 222 which are sequentially stacked from the first base region 21 to the second surface 20B.

[0078] The ion doping concentration of the first sub-anode region 221 is less than or equal to the ion doping concentration of the second sub-anode region 222. The change in the concentration gradient of the anode region 22 can reduce the turn-off loss of the reverse resistance device and improve the turn-off capability, and can also maintain a high reverse recovery -di / dt capability and high current capacity.

[0079] In this embodiment, a second protrusion 221a extending toward the second surface 20B is formed at a position corresponding to the first protrusion 21a on one side of the first sub-anode region 221 away from the first base region 21. A predetermined distance is provided between the top of the second protrusion 221a and the second surface 20B.

[0080] That is to say, the formation of the second boss 221a forms another recess (not marked in the figure, hereinafter referred to as the second recess) at a position corresponding to the second boss 221a on the side of the second sub-anode region 222 close to the first sub-anode region 221, which is used to match the second boss 221a. The formation of the second recess makes the junction depth of the second sub-anode region 222 at the corresponding position smaller than other regions, and much smaller than the overall junction depth of the anode region 22. When the junction depth of the second sub-anode region 222 at this position is smaller than a certain threshold, carriers can easily pass through, and this part of the anode region 22 is similar to a "transparent" anode region, further reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. It can further achieve the adjustment of the reverse blocking rated voltage of the device and the uniformity of the turn-off, and further improve the turn-off capability of large-area power devices.

[0081] In this embodiment, the top of the second boss 221a is located on the side of the top of the first boss 21a close to the second surface 20B, that is, the top of the second boss 221a is spaced a preset distance from the top of the first boss 21a.

[0082] Correspondingly, the first sub-anode region 221 includes a first portion 2211 disposed around the first boss 21 a , and a second portion 2212 located between the top of the first boss 21 a and the top of the second boss 221 a .

[0083] The junction depth of the second portion 2212 is smaller than the junction depth of the first portion 2211 , and the first portion 2211 and the second portion 2212 are in contact with each other.

[0084] The first portion 2211 and the second portion 2212 are in contact with each other, so as to form a connected first sub-anode region 221 .

[0085] The junction depth of the second portion 2212 is smaller than that of the first portion 2211, so that the emission efficiency of the second portion 2212 is smaller than that of the first portion 2211, further realizing the formation of a low emission efficiency region in the anode region 22. The junction depth of the first portion 2211 is usually determined by the chip blocking voltage.

[0086] Furthermore, the ion doping concentration of the second portion 2212 is less than or equal to the ion doping concentration of the first portion 2211 , thereby further reducing the emission efficiency of the second portion 2212 .

[0087] The second sub-anode region 222 includes a third portion 2221 disposed around the second protrusion 221 a , and a fourth portion 2222 located between the top of the second protrusion 221 a and the second surface 20B.

[0088] Among them, the junction depth of the fourth part 2222 is smaller than the junction depth of the third part 2221 , so the emission efficiency of the fourth part 2222 is lower than the emission efficiency of the third part 2221 .

[0089] Among them, the fourth part 2222 is the above-mentioned "transparent" anode area, through which carriers can easily pass, reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. By designing the width W2 of the "transparent" anode area, the uniformity of chip turn-off can be adjusted, and the turn-off capability of large-area switch devices can be improved.

[0090] Furthermore, the ion doping concentration of the fourth portion 2222 is less than or equal to the ion doping concentration of the third portion 2221 , thereby further reducing the emission efficiency of the fourth portion 2222 and further realizing the formation of a “transparent” anode region.

[0091] In this embodiment, the second conductive type second base region 24, the second conductive type third base region 25 and the first conductive type emitter region 26 are located between the first base region 21 and the first surface 20A and are stacked in sequence from the first base region 21 to the first surface 20A.

[0092] The orthographic projection of the emission area 26 on the second surface 20B at least covers a portion of the orthographic projection of the recess on the second surface 20B.

[0093] The emission region 26 is also called the cathode comb bar, that is, the recess of the anode region 22 is arranged at the corresponding position of the cathode comb bar, so that the area with low emission efficiency in the anode region 22 is arranged corresponding to the cathode comb bar, which can further form a rapid carrier extraction channel when the chip is turned off, further reducing the chip shutdown tail time and reverse recovery time, and further reducing the shutdown loss.

[0094] An anode transparent junction J1 is formed between the anode region 22 and the first base region 21 , a blocking voltage main junction J2 is formed between the first base region 21 and the second base region 24 , and a gate cathode junction J3 is formed between the third base region 25 and the emitter region 26 .

[0095] Furthermore, the ion doping concentration of the third base region 25 is greater than the ion doping concentration of the second base region 24 , and the ion doping concentration of the emitter region 26 is greater than the ion doping concentration of the first base region 21 .

[0096] The emitter region 26 covers a portion of the upper surface of the third base region 25. The upper surface of the emitter region 26 and the upper surface of the third base region 25 not covered by the emitter region 26 are both flush with the first surface 20A.

[0097] The cathode 27 is located on the first surface 20A and is electrically connected to the emission region 26 for leading the emission region 26 out.

[0098] The gate 28 is located on the first surface 20A and is electrically connected to the third base region 25 for leading out the third base region 25 .

[0099] The anode 23 is located on the second surface 20B and is electrically connected to the anode region 22 for leading out the anode region 22 .

[0100] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type. Specifically, a reasonable selection can be made according to the type of device to be prepared in actual need.

[0101] The present application provides a cell structure 20 of a power semiconductor device, wherein a first boss 21a extending toward a second surface 20B is arranged at a center position of a first base region 21 in the cell structure 20, so that a recess is formed on a side of an anode region 22 close to the first base region 21 at a position corresponding to the first boss 21a, and the junction depth of the anode region 22 at the recess is deeper than that of other regions, which can reduce the emission efficiency of the reverse resistance anode 23 at the recess and form a channel for rapid carrier extraction when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss.

[0102] Embodiment 2

[0103] like Figure 4 As shown, an embodiment of the present application provides a cell structure 30 of a power semiconductor device, including a substrate (not marked in the figure), a first base region 31, an anode region 32, a second base region 34, a third base region 35, an emitter region 36, a cathode 37, an anode 33 and a gate 38.

[0104] Exemplarily, the substrate is a single crystal silicon substrate, and the substrate includes a first surface 30A and a second surface 30B arranged opposite to each other, wherein the first surface 30A is provided with side grooves (not marked in the figure) downwardly on both sides of the cell structure 30. The formation of the side grooves on the first surface 30A forms a certain height difference between the gate 38 and the cathode 37, shortening the longitudinal commutation path of the power semiconductor device, which is beneficial to the turn-off speed and turn-off capability.

[0105] The first base region 31 is a doped region of the first conductivity type and is located in the substrate. In this embodiment, the first base region 31 is spaced a certain distance from both the first surface 30A and the second surface 30B. The ion doping concentration and junction depth of the first base region 31 are mainly selected based on the blocking voltage, on-state voltage drop and other parameter requirements of the power device.

[0106] In this embodiment, the first base region 31 is provided with a first protrusion 31 a at the center of the cell structure 30 and extending toward the second surface 30B.

[0107] The anode region 32 is a doped region of the second conductivity type, and is located between the first base region 31 and the second surface 30B. The side of the anode region 32 close to the first base region 31 contacts the side of the first base region 31 close to the second surface 30B. The side of the anode region 32 close to the first base region 31 forms a recess (not marked in the figure) at a position corresponding to the first protrusion 31a, which is used to match the first protrusion 31a. The side of the anode region 32 away from the first base region 31 is flush with the second surface 30B.

[0108] In this embodiment, the junction depth of the anode region 32 at the above-mentioned concave portion is smaller than that of other regions, which can not only reduce the emission efficiency of the reverse resistance anode 33 at this position, but also form a rapid carrier extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. In addition, the width of the concave portion can be adjusted, and the reverse blocking rated voltage of the device can be adjusted. The low emission efficiency anode region 32 structural design is conducive to reducing the irradiation dose and continuously maintaining the low on-state loss device characteristics of the reverse resistance type device.

[0109] The width W1 of the concave portion is determined by the rated voltage design value of the anode transparent junction J1 (the PN junction between the first base region 31 and the anode region 32). By adjusting the width W1 of the concave portion, the reverse blocking rated voltage can be adjusted. Usually, the design width of the width W1 is 10 μm to 80 μm, and does not affect the design voltage of the anode transparent junction J1 in the longitudinal direction.

[0110] The anode region 32 includes a second conductivity type first sub-anode region 321 and a second conductivity type second sub-anode region 322 which are sequentially stacked from the first base region 31 toward the second surface 30B.

[0111] The ion doping concentration of the first sub-anode region 321 is less than or equal to the ion doping concentration of the second sub-anode region 322. The change in the concentration gradient of the anode region 32 can reduce the turn-off loss of the reverse resistance device and improve the turn-off capability, while maintaining a high reverse recovery -di / dt capability and high current capacity.

[0112] In this embodiment, a second protrusion 321a extending toward the second surface 30B is formed at a position corresponding to the first protrusion 31a on one side of the first sub-anode region 321 away from the first base region 31. A predetermined distance is provided between the top of the second protrusion 321a and the second surface 30B.

[0113] That is to say, the formation of the second boss 321a forms another recess (not marked in the figure, hereinafter referred to as the second recess) at a position corresponding to the second boss 321a on the side of the second sub-anode region 322 close to the first sub-anode region 321, which is used to match the second boss 321a. The formation of the second recess makes the junction depth of the second sub-anode region 322 at the corresponding position smaller than other regions, and much smaller than the overall junction depth of the anode region 32. When the junction depth of the second sub-anode region 322 at this position is smaller than a certain threshold, carriers can easily pass through, and this part of the anode region 32 is similar to a "transparent" anode region, further reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. It can further achieve the adjustment of the reverse blocking rated voltage of the device and the uniformity of the turn-off, and further improve the turn-off capability of large-area power devices.

[0114] In this embodiment, the top of the first boss 31a is flush with the top of the second boss 321a. At this time, the top of the first boss 31a and the top of the second boss 321a are at the same distance from the second surface 30B.

[0115] Correspondingly, the first sub-anode region 321 includes a first portion 3211 disposed around the first protrusion 31a, that is, the second protrusion 321a is disposed around the first protrusion 31a. The junction depth of the first portion 3211 is usually determined by the chip blocking voltage.

[0116] That is to say, in this embodiment, there is no portion with a lower junction depth, that is, no portion with a lower emission efficiency, at the position corresponding to the first boss 31a in the first sub-anode region 321, but the second boss 321a can still be formed through the first part 3211, and a "transparent" anode region can still be formed in the second sub-anode region 322.

[0117] Furthermore, the top of the first boss 31a can continue to extend toward the second surface 30B (not shown in the figure), and even extend to be flush with the second surface 30B. At this time, since the top of the second boss 321a is still separated from the second surface 30B by a certain distance, the second boss 321a can still form a "transparent" anode area in the second sub-anode area 322. Moreover, the downwardly extending portion of the first boss 31a can further realize the formation of a low emission efficiency area in the anode area 32.

[0118] The second sub-anode region 322 includes a third portion 3221 disposed around the second protrusion 321 a , and a fourth portion 3222 located between the top of the second protrusion 321 a and the second surface 30B.

[0119] Among them, the junction depth of the fourth part 3222 is smaller than the junction depth of the third part 3221 , so the emission efficiency of the fourth part 3222 is lower than the emission efficiency of the third part 3221 .

[0120] Among them, the fourth part 3222 is the above-mentioned "transparent" anode area, through which carriers can easily pass, reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. By designing the width W2 of the "transparent" anode area, the uniformity of chip turn-off can be adjusted, and the turn-off capability of large-area switch devices can be improved.

[0121] Furthermore, the ion doping concentration of the fourth portion 3222 is less than or equal to the ion doping concentration of the third portion 3221 , thereby further reducing the emission efficiency of the fourth portion 3222 and further realizing the formation of a “transparent” anode region.

[0122] In this embodiment, the second conductive type second base region 34, the second conductive type third base region 35 and the first conductive type emitter region 36 are located between the first base region 31 and the first surface 30A and are stacked in sequence from the first base region 31 to the first surface 30A.

[0123] The orthographic projection of the emission area 36 on the second surface 30B at least covers a portion of the orthographic projection of the recess on the second surface 30B.

[0124] The emission region 36 is also called the cathode comb bar, that is, the recess of the anode region 32 is arranged at the corresponding position of the cathode comb bar, so that the area with low emission efficiency in the anode region 32 is arranged corresponding to the cathode comb bar, which can further form a rapid carrier extraction channel at this location when the chip is turned off, further reducing the chip shutdown tail time and reverse recovery time, and further reducing the shutdown loss.

[0125] An anode transparent junction J1 is formed between the anode region 32 and the first base region 31 , a blocking voltage main junction J2 is formed between the first base region 31 and the second base region 34 , and a gate cathode junction J3 is formed between the third base region 35 and the emitter region 36 .

[0126] Furthermore, the ion doping concentration of the third base region 35 is greater than the ion doping concentration of the second base region 34 , and the ion doping concentration of the emitter region 36 is greater than the ion doping concentration of the first base region 31 .

[0127] The emitter region 36 covers a portion of the upper surface of the third base region 35. The upper surface of the emitter region 36 and the upper surface of the third base region 35 not covered by the emitter region 36 are both flush with the first surface 30A.

[0128] The cathode 37 is located on the first surface 30A and is electrically connected to the emission region 36 for leading the emission region 36 out.

[0129] The gate 38 is located on the first surface 30A and is electrically connected to the third base region 35 for leading out the third base region 35 .

[0130] The anode 33 is located on the second surface 30B and is electrically connected to the anode region 32 for leading out the anode region 32 .

[0131] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type. Specifically, a reasonable selection can be made according to the type of device to be prepared in actual need.

[0132] The present application provides a cell structure 30 of a power semiconductor device, wherein a first boss 31a extending toward a second surface 30B is provided at a center position of the cell structure 30 in a first base region 31, so that a recess is formed at a position corresponding to the first boss 31a on a side of the anode region 32 close to the first base region 31, and the junction depth of the anode region 32 at the recess is smaller than that of other regions, which can reduce the emission efficiency of the reverse resistance anode 33 at the recess and form a rapid carrier extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss.

[0133] Embodiment 3

[0134] like Figure 5 As shown, an embodiment of the present application provides a cell structure 40 of a power semiconductor device, including a substrate (not marked in the figure), a first base region 41, an anode region 42, a second base region 44, a third base region 45, an emitter region 46, a cathode 47, an anode 43 and a gate 48.

[0135] Exemplarily, the substrate is a single crystal silicon substrate, and the substrate includes a first surface 40A and a second surface 40B arranged opposite to each other, wherein the first surface 40A is provided with side grooves (not marked in the figure) downwardly on both sides of the cell structure 40. The formation of the side grooves on the first surface 40A forms a certain height difference between the gate 48 and the cathode 47, shortening the longitudinal commutation path of the power semiconductor device, which is beneficial to the turn-off speed and turn-off capability.

[0136] The first base region 41 is a doped region of the first conductivity type and is located in the substrate. In this embodiment, the first base region 41 is spaced a certain distance from both the first surface 40A and the second surface 40B. The ion doping concentration and junction depth of the first base region 41 are mainly selected based on the blocking voltage, on-state voltage drop and other parameter requirements of the power device.

[0137] In this embodiment, the first base region 41 is provided with a first protrusion 41 a at the center of the cell structure 40 and extending toward the second surface 40B.

[0138] The anode region 42 is a doped region of the second conductivity type, and is located between the first base region 41 and the second surface 40B. The side of the anode region 42 close to the first base region 41 contacts the side of the first base region 41 close to the second surface 40B. The side of the anode region 42 close to the first base region 41 forms a recess (not marked in the figure) at a position corresponding to the first protrusion 41a, which is used to match the first protrusion 41a. The side of the anode region 42 away from the first base region 41 is flush with the second surface 40B.

[0139] In this embodiment, the junction depth of the anode region 42 at the above-mentioned concave portion is smaller than that of other regions, which can not only reduce the emission efficiency of the reverse resistance anode 43 at this position, but also form a rapid carrier extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. In addition, the width of the concave portion can be adjusted, and the reverse blocking rated voltage of the device can be adjusted. The low emission efficiency anode region 42 structural design is conducive to reducing the irradiation dose and continuously maintaining the low on-state loss device characteristics of the reverse resistance type device.

[0140] The width W1 of the concave portion is determined by the rated voltage design value of the anode transparent junction J1 (the PN junction between the first base region 41 and the anode region 42). By adjusting the width W1 of the concave portion, the reverse blocking rated voltage can be adjusted. Usually, the design width of the width W1 is 10 μm to 80 μm, and does not affect the design voltage of the anode transparent junction J1 in the longitudinal direction.

[0141] The anode region 42 includes a second conductivity type first sub-anode region 421 and a second conductivity type second sub-anode region 422 which are sequentially stacked from the first base region 41 toward the second surface 40B.

[0142] The ion doping concentration of the first sub-anode region 421 is less than or equal to the ion doping concentration of the second sub-anode region 422. The change in the concentration gradient of the anode region 42 can reduce the turn-off loss of the reverse resistance device and improve the turn-off capability, while maintaining a high reverse recovery -di / dt capability and high current capacity.

[0143] In this embodiment, a second protrusion 421a extending toward the second surface 40B is formed at a position corresponding to the first protrusion 41a on one side of the first sub-anode region 421 away from the first base region 41. A predetermined distance is provided between the top of the second protrusion 421a and the second surface 40B.

[0144] That is to say, the formation of the second boss 421a forms another recess (not marked in the figure, hereinafter referred to as the second recess) at a position corresponding to the second boss 421a on the side of the second sub-anode region 422 close to the first sub-anode region 421, which is used to match the second boss 421a. The formation of the second recess makes the junction depth of the second sub-anode region 422 at the corresponding position smaller than other regions, and much smaller than the overall junction depth of the anode region 42. When the junction depth of the second sub-anode region 422 at this position is smaller than a certain threshold, carriers can easily pass through, and this part of the anode region 42 is similar to a "transparent" anode region, further reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. It can further achieve the adjustment of the reverse blocking rated voltage of the device and the uniformity of the turn-off, and further improve the turn-off capability of large-area power devices.

[0145] In this embodiment, the top of the first boss 41a is flush with the top of the second boss 421a. At this time, the top of the first boss 41a and the top of the second boss 421a are at the same distance from the second surface 40B.

[0146] Correspondingly, the first sub-anode region 421 includes a first portion 4211 disposed around the first protrusion 41a, that is, the second protrusion 421a is disposed around the first protrusion 41a. The junction depth of the first portion 4211 is usually determined by the chip blocking voltage.

[0147] That is to say, in this embodiment, there is no portion with a lower junction depth at the position corresponding to the first boss 41a in the first sub-anode region 421, that is, there is no portion with a lower emission efficiency, but the second boss 421a can still be formed through the first part 4211, and a "transparent" anode region can still be formed in the second sub-anode region 422.

[0148] In this embodiment, a first conductive type short-circuit region 411 is disposed on the top of the first protrusion 41 a at a side away from the second surface 40B.

[0149] The ion doping concentration of the short-circuit region 411 is greater than the ion doping concentration of the first base region 41. It can be understood that the short-circuit region 411 extends into the anode region 42, reducing the emission efficiency of the anode region 42 at this location, so the setting of the short-circuit region 411 can further realize the formation of a low emission efficiency region in the anode region 42.

[0150] The second sub-anode region 422 includes a third portion 4221 disposed around the second protrusion 421 a , and a fourth portion 4222 located between the top of the second protrusion 421 a and the second surface 40B.

[0151] Among them, the junction depth of the fourth part 4222 is smaller than the junction depth of the third part 4221 , so the emission efficiency of the fourth part 4222 is lower than the emission efficiency of the third part 4221 .

[0152] Among them, the fourth part 4222 is the above-mentioned "transparent" anode area, through which carriers can easily pass, reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. By designing the width W2 of the "transparent" anode area, the uniformity of chip turn-off can be adjusted, and the turn-off capability of large-area switch devices can be improved.

[0153] Furthermore, the ion doping concentration of the fourth portion 4222 is less than or equal to the ion doping concentration of the third portion 4221 , thereby further reducing the emission efficiency of the fourth portion 4222 and further achieving the formation of a “transparent” anode region.

[0154] In this embodiment, the second conductive type second base region 44, the second conductive type third base region 45 and the first conductive type emitter region 46 are located between the first base region 41 and the first surface 40A and are stacked in sequence from the first base region 41 to the first surface 40A.

[0155] The orthographic projection of the emission area 46 on the second surface 40B at least covers a portion of the orthographic projection of the recess on the second surface 40B.

[0156] The emission region 46 is also called the cathode comb bar, that is, the recess of the anode region 42 is arranged at the corresponding position of the cathode comb bar, so that the area with low emission efficiency in the anode region 42 is arranged corresponding to the cathode comb bar, which can further form a rapid carrier extraction channel at this location when the chip is turned off, further reducing the chip shutdown tail time and reverse recovery time, and further reducing the shutdown loss.

[0157] An anode transparent junction J1 is formed between the anode region 42 and the first base region 41 , a blocking voltage main junction J2 is formed between the first base region 41 and the second base region 44 , and a gate cathode junction J3 is formed between the third base region 45 and the emitter region 46 .

[0158] Furthermore, the ion doping concentration of the third base region 45 is greater than the ion doping concentration of the second base region 44 , and the ion doping concentration of the emitter region 46 is greater than the ion doping concentration of the first base region 41 .

[0159] The emitter region 46 covers a portion of the upper surface of the third base region 45. The upper surface of the emitter region 46 and the upper surface of the third base region 45 not covered by the emitter region 46 are both flush with the first surface 40A.

[0160] The cathode 47 is located on the first surface 40A and is electrically connected to the emission region 46 for leading the emission region 46 out.

[0161] The gate 48 is located on the first surface 40A and is electrically connected to the third base region 45 for leading out the third base region 45 .

[0162] The anode 43 is located on the second surface 40B and is electrically connected to the anode region 42 for leading out the anode region 42 .

[0163] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type. Specifically, a reasonable selection can be made according to the type of device to be prepared in actual need.

[0164] The present application provides a cell structure 40 of a power semiconductor device, wherein a first boss 41a extending toward a second surface 40B is arranged at a center position of a first base region 41 in the cell structure 40, so that a recess is formed on a side of an anode region 42 close to the first base region 41 at a position corresponding to the first boss 41a, and the junction depth of the anode region 42 at the recess is deeper than that of other regions, which can reduce the emission efficiency of the reverse resistance anode 43 at the recess and form a rapid carrier extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss.

[0165] Embodiment 4

[0166] like Figure 6 As shown, an embodiment of the present application provides a cell structure 50 of a power semiconductor device, including a substrate (not marked in the figure), a first base region 51, an anode region 52, a second base region 54, a third base region 55, an emitter region 56, a cathode 57, an anode 53 and a gate 58.

[0167] Exemplarily, the substrate is a single crystal silicon substrate, and the substrate includes a first surface 50A and a second surface 50B arranged opposite to each other, wherein the first surface 50A is provided with side grooves (not marked in the figure) downwardly on both sides of the cell structure 50. The formation of the side grooves on the first surface 50A forms a certain height difference between the gate 58 and the cathode 57, shortening the longitudinal commutation path of the power semiconductor device, which is beneficial to the turn-off speed and turn-off capability.

[0168] The first base region 51 is a doped region of the first conductivity type and is located in the substrate. In this embodiment, the first base region 51 is spaced a certain distance from both the first surface 50A and the second surface 50B. The ion doping concentration and junction depth of the first base region 51 are mainly selected based on the blocking voltage, on-state voltage drop and other parameter requirements of the power device.

[0169] In this embodiment, the first base region 51 is provided with a first protrusion 51 a at the center of the cell structure 50 and extending toward the second surface 50B.

[0170] The anode region 52 is a doped region of the second conductivity type, and is located between the first base region 51 and the second surface 50B. The side of the anode region 52 close to the first base region 51 contacts the side of the first base region 51 close to the second surface 50B. The side of the anode region 52 close to the first base region 51 forms a recess (not marked in the figure) at a position corresponding to the first protrusion 51a, which is used to match the first protrusion 51a. The side of the anode region 52 away from the first base region 51 is flush with the second surface 50B.

[0171] In this embodiment, the junction depth of the anode region 52 at the above-mentioned concave portion is smaller than that of other regions, which can not only reduce the emission efficiency of the reverse resistance anode 53 at this position, but also form a carrier rapid extraction channel when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. In addition, the width of the concave portion can be adjusted, and the reverse blocking rated voltage of the device can be adjusted. The low emission efficiency anode region 52 structural design is conducive to reducing the irradiation dose and continuously maintaining the low on-state loss device characteristics of the reverse resistance type device.

[0172] The width W1 of the concave portion is determined by the rated voltage design value of the anode transparent junction J1 (the PN junction between the first base region 51 and the anode region 52). By adjusting the width W1 of the concave portion, the reverse blocking rated voltage can be adjusted. Usually, the design width of the width W1 is 10 μm to 80 μm, and does not affect the design voltage of the anode transparent junction J1 in the longitudinal direction.

[0173] The anode region 52 includes a second conductivity type first sub-anode region 521 and a second conductivity type second sub-anode region 522 which are sequentially stacked from the first base region 51 to the second surface 50B.

[0174] The ion doping concentration of the first sub-anode region 521 is less than or equal to the ion doping concentration of the second sub-anode region 522. The change in the concentration gradient of the anode region 52 can reduce the turn-off loss of the reverse resistance device and improve the turn-off capability, and can also maintain a high reverse recovery -di / dt capability and high current capacity.

[0175] In this embodiment, a second protrusion 521a extending toward the second surface 50B is formed at a position corresponding to the first protrusion 51a on one side of the first sub-anode region 521 away from the first base region 51. A predetermined distance is provided between the top of the second protrusion 521a and the second surface 50B.

[0176] That is to say, the formation of the second boss 521a forms another recess (not marked in the figure, hereinafter referred to as the second recess) at a position corresponding to the second boss 521a on the side of the second sub-anode region 522 close to the first sub-anode region 521, which is used to match the second boss 521a. The formation of the second recess makes the junction depth of the second sub-anode region 522 at the corresponding position smaller than other regions, and much smaller than the overall junction depth of the anode region 52. When the junction depth of the second sub-anode region 522 at this position is smaller than a certain threshold, carriers can easily pass through, and this part of the anode region 52 is similar to a "transparent" anode region, further reducing the chip shutdown tail time and reverse recovery time, and reducing the shutdown loss. It can further achieve the adjustment of the reverse blocking rated voltage of the device and the uniformity of the shutdown, and further improve the shutdown capability of large-area power devices.

[0177] In this embodiment, the top of the first boss 51a is flush with the second surface 50B. Correspondingly, the first sub-anode region 521 includes a first portion 5211 disposed around the first boss 51a, that is, the second boss 521a is disposed around the first boss 51a.

[0178] At this time, the first sub-anode region 521 can still form the second boss 521 a through the first portion 5211 , and a “transparent” anode region can still be formed in the second sub-anode region 522 .

[0179] That is to say, in the present embodiment, there is no portion with a lower junction depth, i.e., no portion with a lower emission efficiency, at the position corresponding to the first boss 51a in the first sub-anode region 521. However, since the top of the second boss 521a is still separated from the second surface 50B by a certain distance, a "transparent" anode region can still be formed in the second sub-anode region 522 through the second boss 521a.

[0180] In this embodiment, a first conductive type short-circuit region 511 is disposed on the top of the first protrusion 51 a at a side away from the second surface 50B.

[0181] The ion doping concentration of the short-circuit region 511 is greater than the ion doping concentration of the first base region 51. It can be understood that the short-circuit region 511 extends into the anode region 52, reducing the emission efficiency of the anode region 52 at this location, so the setting of the short-circuit region 511 can further realize the formation of a low emission efficiency region in the anode region 52.

[0182] The second sub-anode region 522 includes a third portion 5221 disposed around the second boss 521 a , and a fourth portion 5222 located between the top of the second boss 521 a and the second surface 50B.

[0183] The junction depth of the fourth portion 5222 is smaller than the junction depth of the third portion 5221 .

[0184] Among them, the fourth part 5222 is the above-mentioned "transparent" anode area, through which carriers can easily pass, reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss. By designing the width W2 of the "transparent" anode area, the uniformity of chip turn-off can be adjusted, and the turn-off capability of large-area switch devices can be improved.

[0185] Furthermore, the ion doping concentration of the fourth portion 5222 is less than or equal to the ion doping concentration of the third portion 5221 , thereby further reducing the emission efficiency of the fourth portion 5222 and further realizing the formation of a “transparent” anode region.

[0186] In this embodiment, the second conductive type second base region 54, the second conductive type third base region 55 and the first conductive type emitter region 56 are located between the first base region 51 and the first surface 50A and are stacked in sequence from the first base region 51 to the first surface 50A.

[0187] The orthographic projection of the emission area 56 on the second surface 50B at least covers a portion of the orthographic projection of the recess on the second surface 50B.

[0188] The emission region 56 is also called the cathode comb bar, that is, the recess of the anode region 52 is arranged at the corresponding position of the cathode comb bar, so that the area with low emission efficiency in the anode region 52 is arranged corresponding to the cathode comb bar, which can further form a rapid carrier extraction channel at this location when the chip is turned off, further reducing the chip shutdown tail time and reverse recovery time, and further reducing the shutdown loss.

[0189] An anode transparent junction J1 is formed between the anode region 52 and the first base region 51 , a blocking voltage main junction J2 is formed between the first base region 51 and the second base region 54 , and a gate cathode junction J3 is formed between the third base region 55 and the emitter region 56 .

[0190] Furthermore, the ion doping concentration of the third base region 55 is greater than the ion doping concentration of the second base region 54 , and the ion doping concentration of the emitter region 56 is greater than the ion doping concentration of the first base region 51 .

[0191] The emitter region 56 covers a portion of the upper surface of the third base region 55. The upper surface of the emitter region 56 and the upper surface of the third base region 55 not covered by the emitter region 56 are both flush with the first surface 50A.

[0192] The cathode 57 is located on the first surface 50A and is electrically connected to the emission region 56 for leading the emission region 56 out.

[0193] The gate 58 is located on the first surface 50A and is electrically connected to the third base region 55 for leading out the third base region 55 .

[0194] The anode 53 is located on the second surface 50B and is electrically connected to the anode region 52 for leading out the anode region 52 .

[0195] In this embodiment, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type. Specifically, a reasonable selection can be made according to the type of device to be prepared in actual need.

[0196] The present application provides a cell structure 50 of a power semiconductor device, wherein a first boss 51a extending toward a second surface 50B is arranged at a center position of the cell structure 50 on a first base region 51, so that a recess is formed on a side of an anode region 52 close to the first base region 51 at a position corresponding to the first boss 51a. The junction depth of the anode region 52 at the recess is deeper than that of other regions, which can reduce the emission efficiency of the reverse resistance anode 53 at the recess and form a channel for rapid carrier extraction when the chip is turned off, thereby reducing the chip turn-off tail time and reverse recovery time, and reducing the turn-off loss.

[0197] Embodiment 5

[0198] Based on the first embodiment, Figure 7a , Figure 7b and Figure 8 As shown, this embodiment provides a power semiconductor device, including several cell structures 20 of the power semiconductor device in the first embodiment, and a gate extraction electrode 60 arranged on a first surface of at least one of the cell structures.

[0199] like Figure 7a As shown, the emission regions 26 (cathode comb strips, i.e., the strip pattern in the figure) in each cellular structure 20 are uniformly arranged in a wafer using sector arcs or circles, and are usually arranged in a concentric radiation state when viewed horizontally.

[0200] The gate lead electrode 60 may be disposed at the edge of the power semiconductor device, such as Figure 7a It can also be set in the center or middle position, such as Fig. 9 shown.

[0201] Furthermore, the width of the fourth portion 2222 (“transparent” anode region) of the anode region 22 in each of the cellular structures 20 gradually increases in a direction away from the gate lead-out electrode.

[0202] By designing the width W2 of the “transparent” anode region, the uniformity of chip shutdown can be adjusted, thereby improving the shutdown capability of large-area power devices.

[0203] Moreover, by controlling the width W2 of the low-emission-efficiency "transparent" anode region, the current density distribution of the chip in the on state is optimized, and current congestion in the reverse-resistance power device at a position far away from the gate lead-out electrode 60 is avoided, thereby increasing the safe operating area of ​​the chip and improving the turn-off capability of the reverse-resistance power device.

[0204] Embodiment 6

[0205] Based on the first embodiment, this embodiment provides another cell structure of a power semiconductor device, including a substrate (not marked in the figure), a first base region, an anode region, a second base region, a third base region, an emitter region, a cathode, an anode and a gate.

[0206] In this embodiment, the power semiconductor device is a reverse resistance type GCT.

[0207] Correspondingly, the first base region is an N-base region, and the doping concentration of the N-base region is selected by optimizing the chip blocking voltage.

[0208] The anode region includes a first sub-anode region and a second sub-anode region.

[0209] The first sub-anode region is a P anode region, and the doping concentration of the P anode region is 1E13cm -3 ~9E16cm -3 The P anode region is formed by diffusion of P-type impurities with a faster diffusion coefficient, such as aluminum (Al) or gallium (Ga) impurities.

[0210] The second sub anode region includes a third portion and a fourth portion.

[0211] The third part is P1 with high emission efficiency + Anode area, the fourth part is the "transparent" P2 with low emission efficiency + Anode area.

[0212] P1 + The doping concentration of the anode region is 5E16cm -3 ~1E19cm -3 , the diffusion junction depth (distance from the second surface) is 20μm to 100μm.

[0213] “Transparent” P2 + The doping concentration of the anode region is 1E16cm-3 ~1E19cm -3 , "Transparent" P2 + The diffusion junction depth of the anode region (the distance from the second surface) is usually deeper than P1. + The depth of the diffusion junction in the anode region should be shallow, usually about 1μm to 30μm.

[0214] “Transparent” P2 + The width W2 of the anode region is usually 20 μm to 400 μm.

[0215] P1 + Anode area and P2 + The anode region is formed by implantation and diffusion of P-type impurities, such as boron (B) impurities.

[0216] The emitter region is N+ emitter region with a doping concentration of 1E17cm -3 ~9E21cm -3 The junction depth is 5μm to 30μm, and is generally formed by diffusion of N-type impurities, such as phosphorus (P). When viewed horizontally, it is usually arranged in a concentric radial state.

[0217] The third base region is a P+ base region with a doping concentration of 5E16cm -3 ~5E18cm -3 The junction depth (distance from the first surface) is 20 μm to 100 μm. It is usually formed by implantation and diffusion of P-type impurities, such as aluminum, gallium, and boron (Al, Ga, B).

[0218] The second base region is a P base region with a doping concentration of 1E13cm -3 ~9E16cm -3 The junction depth is determined by the chip blocking voltage and terminal structure design. It is formed by diffusion of P-type impurities with a faster diffusion coefficient, such as aluminum (Al) or gallium (Ga) impurities.

[0219] The positional relationship of the above-mentioned components is the same as that in the first embodiment and will not be described in detail in this embodiment.

[0220] Embodiment 7

[0221] Based on the first embodiment, this embodiment provides another cell structure of a power semiconductor device, such as Fig.10 As shown, it includes a substrate (not marked in the figure), a first base region, an anode region, a second base region, a third base region, an emitter region, a cathode, an anode and a gate.

[0222] In this embodiment, the power semiconductor device is a 4-inch 6500V reverse resistance GCT.

[0223] The corresponding first base region is an N-base region, and the doping concentration of the N-base region is selected by optimizing the chip blocking voltage.D 8E12cm-3~2E13cm-3, N-base width W D It is 1200μm~1400μm.

[0224] The anode region includes a first sub-anode region and a second sub-anode region.

[0225] The first sub anode region includes a first portion and a second portion.

[0226] The first part is a P anode region with high emission efficiency, and the second part is a P anode region with low emission efficiency.

[0227] The surface doping concentration N of the P anode region with high emission efficiency P 1E15cm -3 ~5E15cm -3 , junction depth (distance from the second surface) X j11 About 100μm~140μm.

[0228] The surface doping concentration N of the P anode region with low emission efficiency P 1E15cm -3 ~5E15cm -3 , junction depth (distance from the second surface) X j12 It is about 60μm to 100μm, and its width W1 is about 20μm to 40μm.

[0229] The second sub anode region includes a third portion and a fourth portion.

[0230] The third part is P1 with high emission efficiency + Anode area, the fourth part is the "transparent" P2 with low emission efficiency + Anode area.

[0231] P1 + The doping concentration of the anode region is N AP1+ 1E18cm -5 ~5E18 cm -3 , junction depth (distance from the second surface) X jAP1+ About 40μm~80μm.

[0232] “Transparent” P2 + The anode area is located on the anode surface below the cathode comb and is concentric with the cathode comb. The surface doping concentration N AP2+ 5E17cm -3 ~1E18 cm -3 , "Transparent" P2 + Anode region junction depth (distance from the second surface) X jAP2+ About 2μm~10μm.

[0233] The emitter region is N+ emitter region, and the doping concentration Ne is 1E19cm -3 ~1E20 cm -3 , junction depth (distance from the second surface) X j3 About 10μm~40μm.

[0234] The third base region is a P+ base region with a surface doping concentration of N P+ 1E17cm -3 ~1E18 cm -3 , junction depth (distance from the second surface) X jP+ About 40μm~80μm.

[0235] The second base region is a P base region with a surface doping concentration of N P 1E15cm -3 ~5E15cm -3 , junction depth (distance from the second surface) X j2 About 100μm~140μm.

[0236] The positional relationship of the above-mentioned components is the same as that in the first embodiment and will not be described in detail in this embodiment.

[0237] Embodiment 8

[0238] Based on the seventh embodiment, this embodiment provides a power semiconductor device, such as Fig.11 shown.

[0239] In this embodiment, the power semiconductor device is a 4-inch 6500V reverse resistance GCT.

[0240] like Fig.11 As shown, the emitter region (cathode comb bar) is marked as No. 1, No. 2, ..., No. 10 from the center to the end of the tube core. The gate lead electrode is located between the No. 5 and No. 6 circles, which is the middle lead gate.

[0241] Among them, since the No.9 and No.10 loops are far away from the gate lead-out electrode and the chip effective area is large, there is a shutdown delay and a high shutdown current density during the shutdown process, so the device damage points are often distributed at the locations of these two loops. 4-inch reverse resistance type 6500V GCT P2 + The anode region (“transparent” anode region) can be mainly designed at the locations of the 9th and 10th turns and connected to the GCT terminals.

[0242] P2 can also be set under each cathode comb bar. + anode area (“transparent” anode area), and P2 + The width of the anode region is designed to gradually increase in a direction away from the gate lead-out electrode.

[0243] No.1, No.2, ..., No.10, P2 + The widths of the anode regions are W21, W22, ..., and their corresponding P2 + The width of the anode area can be designed as follows Fig.12 shown.

[0244] Through this P2 + The design of the width W2 of the anode region can adjust the uniformity of chip shutdown and improve the shutdown capability of large-area power devices.

[0245] Moreover, by controlling the width W2 of the low-emission-efficiency "transparent" anode region, the current density distribution of the chip in the on state is optimized, avoiding current crowding in the reverse-resistance power device at a position far away from the gate-connected lead electrode, thereby increasing the safe operating area of ​​the chip and improving the turn-off capability of the reverse-resistance power device.

[0246] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. Although the implementation methods disclosed in the present application are as above, the content is only an implementation method adopted to facilitate the understanding of the present application and is not intended to limit the present application. Any technician in the technical field to which the present application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application, but the protection scope of the present application shall still be subject to the scope defined by the attached claims.

Claims

1. A cell structure of a power semiconductor device, characterized in that: include: A substrate, wherein the substrate comprises a first surface and a second surface arranged opposite to each other; A first base region of the first conductivity type located in the substrate; wherein the first base region is provided with a first boss extending toward the second surface at the center of the cell structure; an anode region located between the first base region and the second surface; wherein a side of the anode region close to the first base region forms a recess at a position corresponding to the first boss, and a side of the anode region away from the first base region is flush with the second surface; The anode region includes a first sub-anode region of a second conductivity type and a second sub-anode region of a second conductivity type which are sequentially stacked from the first base region to the second surface; Wherein, the ion doping concentration of the first sub-anode region is less than or equal to the ion doping concentration of the second sub-anode region; A second protrusion extending toward the second surface is formed at a position corresponding to the first protrusion on a side of the first sub-anode region away from the first base region.

2. The cell structure of the power semiconductor device according to claim 1, characterized in that: The first sub-anode region includes a first portion disposed around the first boss.

3. The cell structure of the power semiconductor device according to claim 2, characterized in that: The second sub-anode region includes a third portion disposed around the second boss, and a fourth portion located between the top of the second boss and the second surface; The junction depth of the fourth portion is smaller than the junction depth of the third portion.

4. The cell structure of the power semiconductor device according to claim 3, characterized in that: The ion doping concentration of the fourth portion is less than or equal to the ion doping concentration of the third portion.

5. The cell structure of the power semiconductor device according to claim 2, characterized in that: The top of the second boss is located on a side of the top of the first boss close to the second surface; The first sub-anode region further includes a second portion located between the top of the first boss and the top of the second boss; The junction depth of the second portion is smaller than the junction depth of the first portion, and the first portion is in contact with the second portion.

6. The cell structure of the power semiconductor device according to claim 5, characterized in that: The ion doping concentration of the second portion is less than or equal to the ion doping concentration of the first portion.

7. The cell structure of the power semiconductor device according to claim 1, characterized in that: The top of the first boss is flush with the top of the second boss.

8. The cell structure of the power semiconductor device according to claim 1, characterized in that: The top of the first boss is flush with the second surface.

9. The cell structure of a power semiconductor device according to claim 7 or 8, characterized in that: A first conductive type short-circuit region is provided on the top of the first boss at a side away from the second surface; Wherein, the ion doping concentration of the short-circuit region is greater than the ion doping concentration of the first base region.

10. The cell structure of the power semiconductor device according to claim 1, characterized in that: Also includes: A second conductive type second base region, a second conductive type third base region, and a first conductive type emitter region are located between the first base region and the first surface and are sequentially stacked in a direction from the first base region to the first surface; The orthographic projection of the emission area on the second surface at least covers a portion of the orthographic projection of the recess on the second surface.

11. The cell structure of the power semiconductor device according to claim 10, characterized in that: The ion doping concentration of the third base region is greater than the ion doping concentration of the second base region, and the ion doping concentration of the emitter region is greater than the ion doping concentration of the first base region.

12. The cell structure of the power semiconductor device according to claim 10, characterized in that: Also includes: a cathode located on the first surface and electrically connected to the emitting region; a gate electrode located on the first surface and electrically connected to the third base region; An anode is located on the second surface and is electrically connected to the anode region.

13. A power semiconductor device, characterized in that: The invention comprises a plurality of cellular structures of the power semiconductor device according to any one of claims 1 to 12, and a gate extraction electrode arranged on a first surface of at least one of the cellular structures.

14. The power semiconductor device according to claim 13, characterized in that: The width of the fourth portion of the anode region in each of the cell structures gradually increases in a direction away from the gate lead-out electrode.

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