Mask enhancement technique solution based on failure modes predicted by artificial neural networks

Abstract

For lithography mask layout verification, training data is collected for each design intent in a set of design intents by identifying a set of failures expected to occur during the fabrication of the design intent and recording the failure mode and location of each failure in the set of failures. Next, the training data is used to train a machine learning model, such as an artificial neural network, to predict the failure mode and location of failures. Then, the trained machine learning model is used to predict a set of failures for a given design intent. Next, for each predicted failure, a mask enhancement technology (RET) scheme can be selected based on the failure mode of the failure, and the selected RET scheme can be applied to the area around the location of the failure.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 62 / 887,728, filed on Aug. 16, 2019, the content of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This disclosure generally relates to integrated circuit (IC) design. More specifically, this disclosure relates to applying mask enhancement technology (RET) solutions based on failure modes predicted by an artificial neural network. Background Art

[0004] Advances in process technology and the nearly insatiable demand for computing and storage have spurred a rapid increase in the size and complexity of IC design. These advances can be attributed to improvements in semiconductor design and manufacturing technologies, which have enabled tens of millions of devices to be integrated onto a single chip. Summary of the Invention

[0005] Some embodiments described herein are characterized by methods and apparatuses that can collect training data for each design intent in a set of design intents by identifying a set of failures expected to occur when the design intent is fabricated and recording the failure mode and location of each failure in the set of failures. In some embodiments, a design intent may refer to a shape that is desired to be printed on a wafer, i.e., a design intent may not include any modifications performed using RET. In some embodiments, training data can be collected by performing an iterative loop that includes: using lithography verification to identify failure modes in a mask layout, adjusting an RET solution to address the occurrence of the failure modes, and applying the adjusted RET solution to the mask layout. Next, embodiments can use the training data to train a machine learning model, such as an artificial neural network, to predict the failure mode and location of failures for a given design intent that is different from the design intents used during training.

[0006] In some embodiments, supervised learning can be used to train an artificial neural network, where the design intent can be provided as an input and the failure mode and location can be provided as the desired output.

[0007] In some embodiments, a separate design layer can be created for each failure mode to mark the locations of failures belonging to that failure mode, and the location of each failure can be marked by placing polygons near the failures in the design layer. In these embodiments, the adjusted RET solution can be applied to the regions within the polygons in the mask layout that correspond to the failure mode.

[0008] Some embodiments may use a trained artificial neural network to predict the failure modes and locations of failures expected to occur in the design intent. Next, for each predicted failure, the embodiments may select a RET scheme based on the failure mode of the failure and apply the selected RET scheme to the area around the location of the failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure can be understood based on the detailed description and the drawings given below. The drawings are for illustrative purposes and do not limit the scope of the present disclosure. Additionally, the drawings are not necessarily drawn to scale.

[0010] Figure 1 Illustrates a process for determining failure modes in a design intent and a RET scheme for solving the failure modes according to some embodiments described herein.

[0011] Figure 2 Illustrates a process for performing lithography verification according to some embodiments described herein.

[0012] Figure 3 Illustrates how to mark the failure mode locations in a mask layout according to some embodiments described herein.

[0013] Figure 4 Illustrates a process for training an artificial neural network to predict failure modes according to some embodiments described herein.

[0014] Figure 5 Illustrates a process for selectively applying a RET scheme to a mask layout using an artificial neural network according to some embodiments described herein.

[0015] Figure 6 Illustrates a flowchart of an IC design and manufacturing process according to some embodiments described herein.

[0016] Figure 7 Illustrates an exemplary machine of a computer system within which a set of instructions can be executed according to some embodiments described herein to cause the machine to perform any one or more of the methods discussed herein. DETAILED DESCRIPTION

[0017] Semiconductor manufacturing techniques may use multiple physical processes and / or chemical processes to transfer the design intent onto a wafer. In the present disclosure, the term "design intent" refers to the shape expected to be printed on the wafer, for example, by using lithography. The term "mask layout" refers to the shape on a lithography mask used for printing the design intent in lithography. Due to physical and / or chemical phenomena that occur during semiconductor manufacturing, the design intent may not be printed as desired if the design intent is used as is, i.e., without any modification, in the mask layout.

[0018] RET schemes can be used to modify the design intent to obtain a modified mask layout that can subsequently be used in lithography. The modifications added by the RET schemes can compensate for physical or chemical effects that cause the printed pattern to deviate from the design intent. Specifically, when using a mask layout containing the modified mask layout in lithography, the printed shape on the wafer can be within the acceptable tolerances of the design intent.

[0019] Examples of RET include, but are not limited to, rule-based RET, process model-based RET, and inverse imaging-based RET (also known as inverse lithography technology or ILT). For each type of RET, there may be different trade-off points between the amount of computing resources used (e.g., the amount of runtime, memory, and / or computing power used by the RET) and the quality of the results produced (e.g., the quality of the results can correspond to the degree of resolution of manufacturing problems). Specifically, if higher quality results are desired (e.g., if it is desired to eliminate all manufacturing problems), then a large amount of computing resources can be used (e.g., the runtime for applying the RET may be long).

[0020] In the present disclosure, the term "RET scheme" can refer to an RET technique or a sequence of RET techniques, where each RET technique is set at a specific trade-off point between the amount of computing resources used and the quality of the results produced. The phrase "tuning the RET scheme" can refer to changing the type of one or more RETs being used and / or changing the trade-off point of one or more RETs between the amount of computing resources used and the quality of the results produced.

[0021] Processing the entire mask layout using an RET scheme that produces very high-quality results may use an impractically large amount of computing resources. On the other hand, using an RET scheme that uses a small amount of computing resources for the entire mask layout may result in poor result quality. Note that a single manufacturing problem can cause a complete failure of the IC chip. If it is not known which regions are vulnerable to which types of manufacturing problems, then computationally expensive RET techniques may ultimately be used for the entire mask layout, which can significantly increase the amount of time spent on RET.

[0022] The embodiments described in this disclosure may use machine learning, such as an artificial neural network, to predict the types and locations of manufacturing problems expected to occur in a mask layout. Additionally, for each type of manufacturing problem, the embodiments may determine an appropriate RET solution expected to solve the manufacturing problem. Next, given a design intent, the embodiments may use a trained machine learning model, such as a trained artificial neural network, to predict the types and locations of manufacturing problems expected to occur in the design intent. For each type of predicted manufacturing problem, the embodiments may selectively apply an appropriate RET solution (the RET solution is pre-determined) at the location where the predicted manufacturing problem is expected to occur.

[0023] Advantages of the embodiments disclosed herein include, but are not limited to, a process that can produce a high-quality mask layout (e.g., a mask layout expected to have no manufacturing problems) without using a large amount of computing resources.

[0024] Figure 1 A process for determining failure modes in a design intent and RET solutions for solving the failure modes according to some embodiments described herein is shown. The design intent 102 may include shapes desired to be printed on a wafer. In Figure 1 , the design intent 102 is shown as having two polygons, but generally the design intent 102 may have a large number of polygons (e.g., tens of millions of polygons). The design intent 102 may be the design of an actual IC chip. However, the design intent 102 may also be a design that has been created for training an artificial neural network. Specifically, the design intent 102 may include a random arrangement of unit cells, and / or may include random and / or programmed patterns.

[0025] The RET solution 104 may be applied to the design intent 102 to obtain a mask layout 106 that may include one or more modifications (e.g., serifs 108 and assist features 110). In some embodiments, the RET solution 104 may be selected to produce reasonable-quality results and have a reasonable runtime. Specifically, the RET solution 104 may consider nominal process conditions and may have a small number of adjustment iterations. After applying the RET solution 104 to the design intent 102, it may be expected that there are at least some manufacturing problems. Lithography verification (step 112) may be performed to determine whether the desired mask layout 106 prints the design intent 102 on the wafer with high fidelity. As a non-limiting example, a lithography verification tool such as Synopsys's Proteus Lithography Rule Check (PLRC) may be used to perform the lithography verification.

[0026] Figure 2Illustrates a process for performing lithography verification according to some embodiments described herein. A process model 202 can be developed to model a given semiconductor manufacturing technology and can be used to simulate the effects of physical and / or chemical processes that occur during manufacturing. Given a mask layout, the process model 202 can generate a predicted pattern 204 that is expected to be printed on a wafer. The mask layout provided as input to the process model 202 may or may not include RET modifications. For example, the mask layout 106 includes RET modifications such as serifs 108 and assist features 110, which may be generated by applying one or more RETs to the design intent 102. The process model 202 can generate the predicted pattern 204 based on the mask layout 106. Next, failure modes can be identified in step 206 by comparing the predicted pattern 204 with the design intent 102.

[0027] Reference Figure 1 , lithography verification (step 112) can generate failure modes 114, where each failure mode corresponds to one or more differences between the design intent and the shape expected to be printed on the wafer. Each difference outside the tolerance limits can be identified as a failure. The common causes leading to a set of failures can be identified as failure modes.

[0028] For each failure mode, the RET scheme can be adjusted to address the failure mode (step 116). In other words, the RET scheme can be adjusted such that the modifications made by the RET scheme fix a particular type of difference between the design intent and the shape expected to be printed on the wafer. Then, the adjusted RET scheme can be applied to the current mask layout (step 118) to obtain a mask layout 120, which becomes the current mask layout in the next iteration. Note that the adjusted RET scheme can be applied within the area around the difference, rather than being applied to the entire mask layout. It should also be noted that the mask layout provided as input to step 118 may include modifications made by previous rounds of RET processing.

[0029] In some embodiments, the location of a failure mode can be marked by placing a polygon near the location of the failure mode. Specifically, the polygon can be placed such that the failure mode is within the boundary of the polygon, and the polygon can include shapes within the process limits at the location of the failure mode. In some embodiments, the polygon can be placed on a new layer, which may not be part of the output mask but can be used to track the location where a particular failure mode has been identified. When the RET scheme is adjusted, the area within the polygon on the new layer can be used to determine whether the adjustment has addressed the failure mode.

[0030] In some embodiments, multiple new layers can be generated, which can allow classification of manufacturing issues into separate layers. For example, lithography verification can identify regions with poor process windows and regions where nominal corrections do not converge to acceptable values. In such cases, the RET scheme can be adjusted differently to handle these two types of failures. Specifically, for regions with poor process windows, the RET scheme can be adjusted by including additional terms in the optimization cost function to increase the process window. For regions with poor convergence, the RET scheme can be adjusted by increasing the number of optimization steps to meet the nominal correction tolerance.

[0031] Figure 3 Illustrates how failure mode locations can be marked in a mask layout according to some embodiments described herein. Figure 1 The process shown in can be used to identify failure modes in the mask layout region 300. In Figure 3 each shaded rectangle corresponds to the location of a manufacturing issue. A failure mode corresponds to a type of manufacturing issue. For example, the manufacturing issue locations 302-1 and 302-2 correspond to the same failure mode. Similarly, the manufacturing issue locations 304-1 and 304-2 correspond to the same failure mode, which is different from the failure mode corresponding to the manufacturing issue locations 302-1 and 302-2. Finally, the manufacturing issue locations 306-1 and 306-2 correspond to a third failure mode, which is different from the other two failure modes. Each failure mode can correspond to an adjustment of the RET scheme expected to resolve the manufacturing issue associated with the failure mode. Thus, an adjustment of the RET scheme can be developed to resolve the manufacturing issues at locations 302-1 and 302-2. Polygons placed to mark two failure modes can overlap each other. For example, the failure mode locations 304-2 and 306-2 overlap each other (in Figure 3 the specific example shown, the polygons at locations 304-2 and 306-2 can be on different design layers, but polygons on the same layer can also overlap each other).

[0032] In some embodiments, each failure mode can be assigned a separate design layer, and the problem locations corresponding to each failure mode can be included in the corresponding design layer. Thus, if the first failure mode corresponding to the manufacturing issues 302-1 and 302-2 is assigned the first design layer, the first design layer can include only the manufacturing issue locations 302-1 and 302-2. Figure 3 The other manufacturing issue locations shown in (i.e., 304-1, 304-2, 306-1, and 306-2) can be included in their respective design layers. In these embodiments, the adjustment of the RET scheme corresponding to a given failure mode can be applied to all manufacturing issue locations specified in the design layer corresponding to the failure mode.

[0033] Reference Figure 1 , the process can then perform lithography verification (step 112) to determine whether the mask layout 120 is expected to print the design intent 102 on the wafer. If any failure modes remain unresolved when the adjusted RET scheme is applied or if new failure modes are created, steps 114, 116, 118, 120, and 112 can be performed again.

[0034] Specifically, the loop including steps 112, 114, 116, 118, and 120 can be executed one or more times until all failure modes have been considered and resolved within a predetermined tolerance level. During each iteration of the loop, the manufacturability of the mask layout can be improved as the failure is repaired by the adjusted RET scheme. However, for the purpose of artificial neural network training, the locations of the failures are retained. From one iteration to the next, new problem locations can be found. These new problems may be introduced as a side effect of resolving previously identified problems. It is expected that the number of new problems will rapidly decrease with each iteration, and only a few iterations of the loop may be required to identify and fix all manufacturing problems in the mask layout.

[0035] As described above, Figure 1 the process shown can identify failure modes 114 in the design intent 102. Each failure mode can correspond to a type of manufacturing problem that is expected to occur at a specific location in the mask layout if the current version of the mask layout is used. For each failure mode identified by the lithography verification 112, Figure 1 the process shown can also generate a corresponding RET scheme adjustment that, when applied to the area around the manufacturing problem location, partially or fully resolves the manufacturing problem associated with the failure mode.

[0036] Some non-limiting examples of RET, failure modes, and RET schemes that can resolve failure modes are now described. Rule-based RET can use a set of rules to determine the modifications to be made. When a specific pattern in the mask layout is detected, rule-based RET can apply a specific modification to that pattern. For example, rule-based RET can identify a set of line-end patterns in the mask layout and add hammerhead serifs to each line-end pattern to reduce or prevent manufacturing problems caused by line-end shortening or corner rounding or both. Depending on the complexity and number of rules used, there may be different trade-offs between the amount of computing resources used and the quality of the results produced. Specifically, a large number of complex rules can produce relatively high-quality results but may use a large amount of computing resources. Conversely, a small number of simple rules may produce relatively low-quality results but can use a small amount of computing resources.

[0037] Process model - based RET uses a process model to predict the shape expected to be printed and iteratively perturbs the mask layout to correct any differences between the predicted pattern and the design intent. Process model - based RET is sometimes referred to as optical proximity correction (OPC). Process model - based RET can also place assist features to address manufacturing issues, such as those caused by a low process window or low depth of focus. Depending on the accuracy of the process model and the number of iterations, there may be different trade - off points between the amount of computational resources used and the quality of the results produced. Specifically, using a highly accurate process model and a large number of iterations can produce relatively high - quality results, but may use a large amount of computational resources. Conversely, using a fast process model that is not very precise and a small number of iterations may produce relatively low - quality results, but can use a small amount of computational resources.

[0038] Inverse imaging - based RET is based on the inversion of a process model. For example, a printed mask layout can be represented as:

[0039] z(x,y) = T{m(x,y)},

[0040] where T{.} is the process model (e.g., the Hopkins imaging model if we are modeling the imaging process), m(x,y) is the input mask layout, and z(x,y) is the printed pattern. Assume z * (x,y) is the design intent. The goal of the inverse imaging problem is to estimate the mask layout m(x,y) such that the resulting printed pattern T{m(x,y)} is similar to the design intent z * (x,y). Specifically, a distance metric between the two patterns can be used to measure the similarity between the printed pattern and the design intent.

[0041] Some embodiments can formulate the inverse imaging problem as an optimization problem with a cost function that indicates the difference between the design intent and the printed pattern. Specifically, in some embodiments, the cost function f can be:

[0042]

[0043] The goal is to estimate the mask layout m(x, y) that minimizes the L2 norm of the distance between the printed pattern and the design intent. Depending on the desired objective, the cost function in Equation (1) can also be augmented to include more objectives, such as maximizing the image log slope, assist feature printability compliance, optical proximity correction for contour fidelity, minimizing the focus sensitivity for a better process window, etc. In other words, the embodiments described herein are not limited to using the cost function shown in Equation (1). Some embodiments can use pixel-based parameterization to solve the inverse imaging problem. Standard optimization techniques (such as gradient descent, conjugate gradient, quasi-Newton, etc.) can be used to optimize the cost function shown in Equation (1).

[0044] Based on the cost function used during optimization and / or the number of iterations used, there may be different trade-off points between the amount of computing resources used and the quality of the results produced. Specifically, using a complex cost function with multiple non-linear terms and a large number of optimization iterations can produce higher quality results, but may use a large amount of computing resources. Conversely, using a relatively simple cost function and a small number of optimization iterations may produce low quality results, but can use a small amount of computing resources.

[0045] A failure mode may occur when the difference between the width of the printed line (i.e., the critical dimension) and the width of the line in the design intent is greater than the tolerance threshold. The RET scheme can change the width of the line in the design intent such that the width of the printed line is substantially equal to the width of the line in the design intent (e.g., rule-based RET can increase the width of the line in the design intent).

[0046] Another failure mode may occur when there is excessive shortening at the line end. The RET scheme can add one or more serifs to the line end to address this manufacturing issue (e.g., a process model-based RET scheme can iteratively perturb the line end; alternatively, an inverse imaging-based RET can determine a modified line end shape that includes a solution to the manufacturing problem).

[0047] Yet another failure mode may occur when the pattern has a low process window and / or a low depth of focus. For example, the pattern may print satisfactorily under nominal focusing conditions, but may exhibit severe manufacturing problems (such as line end shortening) when the lithographic imaging system is slightly defocused. The RET scheme can add one or more assist features near the pattern to increase the depth of focus (e.g., a process model-based RET scheme can iteratively try different assist feature configurations to increase the depth of focus; alternatively, an inverse imaging-based RET scheme that includes a depth of focus term in the cost function can place one or more assist features to increase the depth of focus).

[0048] Figure 4A process for training an artificial neural network to predict failure modes according to some embodiments described herein is shown. The process may begin by collecting training data for each design intent in a set of design intents by identifying a set of failures expected to occur during fabrication of the design intent and recording the failure mode and location of each failure in the set of failures (step 402). For example, the failure mode may be determined by using the process shown in Figure 1 The failure mode can be determined by using the process shown in

[0049] Next, the process may use the training data to train a machine learning model, such as an artificial neural network, to predict the failure mode and location of failures for a given design intent different from the design intents in the set of design intents (step 404). The input to the artificial neural network may be the design intent, i.e., the shape expected to be printed on the wafer without any RET modification.

[0050] Supervised learning may be used to train the artificial neural network, where the design intent (without any RET modification) may be provided as input to the artificial neural network, and the set of failure modes and their locations (determined by using, for example, the process shown in Figure 1 The failure mode and its location can be determined by using the process shown in

[0051] In some embodiments, the artificial neural network may include an input layer, an output layer, and one or more hidden layers. The design intent may be rasterized, i.e., converted into a two-dimensional pixel map. Each pixel may correspond to a node in the input layer. The value of the pixel may be a floating point number between 0 and 1, where 0 may correspond to a transparent region, 1 may correspond to an opaque region, and a number between 0 and 1 may correspond to the percentage of the transparent / opaque region within the pixel. The output layer may include a set of nodes, where each node may correspond to a specific combination of location and failure mode. During supervised learning, values may be assigned to the input layer nodes based on the rasterized representation of the design intent, and values may be assigned to the output layer nodes based on the location and failure mode of the expected manufacturing problems. Then, backpropagation techniques may be used to adjust the connection weights in the artificial neural network. After the artificial neural network has been trained, the artificial neural network may be used to selectively apply RET schemes to the design intent.

[0052] Figure 5Illustrates a process of selectively applying RET schemes to a mask layout using an artificial neural network according to some embodiments described herein. The process may begin by using a trained machine learning model, such as a trained artificial neural network, to predict the failure modes and locations of failures expected to occur when printing the design intent using a lithography process (step 502). Next, for each predicted failure, the process may select an RET scheme based on the failure mode of the failure and apply the selected RET scheme to the area around the location of the failure (step 504).

[0053] Figure 6 Illustrates an example flow 600 for the design, verification, and fabrication of an integrated circuit according to some embodiments described herein. An EDA process 612 (the acronym "EDA" refers to "electronic design automation") may be used to transform and verify design data and instructions representing the integrated circuit. Each of these processes may be constructed and implemented as multiple modules or operations.

[0054] Flow 600 may begin by creating a product concept 610 using information provided by the designer, which is transformed and verified by using the EDA process 612. When the design is complete, the design is taped out 634, where taping out means that the original artwork of the integrated circuit (e.g., geometric patterns) is sent to a manufacturing facility to fabricate a mask set, which is then used to fabricate the integrated circuit. After taping out, a semiconductor die is fabricated 636, and packaging and assembly 638 are performed to produce the fabricated IC chip 640.

[0055] The specifications of a circuit or electronic structure can range from a low-level transistor material layout to a high-level description language. A high level of abstraction can be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be converted into a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of abstraction as a lower-level description adds more details to the design description. The lower levels of abstraction as less abstract descriptions can be computer-generated, exported from a design library, or created by another design automation process. An example of a language for specifying a lower-level language for a more detailed description is SPICE (which stands for "Simulation Program with Integrated Circuit Emphasis"). The description of each level of abstraction contains details sufficient to be used by the corresponding tools at that layer (e.g., formal verification tools).

[0056] During system design 614, the functionality of the integrated circuit to be fabricated is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. The partitioning of the design into different types of modules or components can occur at this stage.

[0057] During logic design and functional verification 616, the modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specification is checked. For example, it can be verified that the components of the circuit generate outputs that are appropriate for the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as an "emulator" or "prototyping system" is used to accelerate functional verification.

[0058] During synthesis and design for testing 618, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent the components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. The HDL code and the netlist are both hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design when fabricated. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0059] During netlist verification 620, the consistency of the netlist with the timing constraints and the correspondence of the netlist with the HDL code are checked. During design planning 622, an overall layout diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0060] During layout or physical implementation 624, physical placement (the positioning of circuit components such as transistors or capacitors) and routing (connecting the circuit components via multiple conductors) are performed, and cells can be selected from a library to implement a specific logic function. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or a latch). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be implemented as physical structures and in simulation. Parameters such as dimensions are specified for the selected cells (based on "standard cells"), and the parameters are made accessible in a database for use by EDA products.

[0061] During analysis and extraction 626, circuit functionality is verified at the layout level, which allows for refinement of the layout design. During physical verification 628, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and to ensure that the circuit functionality is compatible with the HDL design specifications. During resolution enhancement 630, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0062] During tape-out, data is created for the production of a lithography mask (after applying lithography enhancements where appropriate). During mask data preparation 632, the "tape-out" data is used to generate a lithography mask, which is used to produce the completed integrated circuit.

[0063] A storage subsystem of a computer system (such as Figure 7 computer system 700) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as cells for development libraries and products for physical and logical designs using the libraries.

[0064] Figure 7 An example machine of computer system 700 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0065] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0066] Example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 718, which communicate with each other via a bus 730.

[0067] The processing device 702 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 702 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 can be configured to execute instructions 726 for performing the operations and steps described herein.

[0068] The computer system 700 may also include a network interface device 708 for communicating via a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generating device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0069] The data storage device 718 may include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable medium) on which a set or sets of instructions 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution by the computer system 700, and the main memory 704 and the processing device 702 also constitute a machine-readable storage medium.

[0070] In some implementations, the instructions 726 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing a set or sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine and the processing device 702 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but not be limited to, solid state memories, optical media, and magnetic media.

[0071] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is a sequence of operations that results in a desired outcome. These operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0072] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise expressly stated, it will be appreciated that throughout the specification, certain terms are used to refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage devices of the computer system.

[0073] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purposes or the apparatus may comprise a computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. Additionally, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0075] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium storing instructions that may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer) readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0076] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. Obviously, various modifications can be made to these implementations without departing from the scope and broad spirit of the embodiments of the present disclosure as set forth in the appended claims. In cases where the present disclosure refers to some elements in the singular, more than one element may be depicted in the drawings, and the same elements are labeled with the same numbers. Therefore, the present disclosure and the drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for integrated circuit design, comprising: For each design intent in a set of design intents, collecting training data by: Identifying a set of failures expected to occur when the design intent is fabricated, and Recording the failure mode and location of each failure in the set of failures, wherein Creating a separate design layer for each failure mode to mark the locations of failures belonging to the failure mode; And Using the training data by a processor to train a neural network to predict the failure mode and location of failures for a first design intent, the first design intent being different from the design intents in the set of design intents.

2. The method according to claim 1, wherein the first design intent specifies a shape expected to be printed on a wafer.

3. The method according to claim 1, wherein using the training data to train the neural network includes using supervised learning, wherein the design intent is provided as input, and the failure mode and location are provided as the desired output.

4. The method according to claim 1, wherein collecting training data includes: Using lithography verification to identify failure modes in a mask layout; Adjusting a mask enhancement technology (RET) scheme to address the occurrence of the failure modes; And Applying the adjusted RET scheme to the mask layout.

5. The method according to claim 4, wherein each location of a failure is marked by placing a polygon in the design layer near the location of the failure.

6. The method according to claim 5, wherein applying the adjusted RET scheme to the mask layout comprises: Applying the adjusted RET scheme to the area within the polygon corresponding to the failure mode in the design layer.

7. The method according to claim 1, comprising: Using the trained neural network to identify the failure mode and location of failures expected to occur in a design intent; And For each failure, selecting an RET scheme based on the failure mode of the failure, and applying the selected RET scheme to the area around the location of the failure.

8. A non-transitory storage medium storing instructions that, when executed by a processor, cause the processor to: Use a trained neural network to predict the failure mode and location of failures expected to occur when printing a design intent using a lithography process, wherein a separate design layer is created for each failure mode to mark the locations of failures belonging to the failure mode; and For each failure, Select a mask enhancement technology (RET) scheme based on the failure mode of the failure, and Apply the selected RET scheme to the area around the location of the failure.

9. The non-transitory storage medium according to claim 8, comprising instructions that, when executed by the processor, cause the processor to: Collect training data, wherein the training data includes the failure mode and location of each failure in a set of failures identified using a lithography verification tool; and Use the training data to train an untrained neural network to predict the failure mode and location of failures for a given design intent.

10. The non-transitory storage medium according to claim 9, wherein collecting the training data includes: Using the lithography verification tool to identify failure modes in a mask layout; Adjust a mask enhancement technology RET solution to address the occurrence of the failure mode; and Apply the adjusted RET solution to the mask layout.

11. The non-transitory storage medium according to claim 10, wherein each location of the failure is marked by placing a polygon in the design layer near the location of the failure.

12. The non-transitory storage medium according to claim 11, wherein applying the adjusted RET scheme to the mask layout includes: Apply the adjusted RET solution to the area within the polygon corresponding to the failure mode in the design layer.

13. An apparatus for integrated circuit design, comprising: A memory storing instructions; and A processor coupled to the memory and executing the instructions, the instructions when executed causing the processor to: Collect training data, wherein the training data includes the failure modes and locations of failures identified using a lithography verification tool; Obtain a trained machine learning model by training an untrained machine learning model using the training data; Use the trained machine learning model to predict the failure modes and locations of failures expected to occur in the design intent, wherein a separate design layer is created for each failure mode to mark the locations of failures belonging to the failure mode; and For each predicted failure, Select a mask enhancement technology RET solution based on the failure mode of the failure, and Apply the selected RET solution to the area around the location of the failure.

14. The apparatus according to claim 13, wherein collecting the training data includes: Using the lithography verification tool to identify failure modes in the mask layout; Adjust a mask enhancement technology RET solution to address the occurrence of the failure mode; and Apply the adjusted RET solution to the mask layout.

15. The apparatus according to claim 14, wherein training the untrained machine learning model includes using supervised learning, wherein the design intent is provided as an input, and the failure modes and locations of failures are provided as the desired outputs.

16. The apparatus according to claim 15, wherein each location of the failure is marked by placing a polygon in the design layer near the location of the failure.

17. The apparatus according to claim 16, wherein applying the adjusted RET scheme to the mask layout comprises: Apply the adjusted RET solution to the area within the polygon corresponding to the failure mode in the design layer.

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