Method and apparatus for manufacturing an electronic device

Abstract

The present invention discloses a method for manufacturing an electronic device, comprising: forming a continuous carrier tape made of a conductive material, the continuous carrier tape including fingers; molding a plurality of non-conductive substrates on the carrier tape, the molding process defining holes aligned with the fingers; forming traces on the substrates; electroplating the traces; electrically attaching a plurality of components to the traces to form a plurality of devices; and separating one of the devices from the remainder of the carrier tape. The present invention also discloses a device, comprising: a single-piece carrier tape portion having fingers; a substrate molded on the single-piece carrier tape portion, the substrate having holes aligned with the fingers; a seed layer trace located on the substrate; a plated metal trace located on the seed layer trace; and a component electrically attached to at least one plated metal trace.

Description

[0001] This application is a divisional application of an application with the applicant being "Moles Limited", the application date being June 29, 2016, the application number being 201610500213.X, and the invention title being "Lighting Device, Method and Apparatus for Forming a Lighting Device and Manufacturing an Electronic Device". Technical Field

[0002] The present invention relates to electronic devices and the manufacture of such devices. Background Art

[0003] A molded interconnect device ("MID") is a three-dimensional electromechanical component that typically includes a plastic part and electronic circuit traces. A plastic substrate or base is created and circuits and devices are plated, laminated, or implanted on the plastic substrate. MIDs generally have fewer components than conventionally manufactured devices, which results in space and weight savings. Applications of MID devices include mobile phones, automated teller machines, steering wheel assemblies of vehicles, RFID components, lighting devices (light), medical devices, and many consumer products.

[0004] Current processes for manufacturing MIDs include: two-shot molding and laser direct structuring (LDS). Two-shot molding involves using two separate plastic parts, one of which is platable and the other is non-platable. The platable part forms the circuit, while the non-platable part serves the mechanical function and completes the molding. The two parts are fused together and the circuit is formed by electroless plating. The platable plastic is metallized, while the non-platable plastic remains non-conductive. In contrast, LDS involves injection molding, laser activation of plastic materials, and subsequent metallization steps. The laser etches a wiring pattern on the part and prepares the wiring pattern for metallization. For LDS, only a single thermoplastic material is required, thereby making the molding step a one-shot process.

[0005] However, there is a need for an improved system and process for rapidly and efficiently manufacturing three-dimensional structures including a combination of components. In particular, there is a need to increase electronic packaging in a smaller space to incorporate more functions operating at higher speeds, while using less power and reducing heat generation, all of which reduce a manufacturing cost. Summary of the Invention

[0006] The present invention discloses a lighting device, which includes: a base; a light guide tube connected to the base; and a device formed by a dedicated electronic packaging system installed in the base, the dedicated electronic packaging system having at least one light-emitting diode disposed thereon, and the light guide tube being located above the at least one light-emitting diode.

[0007] According to one aspect of the present invention, a method of manufacturing an electronic device is provided, including: forming a continuous carrier tape made of a conductive material, the continuous carrier tape including fingers; molding a plurality of non-conductive substrates on the carrier tape, the molding process defining holes aligned with the fingers; forming traces on the substrates; electroplating the traces; electrically attaching a plurality of components to the traces to form a plurality of devices; and separating one of the devices from the remainder of the carrier tape.

[0008] Wherein, the forming of the traces includes: ablating the substrate with a laser; depositing an ink on the ablated surface; and sintering the ink.

[0009] Wherein, cavities are molded in the substrates such that portions of the carrier tape are exposed.

[0010] The present application also discloses a device, including: a single-piece carrier tape portion having fingers; a substrate molded on the single-piece carrier tape portion, the substrate having holes aligned with the fingers; a seed layer trace located on the substrate; a plated metal trace located on the seed layer trace; and a component electrically attached to at least one of the plated metal traces.

[0011] The device includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high-current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

[0012] Wherein, the component is disposed in a cavity formed in the substrate.

[0013] Wherein, the cavity is formed in the substrate such that a portion of the single-piece carrier tape portion is exposed.

[0014] Wherein, the single-piece carrier tape portion includes metal.

[0015] Wherein, the single-piece carrier tape portion includes a flexible material.

[0016] Wherein, the flexible material includes a flexible polyimide material.

[0017] Wherein, the plated metal trace includes an electroplated metal trace.

[0018] Wherein, the seed layer trace includes sintered ink.

[0019] Wherein, the seed layer trace includes sintered paste.

[0020] According to another aspect of the present invention, there is provided an apparatus including: a single-piece carrier portion having a formed hole; a substrate molded on the single-piece carrier portion, the molded portion having a molded hole that is aligned with the formed hole; conductive traces formed on the substrate by laser and electroplating, at least one of the conductive traces being electrically connected to the carrier portion via the formed hole; and a component electrically attached to at least one of the conductive traces.

[0021] The apparatus includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high-current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

[0022] Wherein, the component is disposed in a recess formed in the substrate.

[0023] Wherein, the recess is formed in the substrate such that a portion of the single-piece carrier portion is exposed.

[0024] Wherein, the single-piece carrier portion includes metal.

[0025] Wherein, the single-piece carrier portion includes a flexible material.

[0026] Wherein, the flexible material includes a flexible polyimide material.

[0027] The present invention also provides a method of manufacturing an electronic device, including: forming a continuous carrier made of a conductive material; molding a plurality of non-conductive substrates on the carrier; forming a plurality of traces on the substrates; electroplating the traces; electrically attaching a plurality of components to the plurality of traces to form a plurality of devices; separating one of the devices from the remainder of the carrier, wherein a plurality of recesses are molded in the substrates such that a portion of the carrier is exposed, and via holes are formed in at least one of the recesses.

[0028] Wherein, the forming of the traces includes: ablating the substrate with a laser; depositing an ink on the ablated surface; and sintering the ink.

[0029] The present invention also provides an apparatus including: a single-piece carrier portion; a substrate molded on the single-piece carrier portion; seed layer traces located on the substrate; plated metal traces located on the seed layer traces; and a component electrically attached to at least one of the plated metal traces, wherein recesses are formed in the substrate such that a portion of the single-piece carrier portion is exposed, and via holes are formed in the recesses.

[0030] Wherein, the device includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high-current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

[0031] Wherein, the component is disposed in a cavity formed in the substrate.

[0032] Wherein, the single-piece carrier portion includes metal.

[0033] Wherein, the single-piece carrier portion includes a flexible material.

[0034] Wherein, the flexible material includes a flexible polyimide material.

[0035] Wherein, the plated metal traces include electroplated metal traces.

[0036] Wherein, the seed layer traces include sintered ink.

[0037] Wherein, the seed layer traces include sintered paste.

[0038] According to another aspect of the present invention, there is provided a device including: a single-piece carrier portion;

[0039] a substrate molded on the single-piece carrier portion; conductive traces formed on the substrate by laser and electroplating; a component electrically attached to at least one of the conductive traces, wherein a cavity is formed in the substrate such that a portion of the single-piece carrier portion is exposed, and via holes are formed in the cavity.

[0040] Wherein, the device includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high-current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

[0041] Wherein, the component is disposed in the cavity formed in the substrate.

[0042] Wherein, the single-piece carrier portion includes metal.

[0043] Wherein, the single-piece carrier portion includes a flexible material.

[0044] Wherein, the flexible material includes a flexible polyimide material.

[0045] The present invention also discloses a lighting device, which is prepared by a process comprising: forming a continuous carrier tape; molding a plurality of substrates on the carrier tape; forming traces on the substrates; electroplating the traces; electrically connecting components to the traces to form a plurality of devices, wherein at least one of the components on each device is a light-emitting diode; separating one of the plurality of devices from the remaining part of the carrier tape to form a single piece; mounting the device in a base having a light guide; and aligning the light-emitting diode and the light guide.

[0046] The present invention also discloses a method for forming a lighting device, a method for manufacturing an electronic device, and a continuous manufacturing system.

[0047] The present invention also discloses a device comprising: a single-piece carrier tape portion; a substrate molded on the single-piece carrier tape portion; seed layer traces located on the substrate; plated metal traces located on the seed layer traces; and a component electrically connected to at least one of the plated metal traces.

[0048] The present invention also discloses a device comprising: a single-piece carrier tape portion; a substrate molded on the single-piece carrier tape portion; a conductive material deposited on the substrate, the substrate having electrical isolation portions formed thereon; and a component electrically connected to at least one of the electrical isolation portions of the material.

[0049] The illustrated embodiments are directed to a dedicated electronic packaging (“ASEP (Application Specific Electronics Packaging)”) system, which enables the manufacture of additional products using a reel-to-reel (continuous flow) manufacturing process as opposed to the “batch” processes currently employed for manufacturing electronic products and MIDs. Through some ASEP embodiments, it is possible to directly integrate connectors, sensors, LEDs, thermal management devices, antennas, RFID devices, microprocessors, memories, impedance control, and multi-layer functionality into a single product.

[0050] One embodiment of the ASEP system relates to a process for creating a device by continuously depositing seed layer traces after molding a substrate and before electroplating. The seed layer of the traces is provided on a surface of the substrate (which can be 3D) in a reel-to-reel manufacturing process. A process for preparing a device preferably includes stamping a flexible carrier tape forming a lead frame, molding a plastic substrate on the carrier tape, depositing a seed layer of traces connected to an internal bus formed by the carrier tape, electroplating the seed layer of the traces to form electronic circuit traces, and component assembly. If desired, a solder mask step can be provided, and this process flow can be carried out before and after the substrate and can also be carried out on the inner layer. These and other aspects and features will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a flow chart of a manufacturing process.

[0052] Figure 1A is a flow chart of further steps of a manufacturing process.

[0053] Figure 2 is a diagram of a device on a carrier tape at different stages of manufacture.

[0054] Figure 3 is a diagram of a complete device separated from a carrier tape.

[0055] Figure 4 is a schematic diagram of a reel-to-reel carrier tape.

[0056] Figure 5 is a flow chart of a multi-laser continuous process for forming an electronic circuit trace on a substrate.

[0057] Figure 6 is a flow chart showing the formation of a component.

[0058] Figures 7 - 12 Shows undergoing Figure 6 An embodiment of a component of the process shown.

[0059] Figure 13 Shows a perspective view of an automotive lighting device formed by the manufacturing process.

[0060] Figure 14 is an exploded perspective view of the automotive lighting device.

[0061] Figure 15 is a cross-sectional view of a portion of a carrier tape and a molded substrate, and shows a component seated thereon.

[0062] Figure 16 An alternative cross-sectional view of a carrier tape and a molded substrate part.

[0063] Figure 17 A top view showing an example of an ASEP application with a polyimide flexible core for reel-to-reel manufacturing, where bare dies, active devices, and passive devices are encapsulated in the grooves of a molded and imaged substrate.

[0064] Figure 18 Shows Figure 17 A perspective view of an example of an ASEP application. Detailed Description

[0065] The present invention is directed to a dedicated electronic packaging ("ASEP") system and method. The process is beneficial for the formation of devices such as: printed circuit boards, flexible circuits, connectors, thermal management features, EMI shields, high current conductors, RFID devices, antennas, wireless power sources, sensors, MEMS devices, LEDs, microprocessors, and memories, ASICs, passive or other electrical devices, and electromechanical devices.

[0066] A flow diagram of an embodiment for an ASEP manufacturing process shows in Figure 1 while a flowchart shows in Figure 6 In. In Figure 1 In step 1 of, a punched carrier tape 40 is made of a suitable metal or other material. Next, in step 2, an independent plastic substrate 42 is overmolded onto the punched carrier tape 40. The above two steps are referenced at reference numeral 100 in Figure 6 . A seed layer of trace 44 is then deposited on the surface of the plastic substrate 42 in Figure 1 step 3 of and is referenced at reference numeral 110 in Figure 6 . It can be appreciated from the view provided in step 3a that this allows an internal bus 43 formed by the carrier tape 40 to be electrically connected to the seed layer of the trace 44 on the surface of the plastic substrate 42. In Figure 1 step 4 of, the seed layer of the electroplated trace 44 is electroplated by applying a voltage potential to the carrier tape 40 (which is connected to the seed layer of the trace 44 via the internal bus 43), and this is referenced at reference numeral 120 in Figure 6 to form a part 46, and then the part 46 is advanced through an electroplating bath. A solder mask 48 can be applied in step 5. Component assemblies appear in Figure 1in step 6 of and referenced at reference numeral 130 in Figure 6 wherein component 50 is connected to substrate 42 to form a complete device. If component 50 is soldered, a reflow soldering process may be employed to form the complete device. If component 50 is wire bonded, the solder mask step may be eliminated. In a preferred embodiment, the device is manufactured using a reel-to-reel technique. The carrier holes 52 on the sides of carrier tape 40 are shown in the diagrams of each step, and these carrier holes 52 move carrier tape 40 along a manufacturing line in a continuous process. Figure 1 The flowchart of

[0067] In step 1, carrier tape 40 is stamped / formed. Carrier tape 40 may be stamped / formed from a metal (such as a copper alloy (or any other desired conductive material)) to form a lead frame 54, or carrier tape 40 is stamped / formed from a polyimide flexible material (such as a flexible circuit having one or more layers (in some embodiments, the flexible material may have four or more layers)) to form a lead frame 54. As Figure 1 shown, lead frame 54 may have fingers 56 which have holes 58 disposed thereon.

[0068] In step 2, substrate 42 is molded over lead frame 54. Holes 60 may be provided to align with holes 58 of fingers 56.

[0069] As Figure 1 shown in step 3 of Figure 1The flowchart only shows the manufacturing process applied to one side of the substrate 42, but the manufacturing process can be equally applied to the back side and inner layers of the substrate 42. It should be noted that the use of a metal carrier tape 40 is most suitable for a structure that has only two layers (on both sides of the plastic substrate 42) in addition to the metal carrier tape. If additional layers are needed, it is confirmed that using a carrier tape 40 formed of a flexible polyimide is more beneficial for allowing the addition of additional inner layers. More than one carrier tape 40 can be provided on the substrate 42.

[0070] In one embodiment, the carrier tape 40 is stamped / formed (step 1) from a flexible material (such as a flexible circuit having one or more layers (in some embodiments, the flexible material can have four or more layers)) to form a lead frame 54. In one embodiment, the carrier tape 40 is stamped / formed from a copper alloy (or any other desired conductive material) to form a lead frame 54. The molding step (step 2) can rely on an injection or bi-injection process or other traditional molding processes. For the subsequent molding process, a lithographic patterning or laser patterning (step 3) is used to form a pattern, thereby forming a seed layer of the trace 44. Subsequently, the seed layer of the trace 44 is electroplated (step 4) to form an electronic circuit trace 62. The electroplating step (step 4) can include a multi-step plating process, and the multi-step plating process includes copper or other suitable materials of additional thickness.

[0071] In another embodiment, techniques such as those included in the technology of Mesoscribe Technologies can be used to deposit a full thickness of copper (or other conductive material) on a surface. A picosecond laser can then be used to isolate the desired circuit pattern in the conductive material. This method can be used to replace the plating step as described elsewhere in this document, or for occasions where one or more electroplated metals are needed in addition to plating.

[0072] Figure 2 Shows a device 22 formed on a carrier tape 40 at various stages of manufacture. First, a formed carrier tape 40 without a molded substrate 42 shown at A is shown. A molded substrate 42 having electronic circuit traces 62 is shown at B, pin contacts are added at C, additional circuit metallization is shown at D, and a complete device 22 is shown at the reference numeral E. The complete device 22 can be separated from the connected carrier tape 40 to make the device 22 single, as Figure 3 shown. Although the carrier tape 40 is shown on one side of the device 22 in Figure 2 , carrier tapes 40 can be provided on both sides of the device 22.

[0073] As previously mentioned, the process of forming an ASEP device 22 is preferably continuous for reasons of speed and cost. Such asFigure 4 The reel-to-reel technology shown schematically in allows the formation of the device 22 while being connected to a carrier tape 40 that is unreeled from a material source reel 68a and then collected on a second reel 68b. It can be appreciated that several process steps are carried out between the two reels 68a, 68b.

[0074] Figure 5 An embodiment of a continuous process is shown, which can utilize a multi-laser process for creating an electronic circuit trace 62 on a substrate 42. The substrate 42 can be molded in a standard mold using a resin, the resin can be laser-activated or the substrate 42 can be a simple plastic. It can be appreciated that the cross-section of the substrate 42 is shown in Figure 5 In step 9, a laser 70 is used to ablate the surface of the substrate 42 to form a pattern 66. The desired interconnect pattern 66 is etched onto the molded substrate 42 using the laser 70. In an LDS process, the laser-activated material includes an additive that is activated by a reaction induced by the focused beam from the laser 70. By burning the polymer matrix and activating the metal within the resin, the laser 70 forms a pattern 66 that allows the attachment of a metal during a subsequent electroless plating (shown in step 10) to form the electronic circuit trace 62. It is also feasible that the pattern 66 can be applied by an inkjet process that guides a suitable plating onto the activated surface, so that the plating attaches to form the electronic circuit trace 62. Since electroless plating is often slow, it is desirable to place the part 46 in an electrolytic plating bath.

[0075] If the process is not an LDS process, then the laser 70 will ablate the surface of the substrate 42 and simply remove some material. It has been found that the removal of some of the substrate 42 creates a rough channel 72, and thus the rough channel 72 can better directly receive a conductive ink or conductive paste 74. In step 10, a conductive ink or conductive paste 74 can be applied using an inkjet, aerosol or screening process to provide a circuit trace pattern.

[0076] The ink or paste 74 may have high conductivity and a low binder content to increase its conductivity. The ink or paste 74 should also have high chemical stability and a viscosity compatible with the desired dispense method in the plating bath. The deposited ink or paste 74 is then sintered by a laser or flash heat 76 as shown in step 11. The sintering step (step 11) helps ensure that the ink or paste 74 adheres to the substrate 42 and also ensures that the ink or paste 74 is conductive (since it is typically the case that the conductivity of the applied ink or paste 74 is not sufficient to allow an electrical potential to be applied across the electronic circuit trace 62). It can be appreciated that the electroless plating process may skip the sintering step (step 11) since sintering of the electroless plating layer is not required. Finally, in step 12, electroplating is performed to deposit a desired thickness of copper (or other desired conductive element) to form the electronic circuit trace 62. The increased thickness results in increased current-carrying capacity, and generally, the electroplating process tends to form a material with high conductivity, so the performance of the resulting electronic circuit trace 62 will be improved.

[0077] A preferred system and process utilize multiple lasers 70, 76 integrated into a single station. A first laser 70 ablates the surface (step 9) while a second laser 76 sinters the material (step 10) immediately after the conductive ink or paste 74 is applied in step 9. This design saves space in the manufacturing process and helps ensure proper registration of the lasers 70, 76. Additionally, integrating multiple lasers 70, 76 into a single station enables faster processing of the material.

[0078] In another embodiment, a pattern 66 on a surface of the substrate 42 can be prepared using a laser, a plasma process (which can be a vacuum or atmospheric process), a UV process, and / or a fluorination process. Once the surface has the pattern 66 formed thereon by the chosen process, the pattern 66 can be inked or pasted by the desired process and then sintered. The sintering can be accomplished by a laser or other desired process that provides sufficient heat energy to melt the nanoparticles in the ink. Preferably, the pattern 66 is electrically connected to the carrier tape 40 so that an electrical potential can be placed across the pattern 66 and the pattern 66 can be electroplated to form the circuit trace 62. The above process can be applied to syndiotactic polystyrene (SPS) provided by XAREC and provides good retention of the circuit trace 62 to the surface.

[0079] Other materials suitable for additive manufacturing are liquid crystal polymers (LCPs) because many LCPs have good heat resistance and dimensional stability suitable for molding. It has been found that for LCP materials, if the surface is pretreated using a laser process (compared to other processes), the retention of the circuit traces 62 will be surprisingly improved. Once the surface has been roughened by the laser, a conductive ink can be deposited onto the laser-marked pattern using a variety of systems, including an nScrypt micro-pump, an Optmec aerosol, a screen printing process, or an inkjet process. The ink can then be sintered using a laser, a photon rapid curing process, a conventional thermal exposure for copper-based inks, or a formic acid environment in an oven.

[0080] Another alternative method of setting the circuit traces 62 on the LCP is to use a plasma process to directly deposit copper onto the surface. The resulting circuit traces 62 are not as conductive as a pure copper trace, but are sufficient to allow a voltage potential to be placed across the circuit traces 62. One problem with using plasma is that the pattern 66 tends to be finer than desired. However, it has been determined that by using a laser, such as a picosecond laser, a coarse pattern can be formed and then further refined, and the laser can be used to ablate away unwanted copper from the surface without significantly affecting the surface. The laser thus removes the edges to form a pattern 66 that provides the desired functionality. It can be appreciated that the plasma process can avoid the need for a sintering or any pretreatment step, and the copper material is deposited directly onto the surface via the plasma process at a much lower cost than traditional conductive inks. Once the pattern 66 has been formed, it can be electroplated as described above to form the circuit traces 62.

[0081] From Figures 7 - 12 It can be appreciated that the disclosed processes allow for structures of interest. Figure 7 A guide frame 54 is shown, and in a manufacturing process where the guide frame 54 is formed as part of a carrier tape 40, the guide frame 54 can be transported in a reel-to-reel manner (from reel 68a to reel 68b). Specifically, the guide frame 54 is formed as part of the carrier tape 40 and can then be insert-molded into a substrate 42, such as Figure 8 as shown, and then processed as described above to set a pattern 66 on a surface of the substrate 42, such as Figure 9As provided. It should be noted that the guiding frame 54 has fingers 56, and holes 58 are provided in the fingers 56. These holes 58 are aligned with access apertures in the molding material forming the substrate 42. It has been confirmed that this facilitates electrical connection to subsequently formed circuit traces and enables the application of a voltage across the guiding frame 54 to provide a voltage on the electronic circuit traces, and thus facilitates electroplating. Therefore, the use of the holes 60 in the guiding frame 54 is beneficial for manufacturing purposes.

[0082] As Figure 10 and Figure 11 shown, the substrate 42 can be soldermasked, and the components 50 are soldered to the electronic circuit traces 62, and the resulting device 22 can then be separated from the carrier tape 40 as a single piece. Alternatively or in addition to soldermasking / soldering, the components 50 can be wirebonded to the electronic circuit traces 62. As Figure 12 shown, the resulting device 22 can be an integrated device 22 formed generally in an additive manner. Since electroplating is a relatively efficient process, a reciprocating path through a plating bath with a relatively short dwell time of less than thirty minutes may be sufficient, thus making the total process less than one hour while enabling a complex set of geometries and configurations. Naturally, adding additional plating layers may increase the total time of the manufacturing process, but still significantly reduces the end-to-end total time compared to traditional processes using PCBs.

[0083] In an embodiment where the manufacturing process is applied to inner layers, first, appropriate traces are provided on the outer surface of a first layer of the substrate 42, and if desired, components can be provided on the outer surface of the first layer of the substrate 42 and soldered or wirebonded to become electrically connected to these traces. Then, a second layer of the substrate 42 can be molded over all or part of the outer surface and the components. Additional traces can be provided on the second layer as described above and then additional components can be placed on the new surface and these components can then be connected to these traces in the manner described above. More layers can be added as needed, noting that each layer can have a different topology. Thus, without limitation, a first layer can be relatively flat / plane while a second layer can be formed on top of the first layer in a way that provides a non-planar surface. Naturally, the reverse can also be done. The resulting structure can thus have a three-dimensional shape of the inner layer, which varies as needed and may not match the outer layer.

[0084] As Figure 15As shown, in one embodiment, when the substrate 42 is molded onto the carrier tape 40, the substrate 42 is discontinuous such that recesses 80 are formed in the substrate 42 and the material of the carrier tape 40 is exposed. The component 50 is disposed directly on the exposed outer surface of the carrier tape 40. The component 50 can be wire bonded to the electronic circuit traces 62 formed on the substrate 42 via a wire bonding portion 82. The carrier tape 40 serves as a heat sink for the component 50. A non-conductive material 84 (such as an adhesive) can be disposed over the component 50 and the wire bonding portion 82; this non-conductive material 84 then forms part of the outer surface of the substrate 42. Suitable non-conductive materials 84 include, but are not limited to, a non-conductive adhesive.

[0085] As Figure 16 shown, in one embodiment, when the substrate 42 is molded onto the carrier tape 40, the substrate 42 is discontinuous, whereby vias 86 are formed in the substrate 42 to expose the carrier tape 40. The vias 86 are electroplated to form an electrically conductive path between the traces 62 and the carrier tape 40. The component 50 can be disposed on the vias 86. The component 50 can be wire bonded to the electronic circuit traces 62 via a wire bonding portion 82. The carrier tape 40 again serves as a heat sink for the component 50 passing through the vias 86. A non-conductive material 84 (such as an adhesive) can be disposed over the component 50 and the wire bonding portion 82; this non-conductive material 84 then forms part of the outer surface of the substrate 42. Suitable non-conductive materials 84 include, but are not limited to, a non-conductive adhesive. If desired, the vias 86 can be formed within a recess 80 formed in the substrate 42 and the component 50 is disposed within the recess 80.

[0086] The various embodiments described above are illustrated with respect to the device 22; however, these are only a few examples of devices that can be formed using the ASEP technology. With ASEP, it is possible to directly integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memories, impedance control, and multi-layer functionality into a product.

[0087] As Figure 13 shown, one example is a lighting device 20 that includes a device such as the device 22 that can be formed using the ASEP technology. Although the lighting device 20 is intended for use in a vehicle or automobile in the following examples, it can be just a general-purpose lighting device. For example, the lighting device 20 can be used for indoor or outdoor lighting, for use in or at an exhibition, for personal or apparel use, or as part of a mobile personal device. The possible uses of the lighting device 20 are numerous, especially considering use in or with equipment and machinery (as an example).

[0088] The automotive lighting device 20 includes a base 24, the device 22, and a light guide 28. The base 24 can be formed as Figure 14The two parts 24a, 24b shown. The base 24 has: a wall portion 32 forming a channel 34 through the wall portion 32; and a hole 36 extending through the wall portion 32 and communicating with the channel 34. The hole 36 can be transverse to the channel 34. A device 22 formed by an ASEP manufacturing process is installed in the channel 34 of the base 24. The light guide 28 extends through the hole 36 in the base 24 and is installed above a light-emitting diode (LED) 38, and the light-emitting diode 38 is formed as a component 50 (or one of the components 50) on the device 22 as described herein.

[0089] Figure 1 And Figure 1A Combined with providing a representative illustration of the automotive lighting device 20 being prepared and the next steps of preparing the automotive lighting device 20. Figure 1A Steps 7 and 8 and Figure 6 The reference numeral 140 in the figure shows the device 22 separated into a single piece from other devices and assembled with the base 24 and the light guide 28. See the above Figure 1 And Figure 6 For a more detailed description. After the device 22 is formed, the device 22 is installed in the channel 34 of the base 24 and the two parts 24a, 24b of the base 24 are assembled together. The pin contacts 64 remain exposed. The light guide 28 is installed through the hole 36 in the base 24 and is disposed above the LED 38. This completes the assembly of the automotive lighting device 20. The automotive lighting device 20 is now ready to be assembled with a vehicle.

[0090] As mentioned above, various embodiments are described herein and various examples of devices that can be formed using ASEP technology are provided. In another example, a multilayer flexible circuit can be reel-to-reel insert molded with a high-temperature / 3D substrate such as LCP or SPS. Via holes can be molded on the surface of the substrate, and the via holes will form an electrical path between the traces printed on the plastic layer and the inner layer surface of the flexible circuit. These traces form a "bus bar" on the carrier tape, and the carrier tape can electroplate the traces after an inkjet-deposited conductive layer is coated on the device. Although the conductive traces of Cu or Ag inks with nanoparticles are very thin and not highly conductive compared to bulk metal, their conductivity is already high enough to provide a seed layer for the traces printed on the surface.

[0091] Although inkjet technology has limitations for printing circuit patterns onto 3D surfaces, the technology does have a depth of field of approximately 2 mm, which enables the printing of circuit patterns into grooves, cavities, and bare silicon die can be placed on small protruding features. When the die is wire bonded to a trace that travels into a cavity, an electrical connection is formed between the die and the system, which eliminates the need for traditional silicon packaging. By not having to use traditional packaged silicon devices, the size of the final product can be significantly reduced, and the cost of silicon packaging is eliminated. Additionally, circuit patterns with 50-micron lines and spaces can be reliably printed using inkjet technology.

[0092] Unlike traditional PCBs or flexible materials that use 400 gallons of water per square meter in traditional subtractive manufacturing processes, the placement of traces on the surface of an ASEP product is additive. The only process step that uses water is a rinse process immediately after electroplating. A fully additive process that produces circuits with the same conductivity, metal type, and surface finish as standard circuit boards and reduces water usage is highly desirable for sustainable electronics manufacturing.

[0093] Figure 17 (Top view) and 18 (perspective view) illustrate a conceptual design of an ASEP application to a polyimide flexible core for reel-to-reel manufacturing of bare die, active devices, and passive devices, and the bare die, active devices, and passive devices are encapsulated into recesses of a molded and imaged substrate. After the devices are wire bonded or soldered in place, they can be "glob topped" with a non-conductive material. If desired, applications can be developed for electronics that are not visible within the assembly.

[0094] The advantages of such a method are that it can significantly reduce the size and cost of electronics. By printing traces into cavities in which bare die are placed, die-on-die attachment, and wire bonding the die to electroplated traces, the bare die can be directly integrated into a plastic housing. After "glob topping" the components, one may not even know that there is electronics within the device. Additionally, for example, by using multiple flexible inner layers for the device, a very high-density electronics can be formed; components can be located on the front and back sides of the part.

[0095] All references cited herein (including publications, patent applications, and patents) are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and the entire content of each reference were set forth.

[0096] The terms "a" for consonants, "an" for vowels, "the" for definite articles, "at least one", and similar referents used in the context of describing the present invention (especially in the context of the following claims) will be construed to cover both the singular and the plural, unless otherwise specified herein or clearly contradicted by the context. The term "at least one" followed by a list of one or more items (e.g., "at least one of A and B") will be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise specified herein or clearly contradicted by the context. The terms "comprising", "having", "including", and "containing" will be understood to be open-ended terms (i.e., meaning "including but not limited to"), unless otherwise specified. References to ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise specified herein, and each separate value is incorporated into the specification as if it were individually recited herein. All processes described herein may be performed in any suitable order, unless otherwise specified herein or clearly contradicted by the context. Any and all illustrative or exemplary language (e.g., "such as") provided herein is merely for the purpose of better illuminating the present invention and does not impose a limitation on the scope of the present invention, unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the present invention.

[0097] Preferred embodiments of the present invention are described herein, including the best mode known to the inventors for practicing the present invention. It will be apparent to those of ordinary skill in the art that variations of these preferred embodiments may be made by reading the foregoing description. The inventors expect those skilled in the art to appropriately employ such variations, and the inventors anticipate that the present invention will be practiced otherwise than as specifically described herein. Accordingly, the present invention includes all modifications and equivalent structures to the subject matter of the appended claims permitted by applicable law. Additionally, any combination of the above-described components in all possible variations is included within the present invention, unless otherwise specified herein or clearly contradicted by the context.

Claims

1. An electronic device, comprising: A single-piece carrier tape portion; A substrate, molded on the single-piece carrier tape portion; Conductive traces, formed on the substrate by laser and electroplating; And A component, electrically attached to at least one of the conductive traces, wherein the component is disposed in a cavity formed in the substrate, the cavity is formed in the substrate such that a portion of the single-piece carrier tape portion is exposed, and a via hole is formed in the cavity, The via hole is electroplated to form a conductive path between the trace and the carrier tape portion, and the component is disposed on the conductive path.

2. The electronic device according to claim 1, wherein, The device includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high-current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

3. The electronic device according to claim 1, wherein, The single-piece carrier tape portion includes metal.

4. The electronic device according to claim 1, wherein, The single-piece carrier tape portion includes a flexible material.

5. The electronic device according to claim 4, wherein, The flexible material includes a flexible polyimide material.

6. A method of manufacturing an electronic device, comprising: Forming a continuous carrier tape made of a conductive material; Molding a plurality of non-conductive substrates on the carrier tape; Forming a plurality of traces on the substrates; Electroplating the traces; Electrically attaching a plurality of components to the plurality of traces to form a plurality of devices; Separating one of the devices from the remaining portion of the carrier tape to form a single piece, wherein a plurality of cavities are molded in the substrate such that a portion of the carrier tape is exposed, and via holes are formed in the cavities, Electroplating the via holes to form a conductive path between the traces and the carrier tape, and the components are disposed on the conductive path.

7. According to the method of manufacturing an electronic device of claim 6, wherein, The forming of the traces includes: Burning the substrate with a laser; Depositing an ink on the burned surface; and Sintering the ink.

8. An electronic device, comprising: A single-piece carrier tape portion; A substrate, molded on the single-piece carrier tape portion; Seed layer traces, located on the substrate; Plated metal traces, located on the seed layer traces; And A component, electrically attached to at least one of the plated metal traces, wherein a cavity is formed in the substrate such that a portion of the single-piece carrier tape portion is exposed, and the component is disposed in the cavity, a via hole is formed in the cavity, The via hole is electroplated to form a conductive path between the plated metal trace and the carrier tape portion, and the component is disposed on the conductive path.

9. The electronic device according to claim 8, wherein, The device includes at least one of a printed circuit board, a flexible circuit, a connector, a thermal management device, an EMI shield, a high current conductor, an RFID device, an antenna, a wireless power device, a sensor, a MEMS device, an LED device, a microprocessor, a memory device, an ASIC, a passive device, an impedance control device, and an electromechanical device.

10. The electronic device according to claim 8, wherein, the single-piece carrier portion includes metal.

11. The electronic device according to claim 8, wherein, the single-piece carrier portion includes a flexible material.

12. The electronic device according to claim 11, wherein, the flexible material includes a flexible polyimide material.

13. The electronic device according to claim 8, wherein, the plated metal traces include electroplated metal traces.

14. The electronic device according to claim 8, wherein, the seed layer traces include sintered ink.

15. The electronic device according to claim 8, wherein, the seed layer traces include sintered paste.

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