Systems and methods based on chip-based relay protection devices

Abstract

This application relates to a system, relay protection method, storage medium, and computer program product based on a chip-based relay protection device. The system based on the chip-based relay protection device includes a hierarchical structure from bottom to top: a front-end processing layer, a driver layer, an operation layer, and an application layer. The front-end processing layer includes programmable logic circuits integrated within the chip; the driver layer includes multiple peripheral standard driver interfaces for driver communication with external devices, shared and invoked by the protection core and management core within the chip; the operation layer includes a memory management module, a first interface module, and a first task scheduling module suitable for the protection core, and also includes a second interface module and a second task scheduling module suitable for the management core; the application layer includes a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core. This system based on the chip-based relay protection device can improve the working efficiency of the chip-based relay protection device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power grid, in particular to a system based on a chip-based relay protection device, a relay protection method, a storage medium and a computer program product. BACKGROUND

[0002] The relay protection device refers to a kind of anti-accident automatic device installed on each element of entire power system, when specified area in power system fails, it can disconnect fault equipment in very short time (such as tens of milliseconds), ensure normal operation of the remaining part, avoid large-area power failure.

[0003] The initial relay protection device is mainly composed of electromechanical relay, with the development of electronic computer technology, especially the application of microcomputer and microprocessor, computer relay protection device gradually miniaturizes, safety, intelligent, and then chip-based relay protection device appears.

[0004] Current chip-based relay protection device is generally multi-core heterogeneous architecture, including SMP (Symmetrical Multi-Processing, symmetric multi-processing) architecture and AMP (Asymmetric Multi-Processing, asymmetric multi-processing) architecture, in dual-core AMP architecture, the tasks executed by protection core and management core are independent of each other, but there are sharing links in resource calling, driver calling and other aspects, which will lead to the occupation of critical resources and reduce the working efficiency of chip-based relay protection device. SUMMARY

[0005] Therefore, it is necessary to provide a system based on chip-based relay protection device, a relay protection method, a storage medium and a computer program product, which can improve the working efficiency of chip-based relay protection device.

[0006] A system based on chip-based relay protection device, characterized in that the system comprises a hierarchical structure from bottom to top, a front-end processing layer, a driver layer, an operation layer and an application layer, wherein:

[0007] The front-end processing layer comprises programmable logic circuit integrated in the chip, for data preprocessing of power data to obtain preprocessed data, the preprocessed data is shared and called by protection core and management core in the chip, wherein the protection core is in naked running mode, and the management core runs operating system;

[0008] The driver layer comprises a plurality of peripheral standard driver interfaces, for driving communication with external devices, and shared and called by protection core and management core in the chip;

[0009] The operation layer includes a memory management module, a first interface module, and a first task scheduling module suitable for the protection core, and also includes a second interface module and a second task scheduling module suitable for the management core. The first interface module and the second interface module are both used to call the front-end processing layer and the driver layer. The first task scheduling module is used to call the first application algorithm module in the application layer to perform real-time control tasks. The second task scheduling module is used to call the second application algorithm module in the application layer to perform management communication tasks.

[0010] The application layer includes a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core, wherein the first application algorithm module is used to perform real-time control tasks and the second application algorithm module is used to perform management communication tasks.

[0011] In one embodiment, the memory management module is used to divide the storage module in the chip-based relay protection device into a Linux private memory partition used by the management core, a BM private memory partition used by the protection core, and a shared memory partition, and control each memory partition to interlock, so as to ensure that the memory data reading can be performed without interference when the protection core and the management core are running together.

[0012] In one embodiment, when the load information of the protection core meets the high load condition, the protection core is used to transfer the software tasks in the first application algorithm module that meet the low priority condition to the operating system in the management core through the shared memory and system bus, so that the operation layer of the management core can execute the transferred software tasks.

[0013] In one embodiment, for the front-end processing layer, driver layer, operation layer and application layer in the system, each layer embeds a corresponding self-test function through a standardized interface, so that the upper layer can perform software testing on the lower layer through the corresponding self-test function.

[0014] In one embodiment, the plurality of peripheral standard driver interfaces include a GP bus driver unit, an ACP bus driver unit, an SPI / QSPI driver unit, an I2C driver unit, an ADC driver unit, a serial port driver unit, an Ethernet driver unit, and a temperature monitoring unit, wherein:

[0015] The GP bus driver unit is used for medium-speed communication between at least one of the protection cores and management cores and the front-end processing layer.

[0016] The ACP bus driver unit is used for high-speed communication between at least one kernel in the protection kernel and management kernel and the front-end processing layer.

[0017] The SPI / QSPI driver unit is used to connect to an external FLASH memory;

[0018] The I2C driver unit is used to connect external EEPROM and RTC devices;

[0019] The ADC driver unit has a built-in ADC module for measuring operating voltages at various levels and monitoring status.

[0020] The serial port driver unit is used to initialize the UART serial port and perform internal debugging;

[0021] The Ethernet driver unit is used for initializing the corresponding Ethernet interface in the kernel;

[0022] The temperature monitoring unit is used to connect an external temperature sensor to monitor the temperature status.

[0023] In one embodiment, the first application algorithm module includes:

[0024] The protection configuration unit is used to schedule two sets of protection devices to perform protection actions;

[0025] The trip logic unit is used to issue a trip command when two sets of protection devices simultaneously meet the protection action requirements, thereby driving the local DO board to open the node.

[0026] In one embodiment, the second application algorithm module includes:

[0027] The message transceiver unit is used for communication with a variety of general-purpose industrial equipment;

[0028] The remote adjustment unit is used to control the opening and closing of the interrupt controller using a passive contact method;

[0029] The remote signaling unit is used to convert the closing or opening of relay contacts into low-level or high-level signals using a passive contact method, and send them to the chip-based relay protection device.

[0030] Telemetry units are used for acquiring active and reactive power data from transformers, active power data from lines, bus voltage and line current data, temperature, pressure, flow rate data, frequency data, and other analog signal data.

[0031] The remote control unit is used to control the raising and lowering adjustment of the taps of the on-load tap-changing transformer using a passive contact method.

[0032] The fault analysis unit is used to acquire fault data and perform equipment fault diagnosis and fault data analysis based on the fault data.

[0033] In one embodiment, the front-end processing layer includes a network unit, a storm suppression unit, a packet distribution unit, an alarm module unit, a decoding unit, a low-pass filtering unit, an interpolation synchronization unit, and a configuration module unit, wherein:

[0034] The network unit is a standard Ethernet IP module used to support network protocols;

[0035] The storm suppression unit is used to filter out invalid packets;

[0036] The message distribution unit is used to identify messages based on the Ethernet frame field and the application identifier;

[0037] The alarm module unit, based on application identifiers, is used to perform statistics and alarms on subscribed messages;

[0038] The decoding unit is used to implement message parsing function;

[0039] The low-pass filtering unit is used to perform low-pass filtering on SV data;

[0040] The interpolation synchronization unit is used to process SV data;

[0041] The configuration module unit is used to configure network storm suppression parameters, SV parameters, and packet processing parameters.

[0042] The aforementioned system based on a chip-based relay protection device comprises a hierarchical structure from bottom to top: a front-end processing layer, a driver layer, an operation layer, and an application layer. The front-end processing layer includes programmable logic circuits integrated within the chip, used to preprocess power data to obtain preprocessed data, which is shared and accessed by the protection core and management core within the chip. The driver layer includes multiple peripheral standard driver interfaces for driver communication with external devices, shared and accessed by the protection core and management core within the chip. The operation layer includes a memory management module, a first interface module, and a first task scheduling module suitable for the protection core, and also includes a second interface module and a second task scheduling module suitable for the management core. The application layer includes a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core, wherein the first application algorithm module is used to execute real-time control tasks, and the second application algorithm module is used to execute management communication tasks. In this way, the system based on chip-based relay protection devices is divided into a bottom-up hierarchy: front-end processing layer, driver layer, operation layer, and application layer. The protection core and management core independently run the functional modules in their respective operation and application layers, avoiding resource contention. The functional modules in the front-end processing layer and driver layer are common resource modules, and both the protection core and management core can share and call the functional modules in the front-end processing layer and driver layer. This hierarchical design can functionally divide the chip-based relay protection device system, which is beneficial for the development and maintenance of chip-based relay protection software, and can also effectively share knowledge and improve the working efficiency of chip-based relay protection devices.

[0043] A relay protection method, comprising:

[0044] The programmable logic circuit is used to preprocess the power data collected from the target power equipment to obtain preprocessed data.

[0045] The first application algorithm module performs a protection function logic judgment on the preprocessed data;

[0046] If the protection function logic determines that the target power equipment is faulty, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0047] The second application algorithm module stores and reports the relevant data involved in the trip protection operation.

[0048] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0049] The programmable logic circuit is used to preprocess the power data collected from the target power equipment to obtain preprocessed data.

[0050] The first application algorithm module performs a protection function logic judgment on the preprocessed data;

[0051] If the protection function logic determines that the target power equipment is faulty, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0052] The second application algorithm module stores and reports the relevant data involved in the trip protection operation.

[0053] A computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0054] The programmable logic circuit is used to preprocess the power data collected from the target power equipment to obtain preprocessed data.

[0055] The first application algorithm module performs a protection function logic judgment on the preprocessed data;

[0056] If the protection function logic determines that the target power equipment is faulty, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0057] The second application algorithm module stores and reports the relevant data involved in the trip protection operation.

[0058] The aforementioned relay protection method, storage medium, and computer program product preprocess the power data collected from the target power equipment using programmable logic circuits to obtain preprocessed data. A first application algorithm module then performs protection function logic judgment on the preprocessed data. If the protection function logic judgment determines that the target power equipment is faulty, a first task scheduling module calls the first application algorithm module to issue a trip command to the interrupt controller, thereby controlling the interrupt controller to disconnect the target power equipment from the power network. In this way, after the logic judgment is completed in the protection core, the first task module of the protection core calls the first application algorithm module to issue the trip command, saving communication time between units and quickly achieving the goal of protecting other power equipment components, thus improving the working efficiency of the chip-based relay protection device. Furthermore, a second application algorithm module stores and reports relevant data involved in the trip protection operation, providing a basis for subsequent accident analysis. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of a system based on a chip-based relay protection device in one embodiment;

[0061] Figure 2 This is a schematic diagram of the hierarchical structure of a system based on a chip-based relay protection device in another embodiment;

[0062] Figure 3 This is a flowchart illustrating a relay protection method in one embodiment.

[0063] Explanation of reference numerals in the attached figures: 100 - System based on chip-based relay protection device, 101 - Application layer, 102 - Operation layer, 103 - Driver layer, 104 - Front-end processing layer. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0070] As described in the background section, existing chip-based relay protection devices suffer from low operating efficiency. The inventors have discovered that this problem arises because, although the protection core and management core in the relay protection chip are independent of each other, there are shared links in resource access and driver access, which can easily lead to resource contention and thus reduce the operating efficiency of the relay protection chip.

[0071] For the reasons mentioned above, the present invention provides a system based on a chip-based relay protection device.

[0072] In one embodiment, such as Figure 1 As shown, the system based on chip-based relay protection devices includes a hierarchical structure from bottom to top: a front-end processing layer, a driver layer, an operation layer, and an application layer, wherein:

[0073] The front-end processing layer includes programmable logic circuits integrated inside the chip, which are used to preprocess power data to obtain preprocessed data. The preprocessed data is shared and called by the protection core and management core in the chip. The protection core runs in a bare-metal mode, while the management core runs an operating system.

[0074] The driver layer includes multiple peripheral standard driver interfaces for driver communication with external devices, which can be shared and called by the protection core and management core in the chip.

[0075] The operation layer includes a memory management module, a first interface module, and a first task scheduling module for the protection core, and also includes a second interface module and a second task scheduling module for the management core. The first interface module and the second interface module are used to call the front-end processing layer and the driver layer. The first task scheduling module is used to call the first application algorithm module in the application layer to perform real-time control tasks. The second task scheduling module is used to call the second application algorithm module in the application layer to perform management and communication tasks.

[0076] The application layer includes a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core. The first application algorithm module is used to perform real-time control tasks, and the second application algorithm module is used to perform management communication tasks.

[0077] The protection core and management core physically share a 4GB address space, with each core able to access the entire address space. The protection core acts as the master core, and the management core as the slave core. Both the master and slave cores operate their own L1 cache (Level 1 cache) address spaces, accessing only their own. The two cores share resources such as the interrupt controller, 512KB of L2 cache, SCU (Snoop Control Unit), and program FLASH (one of the storage chips). The master core manages these shared resources, while the slave core only has usage rights. High-speed data sharing is achieved without special cache operations in the dual-core software. Furthermore, only the master core has configuration and management permissions for shared resources, effectively ensuring device security. The dual-core architecture uses DDR (Double Data Rate) for data sharing, offering stronger anti-interference capabilities compared to multi-chip architectures.

[0078] In one embodiment, the first interface module is uniformly encapsulated so that the internal application software can be ported to different hardware devices. The hardware device resources that the second interface module needs to call include at least one of FLASH, EEPROM (Electrically Erasable Programmable Read-Only Memory), and ADC (Analog-to-Digital Converter).

[0079] In one embodiment, if an emergency occurs outside the system, inside the system, or in the current program during the operation of the chip-based relay protection device, the first task scheduling module immediately suspends the current program and automatically switches to the corresponding processing program (interrupt service routine). After the processing is completed, the original program execution resumes. Depending on the needs of each service, interrupts can be divided into timed interrupts and triggered interrupts, including external hard interrupts triggered by the FPGA and internal logic-triggered soft interrupts.

[0080] In one embodiment, the protection core of the application layer also includes an external input module. This external input module can collect circuit data within the protected area, such as SV data. SV data consists of voltage and current values ​​collected by the AC protection device through an AC connector within the protected area. The external input module converts the voltage and current values ​​into secondary signals in the SV data format internal to the device. The protection core receives these secondary signals and determines whether to execute a protection action based on the protection algorithm in the first application algorithm module of the protection core. The external input module can also receive externally input setting data, such as protection settings and protection pressure plates. A setting determines the action that will occur when a certain physical quantity reaches a certain value. The protection setting determines the reliability and sensitivity of the device's function and can be adjusted to suit different site conditions. The protection pressure plate determines the activation and deactivation of the device's function and can be adjusted accordingly based on different site conditions. Compared to the management core, the protection core is primarily used for performing tasks with high real-time requirements, such as real-time data acquisition, calculation, and fault handling.

[0081] In one embodiment, the driver layer includes at least one of the following: peripheral function driver design of the relay protection chip, ARM (Advanced RISC Machines, a type of processor) core-related driver, management of general event external interrupts and timers.

[0082] In one embodiment, the second task dispatching module of the management core performs some basic services that are different from the protection procedures with high real-time requirements, such as communicating with other devices, device self-testing, device fault diagnosis, fault data analysis, result display, human-computer interaction, printing, fault report compilation and sending, and other diversified task requirements. These tasks have relatively low real-time requirements and long task cycles.

[0083] The aforementioned system based on a chip-based relay protection device comprises a hierarchical structure from bottom to top: a front-end processing layer, a driver layer, an operation layer, and an application layer. The front-end processing layer includes programmable logic circuits integrated within the chip, used to preprocess power data to obtain preprocessed data, which is shared and accessed by the protection core and management core within the chip. The driver layer includes multiple peripheral standard driver interfaces for driver communication with external devices, shared and accessed by the protection core and management core within the chip. The operation layer includes a memory management module, a first interface module, and a first task scheduling module suitable for the protection core, and also includes a second interface module and a second task scheduling module suitable for the management core. The application layer includes a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core, wherein the first application algorithm module is used to execute real-time control tasks, and the second application algorithm module is used to execute management communication tasks. In this way, the system based on chip-based relay protection devices is divided into a bottom-up hierarchy: front-end processing layer, driver layer, operation layer, and application layer. The protection core and management core independently run the functional modules in their respective operation and application layers, avoiding resource contention. The functional modules in the front-end processing layer and driver layer are common resource modules, and both the protection core and management core can share and call the functional modules in the front-end processing layer and driver layer. This hierarchical design can functionally divide the chip-based relay protection device system, which is beneficial for the development and maintenance of chip-based relay protection software, and can also effectively share knowledge and improve the working efficiency of chip-based relay protection devices.

[0084] In one embodiment, the memory management module is used to divide the storage module in the chip-based relay protection device into a Linux private memory partition used by the management core, a BM private memory partition used by the protection core, and a shared memory partition, and control each memory partition to interlock, so as to ensure that the memory data reading can be performed without interference when the protection core and the management core are running together.

[0085] In the chip-based relay protection device, the hardware memory resources in the storage module are divided according to address, namely Linux private memory used by the management core, BM private memory used by the protection core, and shared memory for peripheral auxiliary control functions. The three memory spaces cannot be mixed.

[0086] In this embodiment, by partitioning the memory and using an interlocking mechanism, it is ensured that each functional module of the relay protection chip can operate normally, and that the protection core and the management core will not interfere with each other or compete for storage resources when they are running simultaneously.

[0087] In one embodiment, when the load information of the protection core meets the high load condition, the protection core is used to transfer the software tasks that meet the low priority condition in the first application algorithm module to the operating system in the management core through shared memory and system bus, so that the operation layer of the management core can execute the transferred software tasks.

[0088] High load conditions can occur when the load on the protection core exceeds a set load threshold. Low priority conditions can occur when the priority is lower than a set threshold, or when software tasks are arranged in descending order of priority, with the lowest-priority tasks being passed to the management core's operation layer. These software tasks primarily consist of real-time control tasks executed by the protection core.

[0089] In one embodiment, when the workload information of the task being executed by the protection core meets the load threshold preset by the protection core, the protection core transmits N low-priority software tasks contained in the first application algorithm module to the operating system in the management core through shared memory and system bus, and the operation layer of the management core performs operations on these software tasks.

[0090] In the above embodiments, when the load information meets the high load condition, the protection core passes the excess unexecuted tasks to the operating system in the management core through shared memory and system bus. The operation layer of the management core performs operations on these software tasks, which can avoid memory overflow of the protection core and speed up the execution speed of software tasks.

[0091] In one embodiment, for the front-end processing layer, driver layer, operation layer and application layer of the system, each layer embeds a corresponding self-test function through a standardized interface, so that the upper layer can perform software testing on the lower layer through the corresponding self-test function.

[0092] In one embodiment, the front-end processing layer, driver layer, operation layer, and application layer are distributed from bottom to top, with corresponding standardized interfaces for data interaction between adjacent layers. Furthermore, each layer embeds a self-test function, allowing the upper layer to monitor the data transmitted upwards from the lower layer and thus determine whether any abnormalities have occurred in the software modules or hardware structures of the lower layer.

[0093] In the above embodiments, by embedding self-test functions in each layer and using the self-test functions of the upper layer to perform software testing on the lower layer, it is possible to monitor whether there are any abnormalities between different layers in the system, thereby enabling timely detection and handling of faults in each layer, avoiding the generation and processing of large-scale abnormal data, and improving the working efficiency of chip-based relay protection devices.

[0094] In one embodiment, multiple peripheral standard driver interfaces include a GP bus driver unit, an ACP bus driver unit, an SPI / QSPI driver unit, an I2C driver unit, an ADC driver unit, a serial port driver unit, an Ethernet driver unit, and a temperature monitoring unit. Specifically: the GP bus driver unit is used for medium-speed communication between at least one core in the protection core and management core and the front-end processing layer; the ACP bus driver unit is used for high-speed communication between at least one core in the protection core and management core and the front-end processing layer; the SPI / QSPI driver unit is used for connecting external FLASH memory; the I2C driver unit is used for connecting external EEPROM and RTC devices; the ADC driver unit has a built-in ADC module for measuring various operating voltages and monitoring their status; the serial port driver unit is used for initializing the UART serial port and internal debugging; the Ethernet driver unit is used for initializing the corresponding Ethernet interface of the core; and the temperature monitoring unit is used for connecting an external temperature sensor for temperature status monitoring.

[0095] In this embodiment, by setting multiple peripheral standard driver interfaces in the driver layer, communication between the protection core and the management core and external devices is facilitated, and the communication rate between the protection core and the management core and external devices is improved.

[0096] In one embodiment, the first application algorithm module includes: a protection configuration unit for scheduling two sets of protection devices to perform protection actions; and a trip logic unit for issuing a trip command to drive the local DO board to open a node when both sets of protection devices simultaneously meet the protection action requirements.

[0097] In one embodiment, the chip-based relay protection device adopts a dual protection configuration unit design, meaning that the two protection devices each have independent measurement circuits, independent protection algorithm modules, and independent protection action outputs. When the two protection devices execute protection actions, they trigger actual protection tripping, driving the output node of the output plug-in.

[0098] In one embodiment, the trip logic unit circuit only receives GOOSE (a fast message transmission mechanism) trip information, which is fast and sensitive.

[0099] In the above embodiments, the functional units in the first application algorithm module cooperate with each other to improve the working efficiency of the chip-based relay protection device. The dual configuration of the protection device can avoid malfunction due to the protection tripping caused by a set of protection devices, thereby improving the reliability of the chip-based relay protection device.

[0100] In one embodiment, the second application algorithm module includes: a message transceiver unit for communicating with various general-purpose industrial equipment; a remote adjustment unit for controlling the opening and closing of the interrupt controller using a passive contact method; a remote signaling unit for converting the closing or opening of relay contacts into low-level or high-level signals using a passive contact method and sending them to the chip-based relay protection device; a telemetry unit for acquiring active and reactive power data of the transformer, active power data of the line, bus voltage and line current data, temperature, pressure, flow rate, etc., as well as frequency and other analog signal data; a remote control unit for controlling the raising and lowering adjustment of the taps of the on-load tap-changing transformer using a passive contact method; and a fault analysis unit for acquiring fault data and performing equipment fault diagnosis and fault data analysis based on the fault data.

[0101] The message transceiver unit is responsible for sending and receiving MMS (Multimedia Messaging Service) messages. The MMS message specification is a general communication protocol that can be used for communication between various general industrial control devices. For example, under the IEC 61850 standard for substations, MMS is used to realize communication between the station control layer and the bay layer. MMS is an application layer protocol in the OSI (Open System Interconnection) seven-layer model, mainly used in substations for issuing control commands and reporting measurement data.

[0102] In one embodiment, the remote adjustment unit, employing a passive contact method, is commonly used for the closing and opening of circuit breakers and capacitors, as well as other applications where relay control is feasible. The remote signaling unit, also employing a passive contact method, requires a pair of relay contacts as the input for a specific remote signal, either closed or open. The closing or opening of the relay contacts is converted into a low-level or high-level signal via the remote signaling terminal block and sent to the relay protection device. This is typically used to measure signals that provide relay-mode outputs, including: switch position signals, transformer internal fault comprehensive signals, protection device operation signals, communication equipment operating status signals, voltage regulating transformer tap position signals, and automatic adjustment device operating status signals. Telemetry units are often further categorized into important telemetry, secondary telemetry, general telemetry, and total telemetry, commonly used for acquiring active and reactive power data from transformers, active power data from lines, bus voltage and line current data, temperature, pressure, flow rate data, frequency data, and other analog signal data. The remote control unit, using a passive contact method, is commonly used for raising and lowering the taps of on-load tap-changing transformers and other applications where a set of relays can be used to control the step-by-step raising and lowering functions.

[0103] In this embodiment, the functional units in the second algorithm module cooperate with each other, mainly to complete the sending and receiving of various files and parameter settings during the relay protection process, ensuring the safe execution of relay protection actions and improving the reliability of the relay protection chip. The remote adjustment unit, remote signaling unit, remote measurement unit, and remote control unit work together to complete the monitoring function of the relay protection device, ensuring that the relay protection device can safely and accurately execute relay protection operations.

[0104] In one embodiment, the front-end processing layer includes a network unit, a storm suppression unit, a packet distribution unit, an alarm module unit, a decoding unit, a low-pass filtering unit, an interpolation synchronization unit, and a configuration module unit, wherein: the network unit is a standard Ethernet IP module used to support network protocols; the storm suppression unit is used to filter out invalid packets; the packet distribution unit is used to identify packets based on Ethernet frame fields and application identifiers; the alarm module unit, based on application identifiers, is used to perform statistics and alarms on subscribed packets; the decoding unit is used to implement packet parsing functions; the low-pass filtering unit is used to perform low-pass filtering on SV data; the interpolation synchronization unit is used to process SV data; and the configuration module unit is used to configure network storm suppression parameters, SV parameters, and packet processing parameters.

[0105] The network unit can be a MAC / IP unit. A MAC (system) / IP (address) unit is a standard Ethernet IP module used to support the IEEE 802.1Q protocol. The decoding unit can be an SV (encoding) decoding unit. The message distribution unit is used to identify SV / GOOSE / MMS / 1588 messages based on the Ethernet frame field + application identifier (ETHERTYPE + APPID). The alarm module unit, using the application identifier (APPID) as the unit, is used to perform statistics and alarms on subscribed messages. The decoding unit can be an SV decoding unit used to implement MAC message parsing functionality.

[0106] In this embodiment, the functional units in the front-end processing layer mainly complete the processing of external input current data, so that the protection check can accurately judge the current data and determine whether there are any security issues in the source system of the current data.

[0107] In one embodiment, such as Figure 2 As shown, the system based on chip-based relay protection devices is divided into hierarchical software modules, including a front-end processing layer, a driver layer, an operation layer, and an application layer. Each layer contains different functional modules and units. This layered architecture of the chip-based relay protection device is adapted to chip-based relay protection devices using the AMP architecture.

[0108] In one embodiment, the operation layer constructs an operating system, including a first interface module, a first task scheduling module, a memory management module, and a time service module in the protection kernel, and a second interface module, a second task scheduling module, a network communication protocol module, and a DTS file module in the management kernel. The memory management unit refers to the allocation and use of computer memory resources during software runtime; its primary purpose is to allocate memory efficiently and quickly, and to release and reclaim memory resources when appropriate.

[0109] In one embodiment, various events and alarms generated during operation by the IEC61850-based chip-based protection device need to be time-stamped and sent to the backend. All business functions within the device with high real-time requirements rely on the time service unit to provide stable and reliable time information. For example, IRIG-B code (a commonly used serial transmission method in time systems) is the most commonly used external clock source in the field of smart substations. The time service module parses IRIG-B code data to obtain the time information from the external clock source and provides it to the high-speed, high-precision timers required by various business functions within the device, thus providing stable and reliable time information for the various business functions of the protection core and management core.

[0110] In one embodiment, the network communication protocol module includes support for standard network communication protocols, including ARP routing, and the sending and receiving of various IP packet formats such as TCP and UDP. The DTS (device tree source) file module is a data structure that describes information about specific hardware devices of the computer. It can separate devices and drivers so that the operating system kernel can manage and use this hardware.

[0111] In one embodiment, the application layer deploys applications for specific tasks, including an external input module for the protection core, a first application algorithm module within the protection core, a protection element module for the protection core, a second application algorithm module for the management core, a setting and pressure plate module, and a waveform recording module. The protection core and management core in the application layer and operation layer run their respective modules independently, while the driver layer and front-end processing layer share common resource modules.

[0112] The first application algorithm module includes a protection configuration unit and a tripping logic unit.

[0113] In one embodiment, the operating system running on the management kernel can be a custom Linux operating system. The Linux kernel can implement many important architectural attributes. At high or low levels, the Linux kernel is divided into multiple subsystems. The Linux kernel can also be viewed as a whole, integrating all these basic services into the kernel. The Linux kernel has a system call interface, which provides function calls from user space to the kernel. The Linux kernel has a process management subsystem; these processes, called threads, represent individual processor virtualizations (including thread code, data, stack, and CPU registers). The Linux kernel can provide an application programming interface to create a new process or stop a process, and to facilitate communication and synchronization between them. Another important resource managed by the Linux kernel is memory. To improve efficiency, the Linux kernel includes methods for managing available memory, as well as the hardware mechanisms used for physical and virtual mapping. The management kernel, based on a custom Linux operating system, improves operational efficiency, simplifies critical operations, and provides fundamental support for high real-time application functions. The Linux kernel also includes a virtual file system (VFS), which provides a common interface abstraction for file systems. The Virtual File System (VFS) provides an exchange layer between the System Call Interface (SCI) and the file systems supported by the kernel. Above the VFS is a generic API (Application Programming Interface) abstraction for functions such as open, close, read, and write. Below the VFS is the file system abstraction, which defines the implementation of higher-level functions; these are plugins for a given file system.

[0114] In one embodiment, the front-end processing layer further includes a storm suppression module, a low-pass filtering module, a decoding module, and a message distribution module. The driver layer further includes an ADC driver module, an Ethernet driver module, an SPI driver module, and an I2C driver module.

[0115] In one embodiment, self-test functions can be embedded between each of the front-end processing layer, driver layer, operation layer and application layer through standardized interfaces, so that the upper layer can perform software testing on the lower layer.

[0116] In this embodiment, the system based on the chip-based relay protection device is divided into hierarchical software modules: an application layer, an operation layer, a driver layer, and a front-end processing layer. This hierarchical software design allows for functional division of the software, facilitating software development and maintenance. Furthermore, standardized interfaces allow for the embedding of self-test functions between each layer, enabling testing of the layers below from the upper layers. Modular software design also facilitates knowledge sharing, utilizes mature software modules, improves system reliability, and enhances the operating efficiency of the chip-based relay protection device.

[0117] In one embodiment, such as Figure 3 As shown, a relay protection method is provided, the method comprising:

[0118] Step S302: The power data collected from the target power equipment is preprocessed using programmable logic circuits to obtain preprocessed data.

[0119] Among them, data preprocessing can be filtering and decoding, the purpose of which is to filter out invalid messages and high-frequency interference in current data.

[0120] In one embodiment, the chip-based relay protection device performs filtering and decoding processing on the power data collected from the target power equipment through the front-end processing layer to obtain the processed power data.

[0121] Step S304: The first application algorithm module performs a protection function logic judgment on the preprocessed data.

[0122] The protection function logic judgment is used to determine whether there is a fault in the power data.

[0123] In one embodiment, the chip-based relay protection device compares the processed power data with a preset threshold in the device through the first application algorithm module of the protection core, thereby determining the protection function logic.

[0124] Step S306: If the target power equipment is determined to be faulty based on the protection function logic, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0125] In one embodiment, if the target power equipment is determined to be faulty based on the protection function logic, the chip-based relay protection device calls the first application algorithm module through the first task scheduling module of the protection core to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0126] In step S308, the relevant data involved in the trip protection operation is stored and reported through the second application algorithm module.

[0127] In one embodiment, the chip-based relay protection device stores and reports relevant data involved in the trip protection operation through the second application algorithm module of the management core. The storage operation can be performed by a specific module, such as a waveform recording module.

[0128] The aforementioned relay protection method uses programmable logic circuits to preprocess power data collected from the target power equipment, obtaining preprocessed data. A first application algorithm module then performs protection function logic judgments on this preprocessed data. If the protection function logic judgment determines that the target power equipment is faulty, a first task scheduling module calls the first application algorithm module to issue a trip command to the interrupt controller, causing the interrupt controller to disconnect the target power equipment from the power network. This process, where the logic judgment is completed in the protection core before the first task module calls the first application algorithm module to issue the trip command, saves communication time between units, quickly achieves the goal of protecting other power equipment components, and improves the working efficiency of the chip-based relay protection device. Furthermore, a second application algorithm module stores and reports relevant data involved in the trip protection operation, providing a basis for subsequent accident analysis.

[0129] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0130] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0131] The power data collected from the target power equipment is preprocessed using programmable logic circuits to obtain preprocessed data.

[0132] The first application algorithm module performs protection function logic judgment on the preprocessed data;

[0133] If the protection function logic determines that the target power equipment is faulty, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0134] The second application algorithm module stores and reports the relevant data involved in the trip protection operation.

[0135] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0136] The power data collected from the target power equipment is preprocessed using programmable logic circuits to obtain preprocessed data.

[0137] The first application algorithm module performs protection function logic judgment on the preprocessed data;

[0138] If the protection function logic determines that the target power equipment is faulty, the first task scheduling module calls the first application algorithm module to send a trip command to the interrupt controller, so as to control the interrupt controller to disconnect the target power equipment from the power network.

[0139] The second application algorithm module stores and reports the relevant data involved in the trip protection operation.

[0140] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A system based on a chipped relay protection device, characterized by, The system comprises a front-end processing layer, a driving layer, an operation layer and an application layer from bottom to top in a hierarchy, wherein: The front-end processing layer comprises programmable logic circuits integrated in a chip, which are used to pre-process power data to obtain pre-processed data, the pre-processed data being shared and called by a protection core and a management core in the chip, wherein the protection core is in a bare run mode, the management core runs an operating system, when load information of the protection core meets a high load condition, the protection core transfers software tasks in a first application algorithm module meeting a low priority condition to the operating system in the management core through shared memory and a system bus, so that the operation layer of the management core implements execution of the transferred software tasks, wherein the transferred software tasks are real-time control tasks, the software tasks meeting the low priority condition are software tasks with a priority lower than a preset threshold, or a preset number of software tasks with a low priority; The driving layer comprises a plurality of peripheral standard driving interfaces, which are used to drive communication with external devices, and are shared and called by the protection core and the management core in the chip; The operation layer comprises a memory management module, a first interface module and a first task scheduling module suitable for the protection core, and further comprises a second interface module and a second task scheduling module suitable for the management core, wherein the first interface module and the second interface module are used to call the front-end processing layer and the driving layer, the first task scheduling module is used to call a first application algorithm module in the application layer to process real-time control tasks, and the second task scheduling module is used to call a second application algorithm module in the application layer to process management communication tasks; The application layer comprises a first application algorithm module suitable for the protection core and a second application algorithm module suitable for the management core, wherein the first application algorithm module is used to execute real-time control tasks, and the second application algorithm module is used to execute management communication tasks.

2. The system of claim 1, wherein, The memory management module is used to divide storage modules in the chip-based relay protection device into a Linux private memory partition used by the management core, a BM private memory partition used by the protection core and a shared memory partition, and control interlocking of the memory partitions, so as to ensure that the protection core and the management core can realize mutual non-interference of memory data reading when they are commonly operated.

3. The system of claim 2, wherein, The protection core is a master core, and the management core is a slave core, the master core has configuration and management authority of shared resources, and the slave core has usage authority of the shared resources.

4. The system of claim 1, wherein, For the front-end processing layer, the driving layer, the operation layer and the application layer in the system, a corresponding self-test function is embedded between each layer through a standardized interface, so that the upper layer performs software testing on the lower layer through the corresponding self-test function.

5. The system of claim 1, wherein, The plurality of peripheral standard driving interfaces comprise a GP bus driving unit, an ACP bus driving unit, an SPI / QSPI driving unit, an I2C driving unit, an ADC driving unit, a serial port driving unit, an Ethernet driving unit and a temperature monitoring unit, wherein: The GP bus driving unit is used for medium-speed communication between at least one of the protection core and the management core and the front-end processing layer. The ACP bus driving unit is used for high-speed communication between at least one of the protection core and the management core and the front-end processing layer. The SPI / QSPI driving unit is used for an external FLASH memory. The I2C driving unit is used for an external EEPROM and an RTC device. The ADC driving unit is used for built-in ADC modules for measuring working voltages at various levels and state monitoring. The serial port driving unit is used for initializing a UART serial port and internal debugging. The Ethernet driving unit is used for initialization of an Ethernet interface corresponding to the core. The temperature monitoring unit is used for an external temperature sensor for temperature state monitoring.

6. The system of claim 1, wherein, The first application algorithm module comprises: A protection configuration unit is configured to schedule two sets of protection devices to perform protection actions. A trip logic unit is configured to issue a trip instruction to drive a local DO board to open a node when the two sets of protection devices simultaneously meet the protection actions.

7. The system of claim 1, wherein, The second application algorithm module comprises: A message transceiving unit is configured to communicate with various general industrial devices. A remote adjustment unit is configured to control an interrupt controller by using a passive contact method. A remote signaling unit is configured to convert closing or opening of a relay contact into a low-level or high-level signal by using a passive contact method and send the signal to a chip-based relay protection device. A remote measurement unit is configured to collect active and reactive power of a transformer, active power of a line, bus voltage and line current, temperature, pressure, flow, and cycle frequency and other analog signals. A remote control unit is configured to control tap adjustment of a load regulation transformer by using a passive contact method. A fault analysis unit is configured to obtain fault data and perform device fault diagnosis and fault data analysis based on the fault data.

8. The system of claim 1, wherein, The front-end processing layer comprises a network unit, a storm suppression unit, a message distribution unit, an alarm module unit, a decoding unit, a low-pass filter unit, an interpolation synchronization unit, and a configuration module unit, wherein: The network unit is a standard Ethernet IP module configured to support a network protocol. The storm suppression unit is configured to filter out invalid messages. The message distribution unit is configured to identify messages according to Ethernet frame fields and application identifiers. The alarm module unit is configured to complete statistics and alarms on subscription messages in units of application identifiers. The decoding unit is configured to implement message analysis functions. The low-pass filter unit is configured to perform low-pass filtering on SV data. The interpolation synchronization unit is configured to process SV data. The configuration module unit is configured to configure network storm suppression parameters, SV parameters, and message processing parameters.

9. A method of relaying protection, characterized by, The method is applied to the chip-based relay protection device-based system in any one of claims 1 to 8, and the method comprises: The programmable logic circuit is used to pre-process power data collected based on target power equipment to obtain pre-processed data. The first application algorithm module is used to perform protection function logic judgment on the pre-processed data. If it is determined that the target power device has a fault based on the protection function logic, a trip instruction is sent to an interrupt controller by the first application algorithm module through the first task scheduling module to control the interrupt controller to disconnect the target power device from the power network; Through the second application algorithm module, relevant data involved in the trip protection operation process are stored and reported.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of claim 9.

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