A test data generation method, test method, device and related equipment

Abstract

An embodiment of the present invention provides a test data generation method, a test method, an apparatus, and related equipment, wherein the test data generation method includes: determining an operation instruction of an operation unit, the operation instruction being used to cause the operation unit to perform a first operation on an operand; determining an expected operation result of the first operation; determining an expected operand corresponding to the expected operation result based on a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation. Since the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation, the operation unit performs the first operation on the expected operand, and after determining the corresponding actual operation result, the actual operation result can be compared with the expected operation result to verify whether the actual operation accuracy of the operation unit reaches the expected operation accuracy, thereby achieving accurate verification of the operation accuracy of the operation unit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to a test data generation method, a test method, an apparatus and related equipment. Background Art

[0002] With the rapid development of artificial intelligence, the demand for computer computing power is increasing. A computer's computing power depends on the data processing capabilities of its computing units. As application scenarios continue to expand, new computing units are constantly being designed. To verify whether the designed computing units meet the expected computational accuracy, they need to be tested. However, currently, most methods use randomly generated test data to perform random verification of computing units, which cannot accurately verify the computing units' computational accuracy. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a test data generation method, a test method, an apparatus, and related devices to accurately verify the calculation accuracy of a calculation unit.

[0004] To solve the above problems, the embodiments of the present invention provide the following technical solutions:

[0005] A first aspect of the present invention provides a test data generating method, comprising:

[0006] determining an arithmetic operation instruction of an arithmetic unit, wherein the arithmetic operation instruction is used to cause the arithmetic unit to perform a first arithmetic operation on an operand;

[0007] determining an expected operation result of the first operation;

[0008] An expected operand corresponding to the expected operation result is determined according to a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation.

[0009] A second aspect of the present invention provides a testing method, comprising:

[0010] Obtaining an expected operand, where the expected operand is determined based on a second operation that is logically inverse of a first operation, the expected operand corresponding to an expected operation result of the first operation, the first operation being determined based on an operation instruction of an operation unit, the operation instruction being used to cause the operation unit to perform the first operation on the operand;

[0011] A first arithmetic operation of the arithmetic unit is tested according to the expected operand.

[0012] A third aspect of the present invention provides a test data generating device, comprising:

[0013] a first operation module, configured to determine an operation instruction of the operation unit, wherein the operation instruction is configured to cause the operation unit to perform a first operation on an operand;

[0014] a second operation module, configured to determine an expected operation result of the first operation;

[0015] A third operation module is used to determine an expected operand corresponding to the expected operation result based on a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation.

[0016] A fourth aspect of the present invention provides a testing device, comprising:

[0017] an acquisition module, configured to acquire an expected operand, wherein the expected operand is determined based on a second operation whose operation logic is inverse to that of the first operation, the expected operand corresponds to an expected operation result of the first operation, the operation precision of the second operation is higher than the expected operation precision of the first operation, and the first operation is determined based on an operation instruction of a calculation unit, the operation instruction being configured to cause the calculation unit to perform the first operation on the operand;

[0018] A testing module is used to test the first operation of the operation unit according to the expected operand.

[0019] A fifth aspect of the present invention provides a computer device, comprising:

[0020] a memory storing at least one set of instructions;

[0021] The processor executes the at least one set of instructions to perform the test data generation method as described in any one of the above items, or the testing method as described in any one of the above items.

[0022] A sixth aspect of the present invention provides a readable storage medium, which stores at least one set of instructions, and the at least one set of instructions is used to enable a processor to execute the test data generation method as described in any one of the above items, or the test method as described in any one of the above items.

[0023] The test data generation method, test method, device and related equipment provided by the embodiments of the present invention determine the operation instruction of the operation unit, which is used to enable the operation unit to perform a first operation on the operand, determine the expected operation result of the first operation, and determine the expected operand corresponding to the expected operation result based on a second operation that is opposite to the operation logic of the first operation.

[0024] Since the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation, the operation unit performs the first operation on the expected operand. After determining the actual operation result corresponding to the expected operand, the actual operation result can be compared with the expected operation result to verify whether the actual operation accuracy of the operation unit performing the first operation reaches the expected operation accuracy, thereby achieving accurate and effective verification of the operation accuracy of the operation operation of the operation unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0026] Figure 1 A flowchart of a test data generation method provided by one embodiment of the present invention;

[0027] Figure 2 A flowchart of a test data generating method provided by another embodiment of the present invention;

[0028] Figure 3 A flowchart of a test data generating method provided by another embodiment of the present invention;

[0029] Figure 4 A schematic diagram of a minimum precision unit provided by an embodiment of the present invention;

[0030] Figure 5 A flowchart of a test data generating method provided by another embodiment of the present invention;

[0031] Figure 6 A schematic diagram of the structure of a test data generating device provided by one embodiment of the present invention;

[0032] Figure 7 A flow chart of a testing method provided in one embodiment of the present invention;

[0033] Figure 8 A schematic structural diagram of a testing device provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] A general-purpose graphics processing unit (GPGPU) is a processor that uses a graphics processor that processes graphics tasks to calculate general computing tasks originally handled by a central processing unit. It has powerful parallel processing capabilities and programmable pipelines and is usually used to perform complex data calculations, such as floating-point data calculations.

[0036] This powerful processor is composed of massively parallel arithmetic units. A compiler parses the upper-level program into various instructions that the arithmetic units can execute. The arithmetic units execute these instructions to perform various basic operations on operands. Common operations include addition, subtraction, multiplication, division, reciprocal, remainder, and square root.

[0037] Verification of the designed arithmetic unit has always been a difficult point, especially the verification of the floating-point arithmetic unit. The floating-point arithmetic unit is used to perform operations on floating-point numbers. Common floating-point precisions include half-precision (16-bit), single-precision (32-bit), double-precision (64-bit), and extended double-precision (128-bit). Taking the operation instructions of two single-precision floating-point numbers as an example, there are 2 possible test data combinations. 32 *2 32 This results in a very large test space for floating-point units. If the unit is verified by traversing and generating operands, the test time will be very long. Although random operand generation can also be used to verify the unit, this can only randomly verify the unit's operating instructions or operations, and cannot accurately verify its calculation accuracy.

[0038] Based on this, an embodiment of the present invention provides a test data generation method, a test method, an apparatus and related equipment to achieve accurate verification of the operation accuracy of an operation unit.

[0039] As an optional implementation of the disclosed content of the embodiment of the present invention, the embodiment of the present invention provides a test data generation method for generating test data of an operation unit to achieve accurate verification of the operation accuracy of the operation unit. Figure 1 The test data generation method shown in FIG. 1 includes:

[0040] S101: Determine an arithmetic operation instruction of an arithmetic unit, where the arithmetic operation instruction is used to cause the arithmetic unit to perform a first arithmetic operation on an operand; wherein the arithmetic unit is an arithmetic unit to be verified, and the arithmetic unit may be an arithmetic unit in a general-purpose graphics processor or an arithmetic unit in a central processing unit. Furthermore, the arithmetic unit may be a floating-point arithmetic unit or other arithmetic units. The floating-point arithmetic unit may be implemented based on RTL hardware or other hardware (such as FPGA). Of course, the present invention is not limited thereto. In other embodiments, the arithmetic unit to be verified may also be an arithmetic reference model developed in a high-level language.

[0041] After determining the arithmetic unit to be verified, an arithmetic operation instruction (opcode, also known as operation code) of the arithmetic unit is obtained, and the arithmetic operation instruction is parsed to obtain a first arithmetic operation corresponding to the arithmetic operation instruction. The arithmetic operation instruction is used to cause the arithmetic unit to perform the first arithmetic operation on the operand.

[0042] The first operation can be a combination of one or more operations selected from addition, subtraction, multiplication, division, reciprocal, remainder, and square root, etc. Furthermore, the first operation can be performed on one operand or multiple operands.

[0043] S102: Determine an expected operation result of the first operation;

[0044] S103: determining an expected operand corresponding to an expected operation result according to a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation.

[0045] The expected operation result is the operation result of the operation that achieves the expected operation accuracy. In other words, the expected operation result is the operation result of the operation that achieves the expected operation accuracy loss. The higher the operation accuracy, the smaller the operation loss. After determining the expected operation result of the first operation, the expected number of operations corresponding to the expected operation result is determined based on a second operation that has the opposite operation logic to the first operation. Since the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation, after performing the second operation on the expected operation result, the expected number of operations obtained is the number of operations that achieve the expected operation accuracy.

[0046] The expected operand is input into the arithmetic unit to be verified. After the arithmetic unit executes the corresponding arithmetic operation instruction, it performs a first arithmetic operation on the expected operand to obtain an actual arithmetic result. If the first arithmetic operation of the arithmetic unit achieves the expected arithmetic accuracy, the actual arithmetic result is equal to or approximately equal to the expected arithmetic result.

[0047] That is to say, if the actual calculation result is equal to or approximately equal to the expected calculation result, it means that the calculation accuracy of the calculation unit to be verified is equal to or approximately equal to the expected calculation accuracy; if the actual calculation result is greater than or less than the expected calculation result, it means that the calculation accuracy of the calculation unit to be verified is higher or lower than the expected calculation accuracy.

[0048] Based on this, by comparing the actual operation result with the expected operation result, it can be verified whether the actual operation accuracy of the operation unit performing the first operation reaches the expected operation accuracy, thereby achieving accurate verification of the operation accuracy of the operation unit.

[0049] In some embodiments of the present invention, after generating the expected operands for any arithmetic operation instruction of the arithmetic unit, the next arithmetic operation instruction of the arithmetic unit can be determined and the expected operands for the next arithmetic operation instruction can be generated. In other words, in some embodiments of the present invention, different arithmetic operation instructions of the arithmetic unit can be accurately verified. That is, not only can the computational accuracy of the arithmetic operation corresponding to any arithmetic operation instruction of the arithmetic unit be accurately verified, but the computational accuracy of the arithmetic operations corresponding to all arithmetic operation instructions of the arithmetic unit can also be accurately verified, thereby further achieving flexibility and comprehensiveness in the verification of the arithmetic unit.

[0050] In some embodiments of the present invention, the expected operation result can be obtained through a third operation that has the same operation logic as the first operation but has an operation precision higher than the expected operation precision of the first operation.

[0051] refer to Figure 2 The flowchart of another test data generation method shown in FIG. 1 shows that after determining the operation instruction of the operation unit, the process proceeds to steps S201 to S203. That is, the process of determining the expected operation result of the first operation includes steps S201 to S203.

[0052] S201: Determine an initial operand of a first operation;

[0053] S202: Obtaining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation;

[0054] S203: Determine that the initial operation result is the expected operation result.

[0055] In some embodiments of the present invention, a random or scanning method may be used to generate the initial operands. Of course, in order to improve test efficiency, the data type and / or data range of the initial operands may be constrained based on the first operation. That is, determining the initial operands for the first operation includes:

[0056] An initial operand is randomly generated according to a data constraint condition of the first operation; the data constraint condition is used to constrain a data type and / or a data range of the initial operand.

[0057] Data types can include single-precision floating-point numbers and double-precision floating-point numbers. The data range can be a pre-set range or a range determined during the test data generation method. For example, after generating an expected operand based on any initial operand, the range of the next initial operand can be determined based on the range of the expected operand to avoid duplication between the initial operand and the expected operand. It can also eliminate some unnecessary operand test data, improving verification test efficiency.

[0058] It should be noted that after parsing the operation instruction, not only the corresponding first operation can be obtained, but also the data type of the corresponding operand can be obtained. The data type includes single-precision floating-point numbers and double-precision floating-point numbers, etc., so that the initial operand can be constrained according to the data type.

[0059] Since the operation precision of the third operation is higher than the expected operation precision of the first operation, after performing the third operation on the initial operand and obtaining the initial operation result, the initial operation result can be determined as the expected operation result, thereby realizing verification of the operation unit.

[0060] Of course, the present invention is not limited to this. In other embodiments, other methods may be used to obtain the expected operation result. For example, after determining the initial operand of the first operation, other operation units are used to perform an operation with the same operation logic as the first operation on the initial operand to obtain a reference operation result. The reference operation result is then corrected using the precision correction value to obtain the expected operation result.

[0061] It should be noted that the operation logic of the first operation is the same as the operation logic of the third operation, which means that the operation expression of the first operation is the same as the operation expression of the third operation. The operation logic of the first operation is opposite to the operation logic of the second operation, which means that the operation expression of the first operation is opposite to the operation expression of the third operation.

[0062] Taking the operation expression of the first operation y = src_a*src_b + src_c as an example, y represents the operation result of the first operation, src_a, src_b, and src_c are the operands of the first operation, then the expression of the second operation is src_a = (y-src_c) / src_b or src_b = (y-src_c) / src_a or src_c = y-src_a*src_b; the expression of the third operation is y = src_a*src_b + src_c.

[0063] It should also be noted that the calculation accuracy of the second calculation operation is higher than the expected calculation accuracy of the first calculation operation, and the error generated by the second calculation operation is smaller than the error generated by the first calculation operation; the calculation accuracy of the third calculation operation is higher than the expected calculation accuracy of the first calculation operation, and the error generated by the third calculation operation is smaller than the error generated by the first calculation operation.

[0064] Taking the operands as floating-point numbers as an example, if the error generated by the second operation is smaller than the error generated by the first operation, the rounding error of the second operation can be smaller than the rounding error of the first operation; if the error generated by the third operation is smaller than the error generated by the first operation, the rounding error of the third operation can be smaller than the rounding error of the first operation. Rounding error refers to the difference between the approximate value obtained by the operation and the exact value. For example, when a floating-point number with a finite number of digits is used to represent a real number (theoretically, there are floating-point numbers with an infinite number of digits), rounding error will occur.

[0065] In order to reduce rounding errors in the second and third arithmetic operations, it is possible to limit the calculation process of the second and third arithmetic operations to not rounding any intermediate results. That is, in some embodiments of the present invention, the second and third arithmetic operations are implemented based on the actual floating-point values ​​that retain the intermediate calculation results, and the first arithmetic operation is implemented based on rounding the intermediate calculation results. The rounding process includes rounding to even numbers, rounding to zero, rounding up, rounding down, etc.

[0066] Of course, in other embodiments of the present invention, the rounding errors of the second and third arithmetic operations can be reduced by limiting the floating-point precision of the operands of the second arithmetic operation to be higher than the floating-point precision of the operands of the first arithmetic operation, and limiting the floating-point precision of the operands of the third arithmetic operation to be higher than the floating-point precision of the operands of the first arithmetic operation. For example, the floating-point precision of the operands of the second and third arithmetic operations is double precision, and the floating-point precision of the operands of the first arithmetic operation is single precision; the floating-point precision of the operands of the second and third arithmetic operations is single precision, and the floating-point precision of the operands of the first arithmetic operation is half precision.

[0067] In some embodiments of the present invention, a high-precision operation unit model can be developed using a computer programming language (such as Python) and the built-in mathematical operation library it provides, and the high-precision operation unit model can be used to perform the second operation operation and the third operation operation in any of the above embodiments to achieve the same operation process as the second operation operation and the third operation operation.

[0068] Although verifying whether the operation accuracy of the operation unit meets the expected operation accuracy is the main requirement of the operation unit verification, how to find out which operand combinations in the huge operand space will produce the largest rounding error for the operation unit is also a major challenge in the accurate verification of the operation accuracy of the operation unit.

[0069] Based on this, in some embodiments of the present invention, the operation to obtain the expected operation result can also have a maximum rounding error while achieving the expected operation accuracy. After performing a second operation on the expected operation result to obtain the expected operand corresponding to the expected operation result, the expected operand is input into the operation unit, so that the operation unit performs the first operation on the expected operand, and the actual operation result obtained can be compared with the expected operation result. If the actual operation result is equal to or approximately equal to the expected operation result, it means that the actual operation result has the maximum rounding error; if the actual operation result is greater than or less than the expected operation result, it means that the rounding error of the actual operation result is greater than or less than the maximum rounding error.

[0070] On this basis, in some embodiments of the present invention, reference Figure 3 The flowchart of another test data generation method shown in FIG. 1 shows that after determining the operation instruction of the operation unit, the process proceeds to steps S301 to S305. That is, the process of determining the expected operation result of the first operation includes steps S301 to S305.

[0071] S301: Determine an initial operand of a first operation;

[0072] S302: determining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation;

[0073] S303: Determine an expected correction value of the first operation;

[0074] S304: Correcting the initial calculation result according to the expected correction value to obtain a corrected calculation result;

[0075] S305: Determine that the corrected calculation result is the expected calculation result.

[0076] Likewise, determining the initial operands for the first arithmetic operation includes:

[0077] An initial operand is randomly generated according to a data constraint condition of the first operation; the data constraint condition is used to constrain a data type and / or a data range of the initial operand.

[0078] Because the computational precision of the third operation is higher than the expected computational precision of the first operation, after performing the third operation on the initial operand to obtain an initial computational result, the initial computational result is corrected based on an expected correction value, such as an expected rounding error value, thereby introducing the expected rounding error value into the initial computational result to obtain a corrected computational result. After determining the corrected computational result as the expected computational result, a second operation with the reverse computational logic of the first operation is performed on the expected computational result to reversely propagate the expected rounding error value into the expected operand, thereby ensuring that the expected operand becomes the operand with the highest probability of causing the computational unit to generate the expected rounding error value.

[0079] After inputting the expected operand into the arithmetic unit, by determining whether the rounding error value of the actual operation result is equal to the expected rounding error value, it can be determined whether the expected operand is the expected operand that causes the arithmetic unit to generate the expected rounding error value, thereby quickly and efficiently identifying which operands are likely to cause the arithmetic unit to generate the expected rounding error value. The expected rounding error can be either the maximum rounding error or the minimum rounding error, and the expected correction value can be either the expected rounding error value or other parameter values, such as a rounding error value.

[0080] That is to say, in some embodiments of the present invention, by introducing the parameter value to be verified into the expected operation result, and passing the parameter value to be verified back to the expected operand through a second operation that is logically opposite to the first operation, the parameters to be verified of the operation unit, such as rounding errors, can be precisely adjusted, thereby further achieving the accuracy of the precision verification of the operation unit.

[0081] In some embodiments of the present invention, the expected correction value is an expected rounding error value, and determining the expected correction value of the first operation includes: determining the expected rounding error value according to a minimum precision unit and a preset correction coefficient.

[0082] In a specific embodiment, the expected rounding error rd_error is expressed as: rd_error=y_ulp*ratio(i), where y_ulp is the minimum precision unit of the initial operation result in any of the above embodiments, and ratio(i) is a preset correction coefficient.

[0083] The preset correction coefficients include one or more of X±i, X, and Y±j; where 0.5≤X≤0.6, 0.9≤Y≤1, 0.01≤i<0.1, and 0.01≤j<0.1. In one specific embodiment, X=0.5, Y=1, i=j=0.01. That is, the preset correction coefficients ratio=(0.49, 0.5, 0.51, 0.99, 1.01), where ratio(i) is any value among 0.49, 0.5, 0.51, 0.99, and 1.01.

[0084] After obtaining the expected rounding error rd_error, the expected rounding error rd_error is added to the initial calculation result y_high to obtain the corrected calculation result. In other words, the corrected calculation result is equal to the sum of the expected correction value and the initial calculation result.

[0085] In some embodiments of the present invention, the minimum precision unit y_ulp is obtained based on the initial operation result y_high in any of the above embodiments and the minimum precision unit calculation function Get_ulp(). That is, y_ulp = Get_ulp(y_high). Actual floating-point numbers are continuous, but because only a limited number of bits can be used to represent floating-point numbers, the actual representable floating-point numbers are discrete, such as Figure 4 As shown in Figure 2, for a continuous number axis, only some discrete points can be accurately represented. For any given floating-point number x, its minimum precision unit, ulp, is defined as the difference between its two nearest adjacent floating-point numbers.

[0086] It should be noted that after obtaining any expected operand of the first operation, the expected operand and other initial operands can be used as test vectors, input into a file and saved as test data for the operation unit to be verified, such as using the expected operand of src_a, the initial operand of src_b and the initial operand of src_c as test vectors. Of course, the present invention is not limited to this. In other embodiments, the expected operand of src_a, the expected operand of src_b and the expected operand of src_c can also be used as test vectors, which will not be repeated here.

[0087] It should also be noted that it is possible to traverse all values ​​of the preset correction coefficient to obtain multiple expected operation results, thereby obtaining a test data set including multiple expected operands. For example, based on the preset correction coefficients of 0.49, 0.5, 0.51, 0.99, or 1.01, a test data set including five expected operands is obtained. In addition, it is also possible to generate multiple initial operands randomly or by scanning to obtain multiple initial operation results, thereby obtaining multiple expected operation results, and thus obtaining a test data set with multiple expected operands.

[0088] exist Figure 3 Based on the embodiment shown, reference Figure 5 The flowchart of another test data generation method shown in FIG. 1 further includes determining the expected operands corresponding to the expected operation result, that is, after step S103, the following steps:

[0089] S104: Determine whether all expected correction values ​​have been traversed; if not, proceed to step S303; if so, proceed to step S105;

[0090] S105: Determine whether to continue generating the expected operands; if not, exit the data generation process; if so, enter step S301.

[0091] Whether to continue generating the expected operands may be determined based on the range of the initial operands or the range of the expected operands.

[0092] As an optional implementation of the disclosed content of the embodiment of the present invention, the embodiment of the present invention provides a test data generating device for generating test data of an operation unit to achieve accurate verification of the operation accuracy of the operation unit. Figure 6 The test data generating device shown in FIG. 1 includes:

[0093] A first operation module 61 is used to determine an operation instruction of the operation unit, where the operation instruction is used to enable the operation unit to perform a first operation on an operand;

[0094] A second operation module 62 is used to determine the expected operation result of the first operation;

[0095] The third operation module 63 is used to determine an expected operand corresponding to an expected operation result according to a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation.

[0096] In some embodiments of the present invention, the second operation module 62 determines the expected operation result of the first operation including:

[0097] determining an initial operand for a first arithmetic operation;

[0098] Obtaining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; wherein the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation;

[0099] Determine that the initial operation result is the expected operation result.

[0100] In some other embodiments of the present invention, the second operation module 62 determines the expected operation result of the first operation including:

[0101] determining an initial operand for a first arithmetic operation;

[0102] determining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; wherein the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation;

[0103] determining an expected correction value for the first arithmetic operation;

[0104] Correcting the initial calculation result according to the expected correction value to obtain a corrected calculation result;

[0105] Determine that the corrected operation result is the expected operation result.

[0106] In some embodiments of the present invention, the first operation is implemented based on rounding the intermediate operation result; the second operation and the third operation are implemented based on retaining the actual floating-point value of the intermediate operation result.

[0107] In some embodiments of the present invention, the floating-point precision of the operand of the second operation and the floating-point precision of the operand of the third operation are higher than the floating-point precision of the operand of the first operation.

[0108] In some embodiments of the present invention, the second operation module 62 determines the initial operand of the first operation, including: randomly generating the initial operand according to the data constraint of the first operation; the data constraint is used to constrain the data type and / or data range of the initial operand.

[0109] In some embodiments of the present invention, the expected correction value is an expected rounding error value, and the second operation module 62 determines the expected correction value of the first operation including: determining the expected rounding error according to the minimum precision unit of the initial operation result and a preset correction coefficient.

[0110] In some embodiments of the present invention, the second operation module 62 is further configured to determine the minimum precision unit of the initial operation result according to the initial operation result and the minimum precision unit calculation function.

[0111] In some embodiments of the present invention, the preset correction coefficient includes one or more of X±i, X, and Y±j; wherein, 0.5≤X≤0.6, 0.9≤Y≤1, 0.01≤i<0.1, and 0.01≤j<0.1.

[0112] As an optional implementation of the disclosure of the embodiment of the present invention, the embodiment of the present invention provides a testing method for generating test data of an operation unit and verifying the operation unit. Figure 7 Flowchart of the test method shown, the test method includes:

[0113] S701: Obtaining an expected operand, where the expected operand is determined based on a second operation that is logically inverse to a first operation, the expected operand corresponds to an expected operation result of the first operation, and the operation precision of the second operation is higher than the expected operation precision of the first operation, the first operation is determined based on an operation instruction of an operation unit, the operation instruction being used to cause the operation unit to perform the first operation on the operand;

[0114] S702: Testing the first operation of the operation unit according to the expected operand.

[0115] It should be noted that the expected operand in step S701 may be generated by the test data generation method provided in any of the above embodiments. In some embodiments of the present invention, testing the first operation of the operation unit according to the expected operand includes:

[0116] Inputting the expected operand into the operation unit, causing the operation unit to perform a first operation on the expected operand to determine an actual operation result corresponding to the expected operand;

[0117] The actual operation result is compared with the expected operation result to verify whether the first operation performed by the operation unit meets expectations.

[0118] As an optional implementation of the disclosed content of the embodiment of the present invention, the embodiment of the present invention provides a testing device for generating test data of an operation unit and accurately verifying the operation accuracy of the operation unit. Figure 8 The structural diagram of the test device shown is as follows, and the test device includes:

[0119] an acquisition module 81, configured to acquire an expected operand, wherein the expected operand is determined based on a second operation whose operation logic is inverse to that of a first operation, the expected operand corresponds to an expected operation result of the first operation, the operation precision of the second operation is higher than the expected operation precision of the first operation, and the first operation is determined based on an operation instruction of an operation unit, the operation instruction being configured to cause the operation unit to perform the first operation on the operand;

[0120] The testing module 82 is configured to test the first operation of the operation unit according to the expected operand.

[0121] Similarly, the expected operands obtained by the acquisition module 81 may be generated by the test data generation device provided in any of the above embodiments. In some embodiments of the present invention, the testing module 82 tests the first operation of the operation unit according to the expected operands, including:

[0122] Inputting the expected operand into the operation unit, causing the operation unit to perform a first operation on the expected operand to determine an actual operation result corresponding to the expected operand;

[0123] The actual operation result is compared with the expected operation result to verify whether the first operation performed by the operation unit meets expectations.

[0124] As an optional implementation of the disclosed content of the embodiment of the present invention, the embodiment of the present invention further provides a computer device, including:

[0125] a memory storing at least one set of instructions;

[0126] The processor executes at least one set of instructions to perform the test data generation method provided in any of the above embodiments, or the test method provided in any of the above embodiments.

[0127] The electronic devices of the embodiments of the present invention include but are not limited to mobile communication devices, ultra-mobile personal computer devices, portable entertainment devices, servers, and other electronic devices with data interaction functions, among which mobile communication devices include but are not limited to smartphones and multimedia phones, ultra-mobile personal computer devices include but are not limited to tablet computers, portable entertainment devices include but are not limited to e-books and handheld game consoles, and servers include but are not limited to computer devices.

[0128] Based on the same inventive concept, an embodiment of the present invention also provides a readable storage medium, which stores at least one set of instructions, and the at least one set of instructions is used to enable the processor to execute the test data generation method provided in any of the above embodiments, or the test method provided in any of the embodiments.

[0129] The readable storage media of the embodiments of the present invention include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be host-readable instructions, data structures, program modules or other data. Examples of host storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0130] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0131] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test data generation method, characterized in that: include: determining an arithmetic operation instruction of an arithmetic unit, wherein the arithmetic operation instruction is used to cause the arithmetic unit to perform a first arithmetic operation on an operand; Determining an expected calculation result of the first calculation operation; the expected calculation result is a calculation result of the first calculation operation that achieves an expected calculation accuracy; An expected operand corresponding to the expected operation result is determined based on a second operation whose operation logic is opposite to that of the first operation; the operation accuracy of the second operation is higher than the expected operation accuracy of the first operation; and the expected operand is used to test the first operation of the operation unit.

2. The test data generation method according to claim 1, wherein: Determining the expected operation result of the first operation includes: determining an initial operand for the first arithmetic operation; determining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; wherein the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation; The initial operation result is determined to be the expected operation result.

3. The test data generation method according to claim 1, wherein: Determining the expected operation result of the first operation includes: determining an initial operand for the first arithmetic operation; determining an initial operation result corresponding to the initial operand according to a third operation having the same operation logic as the first operation; wherein the operation accuracy of the third operation is higher than the expected operation accuracy of the first operation; determining an expected correction value of the first arithmetic operation; Correcting the initial calculation result according to the expected correction value to obtain a corrected calculation result; Determine the corrected calculation result as the expected calculation result.

4. The test data generation method according to claim 2 or 3, characterized in that: The first operation is implemented based on rounding the intermediate operation result; the second operation and the third operation are implemented based on retaining the actual floating-point value of the intermediate operation result.

5. The test data generating method according to claim 2 or 3, characterized in that: The floating-point precision of the operand of the first operation is lower than the floating-point precision of the operand of the second operation; the floating-point precision of the operand of the first operation is lower than the floating-point precision of the operand of the third operation.

6. The test data generating method according to claim 2 or 3, characterized in that: Determining an initial operand of the first arithmetic operation includes: The initial operand is randomly generated according to the data constraint condition of the first operation; the data constraint condition is used to constrain the data type and / or data range of the initial operand.

7. The test data generating method according to claim 3, wherein: The expected correction value is an expected rounding error value, and determining the expected correction value of the first operation includes: The expected rounding error value is determined according to the minimum precision unit of the initial operation result and a preset correction coefficient.

8. The test data generating method according to claim 7, wherein: Also includes: The minimum precision unit of the initial operation result is determined according to the initial operation result and a minimum precision unit calculation function.

9. The test data generating method according to claim 7, wherein: The preset correction coefficients include one or more of X±i, X, and Y±j; Among them, 0.5≤X≤0.6, 0.9≤Y≤1, 0.01≤i<0.1, 0.01≤j<0.

1.

10. A testing method, characterized in that: include: Obtaining an expected operand, where the expected operand is determined based on a second operation whose operation logic is inverse to that of a first operation, the expected operand corresponds to an expected operation result of the first operation, the operation precision of the second operation is higher than the expected operation precision of the first operation, the first operation is determined based on an operation instruction of an operation unit, the operation instruction is used to cause the operation unit to perform the first operation on the operand; and the expected operation result is the operation result of the first operation that achieves the expected operation precision; The first operation of the operation unit is tested according to the expected operand, so as to verify the actual operation result obtained by testing the expected operand through the expected operation result corresponding to the first operation of the expected operand.

11. The testing method according to claim 10, characterized in that: The testing of the first operation of the operation unit according to the expected operand includes: Inputting the expected operand into the operation unit, causing the operation unit to perform the first operation on the expected operand and determine an actual operation result corresponding to the expected operand; The actual operation result is compared with the expected operation result to verify whether the first operation performed by the operation unit meets expectations.

12. A test data generating device, characterized in that: include: a first operation module, configured to determine an operation instruction of the operation unit, wherein the operation instruction is configured to cause the operation unit to perform a first operation on an operand; A second operation module is configured to determine an expected operation result of the first operation; the expected operation result is an operation result of the first operation that achieves an expected operation accuracy; A third operation module is used to determine an expected operand corresponding to the expected operation result based on a second operation operation whose operation logic is opposite to that of the first operation operation; the operation accuracy of the second operation operation is higher than the expected operation accuracy of the first operation operation; the expected operand is used to test the first operation of the operation unit.

13. A testing device, characterized in that: include: an acquisition module, configured to acquire an expected operand, the expected operand being determined based on a second operation having an inverse operation logic to a first operation, the expected operand corresponding to an expected operation result of the first operation, the operation precision of the second operation being higher than the expected operation precision of the first operation, the first operation being determined based on an operation instruction of an operation unit, the operation instruction being configured to cause the operation unit to perform the first operation on the operand; the expected operation result being an operation result of the first operation that achieves the expected operation precision; The testing module is used to test the first operation of the operation unit according to the expected operand, so as to verify the actual operation result obtained by the expected operand test through the expected operation result of the first operation corresponding to the expected operand.

14. A computer device, characterized in that: include: a memory storing at least one set of instructions; The processor executes the at least one set of instructions to perform the test data generation method according to any one of claims 1 to 9, or the test method according to any one of claims 10 to 11.

15. A readable storage medium, characterized in that The readable storage medium stores at least one set of instructions, and the at least one set of instructions is used to enable a processor to execute the test data generating method according to any one of claims 1 to 9, or the test method according to any one of claims 10 to 11.

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