Method, apparatus, medium, and device for calculating chip layout of a wafer

Abstract

The present disclosure provides a method, apparatus, medium and device for calculating the wafer layout of a wafer, belonging to the field of semiconductor technology. The method includes: based on the distribution array of each wafer, taking any wafer as a reference wafer, moving the wafer center in a preset area according to a first step length to determine the first coverage area after each movement, and determining the feasible area of the reference wafer according to the number of complete wafers in the coverage area; moving the wafer center in the feasible area according to a second step length to determine the second coverage area after each movement, and determining the maximum number of complete wafers in the coverage area; placing the reference wafer at different positions in the single-exposure area in turn according to the wafer position distribution pattern of the single-exposure area of the lithography machine to determine the minimum number of exposures for exposing all wafers; determining the positions of each wafer according to the maximum number and the minimum number of exposures to generate a wafer layout. The present disclosure can improve the accuracy and efficiency of calculating the maximum number of wafers.

Description

Background Art

[0002] A wafer is a basic raw material for manufacturing semiconductor devices. Each wafer can be cut into multiple chips, and each chip can be fabricated into a chip after processes and procedures such as packaging and testing. Generally, before cutting each wafer, it is necessary to determine the maximum number of complete chips that can be cut from the wafer in order to increase the chip yield and reduce the manufacturing cost.

[0003] Currently, the number X of complete chips that a wafer can be cut into is mainly calculated by the following formula: However, only an approximate number of chips that can be cut from the wafer can be obtained in this way, and there is a large error between the actual maximum number of chips that can be cut from the wafer in actual production. In some technologies, the number of complete chips in a wafer can also be calculated by the step search method, but the calculation process of this method is relatively complex and the calculation time is also relatively long.

[0004] Therefore, a method capable of quickly and accurately calculating the chip layout in a wafer needs to be provided.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The present disclosure provides a method for calculating the chip layout of a wafer, a device for calculating the chip layout of a wafer, a computer-readable storage medium, and an electronic device, thereby at least to some extent improving the problem of difficulty in determining the maximum number of chips in the prior art.

[0007] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be learned in part through the practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, there is provided a method for calculating a wafer layout of a wafer. The method includes: based on the distribution array of each chip in the wafer, taking any chip as a reference chip, moving the wafer center within a preset area of the reference chip according to a first step length to determine a first coverage area of the wafer after each movement, and determining a feasible area of the reference chip according to the number of complete chips in the first coverage area; moving the wafer center within the feasible area according to a second step length to determine a second coverage area of the wafer after each movement, and determining the maximum number of complete chips in the second coverage area; after determining the maximum number of complete chips, placing the reference chip in different chip positions within the single exposure area of the lithography machine in sequence according to the chip position distribution pattern of the single exposure area of the lithography machine to determine the minimum number of exposures for exposing all chips; determining the positions of each chip in the wafer according to the maximum number of complete chips and the minimum number of exposures for all chips to generate the wafer layout of the wafer.

[0009] In an exemplary embodiment of the present disclosure, the distribution array of each chip in the wafer is determined by the following method: based on a pre-established two-dimensional coordinate system, determining the positions of each chip in the wafer according to the size of the chip to obtain the distribution array of each chip.

[0010] In an exemplary embodiment of the present disclosure, the step of, based on the distribution array of each chip in the wafer, taking any chip as a reference chip, moving the wafer center within a preset area of the reference chip according to a first step length to determine a first coverage area of the wafer after each movement, and determining a feasible area of the reference chip according to the number of complete chips in the first coverage area includes: taking any chip in the distribution array as a reference chip and moving the wafer center within a preset area of the reference chip according to a first step length; after each movement, determining the first coverage area of the wafer according to the current position of the wafer center and calculating the number of complete chips in the first coverage area; when the number of complete chips is the largest, determining the position of the wafer center and determining the wafer area formed by the wafer centers as the feasible area.

[0011] In an exemplary embodiment of the present disclosure, the preset area includes any number of 1 / 4 rectangular areas of the reference chip. The step of moving the wafer center within a preset area of the reference chip according to a first step length includes: dividing any number of 1 / 4 rectangular areas of the reference chip into a plurality of sub-areas, where the sub-areas include squares with side lengths equal to the first step length; moving the wafer center within the plurality of sub-areas according to the first step length until all the sub-areas are traversed.

[0012] In an exemplary embodiment of the present disclosure, determining the wafer region formed by the wafer centers as the feasible region includes: when the wafer centers are located on the same straight line, determining the region with a distance less than a preset distance from the straight line where the wafer centers are located as the feasible region; or when at least three wafer centers are located on different straight lines, connecting each of the wafer centers to determine the largest enclosed region formed by each of the wafer centers as the feasible region.

[0013] In an exemplary embodiment of the present disclosure, moving the wafer center in the feasible region according to the second step length to determine the second coverage area of the wafer after each movement and determining the maximum number of complete wafers in the second coverage area includes: dividing the feasible region into a plurality of squares, the side length of each square being equal to the second step length; using the Moore neighborhood tracking algorithm to move the wafer center in the plurality of squares according to the second step length; after each movement, determining the second coverage area of the wafer according to the current position of the wafer center and determining the maximum number of complete wafers in the second coverage area.

[0014] In an exemplary embodiment of the present disclosure, using the Moore neighborhood tracking algorithm to move the wafer center in the plurality of squares according to the second step length includes: in the plurality of squares, determining any one square in the feasible region as the initial position of the wafer center and moving the wafer center in the plurality of squares in a clockwise or counterclockwise direction according to the second step length; at each movement, determining the second coverage area according to the current position of the wafer center and determining the number of complete wafers in the second coverage area; when moving the wafer center next time, determining the second coverage area according to the current position of the wafer center to use the number of complete wafers in the second coverage area as the current number of complete wafers; comparing the current number of complete wafers with the number of complete wafers at the initial position of the wafer center to use the square where the current wafer center is located as the initial position when the current number of complete wafers is equal to or greater than the number of complete wafers at the initial position of the wafer center.

[0015] In an exemplary embodiment of the present disclosure, after determining the maximum number of complete wafers, the method further includes: determining the wafer coverage area of all effective wafers among all the complete wafers; determining the number of edge effective wafers and non-edge effective wafers of the wafer in the wafer coverage area; calculating the product of the number of edge effective wafers and a preset constant to determine the sum of the product and the number of non-edge effective wafers as the maximum true number of effective wafers.

[0016] In an exemplary embodiment of the present disclosure, placing the reference wafer at different wafer positions within the single-exposure area in sequence to determine the minimum number of exposures for exposing all wafers includes: determining the number of exposures for the lithography machine to expose all wafers at the different wafer positions to obtain the minimum number of exposures for exposing all wafers.

[0017] In an exemplary embodiment of the present disclosure, determining the positions of the wafers in the wafer to generate the wafer layout according to the maximum number of complete wafers and the minimum number of exposures for all wafers includes: determining the target coverage area of the wafer and the positions of the wafers in the target coverage area according to the maximum number of complete wafers and the minimum number of exposures for all wafers to generate the wafer layout; or determining the target coverage area of the wafer and the positions of the wafers in the target coverage area according to the maximum true number of valid wafers and the minimum number of exposures for all wafers to generate the wafer layout; wherein the positions of the wafers include the positions of all complete wafers or all wafers in the wafer.

[0018] In an exemplary embodiment of the present disclosure, when there are multiple target coverage areas, the method further includes: determining the edges where the complete wafers or valid wafers are located in each target coverage area, and calculating the distances between the edges where the complete wafers or valid wafers are located and the edge of the wafer, so as to determine the target coverage area with the maximum distance as the optimal wafer coverage area; determining the positions of all complete wafers or all wafers in the wafer in the optimal wafer coverage area to generate the wafer layout.

[0019] According to a second aspect of the present disclosure, there is provided a wafer layout calculation device for a wafer. The wafer layout calculation device includes: a first moving module, configured to move the wafer center within a preset area of the reference wafer at a first step length based on the distribution array of the wafers in the wafer, taking any wafer as the reference wafer, to determine the first coverage area of the wafer after each movement, and determine the feasible area of the reference wafer according to the number of complete wafers in the first coverage area; a second moving module, configured to move the wafer center within the feasible area at a second step length to determine the second coverage area of the wafer after each movement, and determine the maximum number of complete wafers in the second coverage area; a determining module, configured to, after determining the maximum number of complete wafers, place the reference wafer at different wafer positions within the single-exposure area of the lithography machine in sequence according to the wafer position distribution pattern of the single-exposure area, and determine the minimum number of exposures for exposing all wafers; a generating module, configured to determine the positions of the wafers in the wafer according to the maximum number of complete wafers and the minimum number of exposures for all wafers to generate the wafer layout of the wafer.

[0020] In an exemplary embodiment of the present disclosure, the first moving module is configured to determine the distribution array of each wafer in the following manner: Based on a pre-established two-dimensional coordinate system, determine the positions of the wafers in the wafer according to the sizes of the wafers, so as to obtain the distribution array of the wafers.

[0021] In an exemplary embodiment of the present disclosure, the first moving module is configured to use any wafer in the distribution array as a reference wafer, move the center of the wafer within a preset area of the reference wafer according to a first step length. After each movement, determine the first coverage area of the wafer according to the current position of the center of the wafer, and calculate the number of complete wafers in the first coverage area. When the number of complete wafers is the largest, determine the position of the center of the wafer, and determine the wafer area formed by the centers of the wafers as the feasible area.

[0022] In an exemplary embodiment of the present disclosure, the preset area includes any number of 1 / 4 rectangular areas of the reference wafer. The first moving module is configured to divide any number of 1 / 4 rectangular areas of the reference wafer into multiple sub-areas. The sub-areas include squares with side lengths equal to the first step length, and move the center of the wafer within the multiple sub-areas according to the first step length until all the sub-areas are traversed.

[0023] In an exemplary embodiment of the present disclosure, the first module is further configured to, when the centers of the wafers are on the same straight line, determine the area with a distance less than a preset distance from the straight line where the centers of the wafers are located as the feasible area, or when there are at least three centers of the wafers on different straight lines, connect the centers of the wafers to determine the largest enclosed area formed by the centers of the wafers as the feasible area.

[0024] In an exemplary embodiment of the present disclosure, the second moving module is configured to divide the feasible area into multiple squares, the side lengths of the squares are equal to the second step length. Adopt the Moore neighborhood tracking algorithm, move the center of the wafer within the multiple squares according to the second step length. After each movement, determine the second coverage area of the wafer according to the current position of the center of the wafer, and determine the maximum number of complete wafers in the second coverage area.

[0025] In an exemplary embodiment of the present disclosure, the second moving module is further configured to, among the plurality of squares, determine any square in the feasible region as the initial position of the wafer center, move the wafer center in a clockwise or counterclockwise direction among the plurality of squares according to a second step length. When moving each time, determine a second coverage area according to the current position of the wafer center, and determine the number of complete wafers in the second coverage area. When moving the wafer center next time, determine the second coverage area according to the current position of the wafer center, so as to use the number of complete wafers in the second coverage area as the current number of complete wafers. Compare the current number of complete wafers with the number of complete wafers when the wafer center is at the initial position, so as to, when the current number of complete wafers is equal to or greater than the number of complete wafers when the wafer center is at the initial position, use the square where the current wafer center is located as the initial position.

[0026] In an exemplary embodiment of the present disclosure, after determining the maximum number of complete wafers, the second moving module is further configured to, among all the complete wafers, determine the wafer coverage area of all the effective wafers, determine the number of edge effective wafers and non-edge effective wafers of the wafer in the wafer coverage area, calculate the product of the number of edge effective wafers and a preset constant, so as to determine the sum of the product and the number of non-edge effective wafers as the maximum true number of effective wafers.

[0027] In an exemplary embodiment of the present disclosure, the determining module is configured to determine the number of exposure times for the lithography machine to expose all wafers at different wafer positions, so as to obtain the minimum number of exposure times for exposing all wafers.

[0028] In an exemplary embodiment of the present disclosure, the generating module is configured to determine the target coverage area of the wafer and the positions of each wafer in the target coverage area according to the maximum number of complete wafers and the minimum number of exposure times for all wafers, so as to generate the wafer layout; or determine the target coverage area of the wafer and the positions of each wafer in the target coverage area according to the maximum true number of effective wafers and the minimum number of exposure times for all wafers, so as to generate the wafer layout; wherein, the positions of each wafer include the positions of all complete wafers or all wafers in the wafer.

[0029] In an exemplary embodiment of the present disclosure, when there are multiple target coverage areas, the generating module is further configured to determine the edges where the complete wafers or valid wafers are located in each of the target coverage areas, and calculate the distances between the edges where the complete wafers or the valid wafers are located and the edge of the wafer, so as to determine the target coverage area with the largest distance as the optimal wafer coverage area, and determine the positions of all the complete wafers or all the wafers in the wafer in the optimal wafer coverage area, so as to generate the wafer layout.

[0030] According to a third aspect of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the wafer layout calculation method of any one of the above-mentioned wafers is implemented.

[0031] According to a fourth aspect of the present disclosure, there is provided an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein, the processor is configured to execute the wafer layout calculation method of any one of the above-mentioned wafers by executing the executable instructions.

[0032] The present disclosure has the following beneficial effects:

[0033] According to the wafer chip layout calculation method, wafer chip layout calculation device, computer-readable storage medium, and electronic device in this exemplary embodiment, based on the distribution array of each chip in the wafer, taking any chip as the reference chip, the wafer center can be moved within the preset area of the reference chip according to the first step length. The number of complete chips in the first coverage area of the wafer after each movement is determined, and the feasible area is determined according to the number of complete chips. After determining the feasible area, the entire feasible area is further precisely searched within the feasible area according to the second step length to obtain the maximum number of complete chips. After determining the maximum number of complete chips, according to the chip position distribution pattern of the single exposure area of the lithography machine, the reference chip is successively placed at different chip positions within the single exposure area to determine the minimum number of exposures for exposing all chips. Thus, according to the above maximum number of complete chips and the minimum number of exposures for all chips, the positions of each chip in the wafer are determined to generate the chip layout of the wafer. On the one hand, in this exemplary embodiment, by searching for the feasible area within the preset area of the reference chip according to the first step length and further searching for the maximum number of complete chips within the feasible area according to the second step length, the accuracy of determining the maximum number of complete chips is improved. And since this method only needs to search for a partial area of the reference chip instead of the entire reference chip area, the calculation amount and calculation time for calculating the maximum number of complete chips in the wafer are reduced to a considerable extent, and the efficiency of generating the wafer chip layout is improved. On the other hand, by generating the chip layout of the wafer according to the maximum number of complete chips and the minimum number of exposures for all chips, the optimal cutting plan of the wafer can be determined in advance, enabling the operator to cut the wafer according to this optimal cutting plan, avoiding the problems of low chip yield and high production cost caused by cutting the wafer in the conventional manner.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing the embodiments in line with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 The flowchart showing a wafer chip layout calculation method in this exemplary embodiment;

[0037] Figure 2 The schematic diagram showing a distribution array in this exemplary embodiment;

[0038] Figure 3 Sub - flowchart showing a method for calculating the chip layout of a wafer in this exemplary embodiment;

[0039] Figure 4 Schematic diagram showing a chip structure in this exemplary embodiment;

[0040] Figure 5 Schematic diagram showing the area of a reference wafer in this exemplary embodiment;

[0041] Figure 6A and Figure 6B Schematic diagrams respectively showing a feasible area in this exemplary embodiment;

[0042] Figure 7 Sub - flowchart showing another method for calculating the chip layout of a wafer in this exemplary embodiment;

[0043] Figure 8 Schematic diagram showing a method for moving the center of a wafer in this exemplary embodiment;

[0044] Figure 9 Schematic diagram showing a boundary search method in this exemplary embodiment;

[0045] Figure 10 Schematic diagrams showing edge - effective chips and non - edge - effective chips in this exemplary embodiment;

[0046] Figure 11 Schematic diagram showing a chip position distribution pattern in this exemplary embodiment;

[0047] Figure 12A and Figure 12B Schematic diagrams respectively showing an exposure method in this exemplary embodiment;

[0048] Figure 13A and Figure 13B Schematic diagrams respectively showing an optimal wafer coverage area in this exemplary embodiment;

[0049] Figure 14A and Figure 14B Schematic diagrams respectively showing another optimal wafer coverage area in this exemplary embodiment;

[0050] Figure 15 Block diagram showing the structure of a chip layout calculation device for a wafer in this exemplary embodiment;

[0051] Figure 16 Computer - readable storage medium for implementing the above - mentioned method in this exemplary embodiment;

[0052] Figure 17 An electronic device for implementing the above method in this exemplary embodiment is shown. Detailed implementation manners

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0054] An exemplary embodiment of the present disclosure first provides a method for calculating a wafer layout of a wafer. Figure 1 A process of this exemplary embodiment is shown, which may include the following steps S110 to S140:

[0055] Step S110. Based on the distribution array of each wafer in the wafer, taking any wafer as a reference wafer, move the wafer center within a preset area of the reference wafer according to a first step length to determine the first coverage area of the wafer after each movement, and determine the feasible area of the reference wafer according to the number of complete wafers in the first coverage area.

[0056] Among them, the distribution array of each wafer in the wafer can be used to represent the initial positions of the wafers in the wafer; the reference wafer refers to the wafer used as a position reference in the distribution array, which can be any wafer in the distribution array; the first step length refers to the distance that the wafer center moves each time in the reference wafer, and its value range is generally 10 μm to 100 μm, further it can be 10 μm to 50 μm, and specifically it can be set to 20 μm; the preset area can be any area of the reference wafer. In particular, according to the symmetry of the reference wafer structure, the preset area can only include the symmetric area in the reference wafer; the first coverage area is the area where the circular area formed with the wafer center as the center and the wafer radius as the radius coincides with the distribution array of each wafer after each movement of the wafer center. For example, referring to Figure 2 as shown, in the distribution array 100 of the wafers, the area 200 surrounded by the circle is a first coverage area; a complete wafer can be a wafer without defects in the distribution array of each wafer; the feasible area of the reference wafer can be the area in the reference wafer where a relatively large or the largest number of complete wafers can be obtained.

[0057] In this exemplary embodiment, in order to facilitate determining the positions of each wafer in the distribution array, in an optional implementation manner, the positions of each wafer in the wafer can be determined based on a pre-established two-dimensional coordinate system according to the sizes of the wafers, so as to obtain the distribution array of each wafer. For example, continue to refer to Figure 2As shown in the figure, in a two-dimensional coordinate system with the X-axis as the horizontal axis and the Y-axis as the vertical axis, a single wafer can be presented as a small square with a determined side length. According to the size of the wafer, such as the side length, the distribution array 200 of each wafer can be determined in the two-dimensional coordinate system, and the positions of each wafer in the distribution array can also be determined, such as the coordinates of the wafer center, etc. It should be noted that in the wafer dicing process, for the convenience of dicing, each row and each column of wafers are arranged neatly, and in order to obtain the maximum number of diced wafers, there can be a small dicing gap between adjacent wafers.

[0058] In the distribution array of each wafer, any one wafer can be selected as the reference wafer, and the wafer center can be set within the preset area of the reference wafer. And when the wafer center is at different positions within the preset area of the reference wafer, the number of complete wafers in the first coverage area of the corresponding wafer is different. Therefore, in order to determine the position with a larger or maximum number of complete wafers within the preset area of the reference wafer, the wafer center can be moved within the preset area of the reference wafer according to the first step length. Thus, after each movement, the first coverage area of the wafer can be determined, and the number of complete wafers in this first coverage area can be calculated to determine the feasible area of the reference wafer.

[0059] In an alternative embodiment, when searching for the preset area of the reference wafer according to the first step length, step S110 can be implemented by determining the position of the wafer center with the maximum number of complete wafers in the preset area and determining the feasible area from the positions of each wafer center. Specifically, referring to Figure 3 as shown, it can include the following steps S310 to S330:

[0060] Step S310. Select any wafer in the above distribution array as the reference wafer, and move the wafer center within the preset area of the reference wafer according to the first step length.

[0061] Step S320. After each movement, determine the first coverage area of the wafer according to the current position of the wafer center, and calculate the number of complete wafers in the first coverage area.

[0062] Step S330. When the number of complete wafers is the largest, determine the position of the wafer center, and determine the wafer area composed of this wafer center as the feasible area.

[0063] In a preset area of the reference wafer, the center of the wafer can be moved along a certain direction by a first step length starting from any position, such as the upper left corner position of the reference wafer. After each movement, a circular area, that is, the first coverage area, is determined with the current position of the center of the wafer as the center and the radius of the wafer as the radius. The number of complete wafers in this area is calculated, that is, the complete wafers falling into the above circular area. In this way, the number of complete wafers in the first coverage area of the wafer after each movement of the center of the wafer is determined. Thus, when the maximum value of the number of complete wafers is obtained, the position of the center of the wafer corresponding to this maximum value is determined, and the area formed by this position is determined as the feasible area.

[0064] The researchers of the present disclosure have found through research that when the center of the wafer is at different positions within a wafer, the number of complete wafers that the wafer can obtain shows a certain pattern. Specifically, as shown in Figure 4 When the center of the wafer is located in the color block area with the same color depth in the wafer, the number of complete wafers that a single wafer can obtain is the same. Correspondingly, when the center of the wafer is located in the color block areas with different color depths, the number of complete wafers that a single wafer can obtain is different, and in the entire wafer area, the color distribution of the number of complete wafers shows the characteristics of being symmetric up and down and left and right. Therefore, in order to reduce the computational complexity increased by searching for symmetric areas and improve the efficiency of determining the feasible area, in an optional implementation manner, the above preset area may include any number of 1 / 4 rectangular areas of the reference wafer. As shown in Figure 5 The 1 / 4 rectangular areas 510, 520, 530, and 540 of the reference wafer 500 are located in the upper left corner area, upper right corner area, lower left corner area, and lower right corner area of the reference wafer respectively. Thus, the method of moving the center of the wafer within the preset area of the reference wafer by the first step length can be implemented in the following manner:

[0065] Divide any number of 1 / 4 rectangular areas of the reference wafer into multiple sub-areas, and the sub-areas include squares with side lengths equal to the first step length;

[0066] Move the center of the wafer in multiple sub-areas by the first step length until all sub-areas are traversed.

[0067] Continue to refer to Figure 5As shown, any number of rectangular regions of the reference wafer 500 can be divided into multiple sub-regions. Taking the rectangular region 510 as an example, the rectangular region 510 is divided into multiple sub-regions, and each sub-region can be a square with a side length equal to the first step length. When searching according to the first step length, any position in any sub-region can be used as the starting point, such as the center of the sub-region. The wafer center is moved sequentially, and after each movement, the first coverage area is determined according to the current position of the wafer center, and the number of complete wafers in the first coverage area is calculated until all sub-regions are searched. The maximum number of complete wafers is determined according to the number of complete wafers in the first coverage area corresponding to the wafer center in each sub-region, and the feasible region is determined according to the positions of the wafer centers corresponding to the maximum number. For example, as Figure 5 shown, when obtaining the maximum value of the number of complete wafers, the positions of the wafer centers where the maximum value is located are a, b, c, and d respectively. The rectangular region 520 formed by a, b, c, and d can be used as the feasible region of the above reference wafer.

[0068] In the reference wafer, there may be multiple positions of the wafer center with the maximum number of complete wafers, and the relationship between the positions may not be fixed. Therefore, in an alternative embodiment, the above determination of the wafer region composed of the wafer centers as the feasible region can be achieved by the following method:

[0069] When the wafer centers are on the same straight line, the region with a distance less than the preset distance from the straight line where the wafer centers are located is determined as the feasible region; or

[0070] When there are at least three wafer centers on different straight lines, connect the wafer centers to determine the maximum enclosed region composed of the wafer centers as the feasible region.

[0071] Among them, the preset distance can generally be set according to the value of the first step length. For example, since the value range of the first step length can be 10 μm to 100 μm, further it can be 10 μm to 50 μm, specifically it can be set to 20 μm, then the value range of the preset distance can be 5 μm to 50 μm, further it can be set to 5 μm to 20 μm, specifically it can be set to 10 μm; the maximum enclosed region can be the region within a certain range composed of the wafer centers. For example, it can be the largest enclosed region obtained by connecting the wafer centers, such as Figure 5 the rectangular region formed by a, b, c, and d shown in, or it can also be the region that connects the wafer centers and is less than the above preset distance from the straight line where each wafer center is located.

[0072] Specifically, as Figure 6AAs shown, the centers of the wafers with the largest number of complete wafers in the rectangular region are located on the same straight line. In this case, the region 610 whose distance from the straight line where each wafer center is located is less than the preset distance can be determined as the obtained feasible region; when at least three of the wafer centers are located on different straight lines, the wafer centers can be connected, and the largest enclosed region formed by the wafer centers can be determined as the feasible region. As shown in Figure 6B the largest enclosed region 620 formed by the wafer centers may include each wafer center and the region whose distance from the straight line where each wafer center is located is less than the preset distance.

[0073] In addition, in the above method of dividing any number of 1 / 4 rectangular regions of the reference wafer into multiple sub-regions, the size of each sub-region can be set according to requirements. The smaller the size of the sub-region, the more the number of sub-regions, the higher the corresponding search accuracy, the smaller the range of the obtained feasible region, and the longer the calculation time; conversely, the larger the size of the sub-region, the lower the search accuracy, the larger the range of the obtained feasible region, and the shorter the calculation time.

[0074] Through the above step S110, the search can be carried out in the preset region of the reference wafer according to the first step length, and the feasible region of the reference wafer can be determined. And because the preset region of the reference wafer only includes a part of the reference wafer, the calculation amount and time for determining the feasible region are greatly reduced.

[0075] Step S120. Move the wafer center in the above feasible region according to the second step length to determine the second coverage area of the wafer after each movement, and determine the maximum number of complete wafers in the second coverage area.

[0076] Among them, the value of the second step length is less than the first step length. Generally, the value range of the second step length can be from 0.1 to 10 μm, and specifically, it can be set by the operator himself; the second coverage area refers to the circular area formed with the wafer center as the center and the wafer radius as the radius after each movement when moving the wafer center according to the second step length, that is, the area where the wafer coincides with the distribution array of the wafers when the wafer is at the position of the wafer center after each movement.

[0077] After determining the feasible region, further search can be carried out in the feasible region to determine the exact position with the largest number of complete wafers. Specifically, the wafer center can be moved in the feasible region according to the second step length, and after each movement, the corresponding second coverage area can be determined according to the position of the wafer center, and the number of complete wafers in each second coverage area can be calculated, so as to determine the position of the wafer center with the largest number of complete wafers.

[0078] To improve the efficiency of determining the maximum number of complete wafers in the second coverage area, in an alternative embodiment, a search can be performed in the above-mentioned feasible area by means of boundary tracking method. Specifically, referring to Figure 7 as shown, the following steps S710 to S730 can be included:

[0079] Step S710. Divide the feasible area into a plurality of squares, and the side length of each square is equal to the second step length.

[0080] Step S720. Move the wafer center in the above-mentioned plurality of squares according to the second step length.

[0081] Step S730. After each movement, determine the second coverage area of the wafer according to the current position of the wafer center, and determine the maximum number of complete wafers in the second coverage area.

[0082] Divide the feasible area into a plurality of squares, and the side length of each square is equal to the second step length. For example, it can be set to 1 μm. Taking any position in any square, such as the center of the square, as the starting position, adopt a boundary tracking algorithm, such as the Moore neighborhood boundary tracking algorithm, move the wafer center in the feasible area according to the second step length, and determine the corresponding second coverage area of the wafer after each movement to calculate the maximum number of complete wafers in this area.

[0083] Specifically, in an alternative embodiment, step S720 can also be implemented by the following method:

[0084] In the above-mentioned plurality of squares, determine any square in the above-mentioned feasible area as the initial position of the wafer center, and move the wafer center in the above-mentioned plurality of squares in a clockwise or counterclockwise direction according to the second step length;

[0085] At each movement, determine the second coverage area according to the current position of the wafer center, and determine the number of complete wafers in the second coverage area;

[0086] When moving the wafer center next time, determine the second coverage area according to the current position of the wafer center, and use the number of complete wafers in the second coverage area as the current number of complete wafers;

[0087] Compare the above-mentioned current number of complete wafers with the number of complete wafers when the wafer center is at the above-mentioned initial position. When the above-mentioned current number of complete wafers is equal to or greater than the number of complete wafers when the wafer center is at the above-mentioned initial position, use the square where the current wafer center is located as the initial position.

[0088] Such as Figure 8As shown, the feasible region 800 is divided into multiple squares. Taking any position in any square within the above-mentioned optional region, such as the vertices of the square or any position within the square, such as the center of the square, etc., as the starting position, move the center of the wafer along the second step length in the clockwise or counterclockwise direction. As shown in the figure, taking P as the initial position, determine the second coverage area of the wafer at this position, and calculate the number of complete wafers in this coverage area. Move the center of the wafer along the second step length in the clockwise direction. After the first move, the position of the center of the wafer is P1. At this time, calculate the second coverage area of the wafer again and obtain the number of complete wafers as the current number of complete wafers. Compare the size of this current number of complete wafers with the number of complete wafers when the center of the wafer was at the previous position, that is, the initial position P. When the current number of complete wafers is greater than or equal to the number of complete wafers when the center of the wafer was at the initial position P, determine the position P1 of the center of the wafer at the current moment, that is, the position of the center of the wafer after the first move, as the new initial position, and move the center of the wafer along the second step length in the clockwise direction again; otherwise, do not update the initial position and continue to move the position of the center of the wafer in the clockwise direction to P2, and calculate the corresponding current number of complete wafers. Compare the current number of complete wafers obtained when the center of the wafer is at position P2 with the number of complete wafers when the center of the wafer was at the initial position. If the current number of complete wafers obtained when the center of the wafer is at position P2 is greater than or equal to the number of complete wafers when the center of the wafer was at the initial position, determine P2 as the new initial position; otherwise, continue to move the center of the wafer in the clockwise direction to position P3 and make another judgment. Search the above-mentioned squares in this way until a complete circle is searched clockwise or counterclockwise from a certain initial position and no position with a number of complete wafers greater than or equal to the number of complete wafers when the center of the wafer was at the above initial position is found, then stop the search and determine this initial position as the position of the center of the wafer with the maximum number of complete wafers.

[0089] Through the above search method, the position of the center of the wafer with the maximum number of complete wafers can be further determined in the feasible region. For example, as shown in Figure 9 In the figure, when searching for the position of the center of the wafer with the maximum number of complete wafers through the boundary tracking algorithm, 910 can be used as the initial position. Through the boundary tracking algorithm, determine the position of the center of each wafer with the maximum number of complete wafers until the position 930 of the center of the wafer with the maximum number of complete wafers is searched. The positions of the center of each wafer after each search form the search path 920. In this way, the maximum number of complete wafers in the feasible region and the position of the center of each wafer with the maximum number of complete wafers can be determined.

[0090] Furthermore, since the yield of edge wafers is relatively low, after determining the maximum number of complete wafers in the wafer, it is necessary to determine the maximum actual number of effective wafers in the wafer. Specifically, in an optional implementation manner, it can be achieved through the following method:

[0091] In all complete wafers, determine the wafer coverage areas of all valid wafers;

[0092] In the above-mentioned wafer coverage areas, determine the number of edge valid wafers and non-edge valid wafers of the wafer;

[0093] Calculate the product of the number of edge valid wafers and a preset constant, and determine the sum of this product and the number of non-edge valid wafers as the maximum true number of valid wafers.

[0094] Among them, during the wafer manufacturing process, the wafers at the edge of the wafer have a very low yield due to the manufacturing process, so they will be regarded as invalid wafers in the later stage. While the wafers in the central area have a relatively high yield, so they can be regarded as valid wafers.

[0095] After determining the maximum number of complete wafers in the wafer, the wafer coverage areas of each valid wafer, that is, the central area, can be determined, and in this wafer coverage area, the number of edge valid wafers and non-edge valid wafers of the wafer can be determined. It can be understood that after determining the valid wafers in the central area of the wafer, because the yield of the wafers near the edge of the central area is lower than that near the center of the central area, so when calculating the true number of wafers, a coefficient can be introduced, that is, the maximum true number of valid wafers = the number of edge valid wafers * k + the number of non-edge valid wafers, where 0 < k < 1, so as to obtain the best wafer layout method. The specific value of k can be obtained according to the yield distribution map of the wafer in the actual production process. Specifically, as shown in Figure 10 As shown, the wafer may include an edge area 1010 and a central area 1020. The wafers in the edge area 1010 of the wafer are invalid wafers. The central area 1020 may include an edge valid wafer area 1021 and a non-edge valid wafer area 1022. Among them, the yield coefficient of the wafers in the non-edge valid wafer area 1022 is 1. The valid wafers in the edge valid wafer area 1021 are the edge valid wafers. Multiply the number of edge valid wafers by a coefficient less than 1, and add the number of non-edge valid wafers, which is the maximum true number of all valid wafers. It can be understood that in this exemplary embodiment, the wafers at the junction of the central area and the edge area of the wafer can be regarded as invalid wafers, and the wafers at the junction of the non-edge valid wafer area and the edge valid wafer area of the wafer can be regarded as edge valid wafers. In other embodiments, classification can also be planned according to the actual situation.

[0096] Through the above steps S110 - S120, a feasible area can be determined, and in the feasible area, the maximum number of complete wafers can be further determined. And compared with the method of searching according to the step-by-step method, the efficiency of determining the maximum number of complete wafers is greatly improved.

[0097] Step S130. After determining the maximum number of complete wafers, place the above-mentioned reference wafers at different wafer positions within the single-exposure area in sequence according to the wafer position distribution pattern of the single-exposure area of the lithography machine, so as to determine the minimum number of exposures required to expose all the wafers.

[0098] Among them, the single-exposure area refers to the wafer area that the lithography machine can expose at one time; the wafer position distribution pattern refers to the distribution pattern of the wafers when the lithography machine exposes at one time. For example, as Figure 11 shown, there are 9 wafers distributed in an array within the single-exposure area, and this array distribution pattern is the wafer position distribution pattern of the single-exposure area of the lithography machine. It can be known from Figure 11 that the lithography machine can expose 9 wafers distributed in this array at one time; all the wafers can include all the complete wafers and incomplete wafers in the wafer.

[0099] In the semiconductor manufacturing process, after determining the maximum number of complete wafers in the wafer and the positions of each complete wafer, it is necessary to cut the wafer according to the positions of the wafers in the wafer. At this time, an exposure process needs to be adopted, that is, the wafer position distribution pattern is printed on the wafer through the exposure of light. However, due to the large size of the wafer, the lithography machine can only expose several wafers at one time, and it is difficult to complete the exposure of all the wafers on the wafer through one exposure. Generally, multiple exposures are required. Therefore, in an optional implementation manner, after determining the maximum number of complete wafers, in order to determine the minimum number of exposures required to expose all the wafers, the reference wafers can be placed at different positions in the single-exposure area in sequence according to the wafer position distribution pattern of the single-exposure area of the lithography machine, so as to Figure 11 take [a specific example], the reference wafers can be placed at positions A1, A2... A9 shown in the figure in sequence, obtaining 9 different exposure methods, calculating the number of exposures required to expose all the wafers under each exposure method, so as to obtain the minimum number of exposures required to expose all the wafers, and the exposure method corresponding to this minimum number of exposures is the preferred exposure method for exposing all the wafers.

[0100] Specifically, as Figure 12A shown, when the reference wafer is at position A1 in the single-exposure area, each thick-line box in the figure includes 9 wafers, representing one exposure area. After calculation, when the reference wafer is at position A1 in the single-exposure area, the wafer needs to be exposed 22 times to complete the exposure of all the wafers in the wafer; as Figure 12B shown, when the reference wafer is at position A2 in the single-exposure area, the wafer needs to be exposed 26 times to complete the exposure of all the wafers in the wafer. It can be seen that when the position of the reference wafer is different, the number of exposures required for the lithography machine to expose all the wafers is also different. By determining the minimum number of exposures of the lithography machine, the exposure time and exposure cost can be greatly saved.

[0101] Step S140. Determine the positions of the wafers in the wafer according to the maximum number of complete wafers and the minimum exposure times of all wafers, so as to generate the wafer layout of the wafer.

[0102] Among them, the wafer layout refers to the distribution method of all wafers that can be cut out in the wafer, and may include the positions of all wafers or the positions of all complete wafers, etc.

[0103] After obtaining the maximum number of complete wafers and the minimum exposure times of all wafers corresponding to this maximum number, the positions of the wafers can be determined, and thus the wafer layout in the wafer can be determined according to the positions of the wafers. Cutting the wafer according to this wafer layout can obtain the maximum number of complete wafers, and the number of times required to expose all wafers is also the least. Therefore, the manufacturing cost can be reduced under the condition of ensuring the maximum output.

[0104] In an alternative embodiment, step S140 can determine the target coverage area of the wafer and the positions of the wafers in this target coverage area according to the maximum number of complete wafers and the minimum exposure times of all wafers, so as to determine the wafer layout of the wafer according to the positions of the wafers. Among them, the positions of the wafers can be the positions of all complete wafers in the wafer or the positions of all wafers in the wafer.

[0105] In another alternative embodiment, the target coverage area of the wafer and the positions of the wafers in this target coverage area can also be determined according to the maximum true number of effective wafers and the minimum exposure times of all wafers, so as to determine the wafer layout of the wafer according to the positions of the wafers. The wafer layout determined by the maximum true number of effective wafers and the minimum exposure times of all wafers can obtain the best wafer layout method while ensuring the highest overall yield of the wafer.

[0106] When determining the target coverage area, since there may be multiple target coverage areas with the same maximum number of complete wafers and the same minimum exposure times, in this case, it is necessary to determine the best wafer layout. Specifically, in an alternative embodiment, the best wafer layout can be determined in the following way:

[0107] Determine the edges where the complete wafers are located in each target coverage area, and calculate the distance between the edges where the above complete wafers or effective wafers are located and the edge of the wafer, so as to determine the target coverage area with the largest such distance as the best wafer coverage area;

[0108] Determine the positions of all complete wafers or all wafers in the wafer in the above best wafer coverage area to generate the wafer layout.

[0109] Due to the special nature of the wafer material, the stress of the wafer is more unstable closer to the edge, and the hardness of the wafer near the edge is also relatively high. Unstable stress or high stress is not conducive to wafer processing. Therefore, after determining the target coverage area of the wafer, the optimal wafer layout can be determined by determining the maximum distance of the complete wafer from the edge of the wafer, and the wafer layout corresponding to this maximum distance is determined as the optimal wafer layout. Specifically, referring to Figure 13A As shown, in the target coverage area 1300, the complete wafer coverage area is shown as the shaded part. The edge of the complete wafer coverage area is composed of the edges of the outermost complete wafers. The vertical distance between each point on the edges of the outermost complete wafers and the tangent of the edge of the target coverage area 1300 is used as the spacing between the edges of each complete wafer and the edge of the target coverage area. Further, this spacing can be arranged in an array according to the numerical size, and the median of this array is determined as the minimum spacing. Thus, after obtaining the minimum spacing between the edges of the complete wafers and the edge of the target coverage area in all target coverage areas, the target coverage area with the largest first spacing can be determined as the optimal wafer coverage area. Correspondingly, the positions of the wafers in the optimal wafer coverage area constitute the optimal wafer layout of the wafer. It should be noted that the above method of determining the median as the minimum spacing according to the numerical size of the spacing is only an exemplary illustration. According to actual requirements, the minimum spacing can also be the average value of the sum of each spacing, etc. This exemplary embodiment does not make special limitations on this.

[0110] In specific calculations, referring to Figure 13B As shown, taking the diameter S of the target coverage area 1300 in the direction parallel to the Y-axis as the boundary, when the complete wafer 1311 is located in the lower left of the figure, the minimum distance d1 between the complete wafer 1311 and the target coverage area 1300 is the radius of the target coverage area minus the distance between the center of the target coverage area and the lower left vertex of the complete wafer 1311; when the complete wafer 1312 is located in the lower right of the figure, the minimum distance d2 between the complete wafer 1312 and the target coverage area 1300 is the radius of the target coverage area 1300 minus the distance between the center of the target coverage area and the lower right vertex of the complete wafer 1312.

[0111] In another alternative embodiment, when determining the optimal wafer layout, the wafer layout corresponding to the maximum value of the distance between the edge where the effective wafer is located and the edge of the wafer can also be determined as another optimal layout. Specifically, it can be achieved through the following method:

[0112] Determine the edge where the effective wafer is located in each target coverage area, and calculate the distance between the edge where the effective wafer is located and the edge of the wafer, so as to determine the target coverage area with the largest such distance as the optimal wafer coverage area;

[0113] Determine the positions of all complete wafers or all wafers in the wafer within the above-mentioned optimal wafer coverage area to generate a wafer layout.

[0114] Specifically, referring to Figure 14A As shown, the target coverage area 1300 may include a wafer edge wafer area 1310 and a wafer center effective wafer area 1320. Taking the diameter S of the target coverage area 1300 in the direction parallel to the Y-axis as the boundary, as Figure 14B shown, when the effective wafer 1411 in the wafer center effective wafer area 1320 is located at the lower left in the figure, the minimum distance d3 between the effective wafer 1411 and the target coverage area 1300 is the radius of the target coverage area minus the distance between the center of the target coverage area and the lower left vertex of the effective wafer 1411; when the effective wafer 1412 in the wafer center effective wafer area 1320 is located at the lower right in the figure, the minimum distance d4 between the effective wafer 1412 and the target coverage area 1300 is the radius of the target coverage area minus the distance between the center of the target coverage area and the lower right vertex of the effective wafer 1412.

[0115] Thus, after obtaining the distance between the edge where the effective wafer is located and the wafer edge, the target coverage area corresponding to the maximum distance can be used as the optimal wafer coverage area, and further, another optimal wafer layout of the wafer can be generated according to the positions of the wafers in this optimal wafer coverage area.

[0116] In summary, according to the method for calculating the wafer layout of a wafer in this exemplary embodiment, based on the distribution array of each wafer in the wafer, taking any wafer as the reference wafer, moving the wafer center within the preset area of the reference wafer according to the first step length, determining the number of complete wafers in the first coverage area of the wafer after each movement, and determining the feasible area according to the number of complete wafers; after determining the feasible area, further precisely search the entire feasible area within the feasible area according to the second step length to obtain the maximum number of complete wafers; after determining the maximum number of complete wafers, according to the wafer position distribution pattern of the single exposure area of the lithography machine, sequentially place the reference wafer at different wafer positions within the single exposure area to determine the minimum number of exposures for exposing all wafers, so as to determine the positions of each wafer in the wafer according to the above-mentioned maximum number of complete wafers and the minimum number of exposures for all wafers, and generate the wafer layout of the wafer. On the one hand, in this exemplary embodiment, by searching for the feasible area within the preset area of the reference wafer according to the first step length and further searching for the maximum number of complete wafers within the feasible area according to the second step length, the accuracy of determining the maximum number of complete wafers is improved, and since this method only needs to search for a partial area of the reference wafer instead of the entire reference wafer area, the calculation amount and calculation time for calculating the maximum number of complete wafers in the wafer are reduced to a considerable extent, and the efficiency of generating the wafer layout of the wafer is improved; on the other hand, by generating the wafer layout of the wafer according to the maximum number of complete wafers and the minimum number of exposures for all wafers, the optimal cutting plan of the wafer can be determined in advance, enabling the operator to cut the wafer according to the optimal cutting plan, avoiding the problems of low wafer yield and high production cost caused by cutting the wafer in the conventional manner.

[0117] This exemplary embodiment also provides a device for calculating the wafer layout of a wafer. Refer to Figure 15As shown, the wafer layout calculation device 1500 may include: a first moving module 1510, which may be used to, based on the distribution array of each wafer in the wafer, take any wafer as the reference wafer, move the wafer center within the preset area of the reference wafer according to the first step length to determine the first coverage area of the wafer after each movement, and determine the feasible area of the reference wafer according to the number of complete wafers in the first coverage area; a second moving module 1520, which may be used to move the wafer center within the feasible area according to the second step length to determine the second coverage area of the wafer after each movement, and determine the maximum number of complete wafers in the second coverage area; a determination module 1530, which may be used to, after determining the maximum number of complete wafers, place the reference wafer at different wafer positions within the single exposure area in sequence according to the wafer position distribution pattern of the single exposure area of the lithography machine, and determine the minimum number of exposures required to expose all wafers; a generation module 1540, which may be used to determine the positions of each wafer in the wafer according to the maximum number of complete wafers and the minimum number of exposures required to expose all wafers, so as to generate the wafer layout of the wafer.

[0118] In an exemplary embodiment of the present disclosure, the first moving module 1510 may be used to determine the distribution array of each wafer in the following manner: Based on a pre-established two-dimensional coordinate system, determine the positions of each wafer in the wafer according to the size of the wafer to obtain the distribution array of each wafer.

[0119] In an exemplary embodiment of the present disclosure, the first moving module 1510 may be used to take any wafer in the distribution array as the reference wafer, move the wafer center within the preset area of the reference wafer according to the first step length. After each movement, determine the first coverage area of the wafer according to the current position of the wafer center, and calculate the number of complete wafers in the first coverage area. When the number of complete wafers is the largest, determine the position of the wafer center, and determine the wafer area composed of the wafer centers as the feasible area.

[0120] In an exemplary embodiment of the present disclosure, the preset area includes any number of 1 / 4 rectangular areas of the reference wafer. The first moving module 1510 may be used to divide any number of 1 / 4 rectangular areas of the reference wafer into multiple sub-areas. The sub-areas include squares with side lengths equal to the first step length, and move the wafer center within the multiple sub-areas according to the first step length until all sub-areas are traversed.

[0121] In an exemplary embodiment of the present disclosure, the first moving module 1510 may also be used to, when the wafer centers are on the same straight line, determine the area with a distance less than the preset distance from the straight line where the wafer centers are located as the feasible area, or when there are at least three wafer centers on different straight lines, connect the wafer centers to determine the largest enclosed area composed of the wafer centers as the feasible area.

[0122] In an exemplary embodiment of the present disclosure, the second moving module 1520 can be used to divide the feasible region into a plurality of squares, the side length of each square being equal to the second step length. Using the Moore neighborhood tracking algorithm, the wafer center is moved in the plurality of squares according to the second step length. After each movement, the second coverage area of the wafer is determined based on the current position of the wafer center, and the maximum number of complete wafers is determined in the second coverage area.

[0123] In an exemplary embodiment of the present disclosure, the second moving module 1520 can also be used to determine an initial position of the wafer center in any one of the squares in the feasible region among the plurality of squares, and move the wafer center in the plurality of squares in a clockwise or counterclockwise direction according to the second step length. During each movement, the second coverage area is determined based on the current position of the wafer center, and the number of complete wafers in the second coverage area is determined. When moving the wafer center next time, the second coverage area is determined based on the current position of the wafer center, so as to use the number of complete wafers in the second coverage area as the current number of complete wafers. The current number of complete wafers is compared with the maximum number of complete wafers when the wafer center is at the above initial position, so that when the current number of complete wafers is equal to or greater than the number of complete wafers when the wafer center is at the above initial position, the square where the current wafer center is located is used as the initial position.

[0124] In an exemplary embodiment of the present disclosure, after determining the maximum number of complete wafers, the second moving module 1520 can also be used to determine the wafer coverage area of all effective wafers among all the complete wafers, determine the number of edge effective wafers and non-edge effective wafers of the wafer in the wafer coverage area, calculate the product of the number of edge effective wafers and a preset constant, so as to determine the maximum true number of effective wafers as the sum of the product and the number of non-edge effective wafers.

[0125] In an exemplary embodiment of the present disclosure, the determination module 1530 can be used to determine the exposure times for the lithography machine to expose all wafers at different wafer positions, so as to obtain the minimum exposure times for exposing all wafers.

[0126] In an exemplary embodiment of the present disclosure, the generation module 1540 can be used to determine the target coverage area of the wafer and the positions of each wafer in the target coverage area according to the maximum number of complete wafers and the minimum exposure times of all wafers, so as to generate a wafer layout; or determine the target coverage area of the wafer and the positions of each wafer in the target coverage area according to the maximum true number of effective wafers and the minimum exposure times of all wafers, so as to generate a wafer layout; wherein, the positions of each wafer include the positions of all complete wafers in the wafer or the positions of all wafers.

[0127] In an exemplary embodiment of the present disclosure, when there are multiple target coverage areas, the generating module 1540 may further be configured to determine the edges where the complete wafers or effective wafers are located in each target coverage area, and calculate the distances between the edges where the complete wafers or effective wafers are located and the edge of the wafer, so as to determine the target coverage area with the largest distance as the optimal wafer coverage area, and determine the positions of all the complete wafers or all the wafers in the wafer in the optimal wafer coverage area, so as to generate a wafer layout.

[0128] The specific details of each module in the above device have been described in detail in the embodiments of the method part. For the details of the undisclosed solutions, reference can be made to the embodiments of the method part, and thus will not be elaborated here.

[0129] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method, or a program product. Therefore, various aspects of the present disclosure can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuit", "module", or "system" here.

[0130] The exemplary embodiment of the present disclosure also provides a computer-readable storage medium, on which a program product capable of implementing the above method of this specification is stored. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute the steps according to various exemplary embodiments of the present disclosure described in the above "Exemplary Method" part of this specification.

[0131] Reference Figure 16 As shown, a program product 1600 for implementing the above method according to an exemplary embodiment of the present disclosure is described. It can be a portable compact disc read-only memory (CD-ROM) and includes program code, and can run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited to this. In this document, a readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or combined with an instruction execution system, device, or component.

[0132] The program product 1600 may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0133] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable signal medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0134] The program code contained on the readable medium may be transmitted by any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the above.

[0135] The program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., by using an Internet service provider to connect through the Internet).

[0136] The exemplary embodiments of the present disclosure also provide an electronic device capable of implementing the above method. The following refers to Figure 17 to describe the electronic device 1700 according to this exemplary embodiment of the present disclosure. Figure 17 The illustrated electronic device 1700 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0137] As Figure 17 shown, the electronic device 1700 may be presented in the form of a general-purpose computing device. The components of the electronic device 1700 may include, but are not limited to: at least one of the above-described processing units 1710, at least one of the above-described storage units 1720, a bus 1730 connecting different system components (including the storage unit 1720 and the processing unit 1710), and a display unit 1740.

[0138] Among them, the storage unit 1720 stores program code, and the program code can be executed by the processing unit 1710, so that the processing unit 1710 executes the steps according to various exemplary embodiments of the present disclosure described in the "Exemplary Method" section of the present specification above. For example, the processing unit 1710 may execute Figure 1 , Figure 3 and Figure 7 the method steps shown, etc.

[0139] The storage unit 1720 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 1721 and / or a cache storage unit 1722, and may further include a read-only storage unit (ROM) 1723.

[0140] The storage unit 1720 may further include a program / utilities 1724 having a set (at least one) of program modules 1725. Such program modules 1725 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment.

[0141] The bus 1730 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus structures.

[0142] The electronic device 1700 can also communicate with one or more external devices 1800 (such as a keyboard, a pointing device, a Bluetooth device, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 1700, and / or communicate with any device that enables the electronic device 1700 to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 1750. Moreover, the electronic device 1700 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 1760. As shown in the figure, the network adapter 1760 communicates with other modules of the electronic device 1700 through the bus 1730. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 1700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0143] It should be noted that although several modules or units of the devices for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the exemplary embodiments of the present disclosure, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0144] In addition, the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present disclosure, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the chronological order of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously, for example, in multiple modules.

[0145] Through the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or can be implemented by the way of software combined with necessary hardware. Therefore, the technical solutions according to the exemplary embodiments of the present disclosure can be embodied in the form of a software product, and this software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the exemplary embodiments of the present disclosure.

[0146] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are to be considered as exemplary only, and the true scope and spirit of the present disclosure are pointed out by the claims.

Claims

1. A method for calculating the chip layout of a wafer, characterized in that, the method includes: Based on the distribution array of each chip in the wafer, taking any chip in the distribution array as a reference chip, moving the wafer center within the preset area of the reference chip according to the first step length; After each movement, determine the first coverage area of the wafer according to the current position of the wafer center, and calculate the number of complete chips in the first coverage area; When the number of complete chips is the largest, determine the position of the wafer center, and determine the wafer area composed of the wafer centers as the feasible area; Move the wafer center in the feasible area according to the second step length to determine the second coverage area of the wafer after each movement, and determine the maximum number of complete chips in the second coverage area; After determining the maximum number of complete chips, according to the chip position distribution pattern of the single exposure area of the lithography machine, place the reference chip in different chip positions within the single exposure area in sequence to determine the minimum number of exposures for exposing all chips; According to the maximum number of complete chips and the minimum number of exposures for all chips, determine the positions of each chip in the wafer to generate the chip layout of the wafer.

2. The chip layout calculation method according to claim 1, characterized in that, the distribution array of each chip in the wafer is determined by the following method: Based on a pre-established two-dimensional coordinate system, determine the positions of each chip in the wafer according to the size of the chips to obtain the distribution array of each chip.

3. The chip layout calculation method according to claim 1, characterized in that, the preset area includes any number of 1 / 4 rectangular areas of the reference chip, and moving the wafer center within the preset area of the reference chip according to the first step length includes: Dividing any number of 1 / 4 rectangular areas of the reference chip into multiple sub-areas, and the sub-areas include squares with side lengths equal to the first step length; Moving the wafer center in the multiple sub-areas according to the first step length until all the sub-areas are traversed.

4. The chip layout calculation method according to claim 1, characterized in that, determining the wafer area composed of the wafer centers as the feasible area includes: When the wafer centers are on the same straight line, determine the area with a distance less than the preset distance from the straight line where the wafer centers are located as the feasible area; or When there are at least three wafer centers on different straight lines, connect each wafer center to determine the largest enclosed area composed of each wafer center as the feasible area.

5. The chip layout calculation method according to claim 1, characterized in that, moving the wafer center in the feasible area according to the second step length to determine the second coverage area of the wafer after each movement, and determining the maximum number of complete chips in the second coverage area includes: Dividing the feasible area into multiple squares, and the side lengths of each square are equal to the second step length; Moving the wafer center in the multiple squares according to the second step length; After each movement, determine the second coverage area of the wafer according to the current position of the wafer center, and determine the maximum number of complete wafers in the second coverage area.

6. The method for calculating the wafer layout according to claim 5, wherein, the moving the wafer center in the plurality of squares according to the second step length includes: in the plurality of squares, determining any square in the feasible area as the initial position of the wafer center, and moving the wafer center in the plurality of squares in a clockwise or counterclockwise direction according to the second step length; at each movement, determine the second coverage area according to the current position of the wafer center, and determine the number of complete wafers in the second coverage area; when moving the wafer center next time, determine the second coverage area according to the current position of the wafer center, and use the number of complete wafers in the second coverage area as the current number of complete wafers; compare the current number of complete wafers with the number of complete wafers when the wafer center is at the initial position, and when the current number of complete wafers is equal to or greater than the number of complete wafers when the wafer center is at the initial position, use the square where the current wafer center is located as the initial position.

7. The method for calculating the wafer layout according to any one of claims 1-6, wherein, after determining the maximum number of complete wafers, the method further includes: in all the complete wafers, determine the wafer coverage area of all the valid wafers; determine the number of edge valid wafers and non-edge valid wafers of the wafer in the wafer coverage area; calculate the product of the number of edge valid wafers and a preset constant, and determine the sum of the product and the number of non-edge valid wafers as the maximum true number of valid wafers.

8. The method for calculating the wafer layout according to claim 7, wherein, the placing the reference wafer at different wafer positions in the single exposure area in sequence to determine the minimum number of exposures for exposing all wafers includes: at the different wafer positions, determine the number of exposures for the lithography machine to expose all wafers, so as to obtain the minimum number of exposures for exposing all wafers.

9. The method for calculating the wafer layout according to claim 8, wherein, the determining the positions of the wafers in the wafer according to the maximum number of complete wafers and the minimum number of exposures for all wafers to generate the wafer layout of the wafer includes: according to the maximum number of complete wafers and the minimum number of exposures for all wafers or the maximum true number of valid wafers and the minimum number of exposures for all wafers, determine the target coverage area of the wafer and the positions of the wafers in the target coverage area to generate the wafer layout; or according to the maximum true number of valid wafers and the minimum number of exposures for all wafers, determine the target coverage area of the wafer and the positions of the wafers in the target coverage area to generate the wafer layout; wherein, the positions of the wafers include the positions of all the complete wafers or all the wafers in the wafer.

10. The method for calculating the wafer layout according to claim 9, wherein, when there are multiple target coverage areas, the method further includes: determining the edges where the complete wafers or effective wafers are located in each of the target coverage areas, and calculating the distances between the edges where the complete wafers or the effective wafers are located and the edge of the wafer, so as to determine the target coverage area with the maximum distance as the optimal wafer coverage area; determining the positions of all the complete wafers or all the wafers in the wafer in the optimal wafer coverage area, so as to generate the wafer layout.

11. A device for calculating the wafer layout of a wafer, wherein, the device includes: a first moving module, configured to move the wafer center within a preset area of a reference wafer at a first step length based on the distribution array of each wafer in the wafer, taking any wafer in the distribution array as the reference wafer; after each movement, determining a first coverage area of the wafer according to the current position of the wafer center, and calculating the number of complete wafers in the first coverage area; when the number of complete wafers is the largest, determining the position of the wafer center, and determining the wafer area formed by the wafer centers as the feasible area; a second moving module, configured to move the wafer center within the feasible area at a second step length to determine a second coverage area of the wafer after each movement, and determining the maximum number of complete wafers in the second coverage area; a determining module, configured to, after determining the maximum number of complete wafers, place the reference wafer at different wafer positions within the single exposure area in sequence according to the wafer position distribution pattern of the single exposure area of the lithography machine, and determining the minimum number of exposures for exposing all the wafers; a generating module, configured to determine the positions of each wafer in the wafer according to the maximum number of complete wafers and the minimum number of exposures for all the wafers, so as to generate the wafer layout of the wafer.

12. A computer-readable storage medium, on which a computer program is stored, wherein, the computer program, when executed by a processor, implements the method according to any one of claims 1-10.

13. An electronic device, wherein, it includes: a processor; and a memory, configured to store executable instructions of the processor; wherein, the processor is configured to execute the method according to any one of claims 1-10 by executing the executable instructions.

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