Sensitive amplification circuit, memory, test memory and chip

Abstract

An embodiment of the present invention provides a sense amplifier circuit, a memory, a test memory, and a chip. The sense amplifier circuit includes an input module for inputting a first input signal and a second input signal; a differential input module, which includes a voltage difference generation sub-module and an improved voltage difference amplification sub-module; the voltage difference generation sub-module is configured to generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; and the improved voltage difference amplification sub-module is used to amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference; a mutual feedback amplification module, which is configured to output an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage, thereby reducing the flip error rate of the sense amplifier circuit and further helping to improve the yield of the chip.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of memories, and particularly to a sense amplifier circuit, a memory, a test memory, and a chip. Background Art

[0002] A memory is a device used to store data in a chip. A typical memory such as SRAM (Static Random-Access Memory) is widely used in scenarios that require high-speed data storage due to advantages such as low power consumption and fast read speed.

[0003] To quickly read the data stored in a memory, a sense amplifier circuit is usually provided in the memory to amplify and output the signal of the storage circuit in the memory. However, due to reasons such as process fluctuations (such as manufacturing process deviations), the sense amplifier circuit often has the phenomenon of flip errors. Therefore, how to reduce the flip error rate of the sense amplifier circuit and help improve the yield of the chip has always been a problem considered by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a sense amplifier circuit, a memory, a test memory, and a chip to reduce the flip error rate of the sense amplifier circuit.

[0005] To achieve the above object, embodiments of the present invention provide the following technical solutions:

[0006] A sense amplifier circuit according to an embodiment of the present invention includes:

[0007] An input module for inputting a first input signal and a second input signal;

[0008] A differential input module, the differential input module including a voltage difference generation sub-module and a voltage difference amplification sub-module; the voltage difference generation sub-module is used to generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; the voltage difference amplification sub-module is used to amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference;

[0009] A mutual feedback amplification module for outputting an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage.

[0010] An embodiment of the present invention also provides a memory, the memory including:

[0011] A plurality of storage units;

[0012] The storage unit includes a storage circuit and a sense amplifier circuit connected to the storage circuit, and the sense amplifier circuit is the sense amplifier circuit provided in the above embodiment.

[0013] An embodiment of the present invention further provides a chip, and the chip includes the memory provided in the above embodiment.

[0014] An embodiment of the present invention further provides a circuit control method, which is applied to the sense amplifier circuit provided in the above embodiment. The method includes:

[0015] Input a first input signal and a second input signal;

[0016] Generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal;

[0017] Amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference;

[0018] Output an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage.

[0019] An embodiment of the present invention further provides a test memory, including:

[0020] Multiple groups of storage units;

[0021] The storage unit includes a storage circuit and a sense amplifier circuit connected to the storage circuit;

[0022] Among them, the sense amplifier circuit in at least one group of storage units is the sense amplifier circuit provided in the above embodiment.

[0023] An embodiment of the present invention further provides a test chip, and the test chip includes the test memory provided in the above embodiment.

[0024] An embodiment of the present invention provides a sense amplifier circuit, a memory, a test memory, and a chip. The sense amplifier circuit includes an input module for inputting a first input signal and a second input signal; a differential input module including a voltage difference generation sub-module and a voltage difference amplification sub-module; the voltage difference generation sub-module for generating a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; the voltage difference amplification sub-module for amplifying the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference; and a mutual feedback amplification module for outputting an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage. It can be seen that by providing the voltage difference amplification sub-module, the initial voltage difference generated based on the first input signal and the second input signal is amplified, thereby reducing the flip error rate of the sense amplifier circuit and improving the yield of the chip. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of a sense amplifier circuit;

[0027] Figure 2 For Figure 1 the waveform diagram of the input and output signals in the sense amplifier;

[0028] Figure 3 It is an optional block diagram of the sense amplifier circuit provided by the embodiment of the present invention;

[0029] Figure 4 It is the first optional structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0030] Figure 5 It is the second optional structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0031] Figure 6 It is the third optional structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0032] Figure 7 It is the fourth optional structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0033] Figure 8 It is the fifth optional structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0034] Figure 9 The sixth alternative structure of the sense amplifier circuit provided by the embodiment of the present invention;

[0035] Figure 10 Another alternative structure of the sense amplifier circuit with the first alternative structure provided by the embodiment of the present invention;

[0036] Figure 11 The relationship diagram of the number of Monte Carlo analysis errors shown and the input-output power supply voltage difference;

[0037] Figure 12 The alternative structure diagram of the memory provided by the embodiment of the present invention;

[0038] Figure 13 An alternative flowchart of the circuit control method provided by the embodiment of the present invention;

[0039] Figure 14 The alternative structure diagram of the test memory with a non-predictive non-programmable sense amplifier circuit provided by the embodiment of the present invention;

[0040] Figure 15 The alternative structure diagram of the first pressure difference amplification unit of the alternative structure provided by the embodiment of the present invention;

[0041] Figure 16 The alternative structure diagram of the second pressure difference amplification unit of the alternative structure provided by the embodiment of the present invention;

[0042] Figure 17 The alternative structure diagram of the test memory with a predictive programmable sense amplifier circuit provided by the embodiment of the present invention. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] Based on what is described in the background art, the sense amplifier circuit in the memory often has the phenomenon of flip errors.

[0045] Optionally, Figure 1 A schematic structural diagram of a sense amplifier circuit is shown. Refer to Figure 1, the sensitive amplifier circuit includes an input module 100, a differential input module 110, a mutual feedback amplification module 120, and an output module 130; among them, the input module 100 includes a first input signal line 101 and a second input signal line 102, which are used to input the storage signals sent by the storage circuit. Specifically, the first input signal line 101 inputs a first input signal SAT, and the second input signal line 102 inputs a second input signal SAC; the differential input module 110 includes a first input transistor MNGT and a second input transistor MNGC respectively connected corresponding to the first input signal line and the second input signal line. The first input transistor MNGT generates a first initial voltage based on the first input signal, and the second input transistor MNGC generates a second initial voltage based on the second input signal. The voltage difference between the first initial voltage and the second initial voltage is the initial voltage difference. The mutual feedback amplification module 120 then outputs an output signal with a preset voltage difference based on the initial voltage difference, and is latched and output by the output module 130.

[0046] Specifically, the mutual feedback amplification module 120 includes two inverters connected end to end, that is, the inverter composed of MP0 and MN0 and the inverter composed of MP1 and MN1 are connected end to end, and VDD provides power for the inverter.

[0047] In the working stage of the sensitive amplifier, referring to Figure 2 the waveform diagram of the input and output signals in the shown sensitive amplifier, when the storage signals sent by the storage circuit are signals with voltage differences, that is, the input signals SAT and SAC transmitted by the first input signal line and the second input signal line have voltage differences, this voltage difference causes the nodes on the corresponding input transistor side (i.e., the MIDC node and the MIDT node) to also generate voltage differences (i.e., the initial voltage difference), and the mutual feedback amplification module 120 can quickly amplify the voltage differences between the MIDC node and the MIDT node to form output signals SACO and SATO, and further latch and output by the output module.

[0048] The inventor found that if the voltages of MIDC and MIDT are close to equal, it will cause the voltage difference of the sensitive amplifier circuit to lose its function, and the threshold voltages (Vth) of the MN0 transistor and the MN1 transistor are not exactly equal due to process manufacturing differences. If the difference in the threshold voltages of the MN0 transistor and the MN1 transistor is greater than the voltage difference between the MIDC node and the MIDT node, it may cause the sensitive amplifier circuit to flip incorrectly.

[0049] To address this problem, the inventor further conducted research and analysis and believes that the voltage difference between SACO and SATO can be expressed by formula (1):

[0050] Formula (1):

[0051] Among them, Vo is the voltage difference between SACO and SATO when MP0 or MP1 is turned on, Vthp is the threshold voltage of MP0 and MP1, ΔVin is the input voltage difference between SAC and SAT, β is a process constant, and I 0 is the current flowing through the differential input transistors MNGC and MNGT.

[0052] Based on this, the inventor believes that if the flip error rate of the sense amplifier circuit is to be reduced, the voltage difference Vo between SACO and SATO when MP0 or MP1 is turned on should be increased, so that the lower voltage among SACO and SATO is conducive to the PMOS of an inverter connected end to end to conduct, further charging the higher voltage in SACO or SATO, and the higher voltage among SACO and SATO is conducive to the NMOS of another inverter to conduct, further discharging the lower voltage in SACO and SATO, thus forming a positive feedback and quickly amplifying this voltage difference to high and low logic levels.

[0053] In view of this, an embodiment of the present invention provides a sense amplifier circuit, a memory, a test memory, and a chip. Among them, the sense amplifier circuit includes an input module for inputting a first input signal and a second input signal; a differential input module, the differential input module includes a voltage difference generation sub-module and a voltage difference amplification sub-module, the voltage difference generation sub-module is used to generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; the voltage difference amplification sub-module is used to amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference; a mutual feedback amplification module is used to output an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage.

[0054] Among them, by setting a voltage difference amplification sub-module in the differential input module, the initial voltage difference generated based on the first input signal and the second input signal is amplified, thereby reducing the flip error rate of the sense amplifier circuit and improving the yield of the chip.

[0055] Optionally, Figure 3 shows an optional block diagram of the sense amplifier circuit provided by an embodiment of the present invention. As Figure 3 shown, the sense amplifier circuit may include:

[0056] An input module 200 for inputting a first input signal and a second input signal;

[0057] Differential input module, the differential input module includes a pressure difference generation sub-module 210 and a pressure difference amplification sub-module 220; the pressure difference generation sub-module 210 is used to generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; the pressure difference amplification sub-module 220 is used to amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference;

[0058] Mutual feedback amplification module 230 is used to output an output signal with a preset voltage difference based on the amplified voltage difference.

[0059] It can be understood that the preset voltage difference is greater than the initial voltage difference. Wherein, the input module 200 may include a first input signal line 201 and a second input signal line 202. The first input signal line can transmit a first input signal, and the second input signal line can transmit a second transmission signal. Specifically, the first input signal can be a Sense Amplifier True (SAT) input signal, and the second input signal can be a Sense Amplifier Complementary (SAC) input signal. The two input signals are respectively transmitted from the stored signals of the storage circuit transmitted by the Bit Line True (BLT) and the Bit Line Complementary (BLC).

[0060] In an alternative implementation of the present invention, referring to Figure 4 the first alternative structure of the sense amplifier circuit shown, the input module 200 may further include a first pre-charge unit 203 for pre-charging a first voltage to the first input signal line 201 and the second input signal line 202. Wherein, the first voltage can be the bit line voltage VDDC of the storage circuit, and the change of the stored signal can be manifested as a voltage drop, so that the signal can be amplified based on the dropped voltage.

[0061] Specifically, the first pre-charge unit 203 includes a first charging transistor MP5, a second charging transistor MP6 and a first balancing transistor MP7; the gates of the first charging transistor MP5, the second charging transistor MP6 and the first balancing transistor MP7 are connected to a pre-charge enable signal source; the source of the first charging transistor MP5 is connected to a first voltage source, and the drain is connected to the first input signal line 201; the source of the second charging transistor MP6 is connected to the first voltage source, and the drain is connected to the second input signal line 202; the source of the first balancing transistor MP7 is connected to the first input signal line 201, and the drain is connected to the second input signal line 202;

[0062] Among them, the first charging transistor MP5, the second charging transistor MP6, and the first balancing transistor MP7 have the same conduction type. Optionally, the first charging transistor MP5, the second charging transistor MP6, and the first balancing transistor MP7 are all P-type MOS transistors, and the sizes of the first charging transistor MP5 and the second charging transistor MP6 are symmetric; the pre-charge enable signal source is used to output a pre-charge enable signal SAPCHX, and the first voltage source is used to output a first voltage VDDC; among them, the first balancing transistor MP7 is used to balance the voltages of the first input signal line 201 and the second input signal line 202 during the pre-charge stage.

[0063] Moreover, the sense amplifier circuit further includes a pull-down module 240 for pulling down the signals of the differential input module. Specifically, the pull-down module 240 includes a pull-down transistor MNT. The gate of the pull-down transistor MNT is connected to the amplification enable signal source, the drain is connected to the differential input module, and the source is grounded; the amplification enable signal source is used to output an amplification enable signal SAEN, and the amplification enable signal SAEN is used to enable the sense amplifier circuit, so as to turn on the pull-down transistor when the sense amplifier circuit is started.

[0064] It should be noted that the connection between the differential input module and the drain of the pull-down transistor is not limited to connecting only one transistor in the differential input module to the drain of the pull-down transistor. Instead, any transistor with a pull-down requirement can be grounded through the pull-down transistor.

[0065] When reading the stored data, the change of the storage signal is reflected in the voltage difference between BLT and BLC. For example, when reading the data in the storage circuit, a certain voltage drop will be generated on BLT or BLC, which will further cause a voltage difference between the voltages of BLT and BLC. Correspondingly, the voltage changes on BLT and BLC will be transmitted to the first input signal line and the second input signal line, thereby forming corresponding first input signal SAT and second input signal SAC, and the voltages of the first input signal SAT and the second input signal SAC also have this voltage difference. This voltage difference can be understood as the input voltage difference between the first input signal SAT and the second input signal SAC.

[0066] The differential input module is used to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference based on the voltage difference between the first input signal and the second input signal, so that the mutual feedback amplification module can accurately achieve signal inversion under the amplified voltage difference between the first amplified voltage and the second amplified voltage. Among them, the voltage difference generation sub-module 210 and the voltage difference amplification sub-module 220 constitute the differential input module.

[0067] In an optional example, the differential pressure generation sub-module 210 may generate an initial voltage difference based on the input voltage difference. Specifically, the differential pressure generation sub-module 210 may include a first input transistor MNGT and a second input transistor MNGC. The first input transistor MNGT generates a first initial voltage based on the first input signal, and the second input transistor MNGC generates a second initial voltage based on the second input signal.

[0068] Wherein, the gate of the first input transistor MNGT is connected to the first input signal line 201, the source is connected to the mutual feedback amplification module 230, and the drain is connected to the differential pressure amplification sub-module 220; the gate of the second input transistor MNGC is connected to the second input signal line 202, the source is connected to the mutual feedback amplification module 230, and the drain is connected to the differential pressure amplification sub-module 220. Among them, the first initial voltage can be understood as the source voltage of the first input transistor MNGT when the differential pressure amplification sub-module is not turned on, and the second initial voltage can be understood as the source voltage of the second input transistor MNGC when the differential pressure amplification sub-module is not turned on. Optionally, both the first input transistor MNGT and the second input transistor MNGC are N-type MOS transistors, and the sizes of the first input transistor MNGT and the second input transistor MNGC are symmetrical.

[0069] It can be understood that based on the first input signal line, the voltage across the source and drain of the first input transistor can be controlled; similarly, based on the second input signal line, the voltage across the source and drain of the second input transistor can be controlled, so that a corresponding initial voltage difference can be generated based on the changes in the first input signal and the second input signal. For example, when the first input transistor and the second input transistor are N-type MOS transistors, during the pre-charge stage, the first input transistor and the second input transistor may be in the on state. When the first input signal decreases and the second input signal remains unchanged to form an input voltage difference, the voltage on the first input signal line gradually decreases, so that the first input transistor gradually approaches the off state, thereby maintaining the voltage of the source of the first input transistor (reference node MIDC) (i.e., the first initial voltage). Correspondingly, the second input signal remains unchanged, so that the second input transistor remains on, thereby transmitting the current of the source of the second input transistor (reference node MIDT) to the drain of the second input transistor, and further continuously pulling down the voltage of the source of the second input transistor, so that the voltages of the sources of the two input transistors (i.e., the second initial voltage) continuously decrease, thereby forming an initial voltage difference.

[0070] Combined with reference formula (1), it can be seen that the voltage difference Vo between SACO and SATO can be increased by increasing ΔVin or decreasing I 0Implementation. In an alternative example of the present invention, the initial voltage difference can be amplified by increasing ΔVin, that is, increasing the voltage difference between the first input signal SAT and the second input signal SAC, thereby forming a larger Vo. Or, in another alternative example of the present invention, it can be achieved by reducing I 0 That is, reducing the current transmitted by the first input transistor MNGT and the second input transistor MNGC (i.e., the current flowing from the source to the drain of the transistor), thereby amplifying the initial voltage difference.

[0071] In the embodiment of the present invention, considering that increasing ΔVin requires the storage circuit to consume a relatively long read and discharge time, which may cause an increase in the power consumption of the SRAM and a decrease in the read speed. Therefore, it is preferred to adopt the method of reducing I 0 to amplify the initial voltage difference.

[0072] In an alternative example, with continued reference to Figure 4 , the differential voltage amplification sub-module 220 may include a first differential voltage amplification unit connected to the first input transistor MNGT, and a second differential voltage amplification unit connected to the second input transistor MNGC;

[0073] Among them, the first differential voltage amplification unit includes a first amplification transistor MNG1; the gate of the first amplification transistor MNG1 is connected to the gate of the first input transistor MNGT, the source is connected to the drain of the first input transistor MNGT, and the drain is connected to the drain of the pull-down transistor;

[0074] The second differential voltage amplification unit includes a second amplification transistor MNG2; the gate of the second amplification transistor MNG2 is connected to the gate of the second input transistor MNGC, the source is connected to the drain of the second input transistor MNGC, and the drain is connected to the drain of the pull-down transistor.

[0075] Among them, the conduction type of the first amplification transistor is the same as that of the first input transistor, and the conduction type of the second amplification transistor is the same as that of the second input transistor. Optionally, both the first amplification transistor MNG1 and the second amplification transistor MNG2 are N-type MOS transistors, and the sizes of the first amplification transistor MNG1 and the second amplification transistor MNG2 are symmetrical.

[0076] The gate of the first amplification transistor is connected to the gate of the first input transistor, and the gate of the second amplification transistor is connected to the gate of the second input transistor. Thus, when the first input transistor and the second input transistor are turned on, the first amplification transistor and the second amplification transistor can be turned on simultaneously. The first amplification transistor and the second amplification transistor can be regarded as resistors, which reduce the current flowing through the first input transistor and the second input transistor in the on state, thereby amplifying the initial voltage difference.

[0077] In another alternative example, referring to Figure 5 the second alternative structural diagram of the sense amplifier circuit shown, the differential voltage amplification sub-module may include a first differential voltage amplification unit connected to the first input transistor, and a second differential voltage amplification unit connected to the second input transistor; different from the previous example, the structures of the first differential voltage amplification unit and the second differential voltage amplification unit are different.

[0078] Among them, the first differential voltage amplification unit includes a third amplification transistor MNG3; the gate of the third amplification transistor MNG3 is connected to a first signal source, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor;

[0079] The second differential voltage amplification unit includes a fourth amplification transistor MNG4; the gate of the fourth amplification transistor MNG4 is connected to the first signal source, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor;

[0080] The first signal source is used to output a first signal TIE1, and the first signal controls the third amplification transistor and the fourth amplification transistor to be in a conducting state.

[0081] That is to say, keeping the third amplification transistor MNG3 and the fourth amplification transistor MNG4 in a conducting state, so that when the first input transistor and the second input transistor are turned on, the current flowing through the first input transistor and the second input transistor can be reduced, thereby amplifying the initial voltage difference.

[0082] Optionally, both the third amplification transistor MNG3 and the fourth amplification transistor MNG4 are N-type MOS transistors, and the sizes of the third amplification transistor MNG3 and the fourth amplification transistor MNG4 are symmetrical.

[0083] In a further alternative example, referring to Figure 6The third alternative structural diagram of the sensitive amplification circuit shown, the differential pressure amplification sub-module may include a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; different from the previous example, the structures of the first differential pressure amplification unit and the second differential pressure amplification unit are different.

[0084] Among them, the first differential pressure amplification unit includes a fifth amplification transistor MNG5; the gate of the fifth amplification transistor MNG5 is connected to the gate of the first input transistor, the source is connected to the source of the first input transistor, the drain is connected to the drain of the first input transistor, and is connected to the drain of the pull-down transistor;

[0085] The second differential pressure amplification unit includes a sixth amplification transistor MNG6; the gate of the sixth amplification transistor MNG6 is connected to the gate of the second input transistor, the source is connected to the source of the second input transistor, the drain is connected to the drain of the second input transistor, and is connected to the drain of the pull-down transistor.

[0086] Among them, the conduction type of the fifth amplification transistor is the same as that of the first input transistor, and the conduction type of the sixth amplification transistor is the same as that of the second input transistor. Optionally, both the fifth amplification transistor MNG5 and the sixth amplification transistor MNG6 are N-type MOS transistors, and the sizes of the fifth amplification transistor MNG5 and the sixth amplification transistor MNG6 are symmetrical.

[0087] Based on the gate of the fifth amplification transistor being connected to the gate of the first input transistor, and the gate of the sixth amplification transistor being connected to the gate of the second input transistor, the fifth amplification transistor and the sixth amplification transistor can be turned on simultaneously when the first input transistor and the second input transistor are turned on, and the fifth amplification transistor and the sixth amplification transistor can be regarded as resistors, which can reduce the current flowing through the first input transistor and the second input transistor in the on state, and thus amplify the initial voltage difference.

[0088] In a further optional example, referring to Figure 7 The fourth alternative structural diagram of the sensitive amplification circuit shown, the differential pressure amplification sub-module may include a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; different from the previous example, the structures of the first differential pressure amplification unit and the second differential pressure amplification unit are different.

[0089] Among them, the first differential pressure amplification unit includes a seventh amplification transistor MNG7 and an eighth amplification transistor MNG8; the gate of the seventh amplification transistor MNG7 is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the eighth amplification transistor MNG8 is connected to the gate of the first input transistor, the source is connected to the source of the first input transistor, and the drain is connected to the drain of the seventh amplification transistor MNG7;

[0090] The second differential pressure amplification unit includes a ninth amplification transistor MNG9 and a tenth amplification transistor MNG10; the gate of the ninth amplification transistor MNG9 is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the tenth amplification transistor MNG10 is connected to the gate of the second input transistor, the source is connected to the source of the second input transistor, and the drain is connected to the drain of the ninth amplification transistor MNG9.

[0091] Among them, the conduction types of the seventh amplification transistor and the eighth amplification transistor are the same as that of the first input transistor; the conduction types of the ninth amplification transistor and the tenth amplification transistor are the same as that of the second input transistor. Optionally, the seventh amplification transistor, the eighth amplification transistor, the ninth amplification transistor and the tenth amplification transistor are all N-type MOS transistors, and the sizes of the seventh amplification transistor and the ninth amplification transistor are symmetrical, and the sizes of the eighth amplification transistor and the tenth amplification transistor are symmetrical.

[0092] Based on the fact that the gates of the seventh amplification transistor and the eighth amplification transistor are connected to the gate of the first input transistor, and the gates of the ninth amplification transistor and the tenth amplification transistor are connected to the gate of the second input transistor, the seventh amplification transistor, the eighth amplification transistor, the ninth amplification transistor and the tenth amplification transistor can be turned on simultaneously when the first input transistor and the second input transistor are turned on. The seventh amplification transistor, the eighth amplification transistor, the ninth amplification transistor and the tenth amplification transistor can be regarded as resistors, and the current flowing through the first input transistor and the second input transistor can be reduced in the on state, thereby amplifying the initial voltage difference.

[0093] In a further optional example, referring to Figure 8 the fifth optional structural diagram of the sense amplifier circuit shown, the differential pressure amplification sub-module may include a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; different from the previous example, the structures of the first differential pressure amplification unit and the second differential pressure amplification unit are different.

[0094] Among them, the first differential pressure amplification unit includes an eleventh amplification transistor MNG11 and a twelfth amplification transistor MNG12; the gate of the eleventh amplification transistor MNG11 is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the twelfth amplification transistor MNG12 is connected to the second signal source, the source is connected to the source of the first input transistor, and the drain is connected to the drain of the eleventh amplification transistor MNG11;

[0095] The second differential pressure amplification unit includes a thirteenth amplification transistor MNG13 and a fourteenth amplification transistor MNG14; the gate of the thirteenth amplification transistor MNG13 is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the fourteenth amplification transistor MNG14 is connected to the second signal source, the source is connected to the source of the second input transistor, and the drain is connected to the drain of the thirteenth amplification transistor MNG13;

[0096] The second signal source is used to output a second signal TIE0, and the second signal controls the twelfth amplification transistor MNG12 and the fourteenth amplification transistor MNG14 to be in an off state.

[0097] The off-state twelfth amplification transistor MNG12 and fourteenth amplification transistor MNG14 are used to shunt the currents of the first input transistor and the second input transistor, thereby reducing the currents flowing through the first input transistor and the second input transistor and amplifying the initial voltage difference.

[0098] Among them, the conduction type of the eleventh amplification transistor is the same as that of the first input transistor; the conduction type of the thirteenth amplification transistor is the same as that of the second input transistor. Optionally, the eleventh amplification transistor, the twelfth amplification transistor, the thirteenth amplification transistor, and the fourteenth amplification transistor are all N-type MOS transistors, and the sizes of the eleventh amplification transistor and the thirteenth amplification transistor are symmetrical, and the sizes of the twelfth amplification transistor and the fourteenth amplification transistor are symmetrical.

[0099] Based on the gate of the eleventh amplification transistor being connected to the gate of the first input transistor, and the gate of the thirteenth amplification transistor being connected to the gate of the second input transistor, the eleventh amplification transistor and the thirteenth amplification transistor can be simultaneously turned on when the first input transistor and the second input transistor are turned on. The eleventh amplification transistor and the thirteenth amplification transistor can be regarded as resistors, and in the on state, they can reduce the currents flowing through the first input transistor and the second input transistor, thereby amplifying the initial voltage difference.

[0100] It should be noted that the amplifying transistor in the differential pressure amplification sub-module refers to the transistor provided in this differential pressure amplification sub-module to distinguish it from the transistors in other modules. This amplifying transistor does not mean that it has the function of amplifying voltage, current or power.

[0101] In a further optional example, referring to Figure 9 the sixth optional structural diagram of the sense amplifier circuit shown, the differential pressure amplification sub-module may include a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; different from the previous example, the structures of the first differential pressure amplification unit and the second differential pressure amplification unit are different.

[0102] The first differential pressure amplification unit includes a fifteenth amplifying transistor MNG15 and a sixteenth amplifying transistor MNG16; the gate of the fifteenth amplifying transistor MNG15 is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the sixteenth amplifying transistor MNG16 is connected to the second signal source, the source is connected to the source of the first input transistor, and the drain is connected to the source of the fifteenth amplifying transistor MNG15;

[0103] The second differential pressure amplification unit includes a seventeenth amplifying transistor MNG17 and an eighteenth amplifying transistor MNG18; the gate of the seventeenth amplifying transistor MNG17 is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the eighteenth amplifying transistor MNG18 is connected to the second signal source, the source is connected to the source of the second input transistor, and the drain is connected to the source of the seventeenth amplifying transistor MNG17;

[0104] Wherein, the second signal source is used to output a second signal TIE0, and the second signal TIE0 controls the sixteenth amplifying transistor MNG16 and the eighteenth amplifying transistor MNG18 to be in an off state; through the off-state sixteenth amplifying transistor and the eighteenth amplifying transistor, the currents of the first input transistor and the second input transistor are shunted, so as to reduce the currents flowing through the first input transistor and the second input transistor and amplify the initial voltage difference.

[0105] The conductivity type of the fifteenth amplifying transistor is the same as that of the first input transistor; the conductivity type of the seventeenth amplifying transistor is the same as that of the second input transistor. Optionally, the fifteenth amplifying transistor, the sixteenth amplifying transistor, the seventeenth amplifying transistor, and the eighteenth amplifying transistor are all N-type MOS transistors, and the fifteenth amplifying transistor and the seventeenth amplifying transistor are symmetric in size, and the sixteenth amplifying transistor and the eighteenth amplifying transistor are symmetric in size.

[0106] Based on the gate of the fifteenth amplifying transistor being connected to the gate of the first input transistor, and the gate of the seventeenth amplifying transistor being connected to the gate of the second input transistor, the fifteenth amplifying transistor and the seventeenth amplifying transistor can be turned on simultaneously when the first input transistor and the second input transistor are turned on. The fifteenth amplifying transistor and the seventeenth amplifying transistor can be regarded as resistors, and in the on state, they can reduce the current flowing through the first input transistor and the second input transistor, thereby amplifying the initial voltage difference.

[0107] In a further optional example, referring to Figure 10 Another optional structural diagram of the sense amplifier circuit shown, the mutual feedback amplification module 230 may include a first differential amplification unit and a second differential amplification unit.

[0108] Among them, the first differential amplification unit includes a first differential transistor MP0 and a second differential transistor MN0; the second differential amplification unit includes a third differential transistor MP1 and a fourth differential transistor MN1; the source of the first differential transistor MP0 is connected to the second voltage source, the drain is connected to the source of the second differential transistor MN0, the gate is connected to the drain of the third differential transistor MP1, and the signal in this gate is output as the first output signal SATO; the drain of the second differential transistor MN0 is connected to the first input transistor, the gate is connected to the drain of the third differential transistor MP1, and the signal in this gate is output as the second output signal SACO;

[0109] The source of the third differential transistor MP1 is connected to the second voltage source, the drain is connected to the source of the fourth differential transistor MN1, the gate is connected to the drain of the first differential transistor MP0; the drain of the fourth differential transistor MN1 is connected to the second input transistor, the gate is connected to the drain of the first differential transistor MP0, and the signal in this gate is output as the first output signal.

[0110] Among them, the conduction type of the first differential transistor MP0 is different from that of the second differential transistor MN0, the conduction type of the third differential transistor MP1 is different from that of the fourth differential transistor MN1, and the conduction type of the first differential transistor MP0 is the same as that of the third differential transistor MP1; the second voltage source is used to provide a second voltage VDDP. Optionally, both the first differential transistor MP0 and the third differential transistor MP1 are P-type MOS transistors; both the second differential transistor MN0 and the fourth differential transistor MN1 are N-type MOS transistors, and the sizes of the first differential transistor MP0 and the third differential transistor MP1 are symmetrical, and the sizes of the second differential transistor MN0 and the fourth differential transistor MN1 are symmetrical.

[0111] Specifically, after the voltage difference between the source of the first input transistor and the source of the second input transistor is amplified by the voltage difference amplification sub-module, the mutual feedback amplification module can respond quickly and accurately, so as to output an output signal with a preset voltage difference. For example, when the first input signal decreases and the second input signal remains unchanged to generate an input voltage difference, the voltage difference amplification sub-module can maintain the voltage of the source of the first input transistor (MIDC node) and reduce the voltage of the source of the second input transistor (MIDT node). Correspondingly, in the initial stage of the mutual feedback amplification module, the first differential transistor MP0 and the third differential transistor MP1 are in the off state, and the second differential transistor MN0 and the fourth differential transistor MN1 are in the on state. When the voltage of the source of the second input transistor (MIDT node) decreases, it will pull down the voltage of the drain of the third differential transistor MP1, thereby turning on the first differential transistor MP0, turning off the second differential transistor MN0, and charging the drain of the first differential transistor MP0, so that the second output signal shows a high level; at the same time, the high-level state of the drain of the first differential transistor MP0 further maintains the off state of the gate of the third differential transistor MP1 and the on state of the fourth differential transistor MN1, and combines the grounded states of the voltage difference generation sub-module and the voltage difference amplification sub-module, so that the voltage of the drain of the third differential transistor MP1 approaches 0, and further enables the first output signal to show a low level, so that the output first output signal and the second output signal have a preset voltage difference.

[0112] In a further optional example, continue to refer to Figure 10, the sense amplifier circuit further includes an output module, the output module includes a first output signal line 251, a second output signal line 252 and a second precharge unit 253. The first output signal line 251 is used to transmit a first output signal, the second output signal line 252 is used to transmit a second output signal, and the second precharge unit 253 is used to precharge a second voltage to the first output signal line 251 and the second output signal line 252, so that the mutual feedback amplifier module 230 is in an initial stage.

[0113] Wherein, the second voltage can be a fixed value or a variable value. When the second voltage is a fixed value and the first voltage is equal to the second voltage, the sense amplifier circuit can be applied to a scenario where both the storage circuit and the peripheral circuit are in the same voltage domain. When the second voltage is a variable value, the sense amplifier circuit can be applied to a dual-voltage-domain memory, that is, the storage circuit and the peripheral circuit can be in different voltage domains, or, in a dual-voltage-domain memory, the first voltage is also a variable value at the same time to adapt to different scenario requirements.

[0114] It should be noted that in a dual-voltage-domain memory, the flip error rate of a traditional sense amplifier circuit is higher. In a dual-voltage-domain memory, the memory cell (Bitcell) array is provided with a separate power supply to ensure the read / write performance of the memory and the stability of the data stored in the memory, and can save power consumption. The logic circuit outside the memory cell array is provided with a wide voltage range of power supply. For example, a higher voltage is provided when high performance is required, and a lower voltage or even the peripheral logic power supply is turned off when high performance is not required. Correspondingly, the input signal of the sense amplifier circuit in the memory is in the same voltage domain as the bit line voltage VDDC of the storage circuit, and the output signal is in the same voltage domain as the peripheral logic circuit. Refer to Figure 11 the relationship diagram of the Monte Carlo analysis error number and the input / output power supply voltage difference shown. It can be seen that among the 5000 Monte Carlo analysis error numbers, when VDDC > VDDP, the Monte Carlo simulation analysis finds that the number of flip errors increases significantly, and as the voltage difference of VDDC - VDDP increases, the number of flip errors also increases.

[0115] In the embodiment of the present invention, the initial voltage difference is amplified by the improved differential voltage amplification sub-module to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference, thereby significantly reducing the flip error rate of the sense amplifier circuit.

[0116] Specifically, in the dual-voltage-domain memory scenario, the first voltage is a variable value, the second voltage is a variable value, and the first voltage and the second voltage are equal or are high and low with respect to each other. Specifically, the first voltage may be the voltage provided by the voltage source of the storage circuit, i.e., VDDC, and the second voltage is the voltage VDDP provided by the voltage source of the peripheral circuit. It can be understood that the second voltage VDDP can be a higher voltage when high performance is required for the peripheral circuit, and the second voltage VDDP can be a lower voltage when high performance is not required.

[0117] Further, continuing to refer to Figure 10 , the second precharge unit 253 includes a third charge transistor MP3, a fourth charge transistor MP4, and a second balance transistor MP2;

[0118] The gates of the third charge transistor MP3, the fourth charge transistor MP4, and the second balance transistor MP2 are connected to an amplification enable signal source; the source of the third charge transistor MP3 is connected to a second voltage source, and the drain is connected to the first input signal line; the source of the fourth charge transistor MP4 is connected to the second voltage source, and the drain is connected to the second input signal line;

[0119] The source of the second balance transistor MP2 is connected to the first input signal line, and the drain is connected to the second input signal line;

[0120] Among them, the third charge transistor MP3, the fourth charge transistor MP4, and the second balance transistor MP2 have the same conduction type; optionally, the third charge transistor MP3, the fourth charge transistor MP4, and the second balance transistor MP2 are all P-type MOS transistors, and the sizes of the third charge transistor MP3 and the fourth charge transistor MP4 are symmetrical; the amplification enable signal source is used to output an amplification enable signal SAEN, and the second voltage source is used to output a second voltage VDDP.

[0121] In a further optional example, the output module 250 further includes a latch unit 254, and the latch unit 254 is used to output a stored data signal RDDAT based on the first output signal SATO and the second output signal SACO, and the stored data signal RDDAT is used to represent the data stored in the storage circuit. Among them, the stored data signal RDDAT can be a low-level or high-level signal, and this low-level or high-level signal is used to represent the data read out by the storage circuit. For example, when it is at a high level, it can represent that the data read out in the storage circuit is "1"; when it is at a low level, it can represent that the data read out in the storage circuit is "0".

[0122] As an optional implementation, an embodiment of the present invention further provides a memory, referring to Figure 12An alternative structural diagram of the memory shown, the memory includes a plurality of memory cells, the memory cells include a storage circuit and a sense amplifier circuit connected to the storage circuit, and the sense amplifier circuit is the sense amplifier circuit provided in the above embodiment. Continue to refer to Figure 12 , wherein, a first input signal line (corresponding to SAT) is connected to BLT through a read select signal control transistor, a second input signal line (corresponding to SAC) is connected to BLC through another read select signal control transistor, and the gates of the two read select signal control transistors are connected to a read select signal, denoted as RDCS, so as to control the transmission of the input signal of the sense amplifier circuit by using the read select signal control transistor.

[0123] As an alternative implementation, an embodiment of the present invention further provides a chip, and the chip may include the memory provided by the embodiment of the present invention.

[0124] As an alternative implementation, for the sense amplifier circuit provided by the embodiment of the present invention, a corresponding circuit control method may be further provided, and the content of the corresponding method may refer to the previous description and will not be elaborated here.

[0125] Based on the sense amplifier circuit provided by the embodiment of the present invention, the embodiment of the present invention further provides a circuit control method. The content of the circuit control method introduced below may be executed by the sense amplifier circuit provided by the embodiment of the present invention. The circuit structure of each step of the specific execution method may refer to the previous description and will not be elaborated below.

[0126] Optionally, Figure 13 is an alternative flow of the circuit control method provided by the embodiment of the present invention. Refer to Figure 13 , and the method may include:

[0127] Step S20: Input a first input signal and a second input signal;

[0128] Step S21: Generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal;

[0129] Step S22: Amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference;

[0130] Step S23: Output an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage.

[0131] As an alternative implementation, an embodiment of the present invention further provides a test memory, which is applied to the chip test link after chip design. The test memory includes:

[0132] Multiple groups of memory cells;

[0133] The storage unit includes a storage circuit and a sense amplifier circuit connected to the storage circuit;

[0134] Among them, the sense amplifier circuit in at least one group of storage units is the sense amplifier circuit described in the above embodiment.

[0135] Among them, one group of storage units can be an IO bits group (input / output group). By setting at least one sense amplifier circuit as the sense amplifier circuit described in the above embodiment, the performance of the sense amplifier circuit, such as the flip error rate, can be tested, so as to determine whether to adopt the corresponding sense amplifier circuit.

[0136] It can be understood that the sense amplifier circuit provided by the embodiment of the present invention has a low flip error rate. Especially in the dual-voltage domain scenario, the corresponding flip error rate is much lower than that of the sense amplifier circuits of other structures. However, in order to determine a better-performing structure as the final structure among the structures of multiple sense amplifier circuits provided by the embodiment of the present invention (refer to Figures 4 - 9 ), the embodiment of the present invention further provides a test memory. In multiple groups of storage units of the test memory, in at least one group of storage units, the structure of the differential pressure amplification sub-module is the first structure, and the first structure is as Figure 4 shown; and / or, in at least one group of storage units 300, the structure of the differential pressure amplification sub-module is the second structure, and the second structure is as Figure 5 shown; and / or, in at least one group of storage units 300, the structure of the differential pressure amplification sub-module is the third structure, and the third structure is as Figure 6 shown; and / or, in at least one group of storage units 300, the structure of the differential pressure amplification sub-module is the fourth structure, and the fourth structure is as Figure 7 shown; and / or, in at least one group of storage units 300, the structure of the differential pressure amplification sub-module is the fifth structure, and the fifth structure is as Figure 8 shown; and / or, in at least one group of storage units 300, the structure of the differential pressure amplification sub-module is the sixth structure, and the sixth structure is as Figure 9 shown.

[0137] As a preferred embodiment, 6 groups of storage units can be set, each corresponding to a different structure, in order to Figure 14Taking the optional structural diagram of a test memory with a non-predictable and non-programmable sense amplifier circuit as an example, a group of memory cells may include one or more memory cell arrays (in the figure, one memory cell array is taken as an example), and one memory cell array corresponds to a sense amplifier circuit of one structure. Among them, the sense amplifier circuit is connected to the clock control and address decoding circuit, and the memory cell array is connected to the row decoding drive circuit. Based on the above structure for testing, the yield rate of each structure can be determined according to the corresponding test data, and then the target structure to be adopted can be determined.

[0138] Specifically, the target structure can be selected from sense amplifier circuits of multiple different structures. The test steps may include: respectively connecting sense amplifier circuits of multiple different structures to different memory cell arrays, specifically, connecting to the read output port of the memory cell array; then, performing a tape-out test to determine the sense amplifier circuit structure with the highest yield rate, and using the sense amplifier circuit of this structure as the target structure. Among them, this target structure can be applied to subsequent ECO or mass production SRAM designs.

[0139] In an optional example, the embodiment of the present invention further provides a differential pressure amplification sub-module with an alternative structure. This alternative structure is a programmable alternative structure. Specifically, the sense amplifier circuit includes: a first input transistor MNGT for generating a first initial voltage based on the first input signal and a second input transistor MNGC for generating a second initial voltage based on the second input signal, and a pull-down transistor for pulling down the signal of the differential input module;

[0140] In at least one group of memory cells, the differential pressure amplification sub-module 220 is an alternative structure, and the alternative structure includes: a first differential pressure amplification unit connected to the first input transistor MNGT, and a second differential pressure amplification unit connected to the second input transistor MNGC;

[0141] Reference Figure 15An alternative structural diagram of the first differential pressure amplification unit shown. The first differential pressure amplification unit 221 includes a first alternative transistor MNG21 and a second alternative transistor MNG22, as well as a first switch S01, a second switch S02, a third switch S03, a fourth switch S04, a fifth switch S05, a sixth switch S06, and a seventh switch S07. The gate of the first alternative transistor MNG21 is connected to the gate of the first input transistor MNGT through the first switch S01, and is connected to the first signal source through the second switch S02. The source is connected to the drain of the first input transistor MNGT, and is connected to the drain of the second alternative transistor through the third switch S03. The drain is connected to the drain of the pull-down transistor. The gate of the second alternative transistor MNG22 is connected to the gate of the first input transistor MNGT through the fourth switch S04, and is connected to the second signal source through the fifth switch S05. The source is connected to the source of the first input transistor MNGT through the sixth switch S06, and the drain is connected to the drain of the first alternative transistor MNG21 through the seventh switch S07.

[0142] Reference Figure 16 An alternative structural diagram of the second differential pressure amplification unit shown. The second differential pressure amplification unit 222 includes a third alternative transistor MNG23 and a fourth alternative transistor MNG24, as well as an eighth switch S08, a ninth switch S09, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, and a fourteenth switch S14. The gate of the third alternative transistor MNG23 is connected to the gate of the second input transistor MNGC through the eighth switch S08, and is connected to the first signal source through the ninth switch S09. The source is connected to the drain of the second input transistor MNGC, and is connected to the drain of the fourth alternative transistor MNG24 through the tenth switch S10. The drain is connected to the drain of the pull-down transistor. The gate of the fourth alternative transistor MNG24 is connected to the gate of the second input transistor MNGC through the eleventh switch S11, and is connected to the second signal source through the twelfth switch S12. The source is connected to the source of the second input transistor MNGC through the thirteenth switch S13, and the drain is connected to the drain of the third alternative transistor MNG23 through the fourteenth switch S14.

[0143] The first signal source is used to output a first signal TIE1, and the first signal TIE1 is used to control the first alternative transistor and the third alternative transistor to be in an on state; the second signal source is used to output a second signal TIE0, and the second signal TIE0 controls the second alternative transistor and the fourth alternative transistor to be in an off state; the conduction types of the first alternative transistor and the second alternative transistor are the same as the conduction type of the first input transistor; the conduction types of the third alternative transistor and the fourth alternative transistor are the same as the conduction type of the second input transistor.

[0144] The alternative structure is formed by means of through-silicon via programming. Among them, the through-silicon vias and wires in the alternative structure are used as switches to control the connection relationship of the alternative structure.

[0145] Among them, the alternative structure can realize the test of different-structured differential voltage amplification sub-modules by adjusting the switch states. Specifically, in an optional example, the differential voltage amplification sub-modules in at least 6 groups of memory cells are alternative structures; among them,

[0146] In at least one group of memory cells, in the first differential voltage amplification unit of the alternative structure, the first switch is turned on and the rest of the switches are turned off; in the second differential voltage amplification unit of the alternative structure, the eighth switch is turned on and the rest of the switches are turned off, so that the differential voltage amplification sub-module is Figure 4 the first structure as described above;

[0147] And / or, in at least one group of memory cells, in the first differential voltage amplification unit of the alternative structure, the second switch is turned on and the rest of the switches are turned off; in the second differential voltage amplification unit of the alternative structure, the ninth switch is turned on and the rest of the switches are turned off, so that the differential voltage amplification sub-module is as Figure 5 the second structure as described above;

[0148] And / or, in at least one group of memory cells, in the first differential voltage amplification unit of the alternative structure, the third switch, the fourth switch, the sixth switch and the seventh switch are turned on and the rest of the switches are turned off; in the second differential voltage amplification unit of the alternative structure, the tenth switch, the eleventh switch, the thirteenth switch and the fourteenth switch are turned on and the rest of the switches are turned off, so that the differential voltage amplification sub-module is as Figure 6 the third structure as described above;

[0149] And / or, in at least one group of memory cells, in the first differential voltage amplification unit of the alternative structure, the first switch, the fourth switch, the sixth switch and the seventh switch are turned on and the rest of the switches are turned off; in the second differential voltage amplification unit of the alternative structure, the eighth switch, the eleventh switch, the thirteenth switch and the fourteenth switch are turned on and the rest of the switches are turned off, so that the differential voltage amplification sub-module is asFigure 7 The fourth structure described above;

[0150] And / or, in at least one group of memory cells, in the first differential pressure amplification unit of the alternative structure, the first switch, the fifth switch, the sixth switch, and the seventh switch are turned on, and the remaining switches are turned off; in the second differential pressure amplification unit of the alternative structure, the eighth switch, the twelfth switch, the thirteenth switch, and the fourteenth switch are turned on, and the remaining switches are turned off, so that the differential pressure amplification sub-module is as Figure 8 The fifth structure described above;

[0151] And / or, in at least one group of memory cells, in the first differential pressure amplification unit of the alternative structure, the first switch, the third switch, the fifth switch, and the sixth switch are turned on, and the remaining switches are turned off; in the second differential pressure amplification unit of the alternative structure, the eighth switch, the tenth switch, the twelfth switch, and the thirteenth switch are turned on, and the remaining switches are turned off, so that the differential pressure amplification sub-module is as Figure 9 The sixth structure described above.

[0152] Specifically, refer to the switch states under each structure listed in the following table:

[0153] Table 1: States of S01 to S07 under each structure

[0154] S01 S02 S03 S04 S05 S06 S07 First structure on off off off off off off Second structure off on off off off off off Third structure off off on on off on on Fourth structure on off off on off on on Fifth structure on off off off on on on Sixth structure on off on off on on off

[0155] Table 2: States of S08 to S14 under each structure

[0156] S08 S09 S10 S11 S12 S13 S14 First structure on off off off off off off Second structure off on off off off off off Third structure off off on on off on on Fourth structure on off off on off on on Fifth structure on off off off on on on Sixth structure on off on off on on off

[0157] Among them, on means turned on, and off means turned off.

[0158] In a further optional process, the 6 groups of memory cells can respectively correspond to the differential pressure amplification sub-module structures in different examples, so as to test the sensitivity and yield of 6 structures. And, after determining the optimal structure, in the ECO (Engineering Change Order) process, all sensitive amplification circuits can be adjusted to the optimal structure, so that the optimal structure can be directly used for subsequent tests or as a finished product to execute subsequent processes. It should be noted that during the ECO manufacturing after tape-out testing, the alternative structure can modify only two layers of metal wiring to adjust the sensitive amplification circuit, so that only a small number of photomasks need to be changed, and the chip manufacturing cost can be reduced to the greatest extent.

[0159] In a further optional example, it can be predicted Figures 4 - 9 One of the structures in is the optimal predicted structure, and the chip is tested based on this prediction. Specifically, refer to Figure 17Another alternative structure of the test memory of the predictive programmable sense amplifier circuit shown, where the differential voltage amplification sub-modules in the multiple groups of memory cells are all alternative structures. One group of memory cells can include one or more memory cell arrays (taking one memory cell array as an example in the figure), and one memory cell array corresponds to a sense amplifier circuit of one structure. Among them, at least 6 memory cell arrays are the test cell group 500, and the switch states of the alternative structures in these 6 groups of memory cell arrays are respectively used to form Figures 4 - 9 the structure described; the remaining memory cell arrays are the target cell group 400, and the switch states of the alternative structures in the target cell group 400 are used to form Figures 4 - 9 the optimal structure predicted in Figures 4 - 9 Any structure in. The sense amplifier circuit is connected to the clock control and address decoding circuit, and the memory cell array is connected to the row decoding drive circuit.

[0160] It can be understood that the test cell group 500 can be used as a reference structure of the device, and the target cell group 400 can be used as an effective structure of the device. Thus, during the wafer test process, if the prediction is accurate, there is no need to perform ECO adjustment, which can shorten the verification process and reduce costs. If the prediction is inaccurate, the differential voltage amplification sub-module in the target cell group can be adjusted by ECO, select the structure with the highest yield as the structure of the differential voltage amplification sub-module, and perform unified adjustment on all sense amplifier circuits in the target cell group.

[0161] Specifically, the optimal structure can be selected from the sense amplifier circuits of the test cell group and the target cell group. The test steps can include: connecting sense amplifier circuits of multiple different structures to different memory cell arrays respectively to form the test cell group; connecting the sense amplifier circuit of the optimal predicted structure to the remaining memory cell arrays to form the target cell group; then, performing wafer test to determine the sense amplifier circuit structure with the highest yield. If the optimal predicted structure has the highest yield, there is no need to execute the ECO process. If a structure in the test cell group has the highest yield, the sense amplifier circuits in the target cell group will be adjusted to the structure with the highest yield during the ECO process.

[0162] As an alternative implementation, an embodiment of the present invention also provides a test chip, which can include the above test memory provided by the embodiment of the present invention.

[0163] The above describes multiple embodiment solutions provided by the embodiments of the present invention. The various alternative ways introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thus extending multiple possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0164] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A sensitive amplification circuit, characterized in that, it includes: an input module for inputting a first input signal and a second input signal; a differential input module, which includes a pressure difference generation sub-module and a pressure difference amplification sub-module; the pressure difference generation sub-module includes a first input transistor for generating a first initial voltage based on the first input signal and a second input transistor for generating a second initial voltage based on the second input signal, wherein the first initial voltage and the second initial voltage have an initial voltage difference; the pressure difference amplification sub-module is used to amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference; a mutual feedback amplification module for outputting an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage; the preset voltage difference is greater than the initial voltage difference.

2. The sensitive amplification circuit according to claim 1, characterized in that, the input module includes a first input signal line, a second input signal line and a first pre-charging unit, the first input signal line is used to transmit the first input signal, and the second input signal line is used to transmit the second transmission signal; the first pre-charging unit is used to pre-charge a first voltage for the first input signal line and the second input signal line; the sensitive amplification circuit further includes an output module, the output module includes a first output signal line, a second output signal line and a second pre-charging unit, and the second pre-charging unit is used to pre-charge a second voltage for the first output signal line and the second output signal line; the first voltage is a variable value, the second voltage is a variable value, and the first voltage and the second voltage are equal or are high and low with respect to each other; the preset voltage difference is equal to the value of the second voltage.

3. The sensitive amplification circuit according to claim 2, characterized in that, the gate of the first input transistor is connected to the first input signal line, the source is connected to the mutual feedback amplification module, and the drain is connected to the pressure difference amplification sub-module; the gate of the second input transistor is connected to the second input signal line, the source is connected to the mutual feedback amplification module, and the drain is connected to the pressure difference amplification sub-module.

4. The sensitive amplification circuit according to claim 3, characterized in that, the pressure difference amplification sub-module is used to increase the voltage difference between the first input signal and the second input signal, or reduce the current transmitted by the first input transistor and the second input transistor.

5. The sensitive amplification circuit according to claim 4, characterized in that, it further includes a pull-down module for pulling down the signal of the differential input module; the pull-down module includes a pull-down transistor, the gate of the pull-down transistor is connected to an amplification enable signal source, the drain is connected to the differential input module, and the source is grounded; the amplification enable signal source is used to output an amplification enable signal, and the amplification enable signal is used to enable the sensitive amplification circuit.

6. The sensitive amplification circuit according to claim 5, characterized in that, The differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; The first differential pressure amplification unit includes a first amplification transistor; the gate of the first amplification transistor is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; The second differential pressure amplification unit includes a second amplification transistor; the gate of the second amplification transistor is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; Wherein, the conduction type of the first amplification transistor is the same as that of the first input transistor, and the conduction type of the second amplification transistor is the same as that of the second input transistor.

7. The sensitive amplification circuit according to claim 5, characterized in that, The differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; Wherein, the first differential pressure amplification unit includes a third amplification transistor; the gate of the third amplification transistor is connected to a first signal source, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; The second differential pressure amplification unit includes a fourth amplification transistor; the gate of the fourth amplification transistor is connected to the first signal source, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; The first signal source is used to output a first signal, and the first signal controls the third amplification transistor and the fourth amplification transistor to be in an on state.

8. The sensitive amplification circuit according to claim 5, characterized in that, The differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; Wherein, the first differential pressure amplification unit includes a fifth amplification transistor; the gate of the fifth amplification transistor is connected to the gate of the first input transistor, the source is connected to the source of the first input transistor, the drain is connected to the drain of the first input transistor, and is connected to the drain of the pull-down transistor; The second differential pressure amplification unit includes a sixth amplification transistor; the gate of the sixth amplification transistor is connected to the gate of the second input transistor, the source is connected to the source of the second input transistor, the drain is connected to the drain of the second input transistor, and is connected to the drain of the pull-down transistor; The conduction type of the fifth amplification transistor is the same as that of the first input transistor, and the conduction type of the sixth amplification transistor is the same as that of the second input transistor.

9. The sensitive amplification circuit according to claim 5, characterized in that, The differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; Among them, the first differential pressure amplification unit includes a seventh amplification transistor and an eighth amplification transistor; the gate of the seventh amplification transistor is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the eighth amplification transistor is connected to the gate of the first input transistor, the source is connected to the source of the first input transistor, and the drain is connected to the drain of the seventh amplification transistor; The second differential pressure amplification unit includes a ninth amplification transistor and a tenth amplification transistor; the gate of the ninth amplification transistor is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the tenth amplification transistor is connected to the gate of the second input transistor, the source is connected to the source of the second input transistor, and the drain is connected to the drain of the ninth amplification transistor; The conduction types of the seventh amplification transistor and the eighth amplification transistor are the same as that of the first input transistor; the conduction types of the ninth amplification transistor and the tenth amplification transistor are the same as that of the second input transistor.

10. The sensitive amplification circuit according to claim 5, characterized in that, the differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; the first differential pressure amplification unit includes an eleventh amplification transistor and a twelfth amplification transistor; the gate of the eleventh amplification transistor is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the twelfth amplification transistor is connected to a second signal source, the source is connected to the source of the first input transistor, and the drain is connected to the drain of the eleventh amplification transistor; the second differential pressure amplification unit includes a thirteenth amplification transistor and a fourteenth amplification transistor; the gate of the thirteenth amplification transistor is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; the gate of the fourteenth amplification transistor is connected to the second signal source, the source is connected to the source of the second input transistor, and the drain is connected to the drain of the thirteenth amplification transistor; wherein, the second signal source is used to output a second signal, and the second signal controls the twelfth amplification transistor and the fourteenth amplification transistor to be in an off state; the conduction type of the eleventh amplification transistor is the same as that of the first input transistor; the conduction type of the thirteenth amplification transistor is the same as that of the second input transistor.

11. The sensitive amplification circuit according to claim 5, characterized in that, the differential pressure amplification sub-module includes a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; The first differential pressure amplification unit includes a fifteenth amplification transistor and a sixteenth amplification transistor; the gate of the fifteenth amplification transistor is connected to the gate of the first input transistor, the source is connected to the drain of the first input transistor, and the drain is connected to the drain of the pull-down transistor; The gate of the sixteenth amplification transistor is connected to a second signal source, the source is connected to the source of the first input transistor, and the drain is connected to the source of the fifteenth amplification transistor; The second differential pressure amplification unit includes a seventeenth amplification transistor and an eighteenth amplification transistor; The gate of the seventeenth amplification transistor is connected to the gate of the second input transistor, the source is connected to the drain of the second input transistor, and the drain is connected to the drain of the pull-down transistor; The gate of the eighteenth amplification transistor is connected to a second signal source, the source is connected to the source of the second input transistor, and the drain is connected to the source of the seventeenth amplification transistor; Wherein, the second signal source is used to output a second signal, and the second signal controls the sixteenth amplification transistor and the eighteenth amplification transistor to be in an off state; The conduction type of the fifteenth amplification transistor is the same as that of the first input transistor; the conduction type of the seventeenth amplification transistor is the same as that of the second input transistor.

12. The sensitive amplification circuit according to claim 3, characterized in that the mutual feedback amplification module includes a first differential amplification unit and a second differential amplification unit; The first differential amplification unit includes a first differential transistor and a second differential transistor; the second differential amplification unit includes a third differential transistor and a fourth differential transistor; Wherein, the source of the first differential transistor is connected to a second voltage source, the drain is connected to the source of the second differential transistor, and the gate is connected to the drain of the third differential transistor; the drain of the second differential transistor is connected to the source of the first input transistor, the gate is connected to the drain of the third differential transistor, and the signal in the gate of the second differential transistor is output as a second output signal; The second differential amplification unit includes a third differential transistor and a fourth differential transistor; the source of the third differential transistor is connected to a second voltage source, the drain is connected to the source of the fourth differential transistor, and the gate is connected to the drain of the first differential transistor; the drain of the fourth differential transistor is connected to the source of the second input transistor, the gate is connected to the drain of the first differential transistor, and the signal in the gate of the fourth differential transistor is output as a first output signal; Wherein, the conduction type of the first differential transistor is different from that of the second differential transistor, the conduction type of the third differential transistor is different from that of the fourth differential transistor, and the conduction type of the first differential transistor is the same as that of the third differential transistor; the second voltage source is used to provide a second voltage.

13. The sensitive amplification circuit according to claim 2, characterized in that The first pre-charge unit includes a first charging transistor, a second charging transistor and a first balancing transistor; The gates of the first charging transistor, the second charging transistor, and the first balancing transistor are connected to a pre-charge enable signal source; The source of the first charging transistor is connected to a first voltage source, and the drain is connected to the first input signal line; The source of the second charging transistor is connected to the first voltage source, and the drain is connected to the second input signal line; The source of the first balancing transistor is connected to the first input signal line, and the drain is connected to the second input signal line; Wherein, the first charging transistor, the second charging transistor, and the first balancing transistor have the same conductivity type; the pre-charge enable signal source is used to output a pre-charge enable signal, and the first voltage source is used to output a first voltage; The second pre-charge unit includes a third charging transistor, a fourth charging transistor, and a second balancing transistor; The gates of the third charging transistor, the fourth charging transistor, and the second balancing transistor are connected to an amplification enable signal source; the source of the third charging transistor is connected to a second voltage source, and the drain is connected to the first output signal line; the source of the fourth charging transistor is connected to the second voltage source, and the drain is connected to the second output signal line; The source of the second balancing transistor is connected to the first output signal line, and the drain is connected to the second output signal line; Wherein, the third charging transistor, the fourth charging transistor, and the second balancing transistor have the same conductivity type; the amplification enable signal source is used to output an amplification enable signal, and the second voltage source is used to output a second voltage.

14. The sense amplifier circuit according to claim 2, characterized in that, The output module further includes a latch unit, and the latch unit is configured to output a stored data signal based on the first output signal and the second output signal, and the stored data signal is used to represent the data stored in the storage unit.

15. A memory, characterized in that, The memory includes: A plurality of storage units; The storage unit includes a storage circuit and a sense amplifier circuit connected to the storage circuit, and the sense amplifier circuit is the sense amplifier circuit according to any one of claims 1 to 14.

16. A chip, characterized in that, The chip includes the memory according to claim 15.

17. A circuit control method, characterized in that, Applied to the sense amplifier circuit according to any one of claims 1-14, the method includes: Input a first input signal and a second input signal; Generate a first initial voltage and a second initial voltage with an initial voltage difference based on the first input signal and the second input signal; Amplify the initial voltage difference to generate a first amplified voltage and a second amplified voltage with an amplified voltage difference; Output an output signal with a preset voltage difference based on the first amplified voltage and the second amplified voltage.

18. A test memory, characterized in that, Includes: Multiple groups of storage units; The storage unit includes a storage circuit and a sense amplifier circuit connected to the storage circuit; Wherein, the sense amplifier circuit in at least one group of storage units is the sense amplifier circuit according to any one of claims 1 to 14.

19. The test memory according to claim 18, wherein, among the multiple groups of memory cells, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the first structure, and the first structure is as described in claim 6; and / or, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the second structure, and the second structure is as described in claim 7; and / or, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the third structure, and the third structure is as described in claim 8; and / or, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the fourth structure, and the fourth structure is as described in claim 9; and / or, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the fifth structure, and the fifth structure is as described in claim 10; and / or, in at least one group of memory cells, the structure of the differential pressure amplification sub-module is the sixth structure, and the sixth structure is as described in claim 11.

20. The test memory according to claim 18, wherein, the sense amplifier circuit includes: a first input transistor for generating a first initial voltage based on the first input signal, a second input transistor for generating a second initial voltage based on the second input signal, and a pull-down transistor for pulling down the signal of the differential input module; in at least one group of memory cells, the differential pressure amplification sub-module is an alternative structure, and the alternative structure includes: a first differential pressure amplification unit connected to the first input transistor, and a second differential pressure amplification unit connected to the second input transistor; the first differential pressure amplification unit includes a first alternative transistor and a second alternative transistor, as well as a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a seventh switch; the gate of the first alternative transistor is connected to the gate of the first input transistor through the first switch and to a first signal source through the second switch, the source is connected to the drain of the first input transistor and to the drain of the second alternative transistor through the third switch, and the drain is connected to the drain of the pull-down transistor; the gate of the second alternative transistor is connected to the gate of the first input transistor through the fourth switch and to a second signal source through the fifth switch, the source is connected to the source of the first input transistor through the sixth switch, and the drain is connected to the drain of the first alternative transistor through the seventh switch; The second differential pressure amplification unit includes a third alternative transistor and a fourth alternative transistor, as well as an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the gate of the third alternative transistor is connected to the gate of the second input transistor through the eighth switch and to the first signal source through the ninth switch, the source is connected to the drain of the second input transistor and to the drain of the fourth alternative transistor through the tenth switch, and the drain is connected to the drain of the pull-down transistor; the gate of the fourth alternative transistor is connected to the gate of the second input transistor through the eleventh switch and to the second signal source through the twelfth switch, the source is connected to the source of the second input transistor through the thirteenth switch, and the drain is connected to the drain of the third alternative transistor through the fourteenth switch; The first signal source is used to output a first signal, and the first signal is used to control the first alternative transistor and the third alternative transistor to be in an on state; the second signal source is used to output a second signal, and the second signal controls the second alternative transistor and the fourth alternative transistor to be in an off state; the conduction types of the first alternative transistor and the second alternative transistor are the same as the conduction type of the first input transistor; the conduction types of the third alternative transistor and the fourth alternative transistor are the same as the conduction type of the second input transistor.

21. The test memory according to claim 20, wherein, the alternative structure is formed by a through-silicon via programming method, wherein the through-silicon vias and wires in the alternative structure are used as switches to control the connection relationship of the alternative structure.

22. The test memory according to claim 20, wherein, the differential pressure amplification sub-modules in at least 6 groups of memory cells are alternative structures; wherein, in at least one group of memory cells, in the first differential pressure amplification unit of the alternative structure, the first switch is turned on and the rest of the switches are turned off; in the second differential pressure amplification unit of the alternative structure, the eighth switch is turned on and the rest of the switches are turned off, so that the differential pressure amplification sub-module is the structure according to claim 6; and / or, in at least one group of memory cells, in the first differential pressure amplification unit of the alternative structure, the second switch is turned on and the rest of the switches are turned off; in the second differential pressure amplification unit of the alternative structure, the ninth switch is turned on and the rest of the switches are turned off, so that the differential pressure amplification sub-module is the structure according to claim 7; and / or, in at least one group of memory cells, in the first differential pressure amplification unit of the alternative structure, the third switch, the fourth switch, the sixth switch, and the seventh switch are turned on and the rest of the switches are turned off; in the second differential pressure amplification unit of the alternative structure, the tenth switch, the eleventh switch, the thirteenth switch, and the fourteenth switch are turned on and the rest of the switches are turned off, so that the differential pressure amplification sub-module is the structure according to claim 8; And / or, in at least one set of memory cells, in the first differential voltage amplification unit of the alternative structure, the first switch, the fourth switch, the sixth switch, and the seventh switch are turned on, and the remaining switches are turned off; in the second differential voltage amplification unit of the alternative structure, the eighth switch, the eleventh switch, the thirteenth switch, and the fourteenth switch are turned on, and the remaining switches are turned off, so that the differential voltage amplification sub-module has the structure as described in claim 9. And / or, in at least one set of memory cells, in the first differential voltage amplification unit of the alternative structure, the first switch, the fifth switch, the sixth switch, and the seventh switch are turned on, and the remaining switches are turned off; in the second differential voltage amplification unit of the alternative structure, the eighth switch, the twelfth switch, the thirteenth switch, and the fourteenth switch are turned on, and the remaining switches are turned off, so that the differential voltage amplification sub-module has the structure as described in claim 10. And / or, in at least one set of memory cells, in the first differential voltage amplification unit of the alternative structure, the first switch, the third switch, the fifth switch, and the sixth switch are turned on, and the remaining switches are turned off; in the second differential voltage amplification unit of the alternative structure, the eighth switch, the tenth switch, the twelfth switch, and the thirteenth switch are turned on, and the remaining switches are turned off, so that the differential voltage amplification sub-module has the structure as described in claim 11.

23. The test memory according to claim 20, wherein, the differential voltage amplification sub-modules in the multiple sets of memory cells are all of the alternative structure, wherein at least 6 sets of memory cells are test cell groups, and the switch states of the alternative structure in these 6 sets of memory cells are respectively used to form the structures described in claims 6 to 11; the remaining memory cells are target cell groups, and the switch states of the alternative structure in the target cell groups are used to form the structure described in any one of claims 6 to 11.

24. A test chip, wherein, it includes: the test memory according to any one of claims 18 - 23.

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