Programming apparatus, method and novel memory

Abstract

The application provides a programming device, a method and a novel memory. The device comprises a programming control unit and a programming unit. The programming control unit is used for, in response to an excitation signal of an excitation clock, sequentially taking each valid storage unit in a to-be-programmed row as a first unit, performing processing until all the valid storage units are programmed: according to a predetermined number, selecting the first unit and the valid storage units after the first unit, configuring the selected valid storage units as a programming state, and configuring the valid storage units after the first unit and not selected as a non-programming state; and the programming unit is used for, according to a predetermined period, performing programming on the valid storage units currently configured as the programming state until all the valid storage units are programmed. The application realizes selection of the same number of partial units at any time period, sequential movement in a row, replacement of the programmed units with unprogrammed units, and traversal of the whole row of to-be-programmed units.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a programming device, a programming method and a novel memory. BACKGROUND

[0002] A memory is a collection of many memory cells arranged in order of cell number. Each cell is composed of several binary bits to represent the value stored in the memory cell. Traditional memories, such as flash memory and dynamic random access memory (DRAM), store data "0" and data "1" by changing the threshold voltage and other electrical characteristics of the cell by injecting charge into the cell. Novel memories, such as resistive random access memory (RRAM), store data by switching between high and low resistance states based on their own resistance values.

[0003] Taking flash memory as an example, it is common to erase the entire chip and then program each row. Since each flash memory cell consumes less power, the entire row can be programmed at the same time. The specific method is to select a row, store the data to be written in the page latch, and then write to the cells that need to be programmed at the same time.

[0004] However, the above method of programming the entire row at the same time is not suitable for novel memories, because the programming current of a single resistive cell in a novel memory is very high, and simultaneous programming results in excessive current, which poses a risk of chip burnout due to excessive heat. SUMMARY

[0005] The present application provides a programming device, a programming method and a novel memory to solve the programming problem of novel memories.

[0006] In a first aspect, the present application provides a programming device, comprising: a programming control unit and a programming unit;

[0007] The programming control unit is configured to, in response to an excitation signal of an excitation clock, sequentially take each valid memory cell in a row to be programmed as a first cell, and perform processing until all valid memory cells are programmed: according to a predetermined number, select the first cell and the valid memory cells after the first cell, and configure them to be in a programming state, and configure the valid memory cells after the first cell that are not selected to be in a non-programming state.

[0008] The programming unit is configured to perform programming on the valid memory cells currently configured to be in the programming state according to a predetermined period until all valid memory cells are programmed.

[0009] In a second aspect, the present application provides a programming method applied to a programming device, the programming device comprising a programming control unit and a programming unit; the method comprising: in response to an excitation signal of an excitation clock, the programming control unit sequentially taking each valid storage unit in a to-be-programmed row as a first unit, and performing the following processing until all valid storage units are programmed: according to a predetermined number, selecting the first unit and the valid storage units after the first unit, and configuring the selected valid storage units into a programming state; and the programming unit performing programming on the valid storage units currently configured into the programming state according to a predetermined period until all valid storage units are programmed.

[0010] In a third aspect, the present application provides a hardware code product comprising hardware code, which, when executed by a processor, implements the method of the second aspect.

[0011] In a fourth aspect, the present application provides a readable storage medium, which stores hardware code, and the hardware code, when executed, is used to implement the method of the second aspect.

[0012] In a fifth aspect, the present application provides an electronic device comprising a processor and a memory connected to the processor in communication; the memory stores hardware code; and the processor executes the hardware code stored in the memory to implement the method of the second aspect.

[0013] In a sixth aspect, the present application provides a novel memory comprising a plurality of resistance-type storage units and a programming device of the first aspect; the programming device is used to program the resistance-type storage units.

[0014] The programming device, method and novel memory provided by the present application comprise a programming control unit and a programming unit; the programming control unit is used to, in response to an excitation signal of an excitation clock, sequentially take each valid storage unit in a to-be-programmed row as a first unit, and perform processing until all valid storage units are programmed: according to a predetermined number, select the first unit and the valid storage units after the first unit, and configure the selected valid storage units into a programming state; and the programming unit is used to perform programming on the valid storage units currently configured into the programming state according to a predetermined period until all valid storage units are programmed. The present application configures a predetermined number of partial valid storage units into a programming state at any time period through an excitation clock, realizes programming of only partial units in a row, effectively controls total programming current, and avoids the risk of chip damage caused by high current due to simultaneous programming of all units in a row; and the units programmed in sequence can be replaced by unprogrammed units in a row, realizing traversal of all to-be-programmed units in a row. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0016] Figure 1 A schematic diagram of a programming structure for a conventional flash memory array;

[0017] Figure 2 A schematic diagram of a programming structure for a resistive random access memory array provided by the present application;

[0018] Figure 3 A schematic diagram of a programming device provided by the present application;

[0019] Figure 4 A schematic diagram of the operation of a programming device provided by the present application;

[0020] Figure 5 A circuit diagram of a programming control unit provided by the present application;

[0021] Figure 6 A waveform diagram of an external link signal provided by the present application;

[0022] Figure 7 A schematic diagram of another programming device provided by the present application;

[0023] Figure 8 A schematic diagram of yet another programming device provided by the present application;

[0024] Figure 9 A circuit diagram of another programming control unit provided by the present application;

[0025] Figure 10 A schematic diagram of still another programming device provided by the present application;

[0026] Figure 11 A circuit diagram of still another programming control unit provided by the present application;

[0027] Figure 12 A signal timing diagram of a programming control unit provided by the present application.

[0028] The specific embodiments of the present application have been shown by way of example in the above-described drawings and more particularly described in the above specification. These drawings and this description do not limit the scope of the inventive concept in any way, but serve as an aid in understanding the same. It will be understood that various modifications can be made to the embodiments of the present application seen in the drawings and described above. DETAILED DESCRIPTION

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0030] First, let me explain the terms used in this application:

[0031] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the resistance of a non-conductive material to reversibly switch between a high-resistance state and a low-resistance state under the action of an external electric field.

[0032] Memory is a collection of many storage cells arranged in order of cell number. Each cell consists of several binary bits to represent the value stored in the cell. Newer types of memory differ significantly from traditional memory in their storage methods.

[0033] Traditional memories, such as flash memory and dynamic random access memory (DRAM), primarily determine the storage state based on whether or not a cell is injected with charge. Charge injection alters the cell's threshold voltage and other electrical characteristics, allowing the storage data value to be determined by whether the cell is conducting, using an appropriate external voltage load. Newer memories, such as resistive random access memory (RRAM), primarily use the cell's own resistance as the criterion for determining the stored signal.

[0034] Traditional memory typically involves erasing the entire memory chip before reprogramming each row. For example, Figure 1 A schematic diagram of a traditional flash memory array programming structure, such as Figure 1 As shown, the row to be programmed is programmed. Specifically, a row is selected using a row address decoder, the data to be written is first stored in the page latch, and then the cells to be programmed are written simultaneously. Because each flash memory cell consumes relatively low power, an entire row can be programmed at the same time.

[0035] However, due to the different operating methods and characteristics of new types of memory, simply replacing them with the same method of simultaneous programming of the entire row would result in excessive power consumption. For example, in resistive random access memory (RRAM), the programming current of a single RRAM cell is very high; if programming is performed simultaneously, the excessive current could lead to the chip burning out due to overheating.

[0036] To solve this problem, consider whether the same time in the programming row only a portion of the memory cells are programmed. Figure 2 A schematic diagram of a resistive memory array programming structure provided by the present application is shown in FIG. 1. Figure 2 As shown, only a portion of the resistive cells are programmed in the same time period, which can effectively control the programming current.

[0037] However, Figure 2 The conceived programming mode has the problem of how to control the selection of a portion of the resistive cells. Since it is resource-consuming to externally control the selection of the resistive cells, it is considered to provide a structure outside the array periphery which can both solve the partial selection of the cells and implement the traversal of the cells.

[0038] The programming device, method and novel memory provided by the present application aim to realize the above concept and provide a structure which can both solve the partial selection of the cells and implement the traversal of the cells.

[0039] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0040] Embodiment one

[0041] Figure 3 A structure schematic diagram of a programming device provided by the present application is shown in FIG. 1. The programming device comprises a programming control unit 10 and a programming unit 20. The programming control unit 10 is configured to control the selection of the memory cells to be programmed, and the programming unit 20 is configured to program the selected memory cells.

[0042] The programming control unit 10, in response to the excitation signal of the excitation clock, sequentially takes each valid memory cell in the row to be programmed as a first cell, executes the processing until all the valid memory cells are programmed: according to the predetermined number, selects the first cell and the valid memory cells after the first cell, configures them as a programming state, and configures the valid memory cells after the first cell which are not selected as a non-programming state. The programming unit 20 executes the programming of the valid memory cells currently configured as the programming state according to the predetermined period until all the valid memory cells are programmed.

[0043] Specifically, Figure 4 A working process schematic diagram of a programming device provided by the present application is shown in FIG. 2. When it is needed to write a row into the memory array, a value will be written on the page latch. Among them, 1 represents the cells to be programmed, and 0 represents the cells not to be programmed. As shown in FIG. 2, when it is needed to write a row into the memory array, a value will be written on the page latch. Among them, 1 represents the cells to be programmed, and 0 represents the cells not to be programmed. Figure 4As shown, in the first row of cells, the cells with superscript 1 are the storage cells that need to be programmed. The cells that need to be programmed are selected and arranged in order as well, forming a valid programming cell chain.

[0044] In actual programming, all programming operations only act on the selected valid programming cell chain. It should be noted that the writing of the page latch value is controlled by another program or circuit, and is not performed by the programming control unit 10 and the programming unit 20 in the present application. Since it is not the important invention content of the present application, it will not be described in detail.

[0045] In the above valid programming cell chain, N storage cells are selected and configured in the programming state at a single time. Only adjacent N cells are in the programmed state at any programming time. For example, as shown in Figure 4 As shown, four valid storage cells are selected and configured in the programming state at a single time, and the other valid storage cells are configured in the non-programming state. The programming unit 20 sequentially programs the first cell in the selected four valid storage cells.

[0046] It should be noted that the operation of selecting N storage cells and configuring them in the programming state at a single time is performed in the initialization stage before programming. A feasible way is to input a clock signal to the valid programming cell chain through an external link to control the number N. The circuit structure of the programming control unit 10 will be described in detail later.

[0047] Further, after starting programming, referring to Figure 4 , from the second row to the fourth row, the storage cells configured in the programming state are in the Active cells box. When the programming of the first storage cell in the box is completed, the Active cells are sequentially moved, adding another unprogrammed storage cell, and continuing to program the first storage cell in the current Active cells box. This operation is repeated until the last cell is programmed, and through the pipeline programming control process, the traversal of the entire row of storage cells to be programmed is realized.

[0048] The present application selects the same number of partial cells at any time period, effectively controls the programming current, and avoids causing chip heating damage. The present application sets a control circuit in the programming device to automatically move in a pipeline progressive manner according to the order in the programming of a row, replaces the programmed cells with unprogrammed cells, realizes the traversal of the storage cells to be programmed, does not need to set an external control device, and reduces resource consumption.

[0049] The structure and action process of the programming device will be introduced in combination with the circuit diagram.

[0050] Figure 5A circuit diagram of a programming control unit is provided in the present application. The programming control unit 10 comprises: a programming unit chain composed of a plurality of flip-flops connected in series; wherein the plurality of flip-flops correspond one-to-one to page latches corresponding to each memory cell in a row to be programmed.

[0051] As shown in Figure 5 , a programming unit chain composed of four D flip-flops is shown, each D flip-flop corresponding to a page latch P.L. (abbreviation of Page Latch), and each page latch P.L. corresponding to a memory cell Cell. The input end of the D flip-flop is the "D" end; the output end is the "Q" end; and the clock port is the "CLK" end.

[0052] Wherein, the clock port of each flip-flop is connected to the excitation clock through the first switch A, the output end of each flip-flop is connected to the input end of the next flip-flop through the second switch B, and the input end of each flip-flop is connected to the input end of the next flip-flop through the third switch E.

[0053] Figure 5 The first switch A i+1 , the second switch B i+1 and the third switch E i+1 corresponding to the i+1th flip-flop are shown, and the output value is C i+1 , the subscript representing the corresponding flip-flop. By analogy, the first switch A i+2 , the second switch B i+2 and the third switch E i+2 corresponding to the i+2th flip-flop are not shown in Figure 5 , and the output value is C i+2 .

[0054] The page latch corresponding to each memory cell is used to control the switching state of the first switch A, the second switch B and the third switch E of the corresponding flip-flop based on the storage data of itself, so as to establish an effective programming unit chain; wherein the memory cell corresponding to the flip-flop in the effective programming unit chain is an effective memory cell; wherein the flip-flop corresponding to the effective memory cell in the programming state is configured as the first logic, and the flip-flop corresponding to the effective memory cell in the non-programming state is configured as the second logic. Hereinafter, the first logic is taken as 1 and the second logic is taken as 0 as an example for illustration.

[0055] In one example, the programming control unit 10 further comprises: a plurality of inverters; the plurality of inverters correspond one-to-one to the plurality of flip-flops, the input end of the inverter is connected to the corresponding page latch, and the output end of the inverter is connected to the control end of the third switch E of the corresponding flip-flop.

[0056] Specifically, refer to Figure 5When the storage data in the page latch is 1, the first switch A and the second switch B are in the closed state; and the third switch E is in the open state. Therefore, the clock port of the D flip-flop can receive the clock signal through the first switch A, and the output end of the current D flip-flop is connected with the input end of the next D flip-flop through the second switch B. At this time, the current D flip-flop is connected in the link.

[0057] When the storage data in the page latch is 0, the first switch A and the second switch B are in the open state; and the third switch E is in the closed state. Therefore, the clock port of the D flip-flop cannot receive the clock signal, and the output end of the current D flip-flop is disconnected with the input end of the next D flip-flop. The next D flip-flop can receive the signal output by the previous D flip-flop through the closed third switch E. At this time, the current D flip-flop is bypassed and not connected in the link.

[0058] Before programming, part of the data needs to be written to the valid programming unit chain through the external link, and the number N of valid storage units is selected and configured to be in the programming state, that is, initialized. After running the programming, the number of valid storage units in the programming state at any time period is N, which will not change after being set by the external link. Among them, when the number of remaining valid storage units to be programmed is less than N at the end of the programming of the entire new memory, the number of valid storage units in the programming state in the subsequent period will decrease one by one until the programming of all valid storage units is completed. The following describes the middle period of the programming of the new memory (the number is fixed as N in each period), and does not consider the special case of the end of the programming of the new memory unless otherwise specified.

[0059] In actual application, the number N needs to be obtained through experiment or calculation. If the number N is too large, the programming current will be too large, and the technical problem of the present application cannot be solved. If the number N is too small, the programming efficiency will be affected.

[0060] Figure 6 An external link signal waveform diagram provided by the present application is shown in Figure 6 , and the method of configuring the number N of valid storage units to be in the programming state is introduced in combination with the circuit structure shown in Figure 5 .

[0061] As shown in Figure 6As shown, the programming enable signal Prog_en is used to control whether the array is in programming mode. Prog_en is always at logic 0, so that the array is not in programming mode, and thus can be initialized through the external link before programming. The link input signal Chain_In inputs a signal to the input end D of the D flip-flop, and the link clock signal CLK_O provides a trigger rising edge excitation signal for the D flip-flop.

[0062] Here, the electrical characteristics of the D flip-flop are utilized, and the electrical characteristics of the D flip-flop are described. The D flip-flop is a memory device with two stable states, and is the most basic logic unit for constructing various sequential circuits, and is also an important unit circuit in digital logic circuits. There are two trigger modes, level trigger and edge trigger. The former can be triggered when the clock pulse = 1, and the latter is triggered at the front edge (positive jump 0→1) of the clock pulse. The D flip-flop includes an input end, a clock port, and an output end, and the clock port is used to receive a clock signal. Taking the edge trigger type D flip-flop as an example, the action result is: when the input end is logic 1, after receiving the trigger of the rising edge excitation signal, the output end outputs 1; when the input end is logic 0, after receiving the trigger of the rising edge excitation signal, the output end outputs 0.

[0063] The first step of initialization: write all 1 data to the page latch, so that all D flip-flops are in the link.

[0064] The second step of initialization: all D flip-flops are written to save logic 0 state through external link clock control. The specific process is: the Chain_In signal is always set to logic 0, and a periodic link clock signal CLK_O is inputted uninterruptedly until all D flip-flops are written to save logic 0 state.

[0065] The third step of initialization: store the data to be written in the page latch, so that only the D flip-flop corresponding to the unit to be programmed is in the link, and an effective programming unit chain is established.

[0066] The fourth step of initialization: the Chain_In signal input end is set to logic 1, and the CLK_O signal provides N clock cycles, where N is an arbitrary integer and can be defined by the user. After N cycles are completed, the Chain_In signal input end is set to logic 0. The purpose of this operation is to make the first N D flip-flops in the effective programming unit chain be at logic 1, and the other D flip-flops be at logic 0.

[0067] For example, taking four D flip-flops in Figure 5 as an example, it is assumed that the corresponding page memories of the four D flip-flops are all 1, that is, the four D flip-flops are all in the link. At the same time, it is assumed that N = 2, and the CLK_O signal provides 2 clock cycles, that is, the CLK_O signal has 2 rising edge signals. Figure 5In the middle, from left to right are D i+1 flip-flops, D i+2 flip-flops, D i+3 flip-flops, D i+4 flip-flops.

[0068] Chain_In signal input is logic 1, D i+1 flip-flop input C i signal is logic 1, when D i+1 flip-flop receives the first rising edge signal of CLK_O signal, D i+1 flip-flop output jumps to logic 1, namely C i+1 jump to logic 1. The first rising edge of CLK_O signal, D i+2 flip-flop output at this time still remains logic 0, when receiving the second rising edge signal of CLK_O signal, because C i+1 is logic 1, so D i+2 flip-flop output C i+2 jumps to logic 1. And the second rising edge of CLK_O signal, C i signal is still logic 1, so D i+1 flip-flop output C i+1 remains logic 1. When the two clock cycles of CLK_O signal are completed, Chain_In signal input is logic 0. The state of D flip-flop in the effective programming unit chain will not change again.

[0069] That is, CLK_O signal provides 2 clock cycles, which can make the first 2 D flip-flops in the effective programming unit chain be logic 1. By analogy, when CLK_O signal provides 3 clock cycles, the first 3 D flip-flops in the effective programming unit chain can be logic 1.

[0070] Only when the corresponding storage unit column of D flip-flop and page latch is logic 1 at the same time, the corresponding storage unit can be configured into the electrical condition of programming state, so that the corresponding storage unit enters the programming state. Therefore, during initialization, only the first N units that need to be programmed can enter the programming state when the array enters the programming mode, which ensures that the number of storage units in the programming state at any time will not be more than N.

[0071] When the number N of storage units configured to be in programming state at the same time is set through the external link, the programming enable signal Prog_en signal jumps to logic 1, so that the array is in programming mode. In the programming mode, the clock signal of the programming control unit 10 is based on the internal clock.

[0072] Exemplary, Figure 7Another structure schematic diagram of the programming device provided in the present application is shown in FIG. 3. The programming device further comprises a clock generation unit 30 for providing an excitation clock to the programming control unit 10, i.e. there is an internal self-built clock. The advantage of the self-built clock is that no additional clock generation circuit is needed to generate an initial clock.

[0073] On the basis of the above examples, Figure 8 Another structure schematic diagram of the programming device provided in the present application is shown in FIG. 3. The programming device further comprises a clock generation unit 30 for providing an excitation clock to the programming control unit 10, i.e. there is an internal self-built clock. The advantage of the self-built clock is that no additional clock generation circuit is needed to generate an initial clock.

[0074] An exemplary, Figure 9 Another circuit diagram of the programming control unit provided in the present application is shown in FIG. 4. As shown in FIG. 4, the detection module 31 comprises a plurality of fourth switches S and a first comparator; the plurality of fourth switches correspond to the storage units in the programming row one by one; the first end of the fourth switch S is connected with the corresponding storage unit, and the second end of the fourth switch is connected with the non-inverting input end of the first comparator; the inverting input end of the first comparator is connected with a first reference voltage Vref1. Wherein, the fourth switch S is used for selecting the effective storage unit currently detected by the detection module 31, and the state of the fourth switch depends on the input data and the output data of the corresponding flip-flop; the output data of the first comparator represents whether the currently selected effective storage unit is programmed. Figure 9 Specifically, the fourth switch S i+1 depends on the input data C i and the output data C i+1 of the corresponding flip-flop. In the valid programming unit chain, the storage values C of all flip-flops are logic 0 except that the storage values C of the adjacent and continuous N flip-flops are logic 1, so that there is only one case that the storage value C of the previous flip-flop is logic 0 and the storage value C of the current flip-flop is logic 1 in the whole chain, i.e. the first unit of the valid storage unit configured in the programming state. The output data of the corresponding flip-flop is definitely logic 1, i.e. C i+1 is 1. And the input data C i of the flip-flop is the output data of the previous flip-flop, so it is definitely logic 0. Therefore, the detection module 31 detects the first valid storage unit currently in the programming state.

[0075]

[0076] ​It should be noted that, in order to correctly determine the programming state of the valid memory cell corresponding to the flip-flop with the storage value C1, there is an extra D flip-flop not corresponding to the column in the array at the front end of the D flip-flop chain, which is used to store the value C0, and it is easy to understand that the logic value thereof is 0.

[0077] Further, the first comparator functions as follows: when the voltage received by the first input end thereof is higher than the reference voltage Vref1, the detection result CO output thereby is high; otherwise, the detection result CO output thereby is low. In this embodiment, when the programming of the detected cell is completed, CO is logic 1 high; when the programming is not completed, CO is logic 0.

[0078] Referring to Figure 9 , the detection module 31 further comprises a first enable switch F1; the first enable switch F1 is arranged between the fourth switch and the first comparator; the first enable switch F1 is in a closed state after the programming unit 20 starts programming; the first enable switch F1 is in an open state before the programming unit 20 starts programming. The first enable switch F1 is controlled by an external link signal, such as the Prog_en signal shown in Figure 6 . After the Prog_en jumps to logic 1, the array enters the programming state.

[0079] Referring to Figure 9 , the generation module 32 comprises a first AND gate, a first OR gate, a first delay unit and a first inverter. The first input end of the first AND gate is connected with the output end of the detection module 31, and receives the detection result CO output by the detection module 31. The output end of the first AND gate is connected with the first input end of the first OR gate; the output end of the first OR gate is connected with the input end of the first delay unit; the output end of the first delay unit is connected with the input end of the first inverter; the output end of the first inverter is connected with the second input end of the first AND gate; wherein the second input end of the first OR gate inputs a first control signal Turn-off; according to the first control signal and the output signal of the output end of the first AND gate, the output end of the first OR gate outputs an initial excitation clock CLK_Internal.

[0080] Specifically, the output CO of the comparator can be used as a decision mark for the link self-moving clock jump. CO is not directly used to control the clock CLK_Internal, but is used to output the clock after logical operation with its own delay logic. The control process is as follows: when CO=0, Delay=1, the output of the first AND gate is 0, the output of the first OR gate is 0, and CLK_Intrenal is 0. When CO jumps to 1, Delay=1, the output of the first AND gate is 1, the output of the first OR gate is 1, and CLK_Intrenal jumps to 1. When CO continues to be 1, Delay=0, the output of the first AND gate is 0, the output of the first OR gate is 0, and CLK_Intrenal jumps to 0. By controlling the first delay, the up and down jump intervals of CLK_Intrenal are controlled to avoid the risk of circuit logic caused by too short intervals. CO generates its own delay signal through the first AND gate, the first OR gate, the first delay, and the first inverter, and is output after logical operation of the first AND gate. The above delay has two functions: one is to generate a self-built clock during initialization, and the other is to prevent clock lock phenomenon in special situations during cell programming.

[0081] Further, the clock generation unit 30 further comprises a delay module 33; the delay module 33 comprises a second delay, which is used to delay the initial excitation clock CLK_Internal to generate an excitation clock CLK_dff as the clock of the D flip-flop chain.

[0082] Further, the clock generation unit 30 further comprises a second enable switch F2; the second enable switch F2 is connected between the output end of the second delay and the programming control unit; after the programming unit 20 starts programming, the second enable switch is in a closed state; before the programming unit 20 programs, the second enable switch is in an open state. The second enable switch F2 is controlled by an external link signal, such as the Prog_en signal shown in the figure. Figure 6

[0083] Figure 10 Another structure schematic diagram of a programming device provided in the present application is shown. The programming device further comprises an error reporting unit 40; the error reporting unit 40 is used to control the excitation clock CLK_dff output by the clock generation unit 30 to generate an excitation signal if the currently detected valid storage unit has not completed programming after a preset time length. When the valid storage unit fails to program, the excitation clock output by the clock generation unit 30 will be a continuous low level. In order to continue to complete the programming of the subsequent valid storage unit, an up edge is generated in the excitation clock output by the error reporting unit forced generation module to skip the faulty unit and continue the subsequent programming. Further, the error reporting unit 40 is further used to output an error reporting signal err to provide an external circuit as a decision mark of unit abnormality.

[0084] ​Figure 11 Another circuit diagram of the programming control unit is provided in the present application. The error reporting unit 40 comprises: a second inverter, a fifth switch G1, a sixth switch G2, a first capacitor, and a second comparator. The non-inverting input terminal of the second comparator is connected with the first terminal of the first capacitor and one terminal of the sixth switch G2. The first terminal of the first capacitor is connected with the power signal Lin through the fifth switch G1. The inverting input terminal of the second comparator is connected with the second reference voltage Vref2. The second terminal of the first capacitor is grounded. The other terminal of the sixth switch G2 is grounded. The input terminal of the second inverter is connected with the initial excitation clock CLK_Internal. The output terminal of the second inverter is connected with the control terminal of the fifth switch G1. The control terminal of the sixth switch G2 is connected with the initial excitation clock CLK_Internal. The second comparator is connected with the second input terminal of the first OR gate, for outputting the first control signal Turn-off. Specifically, the first control signal Turn-off is used to control the initial excitation clock CLK_Internal output by the generating module 32 to generate a rising edge, and further control the excitation clock CLK_dff output by the delay module 33 to generate a rising edge.

[0085] Specifically, when the programming is abnormal and cannot be completed for a long time, the initial excitation clock CLK_Internal is low for a long time. Correspondingly, the fifth switch G1 is turned on, and the sixth switch G2 is turned off. The Lin signal continuously charges the first capacitor, so that the voltage at the non-inverting input terminal of the second comparator continuously rises. When the voltage is greater than the second reference voltage Vref2, the first control signal Turn-off output by the second comparator is set to 1, and the first OR gate outputs 1, i.e., the initial excitation clock CLK_Internal generates a rising edge, skips the fault unit, and continues the subsequent programming. At the same time, the first control signal Turn-off can be used as the error signal err, as the judgment flag of the unit abnormality. Figure 11

[0086] After the array is in the programming state, based on the internal clock CLK_internal, up to N units can be programmed simultaneously in each clock cycle, but only the first unit in sequence is judged whether the programming is completed. The specific operation mode is that the programming circuit in the array collects the storage data of the D flip-flop and the page latch in each column. Only the column with all logic 1 is configured to the programming electrical condition, and the unit in the column can be in the programming state. After the judgment is completed, the CLK_internal automatically generates the next rising edge to perform the judgment of the next unit.

[0087] Figure 12 The signal timing diagram of the programming control unit is provided in the present application. Wherein, S i ​This represents the state of the i-th fourth switch. In one example, the fourth switch S... i It turns on in response to a high level and turns off in response to a low level. (Combined) Figure 12 In the example, the initial excitation clock CLK_internal is delayed, and the output excitation clock CLK_dff is then generated. During one cycle of the excitation clock CLK_dff, three scenarios may occur.

[0088] Case 1: The currently detected storage unit is the (i+1)th storage unit, and the (i+1)th storage unit completes its programming within this cycle. For example... Figure 12 In case 1 shown, at the start of the CLK_dff cycle, it is assumed that the (i+1)th cell has not yet been programmed. In practical applications, the delay portion inside the generation module produces the falling edge of CLK_internal. After another delay, CLK_internal provides the clock CLK_dff for the D flip-flop chain. The two delays within the circuit are designed so that the rising edge of CLK_dff is slightly delayed from the falling edge of CLK_internal. This is done to prevent circuit logic risks caused by the short interval between the rising and falling edges of CLK_internal due to the falling edge of CO when the cell is not fully programmed.

[0089] When CLK_dff generates its first rising edge, the switch S of the (i+1)th unit... i+1 The program is opened, making the (i+1)th cell the cell to be compared. When CLK_dff generates a rising edge, the (i+1)th cell has not been programmed, so CO will jump to logic 0 until the cell is programmed. Then CO jumps back to logic 1, causing CLK_internal to generate a rising edge again, ending the current programming cycle and starting the programming cycle for the next cell.

[0090] Case 2: The currently detected storage unit is the (i+1)th storage unit, and the (i+2)th storage unit was programmed before the cycle. For example... Figure 12 In case 2 shown, when CLK_dff generates a second rising edge, the switch S of the (i+2)th unit... i+2 Enable the (i+2)th cell to be compared. In practical applications, for any cell in the array, several cycles before determining whether it has completed programming, it is already in the programming state. Therefore, there is a certain probability that the cell has already completed programming when it is detected. Accordingly, CO will be at logic 1 during detection. Therefore, CLK_internal is set to generate a rising edge again after two delays to generate the next rising edge of CLK_dff, ending the cycle.

[0091] Case 3: the current detected memory cell is the (i+3)th memory cell, the (i+3)th memory cell is in abnormal condition and cannot complete programming, then the programming is forcibly ended by the error reporting unit 40. As shown in case 3, when the CLK_dff generates a third rising edge, the switch S of the (i+3)th cell is opened, and the (i+3)th cell becomes the cell to be compared. Figure 12 i+3 i+3

[0092] If the (i+3)th memory cell is abnormal and cannot complete programming, the CO will output a low level, and the CLK_internal will be in logic 0 for a long time. In this case, the fifth switch G1 in the error reporting unit 40 is turned on under the control of the inverse signal of CLK_internal, and the sixth switch G2 is turned off under the control of CLK_internal. The first end of the first capacitor is connected to the power signal to start charging, and the voltage value of the non-inverting input of the second comparator rises accordingly. When it exceeds Vref2, the Turn-off output by the second comparator jumps to logic 1, and the CLK_internal generates a rising edge to end this cycle.

[0093] After the CLK_internal generates a rising edge, the fifth switch G1 in the error reporting unit 40 is turned off under the control of the inverse signal of CLK_internal, and the sixth switch is turned on under the control of CLK_internal. The first end of the first capacitor is grounded, and then it will be discharged quickly, so that the Turn-off becomes logic 0 again, waiting for the next abnormality judgment. The Turn-off signal can also be output as an error signal err to provide to the external circuit as a judgment mark of cell abnormality.

[0094] The above three cases cover any possible situation of the cell, so the entire circuit structure will progress in this way until the last cell completes programming. Therefore, this structure can realize the automatic pipeline progressive programming method.

[0095] ​The programming device provided by the application comprises a programming control unit 10 and a programming unit 20; the programming control unit 10 is used for, in response to an excitation signal of an excitation clock, sequentially taking each valid storage unit in a row to be programmed as a first unit, and performing processing until all the valid storage units are programmed: according to a predetermined number, selecting the first unit and the valid storage units after the first unit, and configuring the selected valid storage units as a programming state, and configuring the valid storage units after the first unit and not selected as a non-programming state; and the programming unit 20 is used for, according to a predetermined period, performing programming on the valid storage units currently configured as the programming state until all the valid storage units are programmed. The application can realize that the same number of partial units are selected in any time period, and the traversal of the whole row of valid storage units can be realized by sequentially moving in a row, replacing the programmed units with the unprogrammed units.

[0096] Embodiment two

[0097] The application provides a programming method applied to the foregoing programming device, and the programming device comprises a programming control unit 10 and a programming unit 20; the method comprises the following steps: the programming control unit 10, in response to an excitation signal of an excitation clock, sequentially takes each valid storage unit in a row to be programmed as a first unit, and performs the following processing until all the valid storage units are programmed: according to a predetermined number, selecting the first unit and the valid storage units after the first unit, and configuring the selected valid storage units as a programming state, and configuring the valid storage units after the first unit and not selected as a non-programming state; and the programming unit 20, according to a predetermined period, performs programming on the valid storage units currently configured as the programming state until all the valid storage units are programmed.

[0098] The programming method realizes that the same number of partial units are selected in any time period, effectively controls the programming current, and avoids causing damage of a chip due to heating; the application realizes the traversal of the valid storage units by sequentially moving in a row in a pipelined manner, replacing the programmed units with the unprogrammed units, without the need of setting an external control device, and the resource consumption is reduced.

[0099] In one example, the programming method further comprises the following steps: the programming control unit 10 configures each flip-flop in the programming unit chain as the second logic; and the programming control unit 10, based on the input first logic, configures the first predetermined number of flip-flops in the valid programming unit chain as the first logic in response to a predetermined number of external excitation signals.

[0100] The flip-flops with the first logic stored in the page latch corresponding to each flip-flop in the programming unit chain constitute the valid programming unit chain. In the embodiment one of the application, the implementation mode of establishing the valid programming unit chain is introduced in detail in combination with the circuit structure, which is not described herein.

[0101] Before the programming unit 20 is programmed, the valid programming unit chain is initialized by the programming control unit 10 to select N valid memory units and configure them to the programming state. During the initialization stage, part of data is written into the valid programming unit chain by the outside, and the programming control unit 10 is configured to the first logic. Figure 6 The input signal includes a link input signal Chain_in and a link clock signal CLK_O, and the main function is to determine the number N of memory units in the programming state at the same time.

[0102] The first step of initialization: write all 1 data to the page latch, so that all D flip-flops are in the link.

[0103] The second step of initialization: all D flip-flops are written to the state of saving logic 0 by external link clock control. The specific process is: the Chain_In signal is always set to logic 0, and the periodic CLK_O clock signal is input uninterruptedly until all D flip-flops are written to the state of saving logic 0.

[0104] The third step of initialization: the data to be written is stored in the page latch, so that only the D flip-flop corresponding to the unit to be programmed is in the link, and the valid programming unit chain is established.

[0105] The fourth step of initialization: the Chain_In signal input end is set to logic 1, and the CLK_O signal provides N clock cycles, N is an arbitrary integer and can be customized. After N cycles are completed, the Chain_In signal input end is set to logic 0. The purpose of this operation is to make the first N D flip-flops in the valid programming unit chain be logic 1, and other D flip-flops be logic 0.

[0106] In an example, the programming control unit 10, in response to an excitation signal of an excitation clock, sequentially takes each valid memory unit in the to-be-programmed row as a first unit, and performs processing including:

[0107] The programming control unit 10, based on the input second logic, in response to an excitation signal of an excitation clock, configures the first flip-flop and the next flip-flop of the last flip-flop in the valid programming unit chain, which are currently in the first logic, to the second logic and the first logic respectively.

[0108] Specifically, refer to Figure 11 and Figure 12When the first flip-flop is programmed, the CO outputs a rising edge, so that the CLK_internal generates a rising edge again, and the CLK_dff generates a rising edge; the first flip-flop receives the rising edge excitation signal in the CLK_dff, and outputs a logic 0 based on the input logic 0. The next flip-flop of the last flip-flop receives the rising edge excitation signal in the CLK_dff, and outputs a logic 1 based on the logic 1 output by the last flip-flop, that is, the next flip-flop of the last flip-flop and the corresponding page memory are both logic 1, which meets the electrical condition configured to be programmed. That is, the effective memory cells of the N programming states are automatically moved by one position.

[0109] The programming method provided in the application can select the same number of partial cells at any time period, sequentially move in a row, replace the programmed cells with unprogrammed cells, and realize traversal of the entire row of to-be-programmed cells.

[0110] The application further provides a hardware code product, comprising hardware code, which is executed by a processor to implement the method provided in the above embodiments.

[0111] The application further provides a readable storage medium, which stores hardware code, and the hardware code is executed to implement the method provided in the above embodiments.

[0112] The application further provides an electronic device, comprising a processor and a memory connected with the processor in communication; the memory stores hardware code; and the processor executes the hardware code stored in the memory to implement the method provided in the above embodiments.

[0113] The application further provides a novel memory, comprising a plurality of resistance-type memory cells and a programming device as provided in the above embodiments; the programming device is used to program the resistance-type memory cells. The novel memory can be a resistive random access memory (RRAM), a phase change random access memory (PCRAM) or a magnetic random access memory (MRAM).

[0114] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the application be limited only by the scope of the claims, including any appropriate amendments thereof, and that there be accounted to be patentably distinct, inter alia: (i) any variation in the general principles or details of the application described herein; and (ii) any variation in the application resulting from any of the different ways in which the principles and details of the application can be implemented. The specification and examples are to be considered exemplary only, with the true scope and spirit of the application indicated by the following claims.

[0115] It should be understood that the application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is limited only by the claims that follow, including any appropriate amendments thereof.

Claims

1. A programming device, characterized by The device comprises: a programming control unit and a programming unit; the programming control unit is configured to, in response to an excitation signal of an excitation clock, sequentially take each valid storage unit in a to-be-programmed row as a first unit, and perform processing until all the valid storage units are programmed: according to a predetermined number, select the first unit and the valid storage units after the first unit, and configure the selected valid storage units as a programming state; and configure the valid storage units after the first unit and not selected as a non-programming state; the programming unit is configured to perform programming on the valid storage units currently configured as the programming state according to a predetermined period until all the valid storage units are programmed; the programming control unit comprises a programming unit chain composed of a plurality of flip-flops connected in series; wherein the plurality of flip-flops correspond to page latches corresponding to each storage unit in the to-be-programmed row in a one-to-one manner.

2. The apparatus of claim 1, wherein, A clock port of each flip-flop is connected to the excitation clock through a first switch, an output end of each flip-flop is connected to an input end of a next flip-flop through a second switch, and an input end of each flip-flop is connected to an input end of a next flip-flop through a third switch; the page latches corresponding to each storage unit are configured to control the switch states of the first switch, the second switch, and the third switch of the corresponding flip-flop based on the storage data of the page latches, so as to establish an effective programming unit chain; wherein the storage units corresponding to the flip-flops in the effective programming unit chain are the valid storage units; wherein the flip-flops corresponding to the valid storage units configured as the programming state are configured as a first logic, and the flip-flops corresponding to the valid storage units configured as the non-programming state are configured as a second logic.

3. The apparatus of claim 2, wherein, The programming control unit further comprises a plurality of inverters; the plurality of inverters correspond to the plurality of flip-flops in a one-to-one manner, an input end of the inverter is connected to the corresponding page latch, and an output end of the inverter is connected to a control end of the third switch of the corresponding flip-flop.

4. The apparatus of claim 1, wherein, The device further comprises a clock generation unit; the clock generation unit is configured to provide the excitation clock to the programming control unit.

5. The apparatus of claim 4, wherein, The clock generation unit comprises a detection module and a generation module; the detection module is configured to sequentially detect whether a first valid storage unit currently configured as the programming state is programmed, and output a detection result; the generation module is configured to control the excitation clock to generate an excitation signal if the detection result indicates that the programming is completed, and otherwise, control the excitation clock not to generate the excitation signal.

6. The apparatus of claim 5, wherein, The detection module comprises a plurality of fourth switches and a first comparator; the plurality of fourth switches correspond to the storage units in the to-be-programmed row in a one-to-one manner; a first end of the fourth switch is connected to the corresponding storage unit, and a second end of the fourth switch is connected to a non-inverting input end of the first comparator; and an inverting input end of the first comparator is connected to a first reference voltage. The fourth switch is used for selecting the valid storage unit to be detected by the detection module currently, and a state of the fourth switch depends on input data and output data of the corresponding flip-flop; and output data of the first comparator represents whether the valid storage unit currently selected is programmed.

7. The apparatus of claim 6, wherein, The detection module further comprises a first enabling switch. The first enabling switch is arranged between the fourth switch and the first comparator. The first enabling switch is in a closed state after the programming unit starts programming, and is in an open state before the programming unit programs.

8. The apparatus of claim 5, wherein, The generation module comprises a first AND gate, a first OR gate, a first delay unit and a first inverter. A first input end of the first AND gate is connected with an output end of the detection module to receive the detection result output by the detection module. An output end of the first AND gate is connected with a first input end of the first OR gate; an output end of the first OR gate is connected with an input end of the first delay unit; an output end of the first delay unit is connected with an input end of the first inverter; and an output end of the first inverter is connected with a second input end of the first AND gate. The second input end of the first OR gate inputs a first control signal; and the output end of the first OR gate outputs an initial excitation clock according to the first control signal and an output signal of the output end of the first AND gate.

9. The apparatus of claim 8, wherein, The clock generation unit further comprises a delay module. The delay module comprises a second delay unit, which is used for performing delay processing on the initial excitation clock to generate the excitation clock.

10. The apparatus of claim 9, wherein, The clock generation unit further comprises a second enabling switch, which is connected between an output end of the second delay unit and the programming control unit. The second enabling switch is in a closed state after the programming unit starts programming, and is in an open state before the programming unit programs.

11. The apparatus of claim 9, wherein, The device further comprises an error reporting unit. The error reporting unit is configured to control the excitation clock output by the clock generation unit to generate the excitation signal if the valid storage unit currently detected has not been programmed for a preset time length.

12. The apparatus of claim 11, wherein, The error reporting unit comprises a second inverter, a fifth switch, a sixth switch, a first capacitor and a second comparator. A same-phase input end of the second comparator is connected with a first end of the first capacitor and one end of the sixth switch; the first end of the first capacitor is connected with a power supply signal through the fifth switch; an opposite-phase input end of the second comparator is connected with a second reference voltage; a second end of the first capacitor is grounded; and the other end of the sixth switch is grounded. The second comparator is connected with a second input end of a first OR gate to output the first control signal. An input end of the second inverter is connected with the initial excitation clock; and an output end of the second inverter is connected with a control end of the fifth switch; and a control end of the sixth switch is connected with the initial excitation clock.

13. A programming method characterized by, The application is applied to a programming device, and the programming device comprises a programming control unit and a programming unit. The programming control unit comprises a programming unit chain composed of a plurality of flip-flops connected in series; wherein the plurality of flip-flops correspond to page latches corresponding to each memory cell in the row to be programmed one by one; the method comprises: The programming control unit, in response to an excitation signal of an excitation clock, sequentially takes each valid memory cell in the row to be programmed as a first cell, and performs the following processing until all valid memory cells are programmed: according to a predetermined number, selects the first cell and the valid memory cells after the first cell to be configured in a programming state, and configures the valid memory cells after the first cell which are not selected in a non-programming state; The programming unit performs programming on the valid memory cells currently configured in the programming state according to a predetermined period until all the valid memory cells are programmed.

14. The method of claim 13, wherein, The method further comprises: The programming control unit configures each flip-flop in the programming unit chain as a second logic; The programming control unit, based on the input first logic, configures the first predetermined number of flip-flops in the valid programming unit chain as the first logic in response to the predetermined number of external excitation signals. Wherein the flip-flops storing the first logic in the page latches corresponding to each flip-flop in the programming unit chain constitute the valid programming unit chain.

15. The method of claim 14, wherein, The programming control unit, in response to an excitation signal of an excitation clock, sequentially takes each valid memory cell in the row to be programmed as a first cell, and performs the following processing until all valid memory cells are programmed: according to a predetermined number, selects the first cell and the valid memory cells after the first cell to be configured in a programming state, and configures the valid memory cells after the first cell which are not selected in a non-programming state; The programming control unit, based on the input second logic, configures the first flip-flop and the next flip-flop of the last flip-flop currently in the first logic in the valid programming unit chain as the second logic and the first logic respectively in response to the excitation signal of the excitation clock.

16. A new memory characterized in that, The programming device comprises a plurality of resistance type memory cells, and the programming device is used to program the resistance type memory cells. The programming device comprises a plurality of resistance type memory cells, and the programming device is used to program the resistance type memory cells.

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