Structure and preparation process of indirect plasma large cavity etching

Abstract

The present invention discloses a structure of indirect plasma large cavity etching and its preparation process, wherein the structure includes a cavity wafer, a bonding wafer and a chip; the structure preparation process of the indirect plasma large cavity etching includes a pre-treatment process, a plasma deep silicon etching process and a bonding process. The present invention perfectly solves the technical problems of long single cavity etching time and large roughness of the cavity bottom surface formed by etching during deep silicon etching; the proposed indirect plasma large cavity etching structure and its preparation process are easy to realize automated operation, stable process, suitable for multi-cavity etching with high aspect ratio, and suitable for large-scale batch production application scenarios.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a structure of indirect plasma large cavity etching and a preparation process thereof. Background Art

[0002] Plasma etching technology is an important process for selectively removing materials from the surface of wafers and an indispensable process step in the field of modern integrated circuit manufacturing. The purpose of plasma etching is to efficiently replicate the mask pattern on the coated wafer, and to selectively remove unnecessary materials from the wafer surface through chemical and physical processes to form a microcircuit. With the rapid development of integrated circuit technology, plasma etching technology has gradually become a widely used etching technology in nanoscale integrated circuit manufacturing and micro-nano manufacturing processes. However, the unevenness of the inner surface after plasma etching causes the chip to be placed loosely and the wafer surface to be uneven, affecting the accuracy and number of layers of the subsequent rewiring process. The structure and preparation process of the indirect plasma large cavity etching proposed in the present invention solve the technical problems of long single cavity etching time and large roughness of the cavity bottom surface formed by etching during deep silicon etching; the process is stable, the degree of automated operation is high, and multi-cavity etching with a high aspect ratio can be adapted to the application scenario of large-scale batch production. Summary of the invention

[0003] In view of the deficiencies in the prior art, the object of the present invention is to solve the technical problem of large surface roughness of the wafer cavity after plasma etching in the prior art by providing a structure of indirect plasma large cavity etching and its preparation process.

[0004] To achieve the above object, the present invention provides a process for preparing a structure of indirect plasma large cavity etching, which is characterized by comprising the following steps:

[0005] S1: Pre-treatment process: Coat the non-etched surface of the cleaned cavity wafer with thermal conductive silicone oil, adsorb the cavity wafer on the workbench, and coat the upper surface of the wafer to be etched with photoresist; bake the wafer coated with photoresist using a hot plate; expose and develop the upper surface of the photoresist to form a photoresist mask with a pre-designed pattern;

[0006] S2: Plasma deep silicon etching process: using argon plasma to bombard the outer surface of the photoresist mask; using oxygen plasma to remove the corners of the photoresist mask on the upper surface of the photoresist mask; obtaining the photoresist mask with the final pattern; using the photoresist mask with the final pattern to perform plasma deep silicon etching on the cavity wafer to be etched, after the etching is completed, the back side is thinned to achieve cavity wafer through-hole etching;

[0007] S3: Bonding process: Select the bonding surface and implement the wafer surface polishing process to obtain the designed thickness. At the same time, prepare the unetched bonded wafer for thinning and polishing process to reach the specified thickness, so that the sum of the designed and specified thicknesses is equal to the required design thickness; the cavity wafer and the bonded wafer are bonded to obtain a reconstructed wafer to obtain an indirect large cavity deep silicon plasma etching effect.

[0008] In the second aspect, the present invention provides a structure for indirect plasma large cavity etching, characterized in that: it is prepared by the process as described in claim 1, and its structure includes: a cavity wafer, a bonding wafer and a chip; the cavity wafer is distributed with dozens of through holes formed by the etching process, the bonding wafer and the cavity wafer are formed into a reconstructed wafer through bonding technology, and then the chip is placed through a patch process.

[0009] As a preferred solution, the number of through holes on the cavity wafer is determined by the number of chips.

[0010] Furthermore, the cavity wafer is made of any one of silicon-based, silicon carbide-based or ceramic-based materials.

[0011] Furthermore, the bonding process is direct bonding or adhesive bonding.

[0012] Furthermore, the flatness of the inner surface of the reconstructed wafer is determined by a polishing process.

[0013] Furthermore, the diameter of the large cavity is 20 mm.

[0014] The advantages and beneficial effects of the present invention are as follows:

[0015] The structure of indirect plasma large cavity etching and its preparation process proposed in the present invention solve the technical problems of long single cavity etching time and large roughness of cavity bottom surface formed by etching in deep silicon etching process; at the same time, the roughness of the cavity bottom surface of the reconstructed wafer is determined by the polishing technology of the wafer surface, and the polishing technology can achieve nanometer-level surface roughness, instead of being determined by the etching process that cannot control the roughness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 2. It is a front view of the structure of indirect plasma large cavity etching in an embodiment of the present invention;

[0017] Figure 2 is a top view of the structure of indirect plasma large cavity etching in an embodiment of the present invention;

[0018] Figure 3 is a cross-sectional view of a structure of indirect plasma large cavity etching in an embodiment of the present invention;

[0019] Figure 4It is a process flow chart of the preparation of the indirect plasma large cavity etching structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to better understand the above technical solution, the technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.

[0021] Example 1

[0022] In this embodiment, Figure 1-4 As shown, including:

[0023] A process for preparing a structure for indirect plasma large cavity etching comprises the following steps:

[0024] Step S1: Pretreatment process: ultrasonically clean the wafer to be etched with acetone, ethanol and deionized water in turn, uniformly coat the non-etched surface of the cleaned cavity wafer 101 with a thickness of 3 to 8 microns of thermal conductive silicone oil, adsorb the cavity wafer 101 on the workbench, place the cavity wafer 101 to be etched in a hot nitrogen atmosphere, the atmosphere temperature is 85-105° C., and uniformly coat the upper surface of the cavity wafer 101 to be etched with a photoresist thickness of 2-5 μm; bake the wafer coated with photoresist with a hot plate at a temperature of 105-125° C. The baking time is 5-10 minutes, and then put it into a UV exposure machine, take out the wafer after exposure for 8 seconds, and then put it into a NaOH solution with a concentration of 0.5%. After developing for 40 seconds, after the cavity wafer 101 is cooled to room temperature, a photoresist mask with a pre-designed pattern is formed.

[0025] Step S2: plasma deep silicon etching process: argon plasma is used to bombard the outer surface of the photoresist mask, and the bombardment time is 20-120s; oxygen plasma is used to cut the corners of the photoresist mask on the upper surface of the photoresist mask, and the cutting time is 10-30s; the photoresist mask with the final pattern is obtained; through the photoresist mask with the final pattern, the silicon wafer substrate with the photoresist pattern structure is placed in the etcher, SF6 and C4F8 are used as gas and sidewall protection gas respectively, and the photoresist pattern is transferred to the surface of the silicon wafer substrate by reactive ion etching technology, and finally it is placed in a solution configured with concentrated sulfuric acid and hydrogen peroxide in a ratio of 2:1 to remove the residual photoresist. Then, the polymer on the side wall is cleaned and removed, and the roughness of the obtained through-hole side wall is 50nm. The above processes can all adopt conventional processes, which will not be repeated here. After the etching is completed, the back side is thinned to achieve through-hole etching of the cavity wafer 101. The etched wafer was placed in anhydrous ethanol for ultrasonic cleaning for 5 minutes, and then ultrasonically cleaned in deionized water for another 5 minutes.

[0026] Step S3: Bonding process: Select the bonding surface and implement the wafer surface polishing process to obtain the designed thickness, and prepare the unetched bonded wafer 102 for thinning and polishing to reach the specified thickness, so that the sum of the designed and specified thicknesses is equal to the required thickness of the design. After the bonded wafer 102 is rinsed with deionized water and blown dry with dry nitrogen, the polished surface is wiped with acetone until there is no contaminant visible to the naked eye under strong light. Then the bonded wafer 102 is placed in an ashing machine and evacuated with a vacuum pump. When the vacuum reaches 5-10Pa, oxygen plasma bombardment is used to enhance its surface adhesion. After 10 minutes, the machine is turned off and the base silicon wafer is taken out. Since silicon and silicon cannot be bonded directly, it is necessary to use magnetron sputtering coating technology to deposit a 200nm copper film on each silicon wafer. Then the surface of the copper film is pretreated, and its surface is polished by chemical mechanical polishing CMP. The roughness of the surface after treatment is less than 1nm. After cleaning the copper film, it is placed in a bonding machine. After the pressure drops below 0.1 Pa, the copper-copper bonding is used to seal the two at a heating temperature of 300-500°C and a pressure of <0.1 MPa. The cavity wafer 101 and the bonding wafer 102 are bonded to obtain a reconstructed wafer, and an indirect large cavity deep silicon plasma etching effect is obtained.

[0027] The above process prepares an indirect plasma large cavity etching structure, which includes: a cavity wafer 101, a bonding wafer 102 and a chip 103. The cavity wafer 101 is provided with dozens of through holes formed by the etching process, and the bonding wafer 102 and the cavity wafer 101 are bonded to form a reconstructed wafer, and then the chip is placed by the bonding process.

[0028] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A process for preparing a structure for indirect plasma large cavity etching, characterized in that: The steps include: S1: Pre-treatment process: coating the non-etching surface of the cleaned cavity wafer (101) with thermal conductive silicone oil, allowing the cavity wafer (101) to be adsorbed on a workbench, and coating the upper surface of the wafer to be etched with photoresist; baking the wafer coated with the photoresist using a hot plate; exposing and developing the upper surface of the photoresist to form a photoresist mask of a pre-designed pattern; S2: Plasma deep silicon etching process: Argon plasma is used to bombard the outer surface of the photoresist mask; Using oxygen plasma on the upper surface of the photoresist mask to remove the corners of the photoresist mask; Obtaining a photoresist mask with a final pattern; performing plasma deep silicon etching on a cavity wafer (101) to be etched through the photoresist mask with the final pattern, and after the etching is completed, thinning the back side to achieve through-hole etching of the cavity wafer (101); S3: Bonding process: Select a bonding surface and perform a wafer surface polishing process to obtain a designed thickness, and at the same time prepare an unetched bonded wafer (102) for thinning and polishing to reach a specified thickness, so that the sum of the designed and specified thicknesses is equal to the required thickness of the design; the cavity wafer (101) and the bonded wafer (102) are bonded to obtain a reconstructed wafer, thereby obtaining an indirect large cavity deep silicon plasma etching effect.

2. A structure for indirect plasma large cavity etching, characterized in that: Prepared by the process as claimed in claim 1, the structure comprises: a cavity wafer (101), a bonding wafer (102) and a chip (103); the cavity wafer (101) is provided with dozens of through holes formed by an etching process, the bonding wafer (102) and the cavity wafer (101) are bonded to form a reconstructed wafer, and then the chip is placed by a bonding process; The number of through holes on the cavity wafer (101) is determined by the number of chips; The material of the cavity wafer (101) is any one of silicon-based, silicon carbide-based or ceramic-based; The bonding process is direct bonding or adhesive bonding; The flatness of the inner surface of the reconstructed wafer is determined by the polishing process; The diameter of the large cavity is 20 mm.

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