Semiconductor element with composite bond pad

Abstract

A semiconductor element having a composite bond pad is provided. The semiconductor element includes a first dielectric layer disposed on a semiconductor substrate, a lower metal plug and a barrier layer disposed in the first dielectric layer, an inner silicide portion disposed on the lower metal plug, and an outer silicide portion disposed on the barrier layer. The lower metal plug is surrounded by the barrier layer, and an uppermost top surface of the outer silicide portion is higher than an uppermost top surface of the inner silicide portion.

Description

TECHNICAL FIELD

[0001] The present disclosure claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 015,816, filed September 9, 2020, the contents of which are incorporated herein in their entirety.

[0002] The present disclosure relates to a semiconductor device. In particular, the present disclosure relates to a semiconductor device having a composite bonding pad. BACKGROUND

[0003] Semiconductor devices are integral to many modern applications. As electronic technology advances, semiconductor devices become smaller in size while providing better functionality and including larger numbers of integrated circuits. Due to the miniaturization of semiconductor devices, different forms and sizes of semiconductor devices that implement different functions are integrated and packaged in a single module. Furthermore, many fabrication steps are performed on the integration of semiconductor devices of various forms.

[0004] However, the fabrication and integration of semiconductor devices involve many complex steps and operations. The increased complexity of fabrication and integration of semiconductor devices can result in defects such as misalignment in interconnect structures. Therefore, there is a need to continuously improve the structure and process of semiconductor devices.

[0005] The above description of background art is provided merely for purposes of background information and does not constitute an admission, by express or implied reference, that the background art is prior art to the present disclosure, that any publication or patent or publication referred to in the above description should be considered pertinent prior art or that this description was written in language 5 intended to be nothing less than prior art. Any reference to prior art in this description is not, and should not be taken as, an acknowledgment or any form of suggestion that this reference forms part of the prior art that is already in existence, is already known or that it forms the general common general knowledge in the art in any jurisdiction. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor device, comprising a first dielectric layer disposed on a semiconductor substrate, a lower metal plug and a barrier layer disposed in the first dielectric layer, the lower metal plug being surrounded by the barrier layer, an inner silicide portion disposed on the lower metal plug, and an outer silicide portion disposed on the barrier layer, an uppermost top surface of the outer silicide portion being higher than an uppermost top surface of the inner silicide portion.

[0007] In one embodiment, the outer silicide portion surrounds and directly contacts the inner silicide portion, and the inner silicide portion and the outer silicide portion comprise different materials. In one embodiment, the inner silicide portion directly contacts a lower metal plug top surface of the lower metal plug, the outer silicide portion directly contacts a barrier layer top surface of the barrier layer, and the lower metal plug top surface and the barrier layer top surface are substantially coplanar. In one embodiment, the lower metal plug top surface and the barrier layer top surface are higher than a first dielectric layer top surface of the first dielectric layer.

[0008] In one embodiment, the barrier layer has an upper sidewall protruding from the first dielectric layer top surface, and the outer silicide portion directly contacts the upper sidewall of the barrier layer and the first dielectric layer top surface. In one embodiment, the semiconductor device further comprises a second dielectric layer disposed on the first dielectric layer, and an upper metal plug disposed in the second dielectric layer and on the lower metal plug, wherein the upper metal plug directly contacts the inner silicide portion and the outer silicide portion. In one embodiment, a sidewall of the first upper metal plug is partially covered by the outer silicide portion.

[0009] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate. The semiconductor device further includes a first lower metal plug and a barrier layer through the first dielectric layer and in a cell region. The lower metal plug is separated from the first dielectric layer by the barrier layer. The semiconductor device further includes a second lower metal plug and a dielectric pillar through the first dielectric layer and in a peripheral circuit region. The dielectric pillar is separated from the first dielectric layer by the second lower metal plug. In addition, the semiconductor device includes an inner silicide portion and an outer silicide portion disposed on the first dielectric layer and in the cell region. The inner silicide portion directly contacts the first lower metal plug, the outer silicide portion directly contacts the barrier layer, and an outer silicide portion top surface of the outer silicide portion is higher than an inner silicide portion top surface of the inner silicide portion.

[0010] In one embodiment, a material of the barrier layer comprises a titanium material, and a material of the outer silicide portion comprises titanium silicide. In one embodiment, the first lower metal plug and the barrier layer protrude from a top surface of the first dielectric layer, and an upper sidewall of the barrier layer is covered by the outer silicide portion.

[0011] In one embodiment, the semiconductor element further includes a first upper metal plug disposed on the inner silicide portion and the outer silicide portion, wherein the inner silicide portion top surface directly contacts a first upper metal plug bottom surface of the first upper metal plug, and the outer silicide portion top surface directly contacts a sidewall of the first upper metal plug. In addition, the semiconductor element includes a second upper metal plug disposed on the second lower metal plug and the dielectric pillar. In one embodiment, the dielectric pillar is spaced apart from the semiconductor substrate by the second lower metal plug. In one embodiment, the dielectric pillar directly contacts the semiconductor substrate.

[0012] In the present disclosure, various embodiments of a semiconductor element have been provided. In some embodiments, the semiconductor element includes a lower metal plug and a barrier layer disposed on the semiconductor substrate, wherein the lower metal plug is surrounded by the barrier layer. The semiconductor element further includes an inner silicide portion disposed on the lower metal plug and an outer silicide portion disposed on the barrier layer. The inner silicide portion and the outer silicide portion form a composite bond pad to increase the bonding area of an upper metal plug during bonding. As a result, the contact resistance can be reduced, and the misalignment problem between the lower metal plug and the upper metal plug can be prevented and reduced. Therefore, the overall element performance can be improved, and the yield of the semiconductor element can be improved.

[0013] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter that form the subject of the claims of the present disclosure. Those skilled in the art will appreciate the BRIEF DESCRIPTION OF DRAWINGS

[0014] The disclosure will be more fully understood with reference to the detailed description and drawings in which:

[0015] Figure 1 A cross-sectional view of a semiconductor element illustrating some embodiments of the present disclosure.

[0016] Figure 2 A cross-sectional view of a modified semiconductor element illustrating some embodiments of the present disclosure.

[0017] Figure 3 A flow diagram of forming a semiconductor element illustrating some embodiments of the present disclosure.

[0018] Figure 4 A cross-sectional schematic view illustrating an intermediate stage of partially removing a first dielectric layer to form an opening in a cell region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0019] Figure 5 A cross-sectional schematic view illustrating an intermediate stage of forming a barrier material and a metal material in the opening of the cell region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0020] Figure 6 A cross-sectional schematic view illustrating an intermediate stage of forming the barrier layer and the lower metal plug in the opening of the cell region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0021] Figure 7 A cross-sectional schematic view illustrating an intermediate stage of partially removing the first dielectric layer during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0022] Figure 8 A cross-sectional schematic view illustrating an intermediate stage of depositing a silicon layer during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0023] Figure 9 A cross-sectional schematic view illustrating an intermediate stage of forming an inner silicide portion and an outer silicide portion during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0024] Figure 10 A cross-sectional schematic view illustrating an intermediate stage of partially removing the first dielectric layer to form an opening in a peripheral circuit region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0025] Figure 11 A cross-sectional schematic view illustrating an intermediate stage of forming a metal material lining the opening of the peripheral circuit region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0026] Figure 12 A cross-sectional schematic view illustrating an intermediate stage of filling the opening of the peripheral circuit region with a dielectric material during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0027] Figure 13 A cross-sectional schematic view illustrating an intermediate stage of forming a lower metal plug and a dielectric pillar in the opening of the peripheral circuit region during formation of the semiconductor element, according to some embodiments of the present disclosure.

[0028] Figure 14 A top view schematic view illustrating an intermediate stage of forming a lower metal plug and a dielectric pillar in the opening of the peripheral circuit region during formation of the semiconductor element, according to some embodiments of the present disclosure.Figure 13 FIG. 1 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure. Figure 14 FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 along the section line I-I’.

[0029] Figure 15 FIG. 3 is a cross-sectional view of an intermediate stage of forming an opening on the lower metal plug of the unit region during formation of the semiconductor device in accordance with some embodiments of the present disclosure.

[0030] Figure 16 FIG. 4 is a cross-sectional view of an intermediate stage of forming an upper metal plug on the lower metal plug of the unit region during formation of the semiconductor device in accordance with some embodiments of the present disclosure.

[0031] Figure 17 FIG. 5 is a cross-sectional view of an intermediate stage of forming an opening on the lower metal plug of the peripheral circuit region during formation of the semiconductor device in accordance with some embodiments of the present disclosure.

[0032] Figure 18 FIG. 6 is a cross-sectional view of an intermediate stage of partially removing a metal material in the opening of the peripheral circuit region during formation of a modified semiconductor device in accordance with some embodiments of the present disclosure.

[0033] Figure 19 FIG. 7 is a cross-sectional view of an intermediate stage of filling the opening of the peripheral circuit region with a dielectric material during formation of the modified semiconductor device in accordance with some embodiments of the present disclosure.

[0034] Figure 20 FIG. 8 is a cross-sectional view of an intermediate stage of forming a lower metal plug and a dielectric pillar in the opening of the peripheral circuit region during formation of the modified semiconductor device in accordance with some embodiments of the present disclosure.

[0035] Figure 21 FIG. 9 is a partial schematic view of an exemplary integrated circuit including a memory cell array in accordance with some embodiments of the present disclosure.

[0036] REFERENCE NUMERALS:

[0037] 10: fabrication method

[0038] 30: memory cell

[0039] 31: field effect transistor (FET)

[0040] 33: capacitor

[0041] 35: drain

[0042] 37: source

[0043] 39: gate

[0044] 100: semiconductor device

[0045] 101: semiconductor substrate

[0046] 101T: top surface

[0047] 103: first dielectric layer

[0048] 103T1: top surface

[0049] 103T2: top surface

[0050] 163S: sidewall

[0051] 105: patterned mask

[0052] 113: barrier material

[0053] 115: metal material

[0054] 117: barrier layer

[0055] 117S: upper sidewall

[0056] 117T: top surface

[0057] 119: lower metal plug

[0058] 119T: top surface

[0059] 119T: top surface

[0060] 121: silicon layer

[0061] 123: outer silicide portion

[0062] 123T: top surface

[0063] 125: inner silicide portion

[0064] 125T: top surface

[0065] 133: patterned mask

[0066] 140: opening

[0067] 143: metal material

[0068] 145: dielectric material

[0069] 147: lower metal plug

[0070] 147T: top surface

[0071] 149: dielectric pillar

[0072] 149T: top surface

[0073] 151: second dielectric layer

[0074] 153: patterned mask

[0075] 160: opening

[0076] 163: upper metal plug

[0077] 163S: sidewall

[0078] 165: patterned mask

[0079] 170: opening

[0080] 173: upper metal plug

[0081] 200: modified semiconductor element

[0082] 243: metal gap sub

[0083] 245: dielectric material

[0084] 247: lower metal plug

[0085] 247T: top surface

[0086] 249: dielectric pillar

[0087] 249T: top surface

[0088] 1000: memory element

[0089] A: cell region

[0090] B: peripheral circuit region

[0091] BL: bit line

[0092] S11: step

[0093] S13: step

[0094] S15: step

[0095] S17: step

[0096] S19: step

[0097] S21: step

[0098] S23: step

[0099] WL: word line DETAILED DESCRIPTION

[0100] The following description of the present disclosure accompanied by the drawings incorporated therein and forming a part of the specification, illustrate embodiments of the present disclosure, however, the present disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment.

[0101] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0102] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0103] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired nature of the apparatus. Furthermore, the description below of a first feature being formed "on" or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0104] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0105] Figure 1 A cross-sectional schematic diagram of a semiconductor device 100 illustrating some embodiments of this disclosure is shown. For example... Figure 1As shown, the semiconductor element 100 includes a semiconductor substrate 101, a first dielectric layer 103 disposed on the semiconductor element 100, a patterned mask 133 disposed on the first dielectric layer 103, and a second dielectric layer 151 disposed on the patterned mask 133.

[0106] In some embodiments, an isolation structure (not shown) is disposed in the semiconductor substrate 101, and active regions (not shown) are defined by the isolation structure. Each active region can include a source / drain region. In some embodiments, the semiconductor element 100 includes a cell region A and a peripheral circuit region B adjacent to the cell region A. The cell region A is also referred to herein as a pattern-dense region, and the peripheral circuit region B is also referred to as a pattern-sparse region.

[0107] In the cell region A, the semiconductor element 100 includes a barrier layer 117 and a lower metal plug 119 (also referred to as a first lower metal plug) disposed in the first dielectric layer 103. In some embodiments, the barrier layer 117 and the lower metal plug 119 protrude through the first dielectric layer 103. In some embodiments, the barrier layer 117 and the lower metal plug 119 are protruded from the first dielectric layer 103. Specifically, an upper portion of the barrier layer 117 and an upper portion of the lower metal plug 119 are disposed in the patterned mask 133. Further, in some embodiments, the barrier layer 117 encloses the lower metal plug 119. Specifically, the lower metal plug 119 is separated from the first dielectric layer 103 by the barrier layer 117.

[0108] The semiconductor element 100 also includes an inner silicide portion 125 and an outer silicide portion 123 disposed in the patterned mask 133. In some embodiments, the inner silicide portion 125 is disposed on the lower metal plug 119, and the outer silicide portion 123 is disposed on the barrier layer 117. It should be understood that, according to some embodiments, a top surface 123T of the outer silicide portion 123 is higher than a top surface 125T of the inner silicide portion 125. In some embodiments, the top surface 123T of the outer silicide portion 123 is a top surface of the outer silicide portion 123, and the top surface 125T of the inner silicide portion 125 is a top surface of the inner silicide portion 125.

[0109] In the cell region A, the semiconductor element 100 also includes an upper metal plug 163 (also referred to as a first upper metal plug) disposed in the second dielectric layer 151. In some embodiments, the upper metal plug 163 directly contacts the inner silicide portion 125 and the outer silicide portion 123. It should be understood that, according to some embodiments, a sidewall 163S of the upper metal plug 163 is partially covered by the outer silicide portion 123. In some embodiments, the upper metal plug 163 is electrically connected to the lower metal plug 119 through the inner silicide portion 125 and the outer silicide portion 123.

[0110] In the peripheral circuit region B, the semiconductor element 100 includes a lower metal plug 147 (also referred to as a second lower metal plug) disposed in the first dielectric layer 103 and the patterned mask 133, and a dielectric pillar 149. In some embodiments, the dielectric pillar 149 is surrounded by the lower metal plug 147. Specifically, the dielectric pillar 149 is separated from the first dielectric layer 103 by the lower metal plug 147.

[0111] The semiconductor element 100 also includes an upper metal plug 173 (also referred to as a second upper metal plug) disposed in the peripheral circuit region B. In some embodiments, the upper metal plug 173 is disposed in the second dielectric layer 151. In some embodiments, the upper metal plug 173 directly contacts the lower metal plug 147 and the dielectric pillar 149. Further, according to some embodiments, the upper metal plug 173 is electrically connected to the lower metal plug 147.

[0112] The inner silicide portion 125 and the outer silicide portion 123 can constitute a composite bond pad in the cell region A of the semiconductor element 100. In some embodiments, the semiconductor element 100 is a dynamic random access memory (DRAM), and the composite bond pad serves as a bond pad for a bit line (BL) or a bond pad for a storage node of the DRAM. Since the composite bond pad increases the bonding area of the upper metal plug 163, the contact resistance can be reduced, and the misalignment problem between the lower metal plug 119 and the upper metal plug 163 can be prevented and reduced. Thus, the overall element performance can be improved, and the yield of the semiconductor element can be improved.

[0113] Figure 2 A cross-sectional schematic view of a modified semiconductor element 200, which is an alternative embodiment of the semiconductor element 100, is illustrated to exemplify some embodiments of the present disclosure. For consistency and clarity, similar components appearing in Figure 1 and Figure 2 will be labeled with the same reference numerals.

[0114] Similar to the semiconductor element 100, the modified semiconductor element 200 includes a cell region A and a peripheral circuit region B. The difference is that the dielectric pillar 249 in the peripheral circuit region B of the modified semiconductor element 200 directly contacts the semiconductor substrate 101. In other words, instead of forming a cup-shaped metal structure (e.g., the lower metal plug 147) in the semiconductor element 100, a gap-shaped metal structure (e.g., the lower metal plug 247) is formed in the modified semiconductor element 200. Figure 1

[0115] ​Similar to the semiconductor element 100, the inner silicide portion 125 and the outer silicide portion 123 of the modified semiconductor element 200 can constitute a composite bond pad in the cell region A. In some embodiments, the modified semiconductor element 200 is a dynamic random access memory (DRAM), and the composite bond pad is a bond pad for a bit line (BL) or a bond pad for a storage node of the DRAM.

[0116] Figure 3 A flowchart of a method 10 of fabricating a semiconductor element (including the semiconductor element 100 and the modified semiconductor element 200) according to some embodiments of the present disclosure is illustrated, and the method 10 includes steps S11, S13, S15, S17, S19, S21, and S23. Figure 3 The steps S11 to S23 in the method 10 are described in detail in conjunction with the following figures.

[0117] Figures 4 to 13 and Figures 15 to 17 A cross-sectional view of an intermediate stage of forming the semiconductor element 100 according to some embodiments of the present disclosure is illustrated, and Figure 14 A top view of an intermediate stage of forming the semiconductor element 100 according to some embodiments of the present disclosure is illustrated. As shown in FIG. 1C, the semiconductor substrate 101 is provided. The semiconductor substrate 101 can be, for example, a semiconductor wafer of a silicon wafer. Figure 4

[0118] Additionally or alternatively, the semiconductor substrate 101 can include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material can include, for example and without limitation, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material can include, for example and without limitation, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material can include, for example and without limitation, silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide.

[0119] ​In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which can have a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implantation of oxygen (SIMOX) techniques, wafer bonding, and / or other suitable methods.

[0120] Still referring to Figure 4 , according to some embodiments, a first dielectric layer 103 is formed on the semiconductor substrate 101, and a patterned mask 105 is formed on the first dielectric layer 103. The corresponding steps are shown as step Sll in the fabrication method 10 as shown in Figure 3 In some embodiments, the first dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. In addition, the first dielectric layer 103 can be fabricated using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on process, or other suitable process.

[0121] In some embodiments, the first dielectric layer 103 is etched using the patterned mask 105 as a mask to form openings 110 through the first dielectric layer 103 in the cell region A. In other words, portions of the top surface 101T of the semiconductor substrate 101 in the cell region A are exposed by the openings 110. The openings 110 can be formed using a wet etching process, a dry etching process, or a combination thereof. As described above, isolation structures and source / drain regions can be formed in the semiconductor substrate 101. In this case, one of the source / drain regions can be exposed by the openings 110.

[0122] Next, as Figure 5 illustrated, according to some embodiments, a barrier material 113 is formed in the openings 110, and a metal material 115 is formed on the barrier material 113 and fills the remaining portions of the openings 110. In some embodiments, the barrier material 113 is formed to cover the top surface 101T of the portions of the semiconductor substrate 101 exposed by the openings 110, the sidewalls of the openings 110, and the top surface of the patterned mask 105 (if the patterned mask 105 is removed after the formation of the openings 110, the barrier material 113 can be formed to cover the top surface of the first dielectric layer 103).

[0123] In some embodiments, the barrier material 113 comprises a titanium material, such as titanium (Ti) or titanium nitride (TiN). However, other materials may be used alternatively, such as tantalum (Ta), tantalum nitride (TaN), cobalt tungsten (CoW), or combinations thereof. Furthermore, the barrier material 113 may be formed by a CVD process, a PVD process, an ALD process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or other suitable processes.

[0124] In some embodiments, the metal material 115 comprises tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable metal materials. Furthermore, the metal material 115 can be fabricated using CVD, PVD, ALD, MOCVD, sputtering, electroplating, or other suitable processes. In some embodiments, the barrier material 113 and the metal material 115 comprise different materials.

[0125] Subsequently, as disclosed in this publication Figure 6 In some of the illustrated embodiments, a planarization process is performed on the metal material 115 and the barrier material 113 to create an opening 110 in the cell region A (see [link]). Figure 4 A lower metal plug 119 and a barrier layer 117 are formed in the process. The corresponding steps are shown in the example. Figure 3 Step S13 in the preparation method 10 shown. The planarization process may include a chemical mechanical planarization (CMP) process, which removes excess portions of the blocking material 113 and the metal material 115 on the patterned mask 105 and the first dielectric layer 103.

[0126] In some embodiments, the barrier layer 117 covers the sidewalls and bottom surface of the lower metal plug 119. In some embodiments, the top surface 119T of the lower metal plug 119, the top surface 117T of the barrier layer 117, and the top surface 103T1 of the first dielectric layer 103 are substantially coplanar with each other. In the context of this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0127] Next, as Figure 7 For example, according to some embodiments, the first dielectric layer 103 is partially removed to expose the upper sidewall 117S of the barrier layer 117. The corresponding steps are shown in... Figure 3 Step S15 of the fabrication method 10 shown. In some embodiments, the first dielectric layer 103 is partially removed to form Figure 7The top surface 103T2 of the first dielectric layer 103 is lowered. In some embodiments, the top surface 117T of the barrier layer 117 and the top surface 119T of the lower metal plug 119 are higher than the top surface 103T2 of the first dielectric layer 103.

[0128] In some embodiments, the first dielectric layer 103 is partially removed by an etch-back process. In some embodiments, the first dielectric layer 103 is partially removed by a planarization process, such as a CMP process. In some embodiments, after the first dielectric layer 103 is partially removed, the barrier layer 117 and the lower metal plug 119 protrude from the first dielectric layer 103. In some embodiments, after the first dielectric layer 103 is partially removed, the top surface 117T of the barrier layer 117 and the top surface 119T of the lower metal plug 119 remain substantially coplanar.

[0129] After the first dielectric layer 103 is partially removed, as shown in step S17 of the fabrication method 10, Figure 8 For example, according to some embodiments, the silicon layer 121 is conformally deposited on the first dielectric layer 103, on the barrier layer 117, and on the lower metal plug 119 and in direct contact therewith. The corresponding step is shown in step S17 of the fabrication method 10, Figure 3 In some embodiments, the top surface 103T2 of the first dielectric layer 103, the upper sidewall 117S of the barrier layer 117, and the top surface 119T of the lower metal plug 119 are covered by the silicon layer 121. In some embodiments, the silicon layer 121 is formed by a CVD process, a PVD process, an ALD process, a spin-on process, or other applicable processes.

[0130] After the silicon layer 121 is deposited, as shown in step S19 of the fabrication method 10, Figure 9 For example, according to some embodiments, a self-aligned silicide process is performed to form the inner silicide portion 125 on the lower metal plug 119 and the outer silicide portion 123 on the barrier layer 117. The corresponding step is shown in step S19 of the fabrication method 10. Figure 3

[0131] In the present embodiment, the self-aligned silicide process is performed to grow silicide on any exposed metal surface. In more detail, in the example embodiment, the inner silicide portion 125 and the outer silicide portion 123 are formed after the barrier layer 117 and the lower metal plug 119 are reacted with the silicon layer 121, annealed, and etched to remove unreacted portions. Referring to Figure 8 and Figure 9 According to some embodiments, the inner silicide portion 125 is grown on the top surface 119T of the lower metal plug 119, and the outer silicide portion 123 is grown on the top surface 117T and the upper sidewall 117S of the barrier layer 117. ​

[0132] In addition, the material of the barrier layer 117 and the lower metal plug 119 is selected such that the barrier layer 117 exhibits a greater silicidation rate than the lower metal plug 119. As a result, the outer silicide portion 123 grows faster than the inner silicide portion 125. In some embodiments, after the self-aligned silicide process, the top surface 123T of the outer silicide portion 123 is greater than the top surface 125T of the inner silicide portion 125. In some embodiments, the barrier material 113 comprises a titanium material, and the outer silicide portion 123 comprises a titanium silicide.

[0133] In some embodiments, the inner silicide portion 125 is surrounded by the outer silicide portion 123, and the recess 130 is formed on the inner silicide portion 125 and surrounded by the outer silicide portion 123. In addition, according to some embodiments, the outer silicide portion 123 directly contacts the top surface 103T2 of the first dielectric layer 103. Since the inner silicide portion 125 and the outer silicide portion 123 are formed by a self-aligned silicide (salicide) process, the associated cost can be reduced.

[0134] Next, as shown in FIG. 1C, a patterned mask 133 is formed on the first dielectric layer 103, and the patterned mask 133 covers the inner silicide portion 125 and the outer silicide portion 123. In some embodiments, the first dielectric layer 103 is etched with the patterned mask 133 as a mask to form an opening 140 through the first dielectric layer 103 in the peripheral circuit region B. In other words, a portion of the top surface 101T of the semiconductor substrate 101 in the peripheral circuit region B is exposed by the opening 140. The opening 140 can be formed by a wet etching process, a dry etching process, or a combination thereof. Figure 10 Subsequently, as shown in FIG. 1D, a metal material 143 is formed in the opening 140. In some embodiments, the metal material 143 is formed to cover the portion of the top surface 101T of the semiconductor substrate 101 exposed by the opening 140, the sidewall of the opening 140, and the top surface of the patterned mask 133. In some embodiments, the metal material 143 comprises tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination thereof, or other suitable metal material. In addition, the metal material 143 can be formed by a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, or other suitable process.

[0135] Figure 11 Then, as shown in FIG. 1E, the patterned mask 133 is removed. In some embodiments, the patterned mask 133 is removed by a wet etching process, a dry etching process, or a combination thereof.

[0136] Next, as shown in FIG. 1F, a second dielectric layer 145 is formed on the semiconductor substrate 101. In some embodiments, the second dielectric layer 145 is formed to cover the metal material 143 and the top surface 101T of the semiconductor substrate 101. In some embodiments, the second dielectric layer 145 comprises a dielectric material, such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon oxycarbide nitride (SiOCN), silicon oxycarbide oxide (SiOCO), silicon oxycarbide nitride oxide (SiOCNO), silicon oxycarbide carbonitride (SiOCN), silicon oxycarbide oxynitride (SiOCNO), silicon oxycarbide oxycarbonitride (SiOCN), silicon oxycarbide oxycarbonitride oxide (SiOCNCO), or other suitable dielectric material. In addition, the second dielectric layer 145 can be formed by a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, or other suitable process. Figure 12 ​For example, in accordance with some embodiments, a dielectric material 145 is formed on the metal material 143 and fills the remaining portion of the opening 140. In some embodiments, the dielectric material 145 comprises silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. Furthermore, the fabrication technique of the dielectric material 145 can be a CVD process, a PVD process, an ALD process, a spin-on process, or other suitable process.

[0137] After the dielectric material 145 is formed, as Figure 13 and Figure 14 For example, in accordance with some embodiments, a planarization process is performed on the dielectric material 145 and the metal material 143 to form the lower metal plug 147 and the dielectric pillar 149 in the opening 140 (see Figure 10 ) in the peripheral circuit region. Figure 13 is a cross-sectional view along the cross-sectional line I-I' of Figure 14 . As Figure 14 For example, in accordance with some embodiments, the lower metal plug 147 and the dielectric pillar 149 are ring-shaped as viewed from the top. The corresponding step is shown as step S21 in the fabrication method 10 as shown in Figure 3 .

[0138] In some embodiments, the planarization process is performed until the outer silicide portion 123 in the cell region A is exposed. The planarization process can comprise a CMP process that removes the excess portions of the dielectric material 145, the metal material 143, and the patterned mask 133 on the outer silicide portion 123. In some embodiments, the outer silicide portion 123 can be slightly etched. In this case, the uppermost top surface of the outer silicide portion 123 is still higher than the top surface 125T of the inner silicide portion 125, and portions of the patterned mask 133 remain on the inner silicide portion 125.

[0139] In some embodiments, in the peripheral circuit region B, the lower metal plug 147 covers the sidewalls and the bottom surface of the dielectric pillar 149. That is, the lower metal plug 147 is a cup-shaped metal structure that fills the dielectric pillar 149. In some embodiments, the top surface 147T of the lower metal plug 147 and the top surface 149T of the dielectric pillar 149 are substantially coplanar.

[0140] Next, as Figure 15 For example, in accordance with some embodiments, a second dielectric layer 151 is formed on the remaining portions of the patterned mask 133, and another patterned mask 153 is formed on the second dielectric layer 151. In some embodiments, the second dielectric layer 151 is etched with the patterned mask 153 as a mask to form an opening 160 through the second dielectric layer 151 in the cell region A.

[0141] In some embodiments, a portion of the patterned mask 133 on the inner silicide portion 125 is removed, such that the top surface 125T of the inner silicide portion 125 is exposed by the opening 160. Furthermore, the outer silicide portion 123 may be lightly etched during the etching process that forms the opening 160. The opening 160 may be formed by a wet etching process, a dry etching process, or a combination thereof. After forming the opening 160, the patterned mask 153 may be removed.

[0142] Subsequently, as Figure 16 For example, according to some embodiments, in the opening 160 of unit region A (see...) Figure 15 An upper metal plug 163 is formed in the silicide layer and directly contacts the inner silicide portion 125 and the outer silicide portion 123. In some embodiments, the upper metal plug 163 comprises tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable metallic materials. The formation of the upper metal plug 163 may include a deposition process and a planarization process. The deposition process may be a CVD process, a PVD process, an ALD process, a MOCVD process, a sputtering process, an electroplating process, or other suitable processes. The planarization process may be a CMP process.

[0143] After forming the metal plug 163, as Figure 17 For example, according to some embodiments, a patterned mask 165 is formed on the second dielectric layer 151. In some embodiments, the second dielectric layer 151 is etched with the patterned mask 165 as a mask to form an opening 170 through the second dielectric layer 151 in the peripheral circuit region B. In some embodiments, the top surface 149T of the dielectric pillar 149 and the top surface 147T of the lower metal plug 147 are exposed by the opening 170. The opening 170 may be formed by a wet etching process, a dry etching process, or a combination thereof. After the opening 170 is formed, the patterned mask 165 may be removed.

[0144] Then, please return to the reference. Figure 1 According to some embodiments, the upper metal plug 173 has an opening 170 in the peripheral circuit area B (see...). Figure 17 The upper metal plug 173, which forms the peripheral circuit region B, is formed in the dielectric pillar 149 and directly contacts the lower metal plug 147. Some materials and processes used to form the upper metal plug 173 are similar to or the same as those used to form the upper metal plug 163 of the unit region A; details are not described here. The corresponding steps are shown in... Figure 3 Step S23 in preparation method 10 shown.

[0145] In some other embodiments, the upper metal plug 163 of cell region A and the upper metal plug 173 of peripheral circuit region B are formed simultaneously. After the upper metal plugs 163 and 173 are formed, the semiconductor element 100 is obtained.

[0146] Figures 18 to 20 This illustration shows a cross-sectional schematic diagram of an intermediate stage in the formation of a modified semiconductor device 200, as shown in some embodiments of this disclosure. This is after the formation of the metal material 143 (i.e., following...). Figure 11 (After the steps), such as Figure 18 For example, according to some embodiments, an etching process is performed on the metal material 143 to expose a portion of the top surface 101T of the semiconductor substrate 101. In some embodiments, an anisotropic etching process is performed on the metal material 143 to vertically remove an equal amount of metal material 143 at all locations, leaving metal spacers 243 (i.e., vertical portions of the metal material 143) on the sidewalls of the opening 140. In some embodiments, the etching process is a dry etching process.

[0147] Next, as Figure 19 For example, according to some embodiments, a dielectric material 245 is formed on the patterned mask 133 and the metal spacer wall 243, and the remaining portion of the opening 140 is filled with the dielectric material 245. Some materials and processes used to form the dielectric material 245 are similar to or the same as those used in [other embodiments]. Figure 12 The materials and processes used to form dielectric material 145 are not detailed here.

[0148] After the dielectric material 245 is formed, such as Figure 20 For example, according to some embodiments, a planarization process is performed on the dielectric material 245 and the metal spacer 243 to create an opening 140 in the peripheral circuit region (see...). Figure 18 A lower metal plug 247 and dielectric pillar 249B are formed in the cell region A. In some embodiments, the planarization process is performed until the outer silicide portion 123 of the cell region A is exposed. The planarization process may include a CMP process that removes excess portions of the dielectric material 245, metal material 143, and patterned mask 133 on the outer silicide portion 123. After the planarization process, the lower metal plug 247 is a spacer shape.

[0149] In some embodiments, in the peripheral circuit region B, the lower metal plug 247 covers the sidewall of the dielectric pillar 249, and the bottom surface of the dielectric pillar 249 directly contacts the semiconductor substrate 101. In some embodiments, the top surface 247T of the lower metal plug 247 and the top surface 249T of the dielectric pillar 249 are substantially coplanar.

[0150] Next, please return to Figure 2 ,exist Figure 20An exemplary structure is formed to include the second dielectric layer 151, and the upper metal plugs 163 and 173 formed in the second dielectric layer 151. Some materials and processes used to form the second dielectric layer 151, the upper metal plugs 163 and 173 of the modified semiconductor device 200 are similar to or the same as those used to form the second dielectric layer 151, the upper metal plugs 163 and 173 of the semiconductor device 100, the details of which are not repeated here. After the upper metal plugs 163 and 173 are formed, the modified semiconductor device 200 is obtained.

[0151] Figure 21 An exemplary portion of an integrated circuit (e.g., a memory device 1000) including an array of memory cells 30 according to some embodiments of the present disclosure is shown in a schematic diagram. In some embodiments, the memory device 1000 includes a DRAM. In some embodiments, the memory device 1000 includes a plurality of memory cells 30 arranged in a network pattern and including a plurality of rows and columns. The number of memory cells 30 can vary depending on the requirements of the system and the technology of fabrication.

[0152] In some embodiments, each memory cell 30 includes an access device and a storage device. The access device is configured to provide access control to the storage device. In particular, according to some embodiments, the access device is a field effect transistor (FET) 31 and the storage device is a capacitor 33. In each memory cell 30, the FET 31 includes a drain 35 and a source 37 and a gate 39. The capacitor 33 has one end electrically connected to the source 37 of the FET 31, and the other end electrically connected to ground. In addition, in each memory cell 30, the gate 39 of the FET 31 is electrically connected to a word line WL, and the drain 35 of the FET 31 is electrically connected to a bit line BL.

[0153] The FET 31 is electrically connected to the capacitor 33 at the source 37, and is electrically connected to the bit line BL at the drain 35, as mentioned above. However, during read and write operations, the FET 31 can be electrically connected to the capacitor 33 at the drain, and can be electrically connected to the bit line BL at the source. That is, either terminal of the FET 31 can be the source or the drain, depending on the manner in which voltages are applied to the source, the drain, and the gate of the FET 31.

[0154] The voltage of the gate 39 is controlled by the word line WL, which causes a voltage potential to be generated across the field effect transistor FET 31, such that charge can flow from the drain 35 to the capacitor 33. Thus, the charge stored in the capacitor 33 can be interpreted as a binary value stored in the memory cell 30. For example, a positive charge stored in the capacitor 33 above a threshold voltage can be interpreted as a binary value of "1". If the positive charge in the capacitor 33 is below the threshold voltage, a binary value of "0" is said to be stored in the memory cell 30.

[0155] The bit line BL is configured to read data from the memory cell 30 and to write data to the memory cell 30. The word line WL is configured to enable the FET 31 to access a particular row of memory cells 30. Thus, the memory device 1000 also includes a peripheral circuit region, which can include an address buffer and a column decoder and a row decoder. The column decoder and the row decoder selectively access the memory cells 30 in response to an address signal of the address buffer provided during read, write, and refresh operations. The address signal is typically provided by an external controller, such as a microprocessor, or another type of memory controller.

[0156] Referring back to Figure 1 and Figure 2 The composite bond pad (i.e., the inner silicide portion 125 and the outer silicide portion 123) is formed in the cell region A of the semiconductor device 100 and the semiconductor device 200. The cell region A can be any one of the regions of the memory cell 30 in the memory device 1000, and the peripheral circuit region B can be any one of the regions of the address buffer, the row decoder, or the column decoder in the memory device.

[0157] The present disclosure provides an embodiment of a semiconductor device 100 and a semiconductor device 200. In the cell region A, the lower metal plug 119 and the barrier layer 117 are disposed on the semiconductor substrate 101, and the lower metal plug 119 is surrounded by the barrier layer 117. In addition, the inner silicide portion 125 is disposed on the lower metal plug 119, and the outer silicide portion 123 is disposed on the barrier layer 117. The inner silicide portion 125 and the outer silicide portion 123 form a composite bond pad, which increases the bonding area of the upper metal plug 163 during bonding. Thus, the contact resistance can be reduced, and the misalignment problem between the lower metal plug 119 and the upper metal plug 183 can be prevented and reduced. Thus, the overall device performance can be improved, and the yield of the semiconductor device can be improved. In addition, since the composite bond pad is formed by the self-aligned silicide process, the related cost can be reduced.

[0158] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed on the lower metal plug and an outer silicide portion disposed on the barrier layer. An uppermost top surface of the outer silicide portion is higher than an uppermost top surface of the inner silicide portion.

[0159] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate. The semiconductor device also includes a first lower metal plug and a barrier layer extending through the first dielectric layer and in a cell region. The lower metal plug is separated from the first dielectric layer by the barrier layer. The semiconductor device further includes a second lower metal plug and a dielectric pillar extending through the first dielectric layer and in a peripheral circuit region. The dielectric pillar is separated from the first dielectric layer by the second lower metal plug. In addition, the semiconductor device includes an inner silicide portion disposed on the first dielectric layer and in the cell region and an outer silicide portion. The inner silicide portion directly contacts the first lower metal plug, the outer silicide portion directly contacts the barrier layer, and an outer silicide portion top surface of the outer silicide portion is higher than an inner silicide portion top surface of the inner silicide portion.

[0160] Still another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first dielectric layer on a semiconductor substrate. The method also includes forming a barrier layer and a first lower metal plug extending through the first dielectric layer and disposed in a cell region. The first lower metal plug is surrounded by the barrier layer. The method further includes depositing a silicon layer on the first dielectric layer, the barrier layer, and the first lower metal plug. In addition, the method includes performing a self-aligned silicide (salicide) process after the silicon layer is formed to form an inner silicide portion on the first lower metal plug and an outer silicide portion on the barrier layer. The inner silicide portion is surrounded by the outer silicide portion, and a recess is formed on the inner silicide portion.

[0161] Embodiments of the present disclosure have some advantageous features. By forming a composite bond pad on the lower metal plug, the bonding area for subsequently bonding the upper metal plug is increased. Therefore, the overall device performance can be improved, and the yield of the semiconductor device can be improved. Moreover, since the composite bond pad is formed by the self-aligned silicide process, the associated cost can be reduced.

[0162] While the disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the techniques described above can be performed with different hardware or in different orders, or in other processes or combinations thereof.

[0163] Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized according to the present disclosure. Accordingly, the appended claims are intended to cover all such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A semiconductor device, comprising: a first dielectric layer disposed on a semiconductor substrate; a lower metal plug and a barrier layer disposed in the first dielectric layer, wherein the lower metal plug is surrounded by the barrier layer; an inner silicide portion disposed on the lower metal plug; and an outer silicide portion disposed on the barrier layer, wherein an uppermost top surface of the outer silicide portion is higher than an uppermost top surface of the inner silicide portion, wherein the barrier layer has an upper sidewall protruding from a top surface of the first dielectric layer, and the outer silicide portion directly contacts the upper sidewall of the barrier layer and the top surface of the first dielectric layer.

2. The semiconductor device of claim 1, wherein the outer silicide portion surrounds and directly contacts the inner silicide portion, and the inner silicide portion and the outer silicide portion comprise different materials.

3. The semiconductor device of claim 1, wherein the outer silicide portion directly contacts the inner silicide portion, and the inner silicide portion and the outer silicide portion comprise different materials.

4. The semiconductor device of claim 1, wherein the inner silicide portion directly contacts a lower metal plug top surface of the lower metal plug, the outer silicide portion directly contacts a barrier layer top surface of the barrier layer, and the lower metal plug top surface and the barrier layer top surface are substantially coplanar.

5. The semiconductor device of claim 4, wherein the lower metal plug top surface and the barrier layer top surface are higher than a first dielectric layer top surface of the first dielectric layer.

6. The semiconductor device of claim 1, further comprising: a second dielectric layer disposed on the first dielectric layer; and an upper metal plug disposed in the second dielectric layer and disposed on the lower metal plug.

7. The semiconductor device of claim 6, wherein the upper metal plug directly contacts the inner silicide portion and the outer silicide portion.

8. The semiconductor device of claim 6, wherein a sidewall of the upper metal plug is partially covered by the outer silicide portion.

9. The semiconductor device of claim 1, wherein the barrier layer comprises a titanium material, and the outer silicide portion comprises titanium silicide.

10. A semiconductor device, comprising: a first dielectric layer disposed on a semiconductor substrate; a first lower metal plug and a barrier layer penetrating the first dielectric layer and disposed in a cell region, wherein the first lower metal plug isolates the first dielectric layer by the barrier layer; a second lower metal plug and a dielectric pillar penetrating the first dielectric layer and disposed in a peripheral circuit region, wherein the dielectric pillar isolates the first dielectric layer by the first lower metal plug; and an inner silicide portion and an outer silicide portion disposed on the first dielectric layer and disposed in the cell region, wherein the inner silicide portion directly contacts the first lower metal plug, the outer silicide portion directly contacts the barrier layer, and an outer silicide portion top surface of the outer silicide portion is higher than an inner silicide portion top surface of the inner silicide portion.

11. The semiconductor device of claim 10, wherein the barrier layer comprises a titanium material, and the outer silicide portion comprises titanium silicide. ​ ​ 12. The semiconductor device of claim 10, wherein the first lower metal plug and the barrier layer are protruded from a top surface of the first dielectric layer, and an upper sidewall of the barrier layer is covered by the outer silicide portion.

13. The semiconductor device of claim 10, further comprising: a first upper metal plug disposed on the inner silicide portion and on the outer silicide portion; and a second upper metal plug disposed on the second lower metal plug and on the dielectric pillar.

14. The semiconductor device of claim 13, wherein a top surface of the inner silicide portion is directly contacting a first upper metal plug bottom surface of the first upper metal plug.

15. The semiconductor device of claim 13, wherein a top surface of the outer silicide portion is directly contacting a sidewall of the first upper metal plug.

16. The semiconductor device of claim 13, wherein a sidewall of the first upper metal plug is partially covered by the outer silicide portion.

17. The semiconductor device of claim 10, wherein the dielectric pillar is isolating the semiconductor substrate by the second lower metal plug.

18. The semiconductor device of claim 10, wherein the dielectric pillar is directly contacting the semiconductor substrate. ​

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