Array substrate, manufacturing method thereof and mobile terminal

Abstract

The application provides an array substrate, a manufacturing method thereof and a mobile terminal. The array substrate comprises a substrate and an active layer arranged on the substrate. The active layer comprises a first active part arranged on the substrate and a second active part arranged on the first active part. The proportion of crystal quality in the second active part is greater than or equal to the proportion of crystal quality in the first active part. The application sets the active layer to comprise the first active part and the second active part, and makes the second active part and the first active part at least partially crystallized, so that the unstable movement of carriers can be hindered by semiconductor crystallization, and the device stability of the oxide semiconductor thin film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and its manufacturing method, and a mobile terminal. Background Technology

[0002] Thin-film transistors (TFTs) are classified into different types based on the material of their active layer. TFTs with an active layer made of oxide semiconductors are called oxide semiconductor thin-film transistors (OSTs). Based on the state of the oxide semiconductor, OSTs can be further divided into crystalline oxide semiconductors and amorphous oxide semiconductors. Because amorphous oxide semiconductors offer high film uniformity and high product yield, they are currently the most common active layer material for OSTs.

[0003] However, for amorphous oxide semiconductor thin-film transistors, due to the presence of oxygen vacancy defects, unstable carrier movement is easily caused by external thermal or optical stimuli, resulting in positive or negative shifts in the threshold voltage of the thin-film transistor, which is detrimental to the stability of device operation. Summary of the Invention

[0004] This application provides an array substrate and its fabrication method, as well as a mobile terminal, to improve the technical problem of poor device stability of current amorphous oxide semiconductor thin film transistors.

[0005] To solve the above-mentioned technical problems, the technical solution provided in this application is as follows:

[0006] This application provides an array substrate, comprising:

[0007] Substrate;

[0008] An active layer is disposed on the substrate, the active layer including a first active portion disposed on the substrate and a second active portion disposed on the first active portion;

[0009] Wherein, the proportion of crystal mass in the second active part is greater than or equal to the proportion of crystal mass in the first active part.

[0010] In the array substrate of this application, the crystal size in the second active portion is greater than or equal to the crystal size in the first active portion.

[0011] In the array substrate of this application, the number of crystals in the second active portion is less than or equal to the number of crystals in the first active portion within a unit area parallel to the substrate.

[0012] In the array substrate of this application, the array substrate further includes a gate layer disposed on the side of the active layer near the substrate and a source / drain layer disposed on the side of the active layer away from the substrate;

[0013] The gate layer is insulated from the active layer, and the source / drain layer is connected to the second active portion.

[0014] In the array substrate of this application, the array substrate further includes a gate insulating layer disposed between the gate layer and the first active portion and a crystalline insulating layer disposed on the gate insulating layer;

[0015] The crystalline insulating layer is continuously disposed with the second active part.

[0016] In the array substrate of this application, the crystal size in the second active portion is greater than or equal to the crystal size in the crystalline insulating layer, and the number of crystals in the second active portion is less than or equal to the number of crystals in the crystalline insulating layer per unit area parallel to the substrate.

[0017] This application proposes a method for fabricating an array substrate, comprising:

[0018] An active layer is formed on the substrate;

[0019] The active layer is crystallized to form a first active portion and a second active portion located on the first active portion, and the crystal mass ratio in the second active portion is greater than or equal to the crystal mass ratio in the first active portion.

[0020] In the method for fabricating the array substrate of this application, the step of crystallizing the active layer to form a first active portion and a second active portion located on the first active portion includes:

[0021] A seed layer is deposited on the surface of the active layer, the seed layer containing impurity nuclei;

[0022] The seed layer is annealed to form a first active portion and a second active portion located on the first active portion.

[0023] In the method for fabricating the array substrate of this application, the step of depositing a seed layer on the surface of the active layer includes:

[0024] The surface of the active layer is subjected to plasma treatment, wherein the plasma gas used in the plasma treatment includes one or more of oxygen, nitrogen, helium, and argon.

[0025] This application also proposes a mobile terminal, including a terminal body and the aforementioned array substrate, wherein the array substrate and the terminal body are integrated into one unit.

[0026] Beneficial effects:

[0027] This application sets the active layer to include a first active portion and a second active portion, and makes the crystal mass ratio in the second active portion greater than or equal to the crystal mass ratio in the first active portion. That is, the second active portion and the first active portion are at least partially crystallized, thereby hindering the unstable movement of charge carriers through semiconductor crystallization, thereby improving the device stability of oxide semiconductor thin film transistors. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the first structure of the array substrate described in this application;

[0030] Figure 2 This is a schematic diagram of a second structure of the array substrate described in this application;

[0031] Figure 3 This is a flowchart of the method for fabricating the array substrate described in this application;

[0032] Figures 4 to 9 This is a schematic diagram of the fabrication process of the array substrate described in this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] Substrate 100, active layer 200, seed layer 201, first active part 210, second active part 220, gate layer 300, gate insulating layer 400, source drain layer 500, passivation layer 600, isolation protection layer 700, and crystal insulating layer 800. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0036] Commonly used active semiconductor materials for thin film transistors (TFTs) include amorphous silicon (a-Si), low-temperature polysilicon (LTPS), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). These materials are typically deposited uniformly on large-area substrates using DC or AC magnetron sputtering to improve product yield.

[0037] Among them, amorphous oxide semiconductor materials are currently widely used as active layer materials in oxide semiconductor thin-film transistors due to their high film uniformity and high product yield. However, for amorphous oxide semiconductor thin-film transistors, the presence of oxygen vacancy defects makes them susceptible to unstable carrier movement under external thermal or optical stimuli, causing positive or negative shifts in the threshold voltage of the thin-film transistor, which is detrimental to the device's operational stability. This application proposes the following solution based on the aforementioned technical problems.

[0038] Please see Figures 1 to 9 This application provides an array substrate, comprising:

[0039] Substrate 100;

[0040] An active layer 200 is disposed on the substrate 100, and the active layer 200 includes a first active portion 210 disposed on the substrate 100 and a second active portion 220 disposed on the first active portion 210.

[0041] The proportion of crystal mass in the second active part 220 is greater than or equal to the proportion of crystal mass in the first active part 210.

[0042] This application configures the active layer 200 to include a first active portion 210 and a second active portion 220, and makes the crystal mass ratio in the second active portion 220 greater than or equal to the crystal mass ratio in the first active portion 210. That is, the second active portion 220 and the first active portion 210 are at least partially crystallized, thereby hindering the unstable movement of charge carriers through semiconductor crystallization, thereby improving the device stability of oxide semiconductor thin film transistors.

[0043] The technical solutions of this application will now be described with reference to specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] In the array substrate of this application, the substrate 100 can be a glass substrate or a polyimide substrate.

[0045] In this embodiment, the material of the active layer 200 may include oxide semiconductor materials, such as one or more of indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO). The oxide semiconductor material may include either a fully crystalline oxide semiconductor or a partially crystalline amorphous oxide semiconductor. In this embodiment, the oxide semiconductor materials of the second active portion 220 and the first active portion 210 may be the same or different.

[0046] Please see Figure 1 In this embodiment, the array substrate may further include a gate layer 300 disposed on the substrate 100, a gate insulating layer 400 disposed between the gate layer 300 and the active layer 200, a source / drain layer 500 disposed on the active layer 200, a passivation layer 600 disposed on the source / drain layer 500, an isolation protection layer 700 disposed on the passivation layer 600, and a pixel electrode layer (not shown in the figure) disposed on the isolation protection layer 700.

[0047] In this embodiment, the source-drain layer 500 can be connected to the second active portion 220, and the source-drain layer 500 can include a source electrode and a drain electrode respectively connected to two channel regions of the second active portion 220. In this embodiment, the gate layer 300, the active layer 200, and the source-drain layer 500 form a bottom-gate thin-film transistor. In the bottom-gate thin-film transistor, the crystalline second active portion 220 has excellent etching resistance, which can protect the channel region within the active layer 200 and prevent channel damage during the etching process of the source-drain layer 500.

[0048] In this embodiment, the gate layer 300 and the source / drain layer 500 can be made of metallic materials with high work function, good shape stability, electrical conductivity, and thermal conductivity, such as Mo, Al, Cu, Ti, etc.

[0049] In this embodiment, the gate insulating layer 400 and the passivation layer 600 can be made of SiO2. x Or SiN x Inorganic insulating materials are used to prepare materials that can block water vapor and provide insulation, thus protecting other structures of the thin-film transistor.

[0050] In this embodiment, the isolation and protective layer 700 can be made of polymer materials, such as polytetrafluoroethylene.

[0051] In this embodiment, the pixel electrode layer can be made of a transparent conductive material, such as indium tin oxide.

[0052] Please see Figure 1 and Figure 2 In the array substrate of this application, the first active part 210 may include a crystal or may not contain a crystal.

[0053] Please see Figure 1 In this embodiment, the first active portion 210 may contain a crystal, and the mass ratio of the crystal in the first active portion 210 is equal to the mass ratio in the second active portion 220, so that the active layer 200 has a uniform crystal structure, thereby improving the device instability problem of oxide semiconductor thin film transistors.

[0054] Please see Figure 1 In this embodiment, the first active part 210 may not contain crystals. In this case, the crystal mass ratio in the first active part 210 is 0%, so that the first active part 210 and the second active part 220 of the active layer 200 form an amorphous-crystalline bilayer structure.

[0055] Please see Figure 2 In this embodiment, the second active portion 220 can cover the surface of the first active portion 210, that is, the second active portion 220 can be located on the surface of the first active portion 210 except for the surface in contact with the gate insulating layer 400, so that the crystalline second active portion 220 can shield and protect the amorphous first active portion 210 (especially the channel region in the first active portion 210) and prevent channel damage.

[0056] In this embodiment, the upper crystalline second active portion 220 can hinder the unstable movement of charge carriers, thereby improving the device stability of the oxide semiconductor thin film transistor. Furthermore, the crystalline second active portion 220 can also improve the etching resistance of the active layer 200, preventing etching damage and protecting the back channel. The lower amorphous first active portion 210 can improve the film uniformity and carrier mobility of the active layer 200. This embodiment, through the combined effect of the amorphous first active portion 210 and the crystalline second active portion 220, improves the device stability of the semiconductor oxide thin film transistor while ensuring good film uniformity, etching uniformity, and high carrier mobility.

[0057] In the array substrate of this application, the crystal size in the second active portion 220 is greater than or equal to the crystal size in the first active portion 210.

[0058] In this embodiment, the crystal size in the second active part 220 can be larger than the crystal size in the first active part 210. That is, both the second active part 220 and the first active part 210 can contain crystals, or the second active part 220 can contain crystals and the first active part 210 can not contain crystals.

[0059] Please see Figure 1 and Figure 2 In this embodiment, when the second active portion 220 contains a crystal and the first active portion 210 does not contain a crystal, the second active portion 220 can be entirely crystalline, and the first active portion 210 can be entirely amorphous. The second active portion 220 and the first active portion 210 form a crystalline-amorphous bilayer structure, so that the upper crystalline second active portion 220 hinders the unstable movement of charge carriers, improves the device stability of the oxide semiconductor thin film transistor and the etching resistance of the active layer 200, and plays a role in preventing etching damage and protecting the back channel. The lower amorphous first active portion 210 can improve the film uniformity and carrier mobility of the active layer 200.

[0060] It should be noted that when both the second active portion 220 and the first active portion 210 contain crystals, the size of the crystals gradually decreases in the direction from the second active portion 220 to the first active portion 210. In this case, the crystal sizes in the second active portion 220 and the first active portion 210 depend on the crystal growth time; that is, the crystals in the second active portion 220 grow first, resulting in a larger crystal size, while the crystals in the first active portion 210 grow later, resulting in a smaller crystal size.

[0061] In this embodiment, preferably, the crystal size in the second active portion 220 can be the same as the crystal size in the first active portion 210, so that the crystal structure in the active layer 200 has good grain uniformity and uniform grain boundary distribution. At this time, the crystal formation in the first active portion 210 and the second active portion 220 reaches a saturation state, that is, the grain size of all crystals is uniform.

[0062] In the array substrate of this application, within a unit area parallel to the substrate 100, the number of crystals in the second active portion 220 is less than or equal to the number of crystals in the first active portion 210.

[0063] In this embodiment, the number of crystals in the first active portion 210 and the second active portion 220 is related to the crystal size in the first active portion 210 and the second active portion 220. Specifically, when the crystal size in the second active portion 220 is larger than the crystal size in the first active portion 210, the number of crystals in the second active portion 220 is less than the number of crystals in the first active portion 210 per unit area parallel to the substrate 100; when the crystal size in the second active portion 220 is equal to the crystal size in the first active portion 210, the number of crystals in the second active portion 220 is equal to the number of crystals in the first active portion 210 per unit area parallel to the substrate 100.

[0064] It should be noted that in this embodiment, the crystal size and number of crystals in the first active part 210 and the second active part 220 are not independent structural designs, but rather related structures to the crystallization method of the active layer 200 in this embodiment.

[0065] Through the above settings, this embodiment can make the crystal size and number in the first active part 210 and the second active part 220 match, and achieve good effects such as improving device stability and the etching resistance of the active layer 200, preventing etching damage, protecting the back channel, and improving the film uniformity and carrier mobility of the active layer 200.

[0066] Please see Figure 1 and Figure 2 In the array substrate of this application, the array substrate further includes a gate insulating layer 400 disposed between the gate layer 300 and the first active portion 210, and a crystalline insulating layer 800 disposed on the gate insulating layer 400. In this embodiment, the crystalline insulating layer 800 may be disposed on the gate insulating layer 400 in the area other than that in contact with the first active portion 210.

[0067] In this embodiment, the crystalline insulating layer 800 can be prepared from an organic photoresist material.

[0068] In this embodiment, the crystalline insulating layer 800 can be continuously disposed with the second active part 220, so that they can be formed in the same process, simplifying the manufacturing process and reducing the process cost.

[0069] In this embodiment, by providing a crystalline insulating layer 800 on the gate insulating layer 400, the breakdown voltage of the gate metal and source / drain metal in the region other than the thin-film transistor on the array substrate can be increased, thereby reducing the risk of electrostatic discharge (ESD) of the gate metal and source / drain metal.

[0070] In the array substrate of this application, the crystal size in the second active portion 220 is greater than or equal to the crystal size in the crystalline insulating layer 800, and the number of crystals in the second active portion 220 is less than or equal to the number of crystals in the crystalline insulating layer 800 per unit area parallel to the substrate 100.

[0071] In this embodiment, the second active portion 220 is an inorganic material of metal oxide semiconductor, and the crystalline insulating layer 800 is made of an organic photoresist material. Since the second active portion 220 and the crystalline insulating layer 800 can be formed in the same process, meaning their initial nucleus densities are approximately similar, the difference in crystal size and quantity between the second active portion 220 and the crystalline insulating layer 800 depends on the material difference between them. Compared to the crystalline insulating layer 800 made of organic material, the second active portion 220 made of inorganic material has a faster nucleus growth rate, a larger lattice size, and a correspondingly smaller number of crystals per unit area parallel to the substrate 100 compared to the crystalline insulating layer 800.

[0072] In this embodiment, the active layer 200 is configured to include a first active portion 210 and a second active portion 220, and the crystal mass ratio in the second active portion 220 is greater than or equal to the crystal mass ratio in the first active portion 210. That is, the second active portion 220 and the first active portion 210 are at least partially crystallized. This not only ensures the film formation uniformity and etching uniformity of the active layer 200, but also hinders the unstable movement of charge carriers through semiconductor crystallization, thereby improving the device stability of oxide semiconductor thin film transistors.

[0073] Please see Figure 1 This application also provides a method for fabricating an array substrate, comprising:

[0074] S100, An active layer 200 is formed on the substrate 100;

[0075] S200, the active layer 200 is crystallized to form a first active portion 210 and a second active portion 220 located on the first active portion 210, and the proportion of crystal mass in the second active portion 220 is greater than or equal to the proportion of crystal mass in the first active portion 210.

[0076] In this embodiment, the active layer 200 is crystallized. This process controls the grain size and crystallization rate to form a second active portion 220 with a larger crystal mass ratio and a first active portion 210 with a smaller crystal mass ratio. The first active portion 210 improves the film uniformity and carrier mobility of the active layer 200, while the second active portion 220 improves the etching resistance, protects the back channel from etching damage, and reduces unstable carrier movement, thereby improving the device stability of the thin-film transistor.

[0077] In this embodiment, the "crystal mass ratio" can be understood as the ratio of the crystal mass in the first active part 210 / second active part 220 to the total mass of the first active part 210 / second active part 220.

[0078] In the method for fabricating the array substrate of this application, please refer to... Figure 2 and Figures 3 to 9 The S100 step may include:

[0079] S110, A gate material layer is formed on the substrate 100, and a patterned gate layer 300 is formed by developing and etching.

[0080] S120, A gate insulating layer 400 is formed on the gate layer 300;

[0081] S130, An active material layer is formed on the gate insulating layer 400, and a patterned active layer 200 is formed by developing and etching.

[0082] In the method for fabricating the array substrate of this application, please refer to... Figure 4 and Figure 5 The S200 step may include:

[0083] S210, a seed layer 201 is deposited on the surface of the active layer 200, the seed layer 201 containing impurity nuclei.

[0084] In this embodiment, the seed layer 201 deposited on the surface of the active layer 200 can be fabricated by forming crystal nuclei through DC plasma sputtering or AC plasma sputtering.

[0085] In this embodiment, plasma sputtering can be achieved using gases such as oxygen, nitrogen, helium, and argon, which do not increase defects within the oxide semiconductor material. In this embodiment, oxygen is preferably used for the plasma treatment to improve the defect uniformity of the oxide semiconductor material.

[0086] In this embodiment, a crystalline insulating layer 800 can be formed on the surface of the gate insulating layer 400 in the same process, that is, a seed layer 201 can be deposited on the surface of the active layer 200 and the surface of the gate insulating layer 400 in the same process, so as to simplify the manufacturing process and reduce time and economic costs.

[0087] S220, Anneal the seed layer 201 to form a first active part 210 and a second active part 220 located on the first active part 210.

[0088] In this embodiment, the seed layer 201 on the gate insulating layer 400 can be annealed simultaneously in the same process to form the crystalline insulating layer 800.

[0089] In this embodiment, the annealing treatment of the seed layer 201 can be performed by high temperature or laser treatment of the seed layer 201, and the seed layer 201 is cooled to form a crystalline layer in the active layer 200 and on the gate insulating layer 400.

[0090] In this embodiment, the seed layer 201 is fabricated in the above manner and then annealed by high temperature or laser. This not only makes the fabrication of the seed layer 201 more efficient and the crystal nuclei more uniform, but also allows for precise control of the growth rate of the crystal nuclei, thereby controlling the size and number of crystals and improving the uniformity of grain size and grain boundary distribution.

[0091] In the method for fabricating the array substrate of this application, please refer to... Figure 6 and Figure 7 Figure 8 Figure 9 The method for manufacturing the array substrate may further include:

[0092] S300, a source and drain layer 500 is formed on the active layer 200 after crystallization treatment, and patterned source and drain electrodes are etched.

[0093] S400, a passivation layer 600 is formed on the source / drain layer 500, an isolation protection layer 700 is formed on the passivation layer 600, the isolation protection layer 700 is patterned, and a pixel electrode layer opposite to the source / drain layer 500 is formed on the patterned isolation protection layer 700.

[0094] This application also proposes a mobile terminal, which includes a terminal body and the aforementioned array substrate, wherein the terminal body and the array substrate are integrated into one unit. In this embodiment, the mobile terminal can be a smart display device such as a mobile phone, computer, or watch.

[0095] The above provides a detailed description of an array substrate, its fabrication method, and a mobile terminal provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer is disposed on the substrate, the active layer including a first active portion disposed on the substrate and a second active portion disposed on the first active portion; Wherein, the proportion of crystal mass in the second active part is greater than or equal to the proportion of crystal mass in the first active part, and the crystal size in the second active part is greater than or equal to the crystal size in the first active part; within a unit area parallel to the substrate, the number of crystals in the second active part is less than or equal to the number of crystals in the first active part.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes a gate layer disposed on the side of the active layer near the substrate and a source / drain layer disposed on the side of the active layer away from the substrate; The gate layer is insulated from the active layer, and the source / drain layer is connected to the second active portion.

3. The array substrate according to claim 2, characterized in that, The array substrate further includes a gate insulating layer disposed between the gate layer and the first active portion, and a crystalline insulating layer disposed on the gate insulating layer; The crystalline insulating layer is continuously disposed with the second active part.

4. The array substrate according to claim 3, characterized in that, The crystal size in the second active portion is greater than or equal to the crystal size in the crystalline insulating layer, and the number of crystals in the second active portion is less than or equal to the number of crystals in the crystalline insulating layer per unit area parallel to the substrate.

5. A method for fabricating an array substrate, characterized in that, include: An active layer is formed on the substrate; The active layer is crystallized to form a first active portion and a second active portion located on the first active portion, such that the crystal mass ratio in the second active portion is greater than or equal to the crystal mass ratio in the first active portion, and the crystal size in the second active portion is greater than or equal to the crystal size in the first active portion; within a unit area parallel to the substrate, the number of crystals in the second active portion is less than or equal to the number of crystals in the first active portion.

6. The method for fabricating an array substrate according to claim 5, characterized in that, The step of crystallizing the active layer to form a first active portion and a second active portion located on the first active portion includes: A seed layer is deposited on the surface of the active layer, the seed layer containing impurity nuclei; The seed layer is annealed to form a first active portion and a second active portion located on the first active portion.

7. The method for fabricating an array substrate according to claim 6, characterized in that, The step of depositing a seed layer on the surface of the active layer includes: The surface of the active layer is subjected to plasma treatment, wherein the plasma gas used in the plasma treatment includes one or more of oxygen, nitrogen, helium, and argon.

8. A mobile terminal, characterized in that, It includes a terminal body and an array substrate as described in any one of claims 1 to 4, wherein the array substrate and the terminal body are integrated into one unit.

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