A composite substrate structure and a method for improving its morphology

Abstract

The present invention relates to the technical field of semiconductor material processing, and particularly relates to a composite substrate structure and a method for improving its morphology. The structure includes a first stress balance layer, a substrate layer, a second stress balance layer, a dielectric layer, and a functional thin film layer arranged in sequence; the first stress balance layer and the second stress balance layer are made of the same material and have the same manufacturing process; the first stress balance layer is used to adjust the thickness of the first stress balance layer according to the stress distribution in the composite substrate structure so as to improve the morphology of the composite substrate structure; the second stress balance layer is used to balance the stress generated during the production of the first stress balance layer. In this composite substrate structure, by providing a first stress balance layer on the back surface of the substrate layer, the first stress balance layer serves as a stress compensation layer. When preparing a heterogeneous integrated substrate, the morphology of the wafer is optimized by adjusting the thickness of this layer, so that the overall morphology of the heterogeneous wafer is more conducive to subsequent wafer processing.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor material processing, and particularly relates to a composite substrate structure and a method for improving its topography. Background Art

[0002] With the increasing pursuit of data transmission speed, performance, power consumption, etc. of telecommunication devices by people, the rapid development of chip technology has made a single material unable to meet the requirements of improving chip performance and integration. People need to provide new chip integration solutions to achieve high-performance, high-integration and low-power chip technology. Combining multiple materials together to achieve heterogeneous integration of multiple materials has become an important path for improving future chip performance and integration level.

[0003] In the prior art, when manufacturing a heterogeneous thin film material wafer, heterogeneous materials are usually transferred, deposited and grown on a Si substrate or other substrates. However, due to the difference in thermal expansion coefficients between different materials and the internal stress existing in the thin film after growing the material, the crystal circularity of the heterogeneous integration substrate is poor. Specifically, the thin film has a large bow value and warp value, which is not conducive to the subsequent wafer processing technology of the wafer. Therefore, there is an urgent need for a processing method that can change the crystal circularity of the heterogeneous integration substrate to improve the crystal circularity of the heterogeneous integration substrate and make the heterogeneous integration substrate convenient for subsequent wafer processing. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that the crystal circularity of the heterogeneous integration substrate prepared by the prior art is poor, which is not conducive to subsequent wafer processing.

[0005] To solve the above technical problem, in a first aspect, an embodiment of the present application discloses a composite substrate structure, including a first stress balance layer, a substrate layer, a second stress balance layer, a dielectric layer and a functional thin film layer;

[0006] The substrate layer is disposed between the first stress balance layer and the second stress balance layer;

[0007] The dielectric layer is fabricated on the second stress balance layer, and the dielectric layer is used to provide a bonding interface for the functional thin film layer;

[0008] The functional thin film layer is fabricated on the dielectric layer, and the functional thin film layer is used to fabricate a device functional structure;

[0009] The first stress balance layer and the second stress balance layer are made of the same material;

[0010] The first stress balance layer and the second stress balance layer are respectively fabricated on two opposite sides of the substrate layer by the same process and simultaneously;

[0011] The first stress balance layer is used to adjust the thickness of the first stress balance layer according to the stress distribution in the composite substrate structure, so as to improve the topography of the composite substrate structure;

[0012] The second stress balance layer is used to balance the stress generated during the fabrication of the first stress balance layer.

[0013] Furthermore, the materials of the first stress balance layer and the second stress balance layer are polysilicon.

[0014] Furthermore, the thickness of the first stress balance layer is 0 - 2 μm;

[0015] The thickness of the second stress balance layer is 0.5 - 2 μm;

[0016] The thickness of the first stress balance layer is less than or equal to the thickness of the second stress balance layer.

[0017] Furthermore, the in-plane stress inside the functional thin film layer is opposite to the in-plane stress inside the first stress balance layer;

[0018] The in-plane stress inside the functional thin film layer is opposite to the in-plane stress inside the second stress balance layer.

[0019] Furthermore, the in-plane stress inside the first stress balance layer is 100 MPa - 2000 MPa;

[0020] The in-plane stress inside the first stress balance layer is less than the in-plane stress inside the second stress balance layer.

[0021] Furthermore, the material of the dielectric layer is any one of silicon dioxide, aluminum nitride, and silicon carbide;

[0022] The material of the functional thin film layer is any one of lithium niobate, lithium tantalate, aluminum nitride, and silicon carbide.

[0023] In a second aspect, an embodiment of the present application discloses a method for improving the topography of a composite substrate structure, the method comprising:

[0024] Obtain a substrate layer;

[0025] Deposit a first stress balance layer and a second stress balance layer on two opposite side surfaces of the substrate layer simultaneously; wherein, the first stress balance layer is used to adjust the thickness of the first stress balance layer according to the stress distribution in the composite substrate structure, so as to improve the topography of the composite substrate structure; the second stress balance layer is used to balance the stress generated during the fabrication of the first stress balance layer;

[0026] Deposit a dielectric layer on the second stress balance layer;

[0027] Fabricate a functional thin film layer on the dielectric layer;

[0028] Adjust the thickness of the first stress balance layer according to the stress distribution in the functional thin film layer so as to improve the topography of the composite substrate structure.

[0029] Furthermore, the first stress balance layer and the second stress balance layer are deposited with the same thickness.

[0030] Furthermore, after the first stress balance layer and the second stress balance layer are simultaneously deposited on two opposite side surfaces of the substrate layer respectively, the following steps are further included:

[0031] Furthermore, the method for fabricating the functional thin film layer on the dielectric layer at least includes: smart lift-off process or grinding and thinning process.

[0032] Adopting the above technical solution, the composite substrate structure and the method for improving its topography according to the embodiments of the present application have the following beneficial effects:

[0033] In this composite substrate structure, by providing a first stress balance layer on the back surface of the substrate layer, the first stress balance layer serves as a stress compensation layer. When preparing a heterogeneous integrated substrate, the topography of the wafer is optimized by adjusting the thickness of this layer, so that the overall topography of the heterogeneous wafer can be more conducive to subsequent wafer processing. In addition, by providing a second stress balance layer on the front surface of the substrate layer while providing the first stress balance layer, the stress generated during the fabrication of the first stress balance layer can be balanced, enabling the substrate to have a good topography when integrating heterogeneous thin films, which is beneficial to realizing the preparation of high-quality heterogeneous thin films, and further improving the quality of the heterogeneous integrated substrate. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0035] Figure 1 It is a schematic structural diagram of another composite substrate structure provided by the embodiment of the present application;

[0036] Figure 2 It is a stress distribution nephogram of an initial composite substrate structure provided by the embodiment of the present application;

[0037] Figure 3 It is a stress distribution nephogram of a composite substrate structure with improved topography provided by the embodiment of the present application;

[0038] Figure 4Schematic flow chart of a method for improving the topography of a composite substrate structure provided by an embodiment of the present application;

[0039] Figure 5 Structural flow chart of a method for improving the topography of a composite substrate structure provided by an embodiment of the present application;

[0040] The following is a supplementary description of the drawings:

[0041] 101 - First stress balance layer; 102 - Substrate layer; 103 - Second stress balance layer; 104 - Dielectric layer; 105 - Functional thin film layer. Specific embodiments

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0043] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0044] At present, integrating piezoelectric materials with silicon will provide a wafer substrate for material-level integration, providing a material platform for fabricating monolithic integrated modules. In addition, bonding piezoelectric materials to a heterogeneous substrate, especially a rigid substrate with a relatively large Young's modulus, can effectively increase the center frequency and bandwidth of related filters and reduce power consumption. Using the ion beam lift-off method to transfer a piezoelectric single crystal onto a desired substrate can already provide the corresponding wafer material, with a uniform thickness of the functional thin film layer and good stability of the fabricated device. However, when transferring a heterogeneous functional thin film layer through a bonding process, the internal stress of the functional thin film layer and the thermal mismatch between the functional thin film layer and the substrate layer result in a poor wafer morphology.

[0045] In view of this, an embodiment of the present application provides a composite substrate structure. Figure 1 As shown in the structural schematic diagram of a composite substrate structure provided by an embodiment of the present application, as Figure 1 shown, the composite substrate structure includes:

[0046] A first stress balance layer 101, a substrate layer 102, a second stress balance layer 103, a dielectric layer 104, and a functional thin film layer 105. The substrate layer 102 is disposed between the first stress balance layer 101 and the second stress balance layer 103. The dielectric layer 104 is fabricated on the second stress balance layer 103, and the dielectric layer 104 is used to provide a bonding interface for the functional thin film layer 105. The functional thin film layer 105 is fabricated on the dielectric layer 104, and the functional thin film layer 105 is used to fabricate a device functional structure. The first stress balance layer 101 and the second stress balance layer 103 are made of the same material. The first stress balance layer 101 and the second stress balance layer 103 are respectively fabricated on two opposite sides of the substrate layer 102 through the same process and simultaneously. The first stress balance layer 101 is used to adjust the thickness of the first stress balance layer 101 according to the stress distribution in the composite substrate structure, so as to improve the morphology of the composite substrate structure. The second stress balance layer 103 is used to balance the stress generated when fabricating the first stress balance layer 101.

[0047] In the composite substrate structure described in the embodiment of the present application, by disposing the first stress balance layer 101 on the back surface of the substrate layer 102, the first stress balance layer 101 serves as a stress compensation layer. When fabricating a heterogeneous integrated substrate, the morphology of the wafer is optimized by adjusting the thickness of this layer, so that the overall morphology of the heterogeneous wafer can be more conducive to subsequent wafer processing. In addition, by disposing the second stress balance layer 103 on the front surface of the substrate layer 102 while disposing the first stress balance layer 101, the stress generated when fabricating the first stress balance layer 101 can be balanced, enabling the substrate to have a good morphology when integrating heterogeneous thin films, which is beneficial to realizing the fabrication of high-quality heterogeneous thin films, and further improving the quality of the heterogeneous integrated substrate.

[0048] In the embodiments of the present application, the substrate layer 102 may be selected from a silicon substrate, a silicon oxide substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, etc. The first stress balance layer 101 is disposed on the back surface of the substrate layer 102, and the second stress balance layer 103 is disposed on the front surface of the substrate layer 102. The first stress balance layer 101 is a thickness-adjustable layer. When the composite substrate structure is bent due to uneven stress distribution, the stress distribution in the composite substrate structure can be adjusted by adjusting the thickness of the first stress balance layer 101, thereby improving the bending condition of the composite substrate structure and enabling the composite substrate structure to have a flat morphology. The second stress balance layer 103 is mainly provided to balance the thermal stress generated during the preparation of the first stress balance layer 101. If only the first stress balance layer 101 is disposed on the back surface of the substrate layer 102, then when the first stress balance layer 101 is fabricated on the back surface of the substrate layer 102, the substrate layer 102 is stressed on one side, which easily causes the fabricated structure to be bent, and is not conducive to the subsequent heterogeneous thin film bonding and transfer processes. Therefore, when the first stress balance layer 101 is fabricated on the back surface of the substrate layer 102, the second stress balance layer 103 is simultaneously fabricated on the front surface of the substrate layer 102 to balance the single-sided stress generated during the fabrication of the first stress balance layer 101, thereby maintaining a good surface structure of the substrate layer 102 before transferring the thin film and facilitating the transfer of the subsequent functional thin film layer 105. Optionally, the first stress balance layer 101 and the second stress balance layer 103 are made of the same material. For example, materials such as polysilicon, silicon nitride, and silicon carbide can be used. The materials of the first stress balance layer 101 and the second stress balance layer 103 are preferably polysilicon. Polysilicon has good strength, and the fabrication process of using polysilicon to make the stress balance layer is simple and the cost is low. Optionally, the methods used to fabricate the first stress balance layer 101 and the second stress balance layer 103 include, but are not limited to, chemical vapor deposition, physical vapor deposition, vacuum evaporation coating, sputtering, pulsed laser deposition, molecular beam epitaxy, chemical beam epitaxy, hydride vapor epitaxy, physical vapor transport, etc. Optionally, the initially fabricated first stress balance layer 101 and the second stress balance layer 103 have the same thickness to ensure stress balance on both the front and back sides of the substrate layer 102, that is, the first stress balance layer 101 and the second stress balance layer 103 have the same initial in-plane stress. After the entire composite substrate structure is fabricated, the thickness of the first stress balance layer 101 is adjusted to achieve the purpose of improving the morphology of the composite substrate structure. Optionally, after the first stress balance layer 101 is thinned, the thickness of the first stress balance layer 101 is 0 - 2 μm. The thickness of the second stress balance layer 103 is 0.5 - 2 μm. The thickness of the first stress balance layer 101 is less than or equal to the thickness of the second stress balance layer 103.

[0049] In some embodiments, the first stress balance layer 101 and the second stress balance layer 103 can also be made of different materials. Correspondingly, the initially fabricated first stress balance layer 101 and the second stress balance layer 103 can also have different thicknesses. Specifically, it can be determined according to the materials of the first stress balance layer 101 and the second stress balance layer 103 selected and the corresponding manufacturing process.

[0050] In the embodiments of the present application, as Figure 1 shown, the dielectric layer 104 serves as the bonding interface between the functional thin film layer 105 and the second stress balance layer 103 to enhance the bonding strength between the functional thin film layer 105 and the second stress balance layer 103. Optionally, the material of the dielectric layer 104 can be, but is not limited to, silicon dioxide, aluminum nitride, silicon carbide, etc. The material of the dielectric layer 104 can be selected according to the materials of the second stress balance layer 103 and the functional thin film layer 105. In some embodiments, the dielectric layer 104 can also be not provided, but the functional thin film layer 105 can be directly fabricated on the second stress balance layer 103.

[0051] In the embodiments of the present application, both the dielectric layer 104 and the functional thin film layer 105 are fabricated on the front side of the substrate layer 102. During fabrication, due to unidirectional stress, the fabricated composite substrate structure will be bent. Therefore, after the functional thin film layer 105 is fabricated, there are different in-plane stresses in each layer of the composite substrate structure. The in-plane stress inside the functional thin film layer 105 is opposite to the in-plane stress inside the first stress balance layer 101. The in-plane stress inside the functional thin film layer 105 is opposite to the in-plane stress inside the second stress balance layer 103. That is, when the in-plane stress inside the functional thin film layer 105 is tensile stress, the in-plane stresses inside the first stress balance layer 101 and the second stress balance layer 103 are compressive stresses. When the in-plane stress inside the functional thin film layer 105 is compressive stress, the in-plane stresses inside the first stress balance layer 101 and the second stress balance layer 103 are tensile stresses. By thinning the thickness of the first stress balance layer 101, the stress inside the first stress balance layer 101 is reduced, and thus the stress inside the functional thin film layer 105 is reduced. After the first stress balance layer 101 is thinned, the in-plane stress inside the first stress balance layer 101 is 100 MPa - 2000 MPa. After the first stress balance layer 101 is thinned, the in-plane stress inside the first stress balance layer 101 is less than the in-plane stress inside the second stress balance layer 103.

[0052] In the embodiments of the present application, the functional thin film layer 105 is used as an active layer for device fabrication. Optionally, the material of the functional thin film layer 105 can be, but is not limited to, lithium niobate, lithium tantalate, aluminum nitride, silicon carbide, etc.

[0053] In the embodiments of the present application, Figure 2A stress distribution nephogram of an initial composite substrate structure provided by an embodiment of the present application, as shown in Figure 2 shown, the initial thicknesses of the first stress balance layer 101 and the second stress balance layer 103 are the same. By simulation, it is determined that there is a compressive stress of 500 MPa in the first stress balance layer 101 and the second stress balance layer 103, and a tensile stress of 400 MPa in the functional thin film layer 105. Figure 3 shows the deformation of the composite substrate structure in this case. It can be seen from Figure 2 that the wafer has a negative Bow value. Figure 3 A stress distribution nephogram of a composite substrate structure with improved morphology provided by an embodiment of the present application, as shown in Figure 3 shown. By adjusting the thickness of the first stress balance layer 101 in the composite substrate structure shown in Figure 2 the morphology of the composite substrate structure is improved. As shown in Figure 3 shown, through simulation measurement, the thickness of the first stress balance layer 101 is thinned to half of that of the second stress balance layer 103. Correspondingly, the stress in the first stress balance layer 101 is reduced by half. When other conditions are the same, the deformation of the wafer is greatly improved, and the Bow value of the wafer is almost 0.

[0054] An embodiment of the present application also provides a method for improving the morphology of a composite substrate structure. Figure 4 A schematic flow chart of a method for improving the morphology of a composite substrate structure provided by an embodiment of the present application, as shown in Figure 4 shown. The method includes:

[0055] S401: Obtain the substrate layer 102.

[0056] In an embodiment of the present application, Figure 5 A structural flow chart of a method for improving the morphology of a composite substrate structure provided by an embodiment of the present application, as shown in Figure 5 shown. First, a suitable substrate wafer is selected as the substrate layer 102. The substrate layer 102 can be selected from a silicon substrate, a silicon oxide substrate, a silicon carbide substrate, a silicon-on-insulator substrate, etc.

[0057] S403: Deposit the first stress balance layer 101 and the second stress balance layer 103 on two opposite sides of the substrate layer 102 simultaneously and respectively.

[0058] In an embodiment of the present application, as shown in Figure 5As shown, by depositing a first stress balance layer 101 and a second stress balance layer 103 with tensile stress or compressive stress on both the upper and lower surfaces of the substrate layer 102, the deposition of the double-layer stress balance layer enables the wafer to maintain a better crystal morphology, which is beneficial to the subsequent bonding process. The first stress balance layer 101 is used to adjust the thickness of the first stress balance layer 101 according to the stress distribution in the composite substrate structure, so as to improve the morphology of the composite substrate structure. The second stress balance layer 103 is used to balance the stress generated during the fabrication of the first stress balance layer 101. Optionally, the first stress balance layer 101 and the second stress balance layer 103 are deposited with the same thickness.

[0059] As an alternative embodiment, at a relatively high temperature, polysilicon layers are deposited on both the front and back surfaces of the substrate layer 102, and these two polysilicon layers have in-plane compressive stress. In order to maintain a better surface quality of the wafer, which is beneficial to the subsequent bonding process, a double-sided deposition process is adopted to balance the stress on the front and back sides of the wafer.

[0060] S405: Deposit a dielectric layer on the second stress balance layer.

[0061] In the embodiments of the present application, a dielectric layer 104 is deposited on the second stress balance layer 103 to enhance the bonding strength between the functional thin film layer 105 and the substrate layer 102. The introduction of this dielectric layer 104 will not cause a significant change in the surface structure of the substrate layer 102.

[0062] S407: Fabricate a functional thin film layer on the dielectric layer.

[0063] In the embodiments of the present application, in the step of fabricating the functional thin film layer 105 on the dielectric layer 104, the transfer method of the heterogeneous functional thin film layer 105 includes processes such as smart-cut process and grinding and thinning process. As Figure 5 shown, as an alternative embodiment, fabricating the functional thin film layer 105 on the dielectric layer 104 can specifically be: obtaining a bulk wafer of a functional material, such as a lithium tantalate wafer, a lithium niobate wafer, an aluminum nitride wafer, etc., and then performing ion implantation on the bulk wafer of the functional material to introduce defects into the bulk wafer of the functional material. Optionally, the implanted ions can be hydrogen ions, helium ions, or co-implantation of hydrogen and helium ions, etc. After ion implantation on the bulk wafer of the functional material, bond the substrate layer 102 material and the bulk wafer of the functional material to form a bonded body. Annealing causes the bulk wafer of the functional material to peel off along the defects, forming a heterogeneous thin film wafer. The heterogeneous thin film wafer has tensile stress, resulting in a negative Bow value for the heterogeneous thin film wafer. That is, the heterogeneous functional thin film layer 105 is transferred through the bonding process. The internal stress of the functional thin film layer 105 and the thermal mismatch between the functional thin film layer 105 and the substrate layer 102 lead to a poor crystal morphology, which affects the subsequent processing of the wafer. Therefore, it is necessary to adjust and improve the crystal morphology.

[0064] S409: Adjust the thickness of the first stress balance layer according to the stress distribution in the functional thin film layer to improve the topography of the composite substrate structure.

[0065] In an optional embodiment, as Figure 5 shown, before improving the topography of the wafer, the surface of the functional thin film layer 105 can also be treated to remove the surface damage layer and improve the film quality. Specifically, the functional thin film layer 105 is thinned to a specified thickness by chemical mechanical polishing, and the surface damage layer is removed.

[0066] In the embodiment of the present application, as Figure 5 shown, after the functional thin film layer 105 is thinned, the thickness of the first stress balance layer 101 is adjusted according to the stress distribution in the functional thin film layer 105 to improve the topography of the composite substrate structure. Optionally, the method of adjusting the thickness of the first stress balance layer 101 can be methods such as grinding and thinning, chemical etching, dry etching, chemical mechanical polishing, etc. As an example, the thickness of the first stress balance layer 101 is adjusted by wet etching, thereby adjusting the topography of the heterogeneous thin film wafer to make the Bow value of the wafer close to 0.

[0067] For the composite substrate structure and its topography improvement method described in the embodiment of the present application, in order to better control the wafer topography parameters, a stress balance layer with a certain internal stress is deposited on the wafer substrate, and the wafer topography is adjusted by adjusting the thickness of the first stress balance layer, so that the thin film wafer has a good wafer topography to meet the process requirements of subsequent high-precision lithography and other processes.

[0068] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A composite substrate structure, characterized in that, it includes a first stress balance layer (101), a substrate layer (102), a second stress balance layer (103), a dielectric layer (104) and a functional thin film layer (105); The substrate layer (102) is disposed between the first stress balance layer (101) and the second stress balance layer (103); The dielectric layer (104) is fabricated on the second stress balance layer (103), and the dielectric layer (104) is used to provide a bonding interface for the functional thin film layer (105); The functional thin film layer (105) is fabricated on the dielectric layer (104), and the functional thin film layer (105) is used to fabricate device functional structures; The first stress balance layer (101) and the second stress balance layer (103) are made of the same material; The first stress balance layer (101) and the second stress balance layer (103) are respectively fabricated on two opposite side surfaces of the substrate layer (102) simultaneously by the same process; The first stress balance layer (101) is used to adjust the thickness of the first stress balance layer (101) according to the stress distribution in the composite substrate structure, so as to regulate the stress distribution in the composite substrate structure, improve the bending condition of the composite substrate structure, and make the composite substrate structure have a flat morphology; the thickness of the first stress balance layer (101) is 0 - 2 μm; The second stress balance layer (103) is used to balance the stress generated when fabricating the first stress balance layer (101); the thickness of the second stress balance layer (103) is 0.5 - 2 μm; the thickness of the first stress balance layer (101) is less than or equal to the thickness of the second stress balance layer (103); and the in-plane stress inside the first stress balance layer (101) is less than the in-plane stress inside the second stress balance layer (103); the in-plane stress inside the functional thin film layer (105) is opposite to the in-plane stress inside the first stress balance layer (101); the in-plane stress inside the functional thin film layer (105) is opposite to the in-plane stress inside the second stress balance layer (103).

2. The composite substrate structure according to claim 1, characterized in that, The first stress balance layer (101) and the second stress balance layer (103) are made of polysilicon.

3. The composite substrate structure according to any one of claims 1 - 2, characterized in that, The in-plane stress inside the first stress balance layer (101) is 100 MPa - 2000 MPa.

4. The composite substrate structure according to claim 2, characterized in that, The dielectric layer (104) is made of any one of silicon dioxide, aluminum nitride, and silicon carbide; The functional thin film layer (105) is made of any one of lithium niobate, lithium tantalate, aluminum nitride, and silicon carbide.

5. A method for improving the morphology of a composite substrate structure, characterized in that, the method includes: Obtaining a substrate layer (102); Deposit a first stress balance layer (101) and a second stress balance layer (103) simultaneously on two opposite side surfaces of the substrate layer (102); the second stress balance layer (103) is used to balance the stress generated during the fabrication of the first stress balance layer (101). Deposit a dielectric layer (104) on the second stress balance layer (103), and the dielectric layer (104) is used to provide a bonding interface for the functional thin film layer (105). Fabricate the functional thin film layer (105) on the dielectric layer (104), and the functional thin film layer (105) is used to fabricate device functional structures. Adjust the thickness of the first stress balance layer (101) according to the stress distribution in the functional thin film layer (105) to regulate the stress distribution in the composite substrate structure, improve the bending condition of the composite substrate structure, and make the composite substrate structure have a flat morphology; wherein, after the thickness of the first stress balance layer (101) is adjusted, the thickness of the first stress balance layer (101) is 0 - 2 μm; the thickness of the second stress balance layer (103) is 0.5 - 2 μm; the thickness of the first stress balance layer (101) is less than or equal to the thickness of the second stress balance layer (103); and the in-plane stress inside the first stress balance layer (101) is less than the in-plane stress inside the second stress balance layer (103); the in-plane stress inside the functional thin film layer (105) is opposite to the in-plane stress inside the first stress balance layer (101); the in-plane stress inside the functional thin film layer (105) is opposite to the in-plane stress inside the second stress balance layer (103).

6. The method according to claim 5, wherein, the first stress balance layer (101) and the second stress balance layer (103) are deposited with the same thickness.

7. The method according to claim 5, wherein, the method for adjusting the thickness of the first stress balance layer (101) is any one of grinding and thinning, chemical etching, dry etching, and chemical mechanical polishing.

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