A shield-gate type IGBT device and its manufacturing method

Abstract

The present invention discloses a shield-gate type IGBT device and a manufacturing method thereof, including: a plurality of trench structures formed in a semiconductor substrate of a first doping type, the trench structures including top trenches and deep trenches, the top trenches being located on both sides of the deep trenches; a gate dielectric layer is provided in the top trenches and polysilicon gates are filled; a source dielectric layer is formed on the bottom surface and side surfaces of the deep trenches, lower polysilicon and a plurality of spaced upper polysilicons are filled in the deep trenches, a source dielectric layer is provided between the upper polysilicon and the lower polysilicon, and a source dielectric layer is also provided between a plurality of upper polysilicons; the polysilicon gates in the top trenches are connected to the gate through first contact holes; the upper polysilicons in the deep trenches are connected to the emitter or the gate through second contact holes. Advantages: By freely selecting to electrically connect the upper polysilicon to the gate or the emitter in the deep trenches, the capacitance between the electrodes of the device can be adjusted very flexibly, and the EMI of the device can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to a shielded gate type IGBT device and a manufacturing method thereof, belonging to the technical field of semiconductor power devices. Background Art

[0002] Existing shielded gate trench IGBTs have a fixed ratio of gate silicon to source polysilicon sizes, that is, the capacitance between each electrode is fixed. It is difficult to find a suitable and effective method to flexibly adjust the capacitance and the capacitance ratio, which are often the key factors determining the turn-on and turn-off speeds of the device, as well as whether electromagnetic interference and oscillation occur during the fast switching process. How to flexibly adjust the capacitance value between each electrode has become a challenge in the process and design of such devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a shielded gate type IGBT device and a manufacturing method thereof.

[0004] To solve the above technical problem, the present invention provides a shielded gate type IGBT device, including:

[0005] A plurality of trench structures formed in a semiconductor substrate of a first doping type, the trench structures including top trenches and deep trenches, the top trenches being located on both sides of the deep trenches, and the top trenches and the deep trenches being connected; a gate dielectric layer is provided in the top trenches and filled with polysilicon gates; a source dielectric layer is formed on the bottom surface and side surfaces of the deep trenches, and lower polysilicon and a plurality of spaced upper polysilicons are filled in the deep trenches, a source dielectric layer is provided between the upper polysilicon and the lower polysilicon, and a source dielectric layer is also provided between a plurality of upper polysilicons;

[0006] A body region of a second conductive type is formed on the top of the semiconductor substrate, and an emitter region of a first conductive type is formed on the top of the body region; an interlayer film is formed on the top of the emitter region of the first conductive type, and a front metal layer is formed on the top of the interlayer film, and an emitter and a gate are etched on the front metal layer;

[0007] A collector region of a second conductive type is formed on the bottom of the semiconductor substrate;

[0008] The polysilicon gate in the top trench is connected to the gate through a first contact hole;

[0009] The upper polysilicon in the deep trench is connected to the emitter or the gate through a second contact hole.

[0010] Further, a collector metal is provided at the bottom end of the collector region of the second conductive type.

[0011] Further, the bottom of the top trench is higher than the bottom of the deep trench.

[0012] Further, the length and depth of the upper polysilicon are set according to the size of the target capacitor.

[0013] A manufacturing method of a shield-gate IGBT device includes the following steps:

[0014] Step 1: Provide a semiconductor substrate, deposit a layer of silicon oxide on the semiconductor substrate as a mask, and define the formation regions of gate trenches by photolithography, where the gate trenches include multiple ones;

[0015] Step 2: Anisotropically and isotropically etch the semiconductor substrate in the formation regions of the gate trenches to form top trenches and the intermediate communication regions;

[0016] Step 3: Form a gate dielectric layer on the bottom surface and side surfaces of the top trenches and the communication regions, and fill with polysilicon gates;

[0017] Step 4: Anisotropically etch the polysilicon gates and the gate dielectric layer to etch away the polysilicon gates and the gate dielectric layer in the communication regions;

[0018] Step 5: Anisotropically etch the semiconductor substrate to form deep trenches;

[0019] Step 6: Form a source dielectric layer and source polysilicon on the bottom surface and side surfaces of the deep trenches; and remove the silicon oxide on the surface of the semiconductor substrate;

[0020] Step 7: Redeposit a layer of silicon oxide as a mask and define the formation regions of custom regions by photolithography, where the formation regions of the custom regions include multiple ones and are located within the formation regions of the deep trenches;

[0021] Step 8: Etch the semiconductor substrate in the custom regions to form custom regions;

[0022] Step 9: Form a source dielectric layer and custom polysilicon on the bottom surface and side surfaces of the custom regions; and remove the silicon oxide on the surface of the semiconductor substrate;

[0023] Step 10: Form a body region of the second conductive type on the surface of the semiconductor substrate between the gate structures by implantation and annealing processes, and form an emitter region with heavy doping of the first conductive type on the surface of the body region;

[0024] Step 11: Form an interlayer film, contact holes, and a front metal layer, and pattern the front metal layer to form emitters and gates;

[0025] Step 12: Thinning, implanting and activating, and metallizing the back surface of the semiconductor substrate to form a collector, and finally completing device processing.

[0026] Further, the depth of the deep trench is 4 - 7 um calculated from the top of the semiconductor substrate.

[0027] Further, the proportion of the two different structures existing in the deep trench is defined by a custom area defined by lithography;

[0028] Further, a charge storage layer of the first conductivity type is disposed under the body region, and the resistivity of the charge storage layer is less than the resistivity of the semiconductor substrate.

[0029] Further, the gate dielectric and the source dielectric layer are silicon oxide.

[0030] Further, the semiconductor substrate is silicon or silicon carbide.

[0031] Beneficial effects achieved by the present invention:

[0032] In the IGBT device of the present invention, by freely selecting to electrically connect the upper polysilicon to the gate or the emitter in the deep trench, the inter - electrode capacitance of the device can be adjusted very flexibly, and the excellent performance of the original shield - gate IGBT is not affected. Through appropriate settings, the EMI of the device can be effectively reduced, and at the same time, the process is simple and controllable. Description of the Drawings

[0033] Figures 1 to 13 is a cross - sectional structural schematic diagram of the main structure in the manufacturing process of an embodiment of the manufacturing method of a semiconductor shield - gate type IGBT device provided by the present invention. Detailed Embodiments

[0034] The present invention will be further described below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be used to limit the protection scope of the present invention.

[0035] As Figure 13 shown, a shield - gate type IGBT device includes:

[0036] A plurality of trench structures formed in a semiconductor substrate 10 of a first doping type, the trench structures including a top trench 22 and a deep trench 30, the top trench 22 being located on both sides of the deep trench 30, and the top trench 22 communicating with the deep trench 30; a gate dielectric layer 24 is provided in the top trench 22 and filled with a polysilicon gate 25; a source dielectric layer 31 is formed on the bottom surface and side surfaces of the deep trench 30, and lower polysilicon and a plurality of spaced upper polysilicon are filled in the deep trench 30, and the source dielectric layer 31 is provided between the upper polysilicon and the lower polysilicon, and the source dielectric layer 31 is also provided between a plurality of upper polysilicon; the length and depth of the upper polysilicon are set according to the size of the target capacitance. Since the capacitance is determined by the overlapping area and distance between each electrode, in the present application, the upper polysilicon can selectively connect to the gate and the emitter, thereby changing the overlapping area and distance to achieve capacitance adjustment, and the length and depth of the polysilicon can be further selected according to the size of the target capacitance to further adjust the capacitance;

[0037] A body region 50 of a second conductivity type is formed on the top of the semiconductor substrate 10, and an emitter region 51 of a first conductivity type is formed on the top of the body region 50; an interlayer film 60 is formed on the top of the emitter region 51 of the first conductivity type, and a front metal layer 62 is formed on the top of the interlayer film 60, and an emitter and a gate are etched on the front metal layer 62;

[0038] A collector region 63 of a second conductivity type is formed at the bottom of the semiconductor substrate 10;

[0039] The polysilicon gate 25 in the top trench 22 is connected to the gate through a first contact hole 61;

[0040] The polysilicon in the deep trench 30 is connected to the gate or the emitter through a second contact hole 65.

[0041] Further, a collector metal 64 is provided at the bottom end of the collector region 63 of the second conductivity type.

[0042] Further, the bottom of the top trench 22 is higher than the bottom of the deep trench 30. The trench at the bottom will concentrate the strong electric field. If there is CS injection under the top trench, if it is too close to the strong electric field, it will affect the device breakdown voltage. Therefore, the bottom of the top trench 22 should be higher than the bottom of the deep trench 30.

[0043] A manufacturing method of a shielded gate type IGBT device includes the following steps:

[0044] First, as Figure 1As shown, a semiconductor substrate 10 is provided. After the previous terminal process is completed, a layer of silicon oxide 20 is deposited as a mask, and the formation region 21 of the gate trench is defined by photolithography. The gate trench includes multiple ones;

[0045] Next, as Figure 2 shown, the semiconductor substrate in the formation region of the gate trench is anisotropically and isotropically etched to form a top trench 22 and an intermediate communication region 23;

[0046] Next, as Figure 3 shown, a gate dielectric layer 24 is formed on the bottom surface and side surfaces of the top trench and the communication region, and a polysilicon gate 25 is filled;

[0047] Next, as Figure 4 shown, the polysilicon gate and the gate dielectric layer are anisotropically etched to etch away the polysilicon gate and the gate dielectric layer in the communication region;

[0048] Next, as Figure 5 shown, the semiconductor substrate is anisotropically etched to form a deep trench 30;

[0049] Next, as Figure 6 shown, a source dielectric layer 31 and a source polysilicon 32 are formed on the bottom surface and side surfaces of the deep trench; and the silicon oxide on the surface of the semiconductor substrate is removed;

[0050] Next, as Figure 7 shown, a layer of silicon oxide 40 is redeposited as a mask, and the formation region 41 of the self-defined region is defined by photolithography. The top view of the plan is as Figure 8 shown, the formation region 41 (thick black frame region) of the self-defined region includes multiple ones and is located within the formation region of the deep trench;

[0051] Next, as Figure 9 shown, the semiconductor substrate in the self-defined region is etched to form a self-defined region 42;

[0052] Next, as Figure 10 shown, a source dielectric layer 43 and a self-defined polysilicon 44 are formed on the bottom surface and side surfaces of the self-defined region; and the silicon oxide on the surface of the semiconductor substrate is removed;

[0053] Next, as Figure 11 shown, a body region 50 of the second conductive type is formed on the surface of the semiconductor substrate between the gate structures by implantation and annealing processes, and a heavily doped emitter region 51 of the first conductive type is formed on the surface of the body region;

[0054] Next, as Figure 12As shown, an interlayer film 60, contact holes 61, and a front metal layer 62 are formed, and the front metal layer is patterned to form an emitter and a gate;

[0055] Next, as Figure 13 shown, the back surface of the semiconductor substrate is subjected to conventional thinning, implantation activation, metallization, etc. to form a collector, and finally the device processing is completed.

[0056] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A shield-gate type IGBT device, characterized in that, Comprising: A plurality of trench structures formed in a semiconductor substrate (10) of a first doping type, the trench structures including a top trench (22) and a deep trench (30), the top trench (22) being located on both sides of the deep trench (30), and the top trench (22) being connected to the deep trench (30); a gate dielectric layer (24) is provided in the top trench (22) and a polysilicon gate (25) is filled; a first source dielectric layer (31) is formed on the bottom surface and side surfaces of the deep trench (30), lower polysilicon and upper polysilicon are filled in the deep trench (30), and a second source dielectric layer (43) is provided between the upper polysilicon and the lower polysilicon, the upper polysilicon being custom polysilicon (44), and the lower polysilicon being source polysilicon (32); A body region (50) of a second conductivity type is formed on the top of the semiconductor substrate (10), and an emitter region (51) of a first conductivity type is formed on the top of the body region (50); an interlayer film (60) is formed on the top of the emitter region (51) of the first conductivity type, and a front metal layer (62) is formed on the top of the interlayer film (60), and an emitter and a gate are etched on the front metal layer (62); A collector region (63) of a second conductivity type is formed on the bottom of the semiconductor substrate (10); The polysilicon gate (25) in the top trench (22) is connected to the gate through a first contact hole (61); The upper polysilicon in the deep trench (30) is connected to the emitter or the gate through a second contact hole (65); The length and depth of the upper polysilicon are set according to the size of the target capacitance.

2. The shield gate type IGBT device according to claim 1, characterized in that A collector metal (64) is provided at the bottom end of the collector region (63) of the second conductivity type.

3. The shield-gate type IGBT device according to claim 1, characterized in that, The bottom of the top trench (22) is higher than the bottom of the deep trench (30).

4. A method for manufacturing a shield gate type IGBT device according to any one of claims 1-3, characterized in that, Including the following steps: Step 1: Provide a semiconductor substrate, deposit a layer of silicon oxide on the semiconductor substrate as a mask, and define the formation region of the gate trench by photolithography, the gate trench including a plurality of; Step 2: Anisotropically and isotropically etch the semiconductor substrate in the formation region of the gate trench to form a top trench and an intermediate communication region; Step 3: Form a gate dielectric layer on the bottom surface and side surfaces of the top trench and the communication region and fill with a polysilicon gate; Step 4: Anisotropically etch the polysilicon gate and the gate dielectric layer to etch away the polysilicon gate and the gate dielectric layer in the communication region; Step 5: Anisotropically etch the semiconductor substrate to form a deep trench; Step 6: Form a first source dielectric layer and lower polysilicon on the bottom surface and side surfaces of the deep trench; And remove the silicon oxide on the surface of the semiconductor substrate; Step 7: Redeposit a layer of silicon oxide as a mask and define the formation region of the custom region by photolithography, the formation region of the custom region including a plurality of and being located in the formation region of the deep trench; Step 8: Etch the semiconductor substrate in the formation region of the custom region to form a custom region; Step Nine: Form a second source dielectric layer and upper polysilicon on the bottom surface and side surface of the custom area; And remove the silicon oxide on the surface of the semiconductor substrate; Step Ten: Form a body region of the second conductivity type on the surface of the semiconductor substrate between each gate structure through implantation and annealing processes, and form an emitter region heavily doped with the first conductivity type on the surface of the body region; Step Eleven: Form an interlayer film, contact holes, and a front metal layer, and pattern the front metal layer to form emitters and gates; Step Twelve: Thin the back surface of the semiconductor substrate, implant and activate, and metallize to form a collector, and finally complete the device processing.

5. The method according to claim 4, wherein The depth of the deep trench is 4 - 7 um calculated from the top of the semiconductor substrate.

6. The method according to claim 4, wherein The proportion of the two different structures existing in the deep trench is defined by the custom area defined by photolithography.

7. The method according to claim 4, wherein A charge storage layer of the first conductivity type is provided below the body region, and the resistivity of the charge storage layer is less than the resistivity of the semiconductor substrate.

8. The method according to claim 4, characterized in that, The gate dielectric, the first source dielectric layer, and the second source dielectric layer are silicon oxide.

9. The method according to claim 4, wherein The semiconductor substrate is silicon or silicon carbide.

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