Printed circuit board and substrate

Abstract

A printed circuit board and a substrate are provided. The printed circuit board includes a first insulating layer having a first modulus, a second insulating layer disposed on the first insulating layer and having a second modulus, and a cavity passing through the second insulating layer, wherein the second modulus is greater than the first modulus, and wherein an edge portion of a bottom surface of the cavity is formed with an insulating material.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0115386, filed on September 9, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a printed circuit board and a substrate. Background Technology

[0003] Because electronic devices (including mobile phones) in the information technology (IT) field have been designed to have reduced and simplified sizes, there is a need for technologies to insert electronic components such as integrated circuits (ICs) into printed circuit boards (PCBs) to meet these technical requirements. Technologies for embedding electronic components into PCBs in various ways have been developed. Therefore, various cavity structures can be formed on PCBs. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that can achieve a cavity through a sandblasting process without obstructions, and a substrate including the printed circuit board and electronic components embedded therein.

[0005] According to one aspect of this disclosure, by disposing an insulating layer having a relatively high modulus on an insulating layer having a relatively low modulus, and by using an insulating layer having a relatively low modulus as a barrier layer and forming a cavity through the insulating layer having a relatively high modulus by a sandblasting process, a printed circuit board having a cavity and a substrate including the printed circuit board and including embedded electronic components therein can be provided.

[0006] For example, according to one aspect of this disclosure, a printed circuit board may include: a first insulating layer having a first modulus; a second insulating layer disposed on the first insulating layer and having a second modulus; and a cavity passing through the second insulating layer, wherein the second modulus is greater than the first modulus, and wherein the edge of the bottom surface of the cavity is formed using an insulating material.

[0007] For example, according to one aspect of this disclosure, a substrate may include: a core structure including a first insulating body and a plurality of core wiring layers disposed on or within the first insulating body, and the core structure having a cavity; an electronic component disposed in the cavity; and a stacked structure including a second insulating body and one or more stacked wiring layers, the second insulating body covering at least a portion of each of the core structure and the electronic component and filling at least a portion of the cavity, the one or more stacked wiring layers being disposed on or within the second insulating body, wherein the first insulating body includes a first insulating layer and a second insulating layer, the first insulating layer having a first modulus, the second insulating layer being disposed on the first insulating layer and having a second modulus greater than the first modulus, wherein the cavity extends through the second insulating layer, and wherein the edge of the bottom surface of the cavity is formed using an insulating material.

[0008] For example, according to one aspect of this disclosure, a substrate may include: a first insulating body including a first insulating layer and a second insulating layer, the first insulating layer having a first etch rate for microblasting, the second insulating layer having a second etch rate for microblasting, the second etch rate being greater than the first etch rate; and a cavity penetrating the second insulating layer and exposing the surface of the first insulating layer. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an example of an electronic device system;

[0011] Figure 2 This is a perspective view showing an example of an electronic device;

[0012] Figure 3 This is a cross-sectional view showing an example of a printed circuit board;

[0013] Figure 4 It shows the view from above. Figure 3 The printed circuit board shown is a plan view.

[0014] Figure 5 It shows the manufacturing process. Figure 3 A diagram illustrating the manufacturing process of the printed circuit board shown;

[0015] Figure 6 This is a cross-sectional view showing another example of a printed circuit board;

[0016] Figure 7 and Figure 8 It shows the following respectively: Figure 6 Cross-sectional views of an example and another example of a printed circuit board substrate including embedded electronic components.

[0017] Figure 9 This is a cross-sectional view showing another example of a printed circuit board;

[0018] Figure 10 and Figure 11 It shows the following respectively: Figure 9 Cross-sectional views of an example and another example of a printed circuit board substrate including embedded electronic components.

[0019] Figure 12 This is a cross-sectional view showing another example of a printed circuit board;

[0020] Figure 13 and Figure 14 It shows the following respectively: Figure 12 Cross-sectional views of an example and another example of a printed circuit board substrate including embedded electronic components.

[0021] Figure 15 This is a cross-sectional view showing another example of a printed circuit board;

[0022] Figure 16 and Figure 17 It shows the following respectively: Figure 15 Cross-sectional views of an example and another example of a printed circuit board substrate including embedded electronic components.

[0023] Figure 18 This is a cross-sectional view showing another example of a printed circuit board;

[0024] Figure 19 and Figure 20 It shows the following respectively: Figure 18 Cross-sectional views of an example and another example of a printed circuit board substrate including embedded electronic components.

[0025] Figure 21 This is a cross-sectional view showing another example of a printed circuit board; and

[0026] Figure 22 and Figure 23 It shows the following respectively: Figure 21 The diagram shows cross-sectional views of an example and another example of a printed circuit board substrate containing embedded electronic components. Detailed Implementation

[0027] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, for clarity of description, the shape, size, etc., of elements may be exaggerated or simplified.

[0028] Figure 1 This is a block diagram illustrating an example of an electronic device system.

[0029] Reference Figure 1 The electronic device 1000 can house the motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 can be physically or electrically connected to the motherboard 1010. These components can be connected to other components described below via various signal lines 1090.

[0030] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may have a package form including the aforementioned chips.

[0031] Network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols specified after the protocols listed above. However, network-related components 1030 are not limited to these and may also include components that communicate based on various other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0032] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 or network-related components 1030.

[0033] Depending on the type of electronic device 1000, it may include other components that are physically or electrically connected to the motherboard 1010 or not physically or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), an optical disc (CD) drive, a digital versatile disc (DVD) drive, etc. However, these other components are not limited to these, and may include other components for various purposes, depending on the type of electronic device 1000.

[0034] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device that processes data.

[0035] Figure 2 This is a perspective view showing an example of an electronic device.

[0036] Reference Figure 2 The electronic device can be implemented via smartphone 1100. A motherboard 1110 can be housed within smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. A camera module 1130 and / or a speaker 1140 can be housed therein. Some of the electronic components 1120 can be, for example, chip-related components (such as component package 1121), but exemplary embodiments thereof are not limited thereto. In component package 1121, multiple electronic components can be disposed on a multilayer printed circuit board in a surface-mount configuration, but exemplary embodiments thereof are not limited thereto. The electronic device is not limited to smartphone 1100 and can be other electronic devices as described above.

[0037] Figure 3 This is a cross-sectional view showing an example of a printed circuit board.

[0038] Figure 4 This shows the view from above. Figure 3 The printed circuit board shown is a plan view.

[0039] Referring to the accompanying drawings, the printed circuit board 100 in the example embodiment may include: a first insulating layer 110a having a first elastic modulus (also referred to herein as "first modulus"); a second insulating layer 110b disposed on the first insulating layer 110a and having a second elastic modulus (also referred to herein as "second modulus"); and a cavity C passing through the second insulating layer 110b. If necessary, the printed circuit board 100 may further include: a first wiring layer 120a disposed on the first insulating layer 110a and exposed through the cavity C; a second wiring layer 120b disposed on the second insulating layer 110b; and / or a passivation layer 110c disposed on the second insulating layer 110b and covering the second wiring layer 120b. Each of the first insulating layer 110a and the second insulating layer 110b may include multiple insulating layers. For example, the first insulating layer 110a may include multiple insulating layers, each having a first modulus. Furthermore, the second insulating layer 110b may include multiple insulating layers, each having a second modulus.

[0040] Recently, technologies for embedding electronic devices into printed circuit boards (PCBs) in various ways have been developed, enabling the formation of various cavity structures within PCBs. For example, sandblasting has been considered for forming cavity structures to accommodate highly integrated substrates requiring fine pitch. To process cavities via sandblasting, it may be necessary to form a patterned layer, typically used as a barrier. However, forming a patterned layer as described above adds to the patterning process, increasing costs due to the additional steps. Furthermore, misalignment with the patterned layer can occur during cavity formation. Considering this issue, ensuring sufficient space may be necessary to reduce misalignment, but in such cases, minimizing dimensions may be difficult.

[0041] In the printed circuit board 100 of the example embodiment, a first insulating layer 110a with a relatively low modulus can be used as a barrier layer for machining cavity C using a sandblasting process. For example, in the sandblasting process, a second insulating layer 110b with a relatively high elastic modulus can be machined, while the first insulating layer 110a with a relatively low elastic modulus can be used as a barrier layer. Therefore, when the first insulating layer 110a is used as a barrier layer for machining cavity C, a patterned layer serving as a barrier for machining cavity C may be unnecessary. Thus, the number of process steps can be reduced, alignment problems can be avoided, and the size can be reduced. In this case, for example, the edge of the bottom surface of cavity C (i.e., the boundary between the first insulating layer 110a and the second insulating layer 110b) can be formed using an insulating material. For example, the insulating material includes the material of at least one of the first insulating layer 110a and the second insulating layer 110b.

[0042] Specifically, regarding the process used to form cavity C, techniques such as sandblasting (where the abrasive is pneumatically blasted and then machined) can be used, and the amount of etching can vary depending on the elastic modulus (also referred to herein as "modulus") and mechanical properties of the object to be processed. For example, the smaller the modulus, the smaller the amount of etching. Therefore, when the modulus of the first insulating layer 110a is lower than that of the second insulating layer 110b, the first insulating layer 110a can be effectively used as a barrier layer for processing cavity C. Modulus refers to the ratio of stress to strain. For example, a stress-strain curve from room temperature until fracture can be obtained using a universal testing machine (UTM), and the modulus can be obtained by expressing the slope of the initial deformation stage of the stress-strain curve in gigapascals (GPa), but exemplary embodiments are not limited thereto.

[0043] For example, as shown in [Table 1] below, material 1, which can be realized by a liquid crystal polymer (LCP) and can be used as the material for the first insulating layer 110a, may have a relatively low modulus, 5 GPa or less. Therefore, the amount etched by microblasting (uBlast) can be relatively small, about 1 μm. Material 2, which can be realized by prepreg (PPG) and can be used as the material for the second insulating layer 110b, may have a relatively high modulus, 20 GPa or higher. Therefore, the amount etched by microblasting can be relatively large, about 30 μm. Therefore, the modulus of material 2 may be about 4 times or more the modulus of material 1, and thus the amount etched by material 2 may be about 20 times or more the amount etched by material 1. In other words, the etching rate of the material for the second insulating layer used in the microblasting process is greater than the etching rate of the material for the first insulating layer. As an example, the second etching rate is at least ten times the first etching rate. Therefore, when a cavity C through the second insulating layer 110b is formed by the blasting process, the first insulating layer 110a can be effectively used as a barrier layer.

[0044] [Table 1]

[0045] category Modulus [GPa] Etching depth [μm] Material 1 3.1 1.1 Material 2 22-26，30-33 29.6

[0046] The material of the first insulating layer 110a is not limited to LCP, and materials with relatively low modulus, such as polyimide (PI) and Ajinomoto build-up film (ABF), can be used. Furthermore, the material of the second insulating layer 110b is not limited to PPG, and insulating materials of copper-clad laminates (CCL), i.e., materials with relatively high modulus, can be used. Therefore, as the material of the first insulating layer 110a, materials comprising insulating resin but without glass fiber or materials comprising insulating resin and inorganic fillers but without glass fiber can be used. Furthermore, as the material of the second insulating layer 110b, materials comprising insulating resin, inorganic fillers, and glass fiber can be used.

[0047] Each of the first wiring layer 120a and the second wiring layer 120b can perform various functions according to the design. For example, each of the first wiring layer 120a and the second wiring layer 120b may include ground patterns, power patterns, signal patterns, etc. Here, for example, signal patterns may include various signal patterns (such as data signal patterns) other than ground patterns and power patterns. Each of these patterns may have a line shape, a surface shape, or a pad shape. Each of the first wiring layer 120a and the second wiring layer 120b may be formed by plating processes (such as additive process (AP), semi-additive process (SAP), modified semi-additive process (MSAP), via sealing (TT) process, etc.), and may therefore include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. Metallic materials may be used as materials for the first wiring layer 120a and the second wiring layer 120b, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as metallic materials.

[0048] The passivation layer 110c protects the second wiring layer 120b from external physical and chemical damage. As the material for the passivation layer 110c, an insulating material can be used, and as the insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material composed of these resins mixed with an inorganic filler such as silica (such as ABF) can be used, but exemplary embodiments are not limited thereto.

[0049] Figure 5 It shows the manufacturing process. Figure 3 The diagram shows the manufacturing process of the printed circuit board.

[0050] Referring to the figure, firstly, a patterned dry film 190 can be formed on the second insulating layer 110b, exposing the location of the cavity. Subsequently, a microblasting process can be used to process the cavity C through the second insulating layer 110b. In this case, as described above, the first insulating layer 110a can be used as a barrier layer. The dry film 190 can be removed, and if necessary, a passivation layer 110c can be further formed. The printed circuit board 1000 in the above example embodiment can be manufactured through a series of processes, and since the description of other structures is the same as in the prior art, they will not be described in detail.

[0051] Figure 6 This is a cross-sectional view showing another example of a printed circuit board.

[0052] Reference Figure 6The printed circuit board 100A in the example embodiment may include multiple insulating layers (also referred to as core insulating layers) 111, 112, 113, 114, 115, 116, and 117, multiple wiring layers (also referred to as core wiring layers) 121, 122, 123, 124, 125, 126, 127, and 128, and multiple wiring via layers (also referred to as core wiring via layers) 131, 132, 133, 134, 135, 136, and 137, and may also include a passivation layer 150 if desired. Furthermore, the printed circuit board 100A may have a cavity C passing through a fifth insulating layer 115 and a seventh insulating layer 117 disposed above a third insulating layer 113. Therefore, the third insulating layer 113 can serve as a barrier layer for the sandblasting process used to form the cavity C. In this sense, the modulus of the third insulating layer 113 may be lower than the modulus of the fifth insulating layer 115 and the seventh insulating layer 117 in which the cavity C is formed.

[0053] Cavity C may expose at least a portion of the upper surface of the third insulating layer 113. Cavity C may have a tapered shape (its width gradually decreases in the downward direction in cross-section) and may have an annular shape such as a square ring in a plane. The exposed upper surface of the third insulating layer 113 may serve as the bottom surface of cavity C. The edge of the bottom surface of cavity C may be formed by the boundary between the third insulating layer 113 and the fifth insulating layer 115. The fourth wiring layer 124 may include: a first wiring pattern 124a disposed on the upper surface of the third insulating layer 113 and having at least a portion embedded in the fifth insulating layer 115; and a second wiring pattern 124b disposed on the upper surface of the third insulating layer 113 and having at least a portion exposed by cavity C. At least a portion of the fourth wiring layer 124 may be connected to at least a portion of a sixth wiring layer 126 disposed on the fifth insulating layer 115 via a fifth wiring via layer 135 passing through the fifth insulating layer 115.

[0054] In the following description, each of the elements included in a printed circuit board 100A according to an exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0055] The plurality of insulating layers 111, 112, 113, 114, 115, 116, and 117 may include: a first insulating layer 111; a second insulating layer 112 and a third insulating layer 113 disposed on both sides of the first insulating layer 111; a fourth insulating layer 114 and a fifth insulating layer 115 disposed on the second insulating layer 112 and the third insulating layer 113, respectively; and a sixth insulating layer 116 and a seventh insulating layer 117 disposed on the fourth insulating layer 114 and the fifth insulating layer 115, respectively. Therefore, each of the plurality of insulating layers 111, 112, 113, 114, 115, 116, and 117 may be a core-type insulating layer. The plurality of insulating layers 111, 112, 113, 114, 115, 116, and 117 may include a fewer number of insulating layers, or may include a greater number of insulating layers.

[0056] The insulating material can be used as the material for the plurality of insulating layers 111, 112, 113, 114, 115, 116, and 117, and can be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or the aforementioned resin including inorganic fillers such as silica and / or reinforcing materials such as glass fiber. Optionally, LCP and the like can be used as materials for specific insulating layers. For example, copper-clad laminate insulating material can be used as the material for the first insulating layer 111. In addition, PPG can be used as the material for the second insulating layer 112, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117. In addition, ABF, LCP, PI (polyimide), etc. can be used as the material for the third insulating layer 113. The thickness of the first insulating layer 111 can be greater than the thickness of each of the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117.

[0057] The plurality of wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 may include: a first wiring layer 121 and a second wiring layer 122 disposed on both sides of a first insulating layer 111; a third wiring layer 123 and a fourth wiring layer 124 disposed on the second insulating layer 112 and the third insulating layer 113, respectively, and embedded in the fourth insulating layer 114 and the fifth insulating layer 115, respectively; a fifth wiring layer 125 and a sixth wiring layer 126 disposed on the fourth insulating layer 114 and the fifth insulating layer 115, respectively, and embedded in the sixth insulating layer 116 and the seventh insulating layer 117, respectively; and a seventh wiring layer 127 and an eighth wiring layer 128 disposed on the sixth insulating layer 116 and the seventh insulating layer 117, respectively. The plurality of wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 may include fewer wiring layers or may include more wiring layers.

[0058] Metallic materials can be used as the materials for the multiple wiring layers 121, 122, 123, 124, 125, 126, 127, and 128, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the metallic materials. Each of the multiple wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 can perform various functions according to the design. For example, the multiple wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 may include ground patterns, power patterns, signal patterns, etc. Here, for example, signal patterns may include various signal patterns (such as data signal patterns) other than ground patterns and power patterns. Each of these patterns may have a line shape, a surface shape, or a pad shape. Multiple wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 may be formed by plating processes such as AP, SAP, MSAP, or TT, and may therefore include a seed layer (without plating) and an electroplated layer formed based on the seed layer. Certain layers may also include copper foil.

[0059] Multiple wiring via layers 131, 132, 133, 134, 135, 136, and 137 may include: a first wiring via layer 131, passing through a first insulating layer 111 and connecting the first wiring layer 121 and the second wiring layer 122 to each other; a second wiring via layer 132, passing through a second insulating layer 112 and connecting the first wiring layer 121 and the third wiring layer 123 to each other; a third wiring via layer 133, passing through a third insulating layer 113 and connecting the second wiring layer 122 and the fourth wiring layer 124 to each other; and a fourth wiring via layer 124. Via layer 134 passes through fourth insulating layer 114 and connects third wiring layer 123 and fifth wiring layer 125 to each other; fifth wiring via layer 135 passes through fifth insulating layer 115 and connects fourth wiring layer 124 and sixth wiring layer 126 to each other; sixth wiring via layer 136 passes through sixth insulating layer 116 and connects fifth wiring layer 125 and seventh wiring layer 127 to each other; and seventh wiring via layer 137 passes through seventh insulating layer 117 and connects sixth wiring layer 126 and eighth wiring layer 128 to each other. Multiple wiring via layers 131, 132, 133, 134, 135, 136, and 137 may include fewer wiring via layers or more wiring via layers.

[0060] Metallic materials can be used for the multiple wiring via layers 131, 132, 133, 134, 135, 136, and 137, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the metallic material. Depending on the design, each of the multiple wiring via layers 131, 132, 133, 134, 135, 136, and 137 may include signal connection vias, ground connection vias, power connection vias, etc. The wiring vias of the multiple wiring via layers 131, 132, 133, 134, 135, 136, and 137 may be completely filled with metallic material, or metallic material may be formed along the wall surface of the via. The first wiring via layer 131 may have an hourglass shape or a cylindrical shape. Each of the second wiring via layer 132, the third wiring via layer 133, the fourth wiring via layer 134, the fifth wiring via layer 135, the sixth wiring via layer 136, and the seventh wiring via layer 137 may have a tapered shape. The second wiring via layer 132, the fourth wiring via layer 134, and the sixth wiring via layer 136, along with the third wiring via layer 133, the fifth wiring via layer 135, and the seventh wiring via layer 137, may have a tapered shape formed to taper in opposite directions. For example, the plurality of wiring via layers 131, 132, 133, 134, 135, 136, and 137 may be formed by plating processes such as AP, SAP, MSAP, TT, etc., and thus may include electroless plating layers (seed layers) and electroplated layers formed based on seed layers.

[0061] The passivation layer 150 protects the bottommost seventh wiring layer 127 from external physical and chemical damage. The passivation layer 150 may be disposed on the bottommost sixth insulating layer 116 and may cover the bottommost seventh wiring layer 127. If desired, openings may be formed in the passivation layer 150 to expose at least a portion of the bottommost seventh wiring layer 127. The material of the passivation layer 150 may be an insulating material. In this case, for example, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials composed of these resins mixed with inorganic fillers (such as ABF) may be used, but exemplary embodiments are not limited thereto.

[0062] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be repeated.

[0063] Figure 7 It shows including Figure 6 The diagram shows a cross-sectional view of an example of a substrate for a printed circuit board, including embedded electronic components.

[0064] Referring to the accompanying drawings, the substrate 500A1 in the exemplary embodiment, including embedded electronic components, may include: a core structure 10 having a cavity C; a first electronic component 210 disposed in the cavity C; and a stacked structure 20 disposed on the core structure 10 and the first electronic component 210. If desired, the substrate 500A1 may further include at least one of the following: a first passivation layer 150 disposed below the core structure 10; a second passivation layer 350 disposed above the stacked structure 20; a first electrical connection metal element 155 disposed on an opening in the first passivation layer 150; a second electrical connection metal element 355 disposed on an opening in the second passivation layer 350; and a second electronic component 410 and a third electronic component 420, surface-mounted on the stacked structure 20.

[0065] The core structure 10 may include: a first insulating body comprising a plurality of core insulating layers 111, 112, 113, 114, 115, 116, and 117; a plurality of core wiring layers 121, 122, 123, 124, 125, 126, 127, and 128 disposed on or within the first insulating body; and a plurality of core wiring via layers 131, 132, 133, 134, 135, 136, and 137 passing through a portion of the first insulating body and connected to the plurality of core wiring layers 121, 122, 123, 124, 125, 126, 127, and 128. The cavity C of the core structure 10 may pass through a fifth core insulating layer 115 and a seventh core insulating layer 117 disposed above a third core insulating layer 113. Therefore, the third core insulating layer 113 may serve as a barrier layer for the sandblasting process used to form the cavity C. In this case, the modulus of the third core insulating layer 113 may be lower than the modulus of the fifth core insulating layer 115 and the seventh core insulating layer 117 that form the cavity C therein.

[0066] The first electronic component 210 may be disposed in the cavity C. The first electronic component 210 may be configured as an IC in which hundreds to millions of devices are integrated into a single chip. For example, the first electronic component 210 may be implemented by a processor chip such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, and may be implemented by, for example, an application processor (AP), although exemplary embodiments are not limited thereto, and may be implemented by a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc., or a logic chip such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). The first electronic component 210 may be configured to face downwards such that the connection pad 210P is electrically connected via a connection member 250, such as solder adhesive, to at least a portion of the fourth wiring layer 124 exposed through the cavity C. For example, the first electronic component 210 may be configured as a surface-mount passive component (such as a surface-mount inductor or a surface-mount capacitor). The first electronic component 210 can be a combination of a passive component in chip form and an IC, and in this case, multiple cavities C can be formed.

[0067] The stacked structure 20 may include: a second insulating body covering at least a portion of each of the core structure 10 and the first electronic component 210, filling at least a portion of the cavity C, and including one or more stacked insulating layers 311, 312 and 313; one or more stacked wiring layers 321, 322 and 323 disposed on or in the second insulating body; and one or more stacked wiring via layers 331, 332 and 333, each passing through a portion of the second insulating body and connected to one or more stacked wiring layers 321, 322 and 323.

[0068] The second insulating body may include one or more stacked insulating layers 311, 312, and 313, and the number of stacked insulating layers 311, 312, and 313 may be greater than or less than the examples in the figures. The insulating material may be used as the material of the second insulating body, and as the insulating material, for example, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials formed by mixing these resins with inorganic fillers (such as ABF) may be used, but the exemplary embodiments are not limited thereto. If desired, for example, materials that also include reinforcing materials such as glass fibers (such as PPG) may be used.

[0069] The number of one or more stacked wiring layers 321, 322, and 323 may be greater than or less than the examples shown in the figures. Metallic materials may be used for the one or more stacked wiring layers 321, 322, and 323, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as metallic materials. Each of the one or more stacked wiring layers 321, 322, and 323 may perform various functions depending on the design. For example, one or more stacked wiring layers 321, 322, and 323 may include ground patterns, power patterns, signal patterns, etc. Each of these patterns may have a line shape, a surface shape, or a pad shape. One or more stacked wiring layers 321, 322, and 323 may be formed by plating processes (such as AP, SAP, MSAP, TT, etc.), and may therefore include a seed layer (unplated layer) and an electroplated layer formed based on the seed layer. Certain layers may also include copper foil.

[0070] The number of one or more stacked wiring via layers 331, 332, and 333 may be greater than or less than the examples in the figures, and a metallic material may be used for the one or more stacked wiring via layers 331, 332, and 333, and the metallic material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the design, each of the one or more stacked wiring via layers 331, 332, and 333 may include signal connection vias, ground connection vias, and power connection vias. Each of the wiring vias in the one or more stacked wiring via layers 331, 332, and 333 may be completely filled with metallic material, or the metallic material may be formed along the wall surface of the via. The one or more stacked wiring via layers 331, 332, and 333 may have a tapered shape. For example, one or more stacked wiring via layers 331, 332 and 333 may be formed by plating processes (such as AP, SAP, MSAP, TT, etc.) and may include a seed layer (without plating) and an electroplated layer formed based on the seed layer.

[0071] The first passivation layer 150 and the second passivation layer 350 respectively protect the lowermost seventh core wiring layer 127 and the uppermost third stacked wiring layer 323 from external physical and chemical damage. The first passivation layer 150 and the second passivation layer 350 may each have an opening for exposing at least a portion of the lowermost seventh core wiring layer 127 and an opening for exposing at least a portion of the uppermost third stacked wiring layer 323. Multiple openings may be provided. The insulating material may be the same material used for the first passivation layer 150 and the second passivation layer 350. In this case, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or mixtures of these resins with inorganic fillers (such as ABF) may be used, but exemplary embodiments are not limited thereto.

[0072] The first electrical connection metal element 155 and the second electrical connection metal element 355 may be disposed on the openings of the first passivation layer 150 and the second passivation layer 350, respectively. The first electrical connection metal element 155 and the second electrical connection metal element 355 may be connected to at least the exposed portion of the lowermost seventh core wiring layer 127 and at least the exposed portion of the uppermost third stacked wiring layer 323, respectively. The first electrical connection metal element 155 may physically connect and / or electrically connect the substrate 500A1 to an external entity. For example, the substrate 500A1 may be mounted on the motherboard or ball grid array (BGA) substrate of an electronic device via the first electrical connection metal element 155. The second electrical connection metal element 355 may physically connect and / or electrically connect the substrate 500A1 to a second electronic component 410 and a third electronic component 420 surface-mounted on the substrate 500A1. The first electrical connection metal element 155 and the second electrical connection metal element 355 may be formed using tin (Sn) or an alloy including tin (Sn) (such as solder), but exemplary embodiments thereof are not limited thereto. Each of the first electrical connection metal part 155 and the second electrical connection metal part 355 can be configured as a pad, solder ball, pin, etc.

[0073] The second electronic component 410 and the third electronic component 420 may be configured as surface-mount components. The second electronic component 410 and the third electronic component 420 may be active components and / or passive components, respectively. Examples of active components may include the IC described in relation to the first electronic component 210. Examples of passive components may include chip capacitors such as multilayer ceramic capacitors (MLCCs) and chip inductors such as power inductors (PIs). If desired, a molding material covering the second electronic component 410 and the third electronic component 420 may also be provided on the second passivation layer 350, and the molding material may be a general-purpose epoxy molding compound (EMC), but exemplary embodiments thereof are not limited thereto. When the second electronic component 410 and the third electronic component 420 are also provided, the substrate 500A1 may be used as a system-in-package (SiP).

[0074] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0075] Figure 8 It shows including Figure 6 A cross-sectional view of another example of a substrate for a printed circuit board, including embedded electronic components.

[0076] Referring to the accompanying drawings, compared to the substrate 500A1 described in the foregoing exemplary embodiments, in the substrate 500A2 of the exemplary embodiments, which includes embedded electronic components, the first electronic component 210 may be configured to face upwards in the cavity C. The first electronic component 210 may be attached to the bottom surface of the cavity C via an adhesive member 240 (such as a die attachment film (DAF)). The connection pads 210P of the first electronic component 210 may be electrically connected to at least a portion of the first stacked wiring layer 321 via at least a portion of the first stacked wiring via layer 331. At least a portion of the first core wiring layer 121, the second core wiring layer 122, the third core wiring layer 123, the fourth core wiring layer 124, the fifth core wiring layer 125, and the seventh core wiring layer 127, as well as at least a portion of the first core wiring via layer 131, the second core wiring via layer 132, the third core wiring via layer 133, the fourth core wiring via layer 134, and the sixth core wiring via layer 136, may be disposed below the first electronic component 210 and may be used as a heat dissipation path for heat dissipation from the rear surface of the first electronic component 210.

[0077] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0078] Figure 9 This is a cross-sectional view showing another example of a printed circuit board.

[0079] Referring to the accompanying drawings, the printed circuit board 100B in the example embodiment may include multiple insulating layers 111, 112, 113, 114, and 115, multiple wiring layers 121, 122, 123, 124, 125, and 126, and multiple wiring via layers 131, 132, 133, 134, and 135, and may also include a passivation layer 150 if desired. Furthermore, the printed circuit board 100B may also include a cavity C that passes through a fourth insulating layer 114 and a fifth insulating layer 115 disposed above the third insulating layer 113. Therefore, the third insulating layer 113 can serve as a barrier layer for the sandblasting process used to form the cavity C. Consequently, the modulus of the third insulating layer 113 may be lower than the modulus of the fourth insulating layer 114 and the fifth insulating layer 115 in which the cavity C is formed.

[0080] Cavity C may expose at least a portion of the upper surface of the third insulating layer 113. Cavity C may have a tapered shape (its width gradually decreases in the downward direction in cross-section) and may have an annular shape such as a square ring in a plane. The exposed upper surface of the third insulating layer 113 may serve as the bottom surface of cavity C. The edge of the bottom surface of cavity C may be formed by the boundary between the third insulating layer 113 and the fourth insulating layer 114. The fourth wiring layer 124 may include: a first wiring pattern 124a disposed on the upper surface of the third insulating layer 113 and having at least a portion embedded in the fourth insulating layer 114; and a second wiring pattern 124b disposed on the upper surface of the third insulating layer 113 and having at least a portion exposed by cavity C. At least a portion of the fourth wiring layer 124 may be connected to at least a portion of a fifth wiring layer 125 disposed on the fourth insulating layer 114 via a fourth wiring via layer 134 passing through the fourth insulating layer 114.

[0081] In the following description, each of the components included in the printed circuit board 100B according to the example will be described in more detail with reference to the accompanying drawings.

[0082] The plurality of insulating layers 111, 112, 113, 114, and 115 may include: a first insulating layer 111; a second insulating layer 112 disposed on the first insulating layer 111; a third insulating layer 113 disposed on the second insulating layer 112; a fourth insulating layer 114 disposed on the third insulating layer 113; and a fifth insulating layer 115 disposed on the fourth insulating layer 114. Therefore, the plurality of insulating layers 111, 112, 113, 114, and 115 may be coreless. The plurality of insulating layers 111, 112, 113, 114, and 115 may include fewer or more insulating layers.

[0083] The insulating material can be used as the material for the multiple insulating layers 111, 112, 113, 114, and 115, and as the insulating material, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or the aforementioned resins including inorganic fillers such as silica and / or reinforcing materials such as glass fibers can be used. Optionally, LCP and the like can be used as the material for a particular insulating layer. For example, PPG can be used as the material for the first insulating layer 111, the second insulating layer 112, the fourth insulating layer 114, and the fifth insulating layer 115. Furthermore, ABF, LCP, PI (polyimide), etc., can be used as the material for the third insulating layer 113. The thicknesses of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 can be substantially the same, but exemplary embodiments are not limited thereto.

[0084] The plurality of wiring layers 121, 122, 123, 124, 125, and 126 may include: a first wiring layer 121, embedded on the underside of a first insulating layer 111; a second wiring layer 122, disposed on the upper surface of the first insulating layer 111 and embedded below the second insulating layer 112; a third wiring layer 123, disposed on the upper surface of the second insulating layer 112 and embedded below the third insulating layer 113; a fourth wiring layer 124, disposed on the upper surface of the third insulating layer 113 and embedded below the fourth insulating layer 114; a fifth wiring layer 125, disposed on the upper surface of the fourth insulating layer 114 and embedded below the fifth insulating layer 115; and a sixth wiring layer 126, disposed on the upper surface of the fifth insulating layer 115. The plurality of wiring layers 121, 122, 123, 124, 125, and 126 may include a greater number of wiring layers or a lesser number of wiring layers.

[0085] Metallic materials can be used for the multiple wiring layers 121, 122, 123, 124, 125, and 126, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the metallic material. Each of the multiple wiring layers 121, 122, 123, 124, 125, and 126 can perform various functions according to the design. For example, the multiple wiring layers 121, 122, 123, 124, 125, and 126 may include ground patterns, power patterns, signal patterns, etc. Each of these patterns may have a line shape, a surface shape, or a pad shape. Furthermore, the multiple wiring layers 121, 122, 123, 124, 125, and 126 can be formed by plating processes such as AP, SAP, MSAP, TT, etc., and therefore may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. Certain layers may also include copper foil.

[0086] The plurality of wiring via layers 131, 132, 133, 134, and 135 may include: a first wiring via layer 131, which passes through a first insulating layer 111 and connects the first wiring layer 121 and the second wiring layer 122 to each other; a second wiring via layer 132, which passes through a second insulating layer 112 and connects the second wiring layer 122 and the third wiring layer 123 to each other; a third wiring via layer 133, which passes through a third insulating layer 113 and connects the third wiring layer 123 and the fourth wiring layer 124 to each other; a fourth wiring via layer 134, which passes through a fourth insulating layer 114 and connects the fourth wiring layer 124 and the fifth wiring layer 125 to each other; and a fifth wiring via layer 135, which passes through a fifth insulating layer 115 and connects the fifth wiring layer 125 and the sixth wiring layer 126 to each other. The plurality of wiring via layers 131, 132, 133, 134, and 135 may include fewer wiring via layers or may include more wiring via layers.

[0087] Metallic materials can be used for the multiple wiring via layers 131, 132, 133, 134, and 135, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used as the metallic material. Depending on the design, each of the multiple wiring via layers 131, 132, 133, 134, and 135 may include signal connection vias, ground connection vias, power connection vias, etc. The wiring vias of the multiple wiring via layers 131, 132, 133, 134, and 135 may be completely filled with metallic material, or metallic material may be formed along the wall surface of the via. Each of the multiple wiring via layers 131, 132, 133, 134, and 135 may have a tapered shape that tapers in the same direction. In addition, the multiple wiring via layers 131, 132, 133, 134 and 135 can be formed by plating processes such as AP, SAP, MSAP, TT, etc., and therefore may include seed layers (unplated layers) and plating layers formed based on seed layers.

[0088] The passivation layer 150 protects the bottommost first wiring layer 121 from external physical and chemical damage. The passivation layer 150 may be disposed on the bottommost first insulating layer 111 and may cover the bottommost first wiring layer 121. If desired, openings may be formed in the passivation layer 150 to expose at least a portion of the first wiring layer 121. An insulating material may be used as the material for the passivation layer 150. In this case, for example, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials formed by mixing these resins with inorganic fillers (such as ABF) may be used, but exemplary embodiments are not limited thereto.

[0089] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0090] Figure 10 It shows including Figure 9 A cross-sectional view of another example of a substrate for a printed circuit board, including embedded electronic components.

[0091] Referring to the accompanying drawings, the substrate 500B1 in the exemplary embodiment, including embedded electronic components, may include: a core structure 10 having a cavity C; a first electronic component 210 disposed in the cavity C; and a stacked structure 20 disposed on the core structure 10 and the first electronic component 210. If desired, the substrate 500B1 may further include at least one of the following: a first passivation layer 150 disposed below the core structure 10; a second passivation layer 350 disposed above the stacked structure 20; a first electrical connection metal element 155 disposed on an opening of the first passivation layer 150; a second electrical connection metal element 355 disposed on an opening of the second passivation layer 350; and a second electronic component 410 and a third electronic component 420, mounted on the stacked structure 20 via the surface of the second electrical connection metal element 355.

[0092] The core structure 10 may include: a first insulating body comprising a plurality of core insulating layers 111, 112, 113, 114, and 115; a plurality of core wiring layers 121, 122, 123, 124, 125, and 126 disposed on or within the first insulating body; and a plurality of core wiring via layers 131, 132, 133, 134, and 135 passing through a portion of the first insulating body and connected to the plurality of core wiring layers 121, 122, 123, 124, 125, and 126. The cavity C of the core structure 10 may pass through a fourth core insulating layer 114 and a fifth core insulating layer 115 disposed above a third core insulating layer 113. Therefore, the third core insulating layer 113 may serve as a barrier layer for the sandblasting process used to form the cavity C. In this case, the modulus of the third core insulating layer 113 may be lower than the modulus of the fourth core insulating layer 114 and the fifth core insulating layer 115 in which the cavity C is formed.

[0093] The first electronic component 210 may be disposed in the cavity C. The first electronic component 210 may be configured as an IC in which hundreds to millions of devices are integrated into a single chip. For example, the first electronic component 210 may be implemented by a processor chip such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, and may be implemented by, for example, an application processor (AP), although exemplary embodiments are not limited thereto, and may be implemented by a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc., or a logic chip such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). The first electronic component 210 may be configured to face downwards such that the connection pad 210P is electrically connected via a connection member 250, such as solder adhesive, to at least a portion of the fourth wiring layer 124 exposed through the cavity C. For example, the first electronic component 210 may be configured as a surface-mount passive component (such as a surface-mount inductor or a surface-mount capacitor). The first electronic component 210 can be a combination of a passive component in chip form and an IC, and in this case, multiple cavities C can be formed.

[0094] The stacked structure 20 may include: a second insulating body covering at least a portion of each of the core structure 10 and the first electronic component 210, filling at least a portion of the cavity C, and including one or more stacked insulating layers 311, 312 and 313; one or more stacked wiring layers 321, 322 and 323 disposed on or in the second insulating body; and one or more stacked wiring via layers 331, 332 and 333, each passing through a portion of the second insulating body and connected to one or more stacked wiring layers 321, 322 and 323.

[0095] The second insulating body may include one or more stacked insulating layers 311, 312, and 313, and the number of stacked insulating layers 311, 312, and 313 may be greater than or less than the examples in the figures. The insulating material may be used as the material of the second insulating body, and as the insulating material, for example, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials formed by mixing these resins with inorganic fillers (such as ABF) may be used, but the exemplary embodiments are not limited thereto. If desired, for example, materials that also include reinforcing materials (such as glass fibers) (such as PPG) may be used.

[0096] The number of one or more stacked wiring layers 321, 322, and 323 may be greater than or less than the examples shown in the figures. Metallic materials may be used for the one or more stacked wiring layers 321, 322, and 323, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as metallic materials. Each of the one or more stacked wiring layers 321, 322, and 323 may perform various functions depending on the design. For example, one or more stacked wiring layers 321, 322, and 323 may include ground patterns, power patterns, signal patterns, etc. Each of these patterns may have a line shape, a surface shape, or a pad shape. One or more stacked wiring layers 321, 322, and 323 may be formed by plating processes (such as AP, SAP, MSAP, TT, etc.), and may therefore include a seed layer (unplated layer) and an electroplated layer formed based on the seed layer. Certain layers may also include copper foil.

[0097] The number of one or more stacked via layers 331, 332, and 333 may be greater than or less than the examples in the figures, and a metallic material may be used for the one or more stacked via layers 331, 332, and 333. The metallic material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the design, each of the one or more stacked via layers 331, 332, and 333 may include signal connection vias, ground connection vias, and power connection vias. Each of the vias in the one or more stacked via layers 331, 332, and 333 may be completely filled with metallic material, or metallic material may be formed along the wall surface of the via. The one or more stacked via layers 331, 332, and 333 may have a tapered shape. For example, one or more stacked wiring via layers 331, 332 and 333 may be formed by plating processes (such as AP, SAP, MSAP, TT, etc.) and may include a seed layer (without plating) and an electroplated layer formed based on the seed layer.

[0098] The first passivation layer 150 and the second passivation layer 350 respectively protect the lowermost first core wiring layer 121 and the uppermost third stacked wiring layer 323 from external physical and chemical damage. The first passivation layer 150 and the second passivation layer 350 may each have an opening for exposing at least a portion of the lowermost first core wiring layer 121 and an opening for exposing at least a portion of the uppermost third stacked wiring layer 323. Multiple openings may be provided. The insulating material may be the same material used for the first passivation layer 150 and the second passivation layer 350. In this case, thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or mixtures of these resins with inorganic fillers (such as ABF) may be used, but exemplary embodiments are not limited thereto.

[0099] The first electrical connection metal element 155 and the second electrical connection metal element 355 may be disposed on the openings of the first passivation layer 150 and the second passivation layer 350, respectively. The first electrical connection metal element 155 and the second electrical connection metal element 355 may be connected to at least exposed portions of the lowermost first core wiring layer 121 and at least exposed portions of the uppermost third stacked wiring layer 323, respectively. The first electrical connection metal element 155 may physically connect and / or electrically connect the substrate 500B1 to an external entity. For example, the substrate 500B1 may be mounted on a motherboard or BGA substrate of an electronic device via the first electrical connection metal element 155. The second electrical connection metal element 355 may physically connect and / or electrically connect the substrate 500B1 to a second electronic component 410 and a third electronic component 420 surface-mounted on the substrate 500B1. The first electrical connection metal element 155 and the second electrical connection metal element 355 may be formed using tin (Sn) or alloys including tin (Sn), such as solder, but exemplary embodiments thereof are not limited thereto. Each of the first electrical connection metal part 155 and the second electrical connection metal part 355 can be configured as a pad, solder ball, pin, etc.

[0100] The second electronic component 410 and the third electronic component 420 may be configured as surface-mount components. The second electronic component 410 and the third electronic component 420 may be active components and / or passive components, respectively. Examples of active components may include the IC described in relation to the first electronic component 210. Examples of passive components may include chip capacitors such as multilayer ceramic capacitors (MLCCs) and chip inductors such as power inductors (PIs). If desired, a molding material covering the second electronic component 410 and the third electronic component 420 may also be provided on the second passivation layer 350, and the molding material may be a general-purpose epoxy molding compound (EMC), but exemplary embodiments thereof are not limited thereto. When the second electronic component 410 and the third electronic component 420 are also provided, the substrate 500B1 with embedded electronic components can be used as a system-in-package (SiP).

[0101] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0102] Figure 11 It shows including Figure 9 A cross-sectional view of another example of a substrate for a printed circuit board, including embedded electronic components.

[0103] Referring to the accompanying drawings, compared to the substrate 500B1 with embedded electronic components described in the foregoing example embodiment, in the substrate 500B2 with embedded electronic components in the example embodiment, the first electronic component 210 may be positioned facing upwards in the cavity C. The first electronic component 210 may be attached to the bottom surface of the cavity C via an adhesive member 240 such as a DAF. The connection pads 210P of the first electronic component 210 may be electrically connected to at least a portion of the first stacked wiring layer 321 via at least a portion of the first stacked wiring via layer 331. At least a portion of the first core wiring layer 121, the second core wiring layer 122, the third core wiring layer 123, and the fourth core wiring layer 124, and at least a portion of the first core wiring via layer 131, the second core wiring via layer 132, and the third core wiring via layer 133 may be disposed below the first electronic component 210 and may serve as a heat dissipation path for dissipating heat received from the rear surface of the first electronic component 210.

[0104] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0105] Figure 12 This is a cross-sectional view showing another example of a printed circuit board.

[0106] Figure 13 and Figure 14 It shows the following respectively: Figure 12 The diagram shows cross-sectional views of an example and another example of a printed circuit board substrate containing embedded electronic components.

[0107] Referring to the accompanying drawings, compared to printed circuit board 100A and substrates 500A1 and 500A2 including printed circuit board 100A and embedded electronic components therein, in the exemplary embodiment of printed circuit board 100C and substrates 500C1 and 500C2 including printed circuit board 100C and embedded electronic components therein, a fifth insulating layer 115, instead of a third insulating layer 113, can be used as a barrier layer. In this case, the modulus of the fifth insulating layer 115 may be smaller than the modulus of the seventh insulating layer 117 in which the cavity C is formed. The cavity C may further penetrate a portion of the fifth insulating layer 115, such that the upper surface of the fifth insulating layer 115 may have a height difference, and the cavity C may expose at least a portion of the upper surface of the fifth insulating layer 115. Therefore, there may be a height difference between the upper surface of the fifth insulating layer 115 in the area covered by the seventh insulating layer 117 and the upper surface of the fifth insulating layer 115 in the area exposed from the cavity C. The fourth wiring layer 124 may include a first wiring pattern 124a and a second wiring pattern 124b. Both the first wiring pattern 124a and the second wiring pattern 124b may be disposed on the upper surface of the third insulating layer 113 and each may have at least a portion embedded in the fifth insulating layer 115. The upper surface of the first wiring pattern 124a may be covered by the fifth insulating layer 115, while the upper surface of the second wiring pattern 124b may be exposed by the cavity C. The upper surface of the second wiring pattern 124b exposed by the cavity C may have a height difference from the upper surface of the fifth insulating layer 115, which is the bottom surface of the cavity C.

[0108] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0109] Figure 15 This is a cross-sectional view showing another example of a printed circuit board.

[0110] Figure 16 and Figure 17 It shows the following respectively: Figure 15 The diagram shows cross-sectional views of an example and another example of a printed circuit board substrate containing embedded electronic components.

[0111] Referring to the accompanying drawings, compared to the printed circuit board 100B and substrates 500B1 and 500B2 including the printed circuit board 100B and embedded electronic components therein described in the foregoing example embodiments, in the printed circuit board 100D and substrates 500D1 and 500D2 including the printed circuit board 100D and embedded electronic components therein described in the example embodiments, a fourth insulating layer 114, instead of a third insulating layer 113, can be used as a barrier layer. In this case, the modulus of the fourth insulating layer 114 may be lower than the modulus of the fifth insulating layer 115 in which the cavity C is formed. The cavity C may further penetrate a portion of the fourth insulating layer 114, such that the upper surface of the fourth insulating layer 114 may have a height difference, and the cavity C may expose at least a portion of the upper surface of the fourth insulating layer 114. Therefore, there may be a height difference between the upper surface of the fourth insulating layer 114 in the region covered by the fifth insulating layer 115 and the upper surface of the fourth insulating layer 114 in the region exposed from the cavity C. The fourth wiring layer 124 may be disposed on the upper surface of the third insulating layer 113, and may include a first wiring pattern 124a and a second wiring pattern 124b, both of which have at least a portion embedded in the fourth insulating layer 114. The upper surface of the first wiring pattern 124a may be covered by the fourth insulating layer 114, while the upper surface of the second wiring pattern 124b may be exposed by the cavity C. The upper surface of the second wiring pattern 124b exposed by the cavity C may have a height difference with the upper surface of the fourth insulating layer 114 that is set as the bottom surface of the cavity C.

[0112] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0113] Figure 18 This is a cross-sectional view showing another example of a printed circuit board.

[0114] Figure 19 and Figure 20 It shows the following respectively: Figure 18 The diagram shows cross-sectional views of an example and another example of a printed circuit board substrate containing embedded electronic components.

[0115] Referring to the accompanying drawings, compared to the printed circuit board 100A and substrates 500A1 and 500A2 including the printed circuit board 100A and embedded electronic components described in the foregoing example embodiments, in the printed circuit board 100E and substrates 500E1 and 500E2 including the printed circuit board 100E and embedded electronic components described in the foregoing example embodiments, a fourth insulating layer 114, instead of a third insulating layer 113, can be used as a barrier layer. In this case, the modulus of the fourth insulating layer 114 may be lower than the modulus of the first insulating layer 111, second insulating layer 112, third insulating layer 113, fifth insulating layer 115, and seventh insulating layer 117 in which the cavity C is formed. The cavity C may expose at least a portion of the upper surface of the fourth insulating layer 114. The third wiring layer 123 may include: a first wiring pattern 123a, at least a portion of which is embedded in the fourth insulating layer 114 such that at least a portion of its upper surface can be covered by the second insulating layer 112; and a second wiring pattern 123b, embedded in the fourth insulating layer 114 such that at least a portion of its upper surface is exposed through the cavity C. At least a portion of the third wiring layer 123 may be connected to the first wiring layer 121 embedded in the second insulating layer 112 via a second wiring via layer 132, the second wiring via layer 132 passing through the second insulating layer 112 such that its upper surface can be connected to at least a portion of the first wiring layer 121.

[0116] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0117] Figure 21 This is a cross-sectional view showing another example of a printed circuit board.

[0118] Figure 22 and Figure 23 It shows the following respectively: Figure 21 The diagram shows cross-sectional views of an example and another example of a printed circuit board substrate containing embedded electronic components.

[0119] Referring to the accompanying drawings, compared to the printed circuit board 100B and substrates 500B1 and 500B2 including the printed circuit board 100B and embedded electronic components therein described in the foregoing example embodiments, in the printed circuit board 100F and substrates 500F1 and 500F2 including the printed circuit board 100F and embedded electronic components therein, a fourth insulating layer 114, instead of the third insulating layer 113, can be used as a barrier layer and can be inverted. In this case, the modulus of the fourth insulating layer 114 can be lower than the modulus of the insulating layers 111, 112, and 113 in which the cavity C is formed. The cavity C can expose at least a portion of the upper surface of the fourth insulating layer 114. The fourth wiring layer 124 may include: a first wiring pattern 124a, at least a portion of which is embedded in the fourth insulating layer 114 such that at least a portion of its upper surface is covered by the third insulating layer 113; and a second wiring pattern 124b, which is embedded in the fourth insulating layer 114 such that at least a portion of its upper surface is exposed by the cavity C. At least a portion of the fourth wiring layer 124 can be connected to the third wiring layer 123 embedded in the third insulating layer 113 through the third wiring via layer 133, the third wiring via layer 133 passing through the third insulating layer 113 such that its upper surface can be connected to at least a portion of the third wiring layer 123.

[0120] Since the descriptions of the other components are the same as those described above, their detailed descriptions will not be provided.

[0121] According to the foregoing example embodiments, a printed circuit board that can achieve a cavity through a sandblasting process without obstructions, and a substrate including the printed circuit board and electronic components embedded therein, can be provided.

[0122] In the example embodiments, for ease of description, the terms "side," "side surface," etc., can be used to refer to a surface obtained relative to the cross-section in the figures along the right / left direction; for ease of description, the terms "upper side," "upper part," "upper surface," etc., can be used to refer to a surface located or oriented upward relative to the cross-section in the figures; and the terms "lower side," "lower part," "lower surface," etc., can be used to refer to a surface located or oriented downward. The concept of an element disposed on a side region, upper side, upper part region, or lower part region can include a configuration in which the element is in direct contact with an element used as a reference configuration in various directions, and a configuration in which the element is not in direct contact with a reference element. However, for ease of description, these terms may be defined as above, and the scope of the example embodiments is not limited to the terms described above.

[0123] In the example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via adhesive layers, etc. Furthermore, the term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Additionally, the terms "first," "second," etc., can be used to distinguish one element from another and may not limit the order and / or importance associated with the elements. In some cases, without departing from the scope of the example embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0124] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment, but may be provided to describe and highlight the different and unique features of each example embodiment. The example embodiments presented above may be implemented without excluding the possibility of combining features with those of other example embodiments. For example, unless otherwise stated, even if a feature described in one example embodiment is not described in another example embodiment, the description may be understood to be relevant to that other example embodiment.

[0125] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A printed circuit board, comprising: The first insulating layer has a first modulus; A second insulating layer is disposed on the first insulating layer and has a second modulus; A first wiring layer is disposed on one surface of the first insulating layer; as well as The cavity penetrates the second insulating layer and exposes at least a portion of the first wiring layer. Wherein, the second modulus is greater than the first modulus. The bottom surface edge of the cavity is formed using an insulating material, and Wherein, at least a portion of the first wiring layer protrudes beyond the bottom surface of the cavity.

2. The printed circuit board of claim 1, wherein, The insulating material includes at least one of the first insulating layer and the second insulating layer.

3. The printed circuit board of claim 1, wherein, The second modulus is four times or greater than the first modulus.

4. The printed circuit board according to claim 3, wherein The first insulating layer comprises a liquid crystal polymer, and The second insulating layer includes a prepreg.

5. The printed circuit board according to claim 1, wherein The cavity exposes a portion of one surface of the first insulating layer, and The exposed portion of one surface of the first insulating layer is configured as the bottom surface of the cavity.

6. The printed circuit board according to claim 5, wherein The first wiring layer includes a first wiring pattern and a second wiring pattern, at least a portion of the first wiring pattern is embedded in the second insulating layer, and at least a portion of the second wiring pattern is exposed through the cavity.

7. The printed circuit board according to claim 6, further comprising: The second wiring layer is disposed on one surface of the second insulating layer; as well as A wiring via layer that passes through the second insulating layer and connects at least a portion of the first wiring layer to at least a portion of the second wiring layer.

8. The printed circuit board according to claim 1, wherein The cavity also extends through a portion of the first insulating layer. Wherein, the cavity exposes at least a portion of the first insulating layer, and Wherein, one exposed surface of the first insulating layer is set as the bottom surface of the cavity.

9. The printed circuit board of claim 8, wherein, There is a height difference between one surface of the first insulating layer in the region covered by the second insulating layer and one surface in the region exposed by the cavity.

10. The printed circuit board according to claim 9, wherein A portion of the first wiring layer is embedded in the first insulating layer. The first wiring layer includes a first wiring pattern and a second wiring pattern. One surface of the first wiring pattern is covered by the first insulating layer, and one surface of the second wiring pattern is exposed by the cavity. The exposed surface of the second wiring pattern has a height difference with the bottom surface of the cavity.

11. The printed circuit board of claim 1, wherein, The second insulating layer comprises a plurality of insulating layers, each having a second modulus.

12. A substrate, comprising: A core structure includes a first insulating body and a plurality of core wiring layers disposed on or in the first insulating body, and the core structure has a cavity; Electronic components are disposed within the cavity; as well as A stacked structure includes a second insulating body and one or more stacked wiring layers, the second insulating body covering at least a portion of each of the core structure and the electronic components and filling at least a portion of the cavity, the one or more stacked wiring layers being disposed on or within the second insulating body. The first insulating body includes a first insulating layer and a second insulating layer. The first insulating layer has a first modulus, and the second insulating layer is disposed on the first insulating layer and has a second modulus greater than the first modulus. The cavity passes through the second insulating layer. The bottom surface of the cavity has an edge formed using an insulating material. The cavity exposes at least a portion of one of the plurality of core wiring layers, and the at least a portion of the one core wiring layer protrudes beyond the bottom surface of the cavity.

13. The substrate of claim 12, wherein, The electronic component is connected via a connecting member to one of the plurality of core wiring layers exposed by the cavity.

14. The substrate according to claim 12, wherein The core structure further includes multiple core wiring via layers, each core wiring via layer passing through a portion of the first insulating body and connected to the core wiring layer, and the stacked structure further includes multiple stacked wiring via layers, the multiple stacked wiring via layers passing through a portion of the second insulating body and connected to the one or more stacked wiring layers, and The electronic component is attached to the bottom surface of the cavity via an adhesive member, and the electronic component is connected to at least one of the one or more stacked wiring layers via at least a portion of one of the stacked wiring via layers.

15. A substrate, comprising: The first insulating body includes a first insulating layer and a second insulating layer, the first insulating layer having a first etching rate for micro-blasting, and the second insulating layer having a second etching rate for micro-blasting, the second etching rate being greater than the first etching rate. A first wiring layer is disposed on one surface of the first insulating layer; as well as The cavity penetrates the second insulating layer and exposes one surface of the first insulating layer. In this embodiment, at least a portion of the first wiring layer protrudes beyond the bottom surface of the cavity.

16. The substrate according to claim 15, further comprising: An electronic component disposed in the cavity such that at least a portion of the bottom of the cavity is exposed, and the first wiring layer is connected to the electronic component.

17. The substrate of claim 16, further comprising a second insulating body disposed on the second insulating layer, covering at least a portion of the second insulating layer and at least a portion of the electronic component, and filling at least a portion of the cavity.

18. The substrate of claim 15, wherein, The second etch rate is at least ten times the first etch rate.

19. The substrate according to claim 16, further comprising: The second insulating body is disposed on the second insulating layer; as well as The second wiring layer is disposed on or in the second insulating layer, and the second wiring layer is connected to the first wiring layer.

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