Sensing device

Abstract

The present invention discloses a sensing device comprising a first transistor, a second transistor, a third transistor, and a photosensitive element. The first transistor has a first gate, a first drain, and a first source. The first drain is coupled to a first power line and has a concave surface, and the first source is arranged corresponding to the concave surface. The second transistor has a second source coupled to the first gate. The third transistor has a third gate, a third drain, and a third source. The third drain is coupled to the first source, the third source is coupled to a data line, and the third gate is coupled to a read line. The photosensitive element is coupled to the first gate. This design can improve the signal-to-noise ratio or detection accuracy of the sensing device.

Description

[0001] This application is a divisional application of Chinese patent application No. 201710530379.0 (filing date: June 29, 2017, invention title: sensing device). Technical Field

[0002] The present invention relates to a sensing device, and in particular to a sensing device using an asymmetric transistor as a transistor for amplifying a signal. Background Art

[0003] With the rapid advancement of technology, the application of sensing devices is becoming increasingly widespread, with X-ray detection being one of the most popular applications. Due to their advantages such as low radiation dose, fast electronic imaging, and ease of image review, reproduction, capture, transmission, and analysis, digital sensing devices have gradually replaced the traditional method of detecting X-rays using film and have become the current trend in the development of digital medical imaging. Traditional digital sensing devices typically use photodiodes as their photosensitive elements to detect X-ray energy. Because X-ray damage to the human body is cumulative, reducing the X-ray energy used for detection is the best way to prevent excessive X-ray exposure. However, due to the limitations of the signal-to-noise ratio (SN ratio) of digital sensing devices, the energy of X-rays cannot be effectively reduced. Therefore, improving the SNR of sensing devices is a continuous improvement goal in the industry. Summary of the Invention

[0004] One of the objectives of the present invention is to provide a sensing device to improve the signal-to-noise ratio or detection accuracy.

[0005] One embodiment of the present invention provides a sensing device comprising a read line, a data line, a first power line, and a sensing unit. The sensing unit comprises a first transistor, a second transistor, a third transistor, and a photosensitive element. The first transistor has a first gate, a first drain, and a first source, wherein the first drain is coupled to a first power line, the first drain has a concave surface, and the first source is arranged corresponding to the concave surface. The second transistor has a second gate, a second drain, and a second source, wherein the second source is coupled to the first gate. The third transistor has a third gate, a third drain, and a third source, wherein the third drain is coupled to the first source, the third source is coupled to the data line, and the third gate is coupled to the read line. The photosensitive element is coupled to the first gate.

[0006] Another embodiment of the present invention provides a sensing device comprising a read line, a data line, a first power line, and a sensing unit. The sensing unit comprises a first transistor, a second transistor, a third transistor, and a photosensitive element. The first transistor has a first gate, a first drain, a first source, and a first semiconductor layer, wherein the first drain is coupled to the first power line. The second transistor has a second gate, a second drain, a second source, and a second semiconductor layer, wherein the second source is coupled to the first gate. The third transistor has a third gate, a third drain, a third source, and a third semiconductor layer, wherein the third drain is coupled to the first source, the third source is coupled to the data line, and the third gate is coupled to the read line. The photosensitive element is coupled to the first gate. At least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer comprises polycrystalline silicon, and at least another one of them comprises an oxide semiconductor or amorphous silicon.

[0007] Another embodiment of the present invention provides a sensing device comprising a read line, a data line, a first power line, and a sensing unit. The sensing unit comprises a first transistor, a second transistor, a third transistor, and a photosensitive element. The first transistor comprises a first gate, a first drain, a first source, and a first semiconductor layer, wherein the first drain is coupled to the first power line. The second transistor comprises a second gate, a second drain, a second source, and a second semiconductor layer, wherein the second source is coupled to the first gate. The third transistor comprises a third gate, a third drain, a third source, and a third semiconductor layer, wherein the third drain is coupled to the first source, the third source is coupled to the data line, and the third gate is coupled to the read line. The photosensitive element is coupled to the first gate. At least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer comprises an oxide semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG2 is a schematic top view of a sensing device according to a first embodiment of the present invention;

[0009] Figure 2 FIG2 is a circuit diagram of a single sensing unit, a single data line and a readout circuit according to a first embodiment of the present invention;

[0010] Figure 3 FIG2 is a circuit diagram of a single sensing unit according to another embodiment of the present invention;

[0011] Figure 4 Shown is a schematic diagram of the working timing of a single sensing unit;

[0012] Figure 5 Schematic diagram of energy level curves between the first source and the first drain under different voltage differences between the first drain and the first source when the voltage difference between the first gate and the first source of the first transistor is zero;

[0013] Figure 6A FIG2 is a schematic top view of a first transistor according to a first embodiment of the present invention;

[0014] Figure 6B FIG2 is a schematic top view of a first transistor according to another embodiment of the present invention;

[0015] Figure 6C FIG2 is a schematic top view of a first transistor according to another embodiment of the present invention;

[0016] Figure 7A Shown along Figure 6A A schematic cross-sectional view of the section line AA';

[0017] Figure 7B FIG2 is a schematic cross-sectional view of a first transistor according to another embodiment of the present invention;

[0018] Figure 8 FIG2 is a schematic top view of a first transistor according to another embodiment of the present invention;

[0019] Figure 9 FIG2 is a schematic top view of a first transistor of a comparative embodiment;

[0020] Figure 10 and Figure 11 Schematic diagrams showing the relationship between the drain current and the drain voltage of the first transistor under different gate voltages of the first embodiment and the comparative embodiment respectively;

[0021] Figure 12 FIG2 is a schematic top view of a sensing device according to a second embodiment of the present invention;

[0022] Figure 13 FIG. 1 is a schematic cross-sectional view of a sensing device according to a third embodiment of the present invention.

[0023] Explanation of reference numerals: 100, 200, 300 - sensing device; 102, 102', 1042 - concave surface; 104, 104' - convex surface; 1041 - plane; 102a, 102a', 104a - first end; 102b, 102b', 104b - second end; 102c - bottom; 104c - top; Sub - substrate; SU, SU' - sensing unit; DL - data line; RDL - read line; PL1, PL1' - first power line; Tr1, Tr 1', Tr1", Tr1a, Tr1b, Tr1c - first transistor; Tr2 - second transistor; Tr3 - third transistor; SD - photosensitive element; GE1, GE1', GE1", GE1c - first gate; GE2 - second gate; GE3 - third gate; DE1, DE1', DE1", DE1c - first drain; DE2 - second drain; DE3 - third drain; SE1, SE1', SE1", SE1a, SE1b, SE1c - first Source; SE2-second source; SE3-third source; Id-drain current; RSL-reset line; PL2-second power line; RC-readout circuit; G-ground; C1-first parasitic capacitor; R-parasitic resistor; OP-operational amplifier; Cf-feedback capacitor; SW-switch; PD-photodiode; BL1, BL2-bias lines; Treset-reset period; Tint-integration period; Tread-read period; CL1, CL2, CL3, CL4-curves line; Vth - threshold voltage; Vb1, Vb2 - channel potential barrier; Lch, Lch1, Lch2 - channel length; DR - depletion region; Wch, Wch1, Wch2 - channel width; X, Y - direction; Vg - gate voltage; SEM1, SEM1', SEM1", SEM1a, SEM1c - first semiconductor layer; IN, IN1, IN2 - insulating layer; Z - top view direction; SEM2 - second semiconductor layer; SEM3 - third semiconductor layer; TH - through hole. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to further understand the present invention, the following specifically lists a number of embodiments of the present invention and, in conjunction with the accompanying drawings, describes in detail the composition of the present invention and the effects to be achieved. These embodiments are not intended to limit the present invention. In addition, it is understood that the terms "including" and / or "having", when used in this specification, specify the presence of the features, regions, steps, operations and / or elements, but do not exclude the presence or addition of one or more other features, regions, steps, operations, elements and / or combinations thereof. It should be understood that when an element such as a layer or region is referred to as being "on" or extending "on" another element (or a variation thereof), it can be directly on or directly extended to the other element, or there can also be an intervening element. In contrast, when an element is said to be "directly on" another element (or a variation thereof) or "directly" extended to the other element, there is no intervening element. It should also be understood that when an element is referred to as being "coupled" to another element (or a variation thereof), it can be directly connected to the other element or indirectly connected (e.g., electrically connected) to the other element through one or more elements.

[0025] In the present invention, the flow of electrons in the transistor is from the source to the drain. A voltage is applied to the gate of the transistor so that electrons can flow through the channel region of the transistor. The electrons stored in the source of the transistor flow to the drain of the transistor through the channel.

[0026] Please refer to Figure 1, which shows a top view of a sensing device according to a first embodiment of the present invention. The sensing device 100 may include a substrate Sub, at least one sensing unit SU, at least one data line DL, at least one read line RDL, and at least one first power line PL1. The sensing unit SU, data line DL, read line RDL, and first power line PL1 are disposed on the substrate Sub. The sensing unit SU detects light intensity and is coupled to the data line DL, read line RDL, and first power line PL1. In this embodiment, the sensing device 100 may include a plurality of sensing units SU arranged in an array to detect images corresponding to light intensities, such as X-rays, visible light, or infrared light. Therefore, the number of data lines DL, read lines RDL, and first power lines PL1 may also be multiple. Each data line DL may connect to sensing units SU in the same row, and each first power line PL1 and each read line RDL may connect to sensing units SU in the same column, but the present invention is not limited to this. In this embodiment, the substrate Sub may be made of glass. In other embodiments, the substrate Sub may be made of plastic, metal, or other suitable substrate materials. In this embodiment, the sensing unit SU is a diode element (photodiode). In other embodiments, the sensing unit SU may be a transistor element or other electronic component suitable for detecting light. In this embodiment, the data line DL, the read line RDL, and the first power line PL1 are made of metal. In other embodiments, the data line DL, the read line RDL, and the first power line PL1 may be made of a metal oxide or other conductive material in a single or multi-layer structure.

[0027] Please refer to Figure 2, which shows a circuit diagram of a single sensing unit, a single data line, and a readout circuit according to a first embodiment of the present invention. Each sensing unit SU of this embodiment may include a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, and a photosensitive element SD. The semiconductor layer material of the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3 may be amorphous silicon, polysilicon, or an oxide semiconductor (such as indium gallium zinc oxide InGaZnO, IGZO). The first transistor Tr1 is used to amplify the light signal sensed by the photosensitive element SD. The first transistor Tr1 has a first gate GE1, a first drain DE1, and a first source SE1, and the first end (anode) of the photosensitive element SD is coupled to the first gate GE1. When the photosensitive element SD is illuminated by light and absorbs the light, generating charge through the photoelectric effect, the charge accumulates in the first gate GE1, thereby changing the voltage of the first gate GE1. This causes a change in the drain current Id between the first drain DE1 and the first source SE1 of the first transistor Tr1, amplifying the voltage signal of the first gate GE1. This current change can be used to measure the amount of charge generated by the photosensitive element SD in response to the light. To enable the first transistor Tr1 to amplify the voltage signal of the first gate GE1, the first transistor Tr1 must operate in the saturation region. In other words, the first drain DE1 is coupled to the first power line PL1, which provides a first voltage, and the voltage difference between the first gate GE1 voltage and the first voltage is less than the threshold voltage of the first transistor Tr1. In the present invention, a portion of the transistor that is not connected to the power line through the transistor channel is referred to as a drain.

[0028] The second transistor Tr2 is used to reset the voltage of the first gate GE1 to an initial state so as to re-sensing light through the photosensitive element SD. The second transistor Tr2 has a second gate GE2, a second drain DE2, and a second source SE2, and the second source SE2 is coupled to the first gate GE1. In this embodiment, the sensing device 100 may further include a reset line RSL and a second power line PL2. The reset line RSL is coupled to the second gate GE2 to control whether to reset the voltage of the first gate GE1. The second drain DE2 is coupled to the second power line PL2 that provides a second voltage, so that the second voltage can be used to reset the voltage of the first gate GE1 to an initial state. Because the second voltage is lower than the first voltage, the first transistor Tr1 can still operate in the saturation region after resetting the voltage of the first gate GE1. In the present invention, the drain is not connected to the power line through the transistor channel.

[0029] The third transistor Tr3 functions as a read transistor, controlling whether the current from the first transistor Tr1 is output. The third transistor Tr3 has a third gate GE3, a third drain DE3, and a third source SE3. The third drain DE3 is coupled to the first source SE1, the third source SE3 is coupled to the corresponding data line DL, and the third gate is coupled to the corresponding read line RDL. The read line RDL can activate the third transistor Tr3, causing it to operate in a linear region and output the drain current Id of the first transistor Tr1 to the data line DL.

[0030] In this embodiment, the data line DL extends from the sensing region to the peripheral region to couple to a readout circuit RC located within or outside the peripheral region, thereby outputting the current of the first transistor Tr1 to the readout circuit RC via the data line DL. Since the data line DL is capacitively coupled to the ground terminal G and has a certain impedance, the data line DL may include a first parasitic capacitor C1 and a parasitic resistor R. The first parasitic capacitor C1 exists (is coupled) between the data line DL and the ground terminal G, and the parasitic resistor R exists (is coupled) between the third gate GE3 and the readout circuit RC. In addition, the readout circuit RC may, for example, include an operational amplifier OP and a feedback capacitor Cf. For example, one input terminal of the operational amplifier OP may be coupled to the data line DL, and the other input terminal may be coupled to the ground terminal G, and the feedback capacitor Cf may be coupled between the output terminal of the operational amplifier OP and the data line DL. The readout circuit RC may further include a switch SW connected in parallel with the feedback capacitor Cf.

[0031] Each photosensitive element SD may include a photodiode PD (photo diode) having an anode (first electrode) and a cathode (second electrode). For example, the photodiode PD may be a PIN structure, but is not limited thereto, and the photodiode PD may be made of different materials depending on the absorption wavelength. For example, the photodiode PD may include silicon to detect X-rays. In order for the photodiode PD to perform photoelectric conversion detection, the photodiode PD needs to operate at a reverse bias. In this embodiment, in order for the photodiode PD to operate at a reverse bias, the anode (first electrode) may be coupled to the first gate GE1, and the cathode (second electrode) may be coupled to the bias line BL1, wherein the voltage provided by the bias line BL1 is greater than the second voltage, but the present invention is not limited thereto. In another embodiment, the cathode (second electrode) may be coupled to the first gate GE1, and the anode (first electrode) may be coupled to the bias line BL1. In another embodiment, the cathode (second electrode) may also be coupled to the first power line PL1. In another embodiment, the anode (first electrode) may also be coupled to the first power line PL1. In the sensing unit SU' of another embodiment, as Figure 3As shown, the second drain DE2 can also be coupled to the first power line PL1, and the cathode (second electrode) of the photodiode PD is coupled to the first gate GE1, and the anode (first electrode) is coupled to another bias line BL2 that provides a voltage less than the first voltage. In another embodiment, the anode (first electrode) of the photodiode PD is coupled to the first gate GE1, and the cathode (second electrode) is coupled to another bias line BL2 that provides a voltage less than the first voltage. In addition, because the photodiode PD needs to operate in reverse bias, each photosensitive element SD may also include a second parasitic capacitor C2, which is equivalent to the parasitic capacitance of the photodiode PD when reverse biased. The configuration relationship between the photosensitive element SD and the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3 can be determined according to actual needs. For example, when observed from the normal direction perpendicular to the surface of the substrate Sub (top view), the photosensitive element SD may overlap and cover the first transistor Tr1, the second transistor Tr2 and the third transistor Tr3, or the photosensitive element SD may partially overlap with at least one of the first transistor Tr1, the second transistor Tr2 and the third transistor Tr3, or the photosensitive element SD may not overlap with the first transistor Tr1, the second transistor Tr2 and the third transistor Tr3, but is not limited to this.

[0032] Please refer to Figure 4 , which shows the working sequence diagram of a single sensing unit. Figure 4 As shown, the sensing operation of each sensing unit can include three periods: a reset period Treset, an integration period Tint, and a read period Tread. During the reset period Treset, the reset line RSL provides a reset voltage Vreset to turn on the second transistor Tr2, resetting the voltage of the first gate GE1 to the second voltage of the second power line PL2. Then, during the integration period Tint, the reset voltage Vreset is stopped, turning off the second transistor Tr2. Light is detected by the photosensitive element SD, accumulating charge at the first gate GE1. This accumulated charge is converted into a drain current Id through the first transistor Tr1. Subsequently, during the read period Tread, the read line RDL provides a read voltage Vread to turn on the third transistor Tr3, causing the drain current Id to enter the data line DL and be output to the readout circuit RC. This allows the amount of charge generated by the photosensitive element SD over a certain period of time to be detected.

[0033] In the present embodiment, since the same first power line PL1 and the same read line RDL are coupled to the sensing unit SU of the same column, during the read period Tread, the read voltage provided by the read line RDL will simultaneously turn on the third transistor Tr3 of the sensing unit SU of the same column, so that the first transistor Tr1 of the same column needs to output the drain current Id to the data line DL at the same time. In this way, the first power line PL1 connected to the first transistor Tr1 of the same column will produce an obvious load effect due to the simultaneous opening of the third transistor Tr3, so that the first voltage provided by the first power line PL1 to different first transistors Tr1 will be different. Basically, when the channel of the first transistor Tr1 is turned on and electrons can flow due to the gate voltage, the electrons will flow from the first source SE1 to the first drain DE1, and the electrons stored in the first source SE1 will reach the first drain DE1 by crossing the energy barrier. In the present invention, the power line that is not connected through the transistor channel is called the drain. Please refer to Figure 5 , which shows a schematic diagram of the energy level curve between the first source and the first drain under different voltage differences between the first drain and the first source when the voltage difference between the first gate and the first source of the first transistor is zero. Curves CL1 to CL4 represent the energy levels between the first source and the first drain when the voltage difference between the first drain and the first source gradually increases. Taking curves CL1 and CL4 as an example, when the voltage difference between the first source SE1 and the first drain DE1 increases (as shown by the arrow direction), not only does the channel potential barrier Vb1 (channel barrier) of the semiconductor layer of the first transistor Tr1 decrease to the channel potential barrier Vb2, but the effective channel length Lch1 of the first transistor Tr1 also decreases to the channel length Lch2, which is the so-called short channel effect. In other words, when the first voltage of the first drain DE1 is different, the effective channel length of the semiconductor layer of the first transistor Tr1 will also be different.

[0034] Please refer to Figure 6A and Figure 7A , Figure 6A FIG2 is a schematic top view of a first transistor according to a first embodiment of the present invention. Figure 7A Shown along Figure 6A The schematic cross-sectional view of the section line A-A'. Figure 6A and Figure 7AAs shown, the first drain electrode DE1 of this embodiment has a concave surface 102 (also referred to as a concave portion, having an open, recessed area), and the first source electrode SE1 is disposed corresponding to the concave surface 102. For example, the first source electrode SE1 may have a convex surface 104 (also referred to as a convex portion, having a protruding area), with the convex surface 104 corresponding to the concave surface 102. In this embodiment, the concave surface 102 and the convex surface 104 have substantially corresponding shapes. In a top-down direction Z perpendicular to the substrate Sub, the concave surface 102 and the convex surface 104 may each have no arc-shaped edges, partially arc-shaped edges, or completely arc-shaped edges, without limitation. The first end 102a and the second end 102b of the concave surface 102 are the starting point and the end point of a concave trajectory corresponding to the convex surface 104. Conversely, the first end 104a and the second end 104b of the convex surface 104 are the starting point and the end point of a convex trajectory corresponding to the concave surface 102. The spacing between corresponding locations on the concave surface 102 and the convex surface 104 is approximately equal. However, portions near the ends or in the center may be slightly wider or narrower due to the photolithography process or graphic design, and this is not a limitation. In the top view direction Z, the concave length of the concave surface 102 from the first end 102a to the second end 102b along the concave path is greater than the convex length of the convex surface 104 from the first end 104a to the second end 104b along the convex path. The channel area is within the area enclosed by the first end 102a, the first end 104a, the second end 102b, and the second end 104b. In the top-down direction Z, the channel length Lch can be the distance between the first end 102a and the first end 104a, or the distance between the second end 102b and the second end 104b, or the distance between a top 104c of the convex surface 104 and a bottom 102c of the concave surface 102, with the top 104c located between the first end 104a and the second end 104b, and the bottom 102c located between the first end 102a and the second end 102b. In the top-down direction, the channel width Wch can be half the sum of the concave length of the concave surface 102 and the convex length of the convex surface 104, or the length of the channel region along a cross-sectional line extending from the first end to the center of the second end. In other words, the first transistor Tr1 of this embodiment is an asymmetric transistor. It is worth noting that since the first drain DE1 is coupled to the first power line PL1, the voltage of the first drain DE1 is greater than the voltage of the first source SE1. Therefore, when the first transistor Tr1 generates a short channel effect, the depletion region DR adjacent to the first drain DE1 expands from the first drain DE1 toward the first source SE1, thereby shortening the original channel length Lch1 to a channel length Lch2. At this time, since the first drain DE1 has a concave surface 102, the channel width Wch1 between the first drain DE1 and the first source SE1 is reduced to a channel width Wch2. Considering the channel length modulation phenomenon, the current-voltage equation (1) of the first transistor Tr1 operating in the saturation region is as follows:

[0035]

[0036] Where Id is the drain current, μ is the carrier mobility in the channel region, Cox is the capacitance of the gate oxide layer, Lch is the channel length, Wch is the channel width, Vg is the gate voltage, Vth is the threshold voltage, and Vd is the drain voltage. As can be seen from formula (1), the drain current Id is not only inversely proportional to the channel length but also directly proportional to the channel width. Therefore, in this embodiment, by designing the first transistor Tr1 as an asymmetric transistor structure and coupling the first drain DE1 to the first power line PL1 with a higher voltage, the channel width of the first transistor Tr1 can be shortened while the channel length of the first transistor Tr1 is shortened, thereby reducing the impact of the short channel effect on the current of the first transistor Tr1. Therefore, although the first voltages provided to different first transistors Tr1 may be different, the design of the first transistor Tr1 in this embodiment can effectively mitigate the changes in the drain current Id of each first transistor Tr1 caused by the different first voltages, thereby improving the detection uniformity and accuracy of the sensing device 100, or enhancing the signal-to-noise ratio of the sensing device 100.

[0037] In another embodiment, the first transistor Tr1a is Figure 6B As shown, the surface of the first source electrode SE1a corresponding to the concave surface 102 may be a plane 1041 (without a protruding area or a concave area). In another embodiment, in the first transistor Tr1b, as shown in FIG. Figure 6C As shown, the surface of the concave surface 102 corresponding to the first source SE1b can be a concave surface 1042 (also called a concave portion, a recessed area with an opening), and the shape of the concave surface 1042 in the top-view direction Z perpendicular to the substrate Sub can be, for example, an arc or other geometric shape. The concave surface 1042 can be a pattern without arc-shaped edges, with partial arc-shaped edges, or with all edges being arc-shaped, without limitation.

[0038] In this embodiment, the first source SE1 may extend along the direction X, the first drain DE1 of the first transistor Tr1 and the first source SE1 may not overlap in the direction Y, and the top-view shape of the concave surface 102 and the top-view shape of the convex surface 104 may be trapezoidal, but the present invention is not limited thereto. In another embodiment, the first source SE1 may also be displaced in the direction Y, so that the center point of the surface of the first source SE1 facing the concave surface 102 in the direction Y and the center point of the concave surface 104 in the direction Y are not arranged in the direction X. In yet another embodiment, the first source SE1 may also be rotated so that the extension direction of the first source SE1 is not parallel to the direction X, but forms an angle with the direction X. In the first transistor Tr1' of another embodiment, as Figure 8As shown, the concave surface 102' of the first drain electrode DE1' has a recessed portion. This recessed portion is an open-shaped recessed area formed by the first ends 102a' and 102b' and the concave surface trajectory. The first source electrode SE1' may be correspondingly disposed within the recessed portion of the concave surface 102'. In other words, in this embodiment, the first source electrode SE1' and the recessed portion of the concave surface 102' at least partially overlap in a top-down direction Z perpendicular to the substrate Sub. In other embodiments, the first source electrode SE1' and the recessed portion of the concave surface 102' may not overlap in a top-down direction Z perpendicular to the substrate Sub. For example, the convex surface 104' of the first source electrode SE1' may be correspondingly disposed within the recessed portion of the concave surface 102' of the first drain electrode DE1'. For example, the top-down shapes of the convex surface 104' and the concave surface 102' may each be U-shaped, and the convex surface 104' and the concave surface 102' may be uniformly spaced, but this is not limited to this. The top view shapes of the convex surface 104' and the concave surface 102' may also be other shapes, such as rectangle, semicircle or arc. In the top view direction Z perpendicular to the substrate Sub, at least part of the convex surface 104' is arc-shaped, and at least part of the concave surface 102' is arc-shaped.

[0039] Please refer to further Figures 9 to 11 , Figure 9 FIG. 1 is a schematic top view of a first transistor of a comparative embodiment. Figure 10 and Figure 11 Schematic diagrams showing the relationship between drain current and drain voltage of the first transistor under different gate voltages in the first embodiment and the comparative embodiment are shown. Figure 9 As shown, the first transistor Tr1″ of the comparative embodiment is a symmetrical transistor. Specifically, the surface of the first drain DE1″ of the first transistor Tr1″ facing the first source SE1″ and the surface of the first source SE1″ facing the first drain DE1″ are parallel to each other. Therefore, although the depletion region adjacent to the first drain DE1″ will expand from the first drain DE1″ toward the first source SE1″ when the short channel effect occurs in the first transistor Tr1″, thereby changing the channel length, the channel width of the first transistor Tr1″ will not change due to the change in the channel length. As a result, the first transistor Tr1″ of the comparative embodiment cannot effectively mitigate the short channel effect. Figure 10 and Figure 11 As shown, compared with the control embodiment, the slope of the curve in the saturation region of the first transistor Tr1 of this embodiment can be lower under different gate voltages Vg, thereby significantly reducing the relationship between the drain current and the drain voltage, thereby reducing the short channel effect.

[0040] Also, please continue to refer to Figure 6A and Figure 7A. The first transistor Tr1 of this embodiment may further include a first semiconductor layer SEM1 and an insulating layer IN. The insulating layer is disposed between the first gate GE1 and the first semiconductor layer SEM1, and the first drain DE1 and the first source SE1 are disposed on the first semiconductor layer SEM1. Specifically, the first gate GE1 may be disposed between the first semiconductor layer and the substrate Sub. In other words, the first transistor Tr1 may be a bottom gate type transistor, and the first semiconductor layer SEM1 may include, for example, an oxide semiconductor or amorphous silicon, but is not limited thereto. The oxide semiconductor may include, for example, indium gallium zinc oxide (InGaZnO, IGZO), but is not limited thereto. In another embodiment, when the first transistor Tr1 is a bottom gate type transistor, the first semiconductor layer SEM1 may also include polycrystalline silicon, such as low temperature polysilicon. It is worth noting that the first semiconductor layer SEM1 corresponding to the first drain DE1 and the first source SE1 is larger than the portion of the first gate GE1 corresponding to the first drain DE1 and the first source SE1, so that the portion of the first semiconductor layer SEM1 in contact with the first drain DE1 protrudes outside the first gate GE1 in the top-down direction Z perpendicular to the substrate Sub. The portion of the first semiconductor layer SEM1 in contact with the first source SE1 also protrudes outside the first gate GE1 in the top-down direction Z. This can reduce or avoid gate induced drain leakage (GIDL). In another embodiment, the first semiconductor layer SEM1 corresponding to the first drain DE1 and the first source SE1 can also be smaller than the portion of the first gate GE1 corresponding to the first drain DE1 and the first source SE1. In this embodiment, the second transistor Tr2 can be as follows: Figure 9 The symmetrical transistor shown or Figures 6A to 6C and Figure 8 The asymmetric thin film transistor shown in FIG. 1 and the third transistor Tr3 may also be as shown in FIG. Figure 9 The symmetrical transistor shown or Figures 6A to 6C and Figure 8 The asymmetric thin film transistor shown.

[0041] In another embodiment, if Figure 7BAs shown, the first transistor Tr1c can also be a top-gate transistor, and the first semiconductor layer SEM1c can include, for example, but is not limited to, polycrystalline silicon. Specifically, the first semiconductor layer SEM1c is disposed on the substrate Sub, the insulating layer IN1 is disposed on the first semiconductor layer SEM1c, the first gate GE1c is disposed on the insulating layer IN1 corresponding to the first semiconductor layer SEM1c, and the insulating layer IN2 is disposed on the first gate GE1c and the insulating layer IN1. The insulating layers IN1 and IN2 have two through-holes TH, corresponding to two portions of the first semiconductor layer SEM1c. The first source electrode SE1c and the first drain electrode DE1c are respectively disposed on the insulating layer IN2 and electrically connected to the first semiconductor layer SEM1c through the corresponding through-holes TH. In another embodiment, when the first transistor Tr1c is a top-gate transistor, the first semiconductor layer SEM1c can also include, for example, an oxide semiconductor or amorphous silicon.

[0042] The sensing device provided by the present invention is not limited to the above-mentioned embodiment. Other embodiments of the present invention will be further disclosed below. However, in order to simplify the description and highlight the differences between the embodiments, the same reference numerals are used below to mark the same elements, and repeated parts will not be repeated.

[0043] Please refer to Figure 12 , which is a top view schematic diagram of a sensing device according to a second embodiment of the present invention. Figure 12 As shown, compared to the first embodiment, different sensing units SU connected to the same read line RDL are coupled to different first power lines PL1'. In the sensing device 200 of this embodiment, each first power line PL1' and each data line DL may extend along a first direction D1, and each read line RDL may extend along a second direction D2, such that the extending direction of each first power line PL1' is different from the extending direction of the read line RDL. For example, the first direction D1 and the second direction D2 are perpendicular to each other, but this is not limited to this. Taking two adjacent sensing units SU as an example, the third gates of the two third transistors Tr3 are coupled to the same read line RDL, while the two third sources are coupled to different data lines DL. Furthermore, the first drains of the two first transistors Tr1 are coupled to different first power lines PL1'. By coupling different sensing units SU connected to the same read line RDL to different first power lines PL1', the loading effect of the first power line PL1' when the third transistors Tr3 in the same column are turned on can be reduced or avoided, thereby reducing the uneven first voltage provided by the first power line PL1' to different sensing units SU. Thereby, the detection uniformity and accuracy of the sensing device 200 can be improved, or the signal-to-noise ratio of the sensing device 200 can be enhanced.

[0044] Please refer to Figure 13, which is a cross-sectional schematic diagram of a sensing device according to a third embodiment of the present invention. In the sensing device 300 of this embodiment, the second transistor Tr2 may further include a second semiconductor layer SEM2, and the third transistor Tr3 may further include a third semiconductor layer SEM3. At least one of the first semiconductor layer SEM1, the second semiconductor layer SEM2 and the third semiconductor layer SEM3 includes polycrystalline silicon, and at least the other one includes an oxide semiconductor or amorphous silicon. Alternatively, at least one of the first semiconductor layer SEM1, the second semiconductor layer SEM2 and the third semiconductor layer SEM3 includes an oxide semiconductor. Please refer to Table 1 for details, which lists the applicable material combinations of the first semiconductor layer SEM1, the second semiconductor layer SEM2 and the third semiconductor layer SEM3 of the present invention. For example, when at least one of the first semiconductor layer SEM1, the second semiconductor layer SEM2 and the third semiconductor layer SEM3 includes an oxide semiconductor, the other two of the first semiconductor layer SEM1, the second semiconductor layer SEM2 and the third semiconductor layer SEM3 may include an oxide semiconductor or amorphous silicon. The structures of the first transistor Tr1, the second transistor Tr2 and the third transistor Tr3 of the present invention are not limited to the following. Figure 13 The first transistor Tr1, the second transistor Tr2 and the third transistor Tr3 of the present invention can also be selected as follows: Figure 7B For example, when the first semiconductor layer SEM1 includes polysilicon, the first transistor Tr1 may be a top-gate transistor. Figure 7B The second transistor Tr2 may be a top-gate transistor as shown, and when the second semiconductor layer SEM2 includes an oxide semiconductor or amorphous silicon, the second transistor Tr2 may be a bottom-gate transistor. Alternatively, when the third semiconductor layer SEM1 includes polysilicon, the third transistor Tr3 may be a bottom-gate transistor as shown. Figure 7B The second transistor Tr2 is a top-gate transistor as shown, and when the second semiconductor layer SEM2 includes an oxide semiconductor or amorphous silicon, the second transistor Tr2 may be a bottom-gate transistor.

[0045] Table 1

[0046] First semiconductor layer Second semiconductor layer The third semiconductor layer polysilicon polysilicon amorphous silicon polysilicon polysilicon oxide semiconductors polysilicon amorphous silicon amorphous silicon polysilicon amorphous silicon polysilicon polysilicon amorphous silicon oxide semiconductors polysilicon oxide semiconductors oxide semiconductors polysilicon oxide semiconductors polysilicon polysilicon oxide semiconductors amorphous silicon oxide semiconductors oxide semiconductors oxide semiconductors oxide semiconductors oxide semiconductors polysilicon oxide semiconductors oxide semiconductors amorphous silicon oxide semiconductors polysilicon polysilicon oxide semiconductors polysilicon oxide semiconductors oxide semiconductors polysilicon amorphous silicon oxide semiconductors amorphous silicon amorphous silicon oxide semiconductors amorphous silicon polysilicon oxide semiconductors amorphous silicon oxide semiconductors amorphous silicon amorphous silicon polysilicon amorphous silicon amorphous silicon oxide semiconductors amorphous silicon polysilicon polysilicon amorphous silicon polysilicon oxide semiconductors amorphous silicon polysilicon amorphous silicon amorphous silicon oxide semiconductors oxide semiconductors amorphous silicon oxide semiconductors polysilicon amorphous silicon oxide semiconductors amorphous silicon

[0047] The following further takes the example that the first semiconductor layer SEMI1 comprises polysilicon, and the second semiconductor layer SEM2 and the third semiconductor layer SEM3 comprise oxide semiconductor or amorphous silicon respectively. The transistor gain formula (2) is as follows:

[0048]

[0049] Where G is the gain of the transistor, C2 is the capacitance of the second parasitic capacitor, and Tread is the length of the reading period. From formula (2), it can be seen that the gain of the transistor is proportional to the carrier mobility of the semiconductor layer serving as the channel region. It is worth mentioning that since the first transistor Tr1 operates in the saturation region, it is not necessary to consider the switching characteristics. Instead, the gain of the first transistor Tr1 can be increased by using polycrystalline silicon, which has a carrier mobility greater than that of oxide semiconductor and amorphous silicon, to improve the sensitivity of detecting light intensity, thereby improving the signal-to-noise ratio of the sensing device 300. In addition, since the second transistor Tr2 and the third transistor Tr3 need to perform a switching function, oxide semiconductors or amorphous silicon, which have a leakage current less than that of polycrystalline silicon when turned off, can be used in the second semiconductor layer SEM2 and the third semiconductor layer SEM3 to reduce the inaccuracy of detecting light intensity and the error rate of reading the drain current Id of the first transistor Tr1. As can be seen from the above, the sensing device 300 of this embodiment improves the signal-to-noise ratio or reduces the detection error rate by differentiating the materials of the first semiconductor layer SEM1 , the second semiconductor layer SEM2 , and the third semiconductor layer SEM3 .

[0050] In summary, in the sensing device provided by the present invention, the signal-to-noise ratio or detection accuracy of the sensing device can be effectively improved by designing the first transistor as an asymmetric transistor, coupling different sensing units connected to the same read line to different first power lines, and differentiating the material of the first semiconductor layer from the materials of the second semiconductor layer and the third semiconductor layer.

[0051] The foregoing description is merely an embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A sensing device, characterized in that: include: Read line; Data cable; a first power line, wherein the pickup line is perpendicular to the first power line; as well as A sensing unit, comprising: a first transistor having a first gate, a first drain, and a first source, wherein the first source extends along a direction, the first drain is coupled to the first power line, the first drain has a concave surface in a top view of the first transistor, the first source is arranged corresponding to the concave surface, and the first source and the concave surface are aligned along the direction; a second transistor having a second gate, a second drain, and a second source, wherein the second source is coupled to the first gate; a third transistor having a third gate, a third drain, and a third source, wherein the third drain is coupled to the first source, the third source is coupled to the data line, and the third gate is coupled to the read line; a photosensitive element comprising a photodiode, one end of the photodiode being coupled to the first gate; and A bias line coupled to the other end of the photodiode, The voltage provided by the bias line is smaller than the voltage of the first power line.

2. The sensing device according to claim 1, wherein The first transistor further includes a first semiconductor layer, the second transistor further includes a second semiconductor layer, and the third transistor further includes a third semiconductor layer, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes an oxide semiconductor.

3. The sensing device according to claim 2, wherein: The first semiconductor layer includes polycrystalline silicon or amorphous silicon.

4. The sensing device according to claim 1, wherein: The first transistor further includes a first semiconductor layer, the second transistor further includes a second semiconductor layer, and the third transistor further includes a third semiconductor layer, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes amorphous silicon.

5. The sensing device according to claim 4, characterized in that The first semiconductor layer includes polysilicon.

6. The sensing device according to claim 1, wherein: The first transistor further includes a first semiconductor layer, the second transistor further includes a second semiconductor layer, and the third transistor further includes a third semiconductor layer, wherein at least one of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer includes polysilicon.

7. The sensing device according to claim 1, wherein: The photodiode has an anode and a cathode, the anode is coupled to the first gate, and the cathode is coupled to the bias line.

8. The sensing device according to claim 1, wherein: The photodiode has an anode and a cathode, the cathode is coupled to the first gate, and the anode is coupled to the bias line.

9. The sensing device according to claim 1, wherein: The concave surface has a recessed portion, and the first source electrode is correspondingly disposed in the recessed portion of the concave surface.

10. The sensing device according to claim 1, wherein: In a top view, part of the concave surface is arc-shaped.

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