Chip test mode configuration method and device, SOC chip and electronic equipment

Abstract

The application relates to a chip test mode configuration method and device, an SOC chip and electronic equipment, and belongs to the technical field of integrated circuits. The chip test mode configuration method comprises the following steps: obtaining a control instruction input by a user for testing a specified test mode of an SOC chip; sending the control instruction to the SOC chip to trigger the SOC chip to run preset code corresponding to the control instruction, to configure register-related parameters in the SOC chip, so that the SOC chip enters the specified test mode, wherein the preset code contains configuration parameters of registers in the specified test mode. The method does not require a test engineer to understand various serial port protocols for configuring registers, nor to understand how specific registers are configured, and only a few instruction selections can easily enable the chip to enter a desired test scene.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, specifically relating to a configuration method, apparatus, SOC chip, and electronic device for a chip testing mode. Background Technology

[0002] With the development of integrated circuit technology, integrated systems have evolved, consisting of multiple integrated circuits with specific functions combined on a single chip, capable of processing various types of information. These integrated systems are called System-on-Chips (SOCs). SOCs significantly reduce system costs, shorten design cycles, and accelerate time-to-market. This new design paradigm shortens the design cycle and reduces design risks for SOC system integration, but it also brings significant challenges to SOC testing.

[0003] Testing of SOC chips (such as RF SOC chips) is typically performed using Automatic Test Equipment (ATE). Most existing RF SOC chips control their mode, channel, power, etc., via a serial communication interface protocol. The ATE writes control commands to the SOC's registers through the serial communication interface, controlling the chip to switch to different frequency bands and test modes (such as transmit, receive, power-off, and standby) for testing.

[0004] Taking the testing of a Bluetooth SoC chip as an example, such as Figure 1 As shown, the chip requires multiple register configurations to enter the desired test mode. This necessitates that test engineers be thoroughly familiar with the serial port protocol standard and able to translate register control commands into ATE machine vectors using ATE equipment tools to achieve the desired control. Furthermore, test engineers must fully understand the register control settings required for each test item, the sequence of register control switches, the meaning of specific register parameters, and the waiting time between register control commands. Incorrect settings can prevent the chip from entering the correct mode, leading to incorrect test results. The troubleshooting process is also complex and time-consuming, impacting debugging progress and efficiency. During the chip debugging phase, register parameters will inevitably be modified continuously, further increasing the risk of errors. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a method, apparatus, SOC chip, and electronic device for configuring chip test modes, so as to improve the problems of high requirements for test engineers, easy test errors, and low test efficiency when configuring test modes for existing SOC chips.

[0006] The embodiments of this application are implemented as follows:

[0007] Firstly, embodiments of this application provide a method for configuring a chip test mode, comprising: acquiring a control instruction input by a user for testing a SOC chip in a specified test mode; sending the control instruction to the SOC chip to trigger the SOC chip to run preset code corresponding to the control instruction, thereby configuring register-related parameters in the SOC chip to enable the SOC chip to enter the specified test mode, wherein the preset code contains configuration parameters of the registers in the specified test mode. In this application example, by pre-including the register-related parameters required for the SOC chip to enter the specified test mode in the code, subsequent triggering of the corresponding preset code automatically configures the register-related parameters in the SOC chip, enabling the SOC chip to enter the specified test mode. This eliminates the need for test engineers to understand the serial port protocols used to configure registers or how to configure specific registers; a few simple instruction selections can easily put the chip into the desired test scenario.

[0008] In one possible implementation of the first aspect embodiment, the method further includes: storing code containing the configuration parameters required for registers in each test mode of the SOC chip into a memory within the SOC chip or a memory connected to the SOC chip.

[0009] In one possible implementation of the first aspect embodiment, according to the ATE test requirements, for each test mode of the SOC chip, the required configuration parameters of the registers in that test mode are written into the code, and control instructions for triggering that test mode are set in the code. In this application example, by setting control instructions for triggering the test mode in the code, the switching of test modes can be made very convenient.

[0010] In one possible implementation of the first aspect embodiment, the code is stored in the memory by burning or written to the memory by an ATE device.

[0011] In one possible implementation of the first aspect embodiment, the control command is a combination of 0 and / or 1 digital signals. The control command is sent to the SOC chip by changing the level of the test I / O pins. In this embodiment, by using a combination of 0 and / or 1 digital signals, only a few simple changes to the logic level of signal pins are needed to quickly switch to the desired test mode.

[0012] In one possible implementation of the first aspect embodiment, the SOC chip is a Bluetooth chip, and the test modes of the SOC chip include: standby mode, transmit power test mode, modulation characteristic test mode, and receive sensitivity test mode.

[0013] Secondly, embodiments of this application also provide a chip test mode configuration device, including: an acquisition module and a sending module; the acquisition module is used to acquire a control command input by a user for testing a specified test mode of a SOC chip; the sending module is used to send the control command to the SOC chip to trigger the SOC chip to run a preset code corresponding to the control command, so as to configure the register-related parameters in the SOC chip, so that the SOC chip enters the specified test mode, wherein the preset code contains the configuration parameters of the registers under the specified test mode.

[0014] Thirdly, this application embodiment also provides a SOC chip, wherein the SOC chip stores preset code, the preset code is used to configure the register-related parameters in the SOC chip so that the SOC chip enters a specified test mode, wherein the preset code contains the configuration parameters of the registers in the specified test mode.

[0015] Fourthly, embodiments of this application also provide an electronic device, including: a memory and a processor, the processor being connected to the memory; the memory being used to store a program; the processor being used to invoke the program stored in the memory to execute the method provided by any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment.

[0016] Fifthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the method provided by any possible implementation of the first aspect embodiments and / or in combination with the first aspect embodiments.

[0017] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0019] Figure 1 The configuration principle of the test mode for existing Bluetooth chips.

[0020] Figure 2 The diagram shows a schematic flowchart of a chip testing mode configuration method provided in an embodiment of this application.

[0021] Figure 3 This illustration shows a schematic diagram of a configuration device for a chip testing mode provided in an embodiment of this application.

[0022] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0023] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0024] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0025] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0026] To address the issues of high skill requirements for test engineers when configuring test modes for existing System-on-Chips (SoCs), including a need for thorough familiarity with serial port protocol standards, understanding of register control settings for each test item, the sequence of register control switches, the meaning of specific register parameters, and the waiting time between register control instructions, as well as the inherent errors and low efficiency of testing, this application provides an extremely simplified method for configuring chip test modes. This method eliminates the need for test engineers to understand the serial port protocols used for register configuration or specific register configuration details. A few simple instruction selections are all it takes to easily put the chip into the desired test scenario.

[0027] The following will combine Figure 2 The configuration method of the chip test mode provided in the embodiments of this application will be described.

[0028] S1: Obtain the control command input by the user for testing the SOC chip in the specified test mode.

[0029] When testing a System-on-a-Chip (SoC) chip, one implementation involves connecting the SoC chip to be tested to an Automatic Test Equipment (ATE) tester. The specific connection method is consistent with existing testing methods and will not be described here. The user (test engineer) inputs control commands on the ATE tester to put the SoC chip into a specified test mode (or test scenario) according to the test scenario requirements. The ATE tester responds to the user's input and obtains the control commands input by the user for testing the SoC chip in the specified test mode.

[0030] In one optional implementation, the control command can be a combination of 0s and / or 1s, such as 0000, 0001, 0010, ..., 1111, etc., consisting of 0s and / or 1s. It should be noted that the number of bits in the combination of digital signals can be determined based on the test modes available in the SOC chip. For example, if there are fewer than 16 test modes, a 4-bit digital signal can be used for control; if there are fewer than 32 test modes, a 5-bit digital signal can be used, and so on.

[0031] Different SoC chips require different test modes (test scenarios). Taking a Bluetooth SoC as an example, the test modes include: Standby mode, transmit power test modes (such as TX_power_2402MHz, TX_power_2440MHz, TX_power_2480MHz, etc.), modulation characteristic test modes (TX_ModChar1_2402MHz, TX_ModChar2_2402MHz, TX_ModChar1_2440MHz, TX_ModChar2_2440MHz, TX_ModChar1_2480MHz, TX_ModChar2_2480MHz), and receive sensitivity test modes (such as RX_PER_2402MHz, RX_PER_2440MHz, RX_PER_2480MHz). It should be noted that these are existing test modes for Bluetooth chips.

[0032] S2: Send the control command to the SOC chip to trigger the SOC chip to run the preset code corresponding to the control command, so as to configure the relevant parameters of the registers in the SOC chip, so that the SOC chip enters the specified test mode.

[0033] After receiving the control command input by the user, the ATE tester sends the control command to the SOC chip to trigger the SOC chip to run the preset code corresponding to the control command, so as to configure the relevant parameters of the registers in the SOC chip and enable the SOC chip to enter the specified test mode.

[0034] The preset code contains the configuration parameters of the registers in the specified test mode. The SOC chip runs the preset code, obtains the configuration parameters of the registers, configures the relevant registers, and after the configuration is completed, the SOC chip enters the specified test mode. Then, the SOC chip in the specified test mode can be tested.

[0035] In one optional implementation, the preset code also includes a control instruction for triggering the test mode. When the SOC chip receives the control instruction, it will run the preset code containing the control instruction.

[0036] Prior to S2, the configuration method for the chip test mode also includes storing the code containing the configuration parameters required for the registers in each test mode of the SOC chip into the memory within the SOC chip or into the memory connected to the SOC chip, so that the SOC chip can load the code stored in the memory and run it when it receives a control command.

[0037] If the SOC chip has integrated memory, the code (containing the configuration parameters required for the registers in each test mode of the SOC chip) only needs to be written into the memory according to the memory read / write requirements using an ATE (Automatic Test Equipment). On the ATE tester, the code is written into memory in a vector format. If the SOC chip does not have built-in memory, external storage devices can be used to store the code (containing the configuration parameters required for the registers in each test mode of the SOC chip). This can be done by directly programming the code into memory using a programmer, or by using an ATE device to write the code into external memory in vector format.

[0038] In this embodiment, to simplify the existing cumbersome configuration, the required configuration parameters of the registers for each test mode of the SOC chip under test are written into the code according to the ATE test requirements. The control instructions for triggering the test mode are set in the code. Then, these codes are stored in the memory inside the SOC chip or in the memory connected to the SOC chip. This allows the chip to easily enter the desired test scenario by inputting the corresponding control instructions, such as a combination of 0 and / or 1 digital signals, according to the test requirements during subsequent test configuration. Test engineers do not need to understand the serial port protocols used to configure the registers, nor do they need to know how to configure the specific registers.

[0039] During the RF module verification phase, chip design engineers conduct comprehensive performance testing of the chip using debugging tools. This debugging process involves configuring the parameters of registers used in various test modes and writing control commands or code to the chip via an interface. Design engineers simply need to package the corresponding code into modules based on the scenarios covered by the ATE test requirements and store them in the memory within the SOC chip or in memory connected to the SOC chip. It's important to note that, given the need for flexible configuration of multiple registers for different test modes, the code can also include simple control instructions to trigger each test mode for later switching control.

[0040] During testing, the SOC chip powers on and automatically loads the software code from memory into its kernel, then executes it. It first completes initialization settings such as reset, clock configuration, and interface startup before entering DTM (Direct Test Mode, a mode for testing Bluetooth Low Energy RF performance). Upon receiving control commands from the ATE (Automatic Test Equipment), it runs the corresponding code to switch to the appropriate test mode. This can be achieved by setting the corresponding I / O pin levels on the ATE, based on predefined control commands (such as combinations of 0 and / or 1 digital signals) in the software code. This changes the levels of the SOC chip's test I / O pins, sending control commands to the SOC chip. Since the code pre-sets the control commands for each test mode and includes register parameter settings, the SOC chip can execute the corresponding code upon detecting a level change, automatically configuring the registers and switching directly to the appropriate mode for testing.

[0041] To better understand the above testing process, the following explanation uses a Bluetooth chip as an example of a SOC chip. The chip test mode configuration method of this application embodiment allows for quick switching to the desired test mode during actual testing by simply changing the logic levels of a few signal pins.

[0042] In one implementation, the relationship between the signal pin logic level and the test mode is shown in Table 1.

[0043] Table 1

[0044]

[0045]

[0046] The test modes shown in Table 1 are existing test modes of Bluetooth chips. Before adopting the method of this application, if you want the SOC chip to enter the TX_power_2440MHz mode, based on the existing solution, you first need to configure the registers to initialize the chip, enter the DTM (Direct Test Mode) test mode, then configure the registers to set the chip to transmit mode, set the frequency to 2440MHz, and adjust the transmit gain to the maximum. The format of the transmitted video signal, the data rate, the number of packets to be transmitted, etc., all need to be configured in the registers one by one. If you switch from the transmit test mode to the receive test mode, the registers need to be configured again, which is very cumbersome. However, after adopting this application, you only need to set GPIO[3:0] = 0010. When the running software code scans GPIO[3:0] and there is a jump, since the corresponding register settings are already written in the software code, the relevant parameters of the registers in the SOC chip are automatically configured by running the corresponding software code. Only a few external digital pins are needed to control the signal, so the ATE does not need to configure the registers at all. Test engineers do not need to be familiar with register processes, register configuration interface protocols, and how to convert and configure registers, which simplifies debugging and greatly improves the development efficiency of mass production programs.

[0047] Based on the same inventive concept, this application also provides a SOC chip, which stores preset code. The preset code is used to configure the register-related parameters in the SOC chip so that the SOC chip enters a specified test mode. The preset code contains the configuration parameters of the registers in the specified test mode.

[0048] The SOC chip can be any chip that needs to be tested, such as an RF chip, a Bluetooth chip, or a WiFi chip. The test can be performed by configuring the register parameters required for the test in advance, writing control commands or code to the chip through the interface, and then packaging the corresponding code into a module and storing it in the memory inside the SOC chip.

[0049] The SOC chip provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the SOC chip embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0050] Based on the same inventive concept, embodiments of this application also provide a configuration device for a chip testing mode, such as... Figure 3 As shown. The configuration device 100 for this chip test mode includes an acquisition module 110 and a transmission module 120.

[0051] The acquisition module 110 is used to acquire control commands input by the user for testing the SOC chip in a specified test mode;

[0052] The sending module 120 is used to send the control command to the SOC chip to trigger the SOC chip to run the preset code corresponding to the control command, so as to configure the relevant parameters of the registers in the SOC chip, so that the SOC chip enters the specified test mode, wherein the preset code contains the configuration parameters of the registers in the specified test mode.

[0053] The chip testing mode configuration device 100 provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0054] like Figure 4 As shown, Figure 4 This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0055] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as... Figure 3 The software functional module shown is the chip test mode configuration device 100. The chip test mode configuration device 100 includes at least one software functional module that can be stored in the memory 220 as software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute executable modules stored in the memory 220, such as the software functional module or computer program included in the chip test mode configuration device 100. For example, the processor 240 is used to acquire control instructions input by the user for testing a specified test mode of the SOC chip; send the control instructions to the SOC chip to trigger the SOC chip to run preset code corresponding to the control instructions, so as to configure the register-related parameters in the SOC chip to enable the SOC chip to enter the specified test mode, wherein the preset code contains the configuration parameters of the registers in the specified test mode.

[0056] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0057] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or processor 240 can be any conventional processor.

[0058] Among them, the aforementioned electronic equipment 200 includes, but is not limited to, the aforementioned ATE test machine, etc.

[0059] This application embodiment also provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium) storing a computer program, which is executed by a computer such as the above-described electronic device 200 to perform the configuration method of the chip test mode shown above.

[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0061] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0062] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0063] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0064] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for configuring a chip test mode, characterized in that, include: The code containing the configuration parameters required for the registers in each test mode of the SOC chip and the control instructions for triggering each test mode is stored in the memory within the SOC chip or in the memory connected to the SOC chip. The code is software code that can run in the kernel of the SOC chip, and the configuration parameters in the code are the configuration parameters required for the registers of the SOC chip to enter the specified test mode in order to meet the ATE test requirements. The system obtains a control command input by the user for testing a specified test mode of the SOC chip; sends the control command to the SOC chip to trigger the SOC chip to run a preset code in the memory corresponding to the control command, so as to obtain the configuration parameters in the preset code to perform write operations on the relevant parameters of the registers in the SOC chip, so as to enable the SOC chip to enter the specified test mode. The preset code contains the configuration parameters of the registers in the specified test mode and the control command for triggering the specified test mode.

2. The method according to claim 1, characterized in that, In advance, according to the ATE test requirements, for each test mode of the SOC chip, the required configuration parameters of the registers in that test mode are written into the code, and the control instructions for triggering that test mode are set in the code.

3. The method according to claim 1, characterized in that, The code is stored in the memory by burning or written to the memory by using an ATE device.

4. The method according to claim 1, characterized in that, The control command is a combination of 0 and / or 1 digital signals, which are sent to the SOC chip by changing the level of the test IO pin.

5. The method according to claim 1, characterized in that, The SOC chip is a Bluetooth chip, and the test modes of the SOC chip include: standby mode, transmit power test mode, modulation characteristic test mode, and receive sensitivity test mode.

6. A configuration device for a chip testing mode, characterized in that, include: The storage module is used to store the code containing the configuration parameters of the registers required for each test mode of the SOC chip and the control instructions for triggering each test mode into the memory within the SOC chip or the memory connected to the SOC chip. The code is software code that can run in the kernel of the SOC chip, and the configuration parameters in the code are the configuration parameters of the registers required to enable the SOC chip to enter the specified test mode in order to meet the ATE test requirements. The acquisition module is used to acquire control commands input by the user for testing the SOC chip in a specified test mode; The sending module is used to send the control command to the SOC chip to trigger the SOC chip to run the preset code in the memory corresponding to the control command, so as to obtain the configuration parameters in the preset code to perform write operation configuration on the register-related parameters in the SOC chip, so as to enable the SOC chip to enter the specified test mode. The preset code contains the configuration parameters of the registers in the specified test mode and the control command for triggering the specified test mode.

7. A SOC chip, characterized in that, The memory within the SOC chip or the memory connected to the SOC chip stores preset code. The preset code is used to configure the register-related parameters in the SOC chip so that the SOC chip enters a specified test mode. The preset code contains the configuration parameters of the registers in the specified test mode and the control instructions for triggering the specified test mode. The preset code is software code that can run in the kernel of the SOC chip, and the configuration parameters in the preset code are the configuration parameters of the registers required to meet the ATE test requirements and enable the SOC chip to enter the specified test mode. When the SOC chip receives a control command from the ATE for testing a specified test mode of the SOC chip, the SOC chip runs a preset code in the memory corresponding to the control command to obtain the configuration parameters in the preset code and perform write operations on the relevant parameters of the registers in the SOC chip.

8. An electronic device, characterized in that, include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, performs the method as described in any one of claims 1-5.

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