Self-healing system architecture based on reversible logic

Abstract

A primary cell for a self-healing system architecture is provided, comprising a first input and a second input, at least one output, and at least one functional block, wherein the cell is configurable to operate in a first state or a second state, and if operating in the first state: using the functional block to set the at least one output based on the first input using a first function of a plurality of functions during a time period, and if operating in the second state and by using time division multiplexing: using the functional block to set the at least one output based on the first input using the first function during only a part of the time period and based on a second input using a second function of the plurality of functions during another part of the time period. A self-healing system architecture using at least two such cells is also provided.

Description

Technical Field

[0001] This invention generally relates to field semiconductor architectures for computing. More particularly, it relates to the task of optimizing such architectures relative to area requirements, timing delays, and power consumption. Background Technology

[0002] With modern technological trends, we can envision future semiconductor products, such as central processing units (CPUs), system-on-a-chip (SoC) designs, or similar designs, being smaller, more powerful, more reliable, and more energy-efficient than their counterparts available today.

[0003] While continued advancements in semiconductor manufacturing push the boundaries of how many transistors can be placed within a predefined area (or volume), the increasing transistor density also brings problems such as how to handle the excessive heat generated. Therefore, excessive power consumption has become a significant bottleneck for future high-performance computing devices and has been listed as a key challenge in various roadmaps for future devices. Simultaneously, with the emergence of increasingly complex systems and processes, the self-healing capabilities of the various functional units included in semiconductor (digital) circuits are required to ensure reliability. However, achieving such self-healing capabilities can be difficult, often relying on adding multiple redundant functional units without increasing area overhead and reducing computational throughput. Summary of the Invention

[0004] To at least partially address the issues identified above, this disclosure provides an embryonic cell for a self-healing system architecture comprising two or more such embryonic cells, as defined in the independent claims. Additional embodiments are defined in the dependent claims.

[0005] According to a first aspect of this disclosure, a primary unit for a self-healing system architecture is provided. The unit includes at least a first input and a second input, at least one output, and a function block. The function block can be configured to use one of a plurality of functions to set the at least one output based on at least one of the first and second inputs. The unit can be configured to operate in a first state or a second state different from the first state. The unit is further configured to, if operating in the first state, use the function block to set the at least one output based on the first input using the first function of the plurality of functions during a time period. The unit is further configured to, if operating in the second state and using time-division multiplexing, use the function block to set the at least one output based on the first input using the first function during only a portion of the time period, and to set the at least one output based on the second input using the second function of the plurality of functions during another portion of the time period. Here, the function block is implemented using reversible logic.

[0006] Because the unit can be configured such that each unit can perform its own specialized task as well as the task of an adjacent failed unit, the primary unit according to this disclosure provides self-healing capability without relying on adding additional backup units. This reduces the area overhead problem present in conventional self-healing techniques. Since the unit can also use time-division multiplexing to perform two tasks in a single clock cycle, there is no need to reduce computational throughput even if an adjacent unit fails. Finally, since reversible logic allows the unit's functions to be performed without losing any information, the computation performed by the unit does not necessarily lead to an increase in entropy, and the power dissipation caused by the unit can be reduced. In other words, according to the first aspect and the primary unit as described herein, a simultaneous overall optimization of the power, area, and (timing) delay (PAD) product is provided based on a trade-off between the reduced area overhead of the primary unit and the network in which the unit operates, the reduced timing delay due to time-division multiplexing, and the reduced power dissipation due to the reversible logic of the functional blocks of the unit (even though this also provides a slight increase in area due to the presence of one or more additional outputs required for reversibility).

[0007] In some embodiments, the primary unit may include a multiplexer. The multiplexer can be used to select between a first input and a second input as input to a function block.

[0008] In some embodiments, the multiplexer may also be implemented using reversible logic, thereby further reducing the overall power dissipation caused by the primary unit.

[0009] In some embodiments, the functional block of the primary unit may include (or may be) an arithmetic logic unit (ALU). As previously described herein, this ALU may be envisioned to be implemented at least in part using reversible logic.

[0010] In some embodiments, the functional blocks of the primary unit may include (or may be) an artificial neural network (ANN). The neural network may be trained to perform functions of an ALU, for example, that would otherwise be implemented using various gates. As previously described herein, it is conceivable that such a neural network may be implemented at least in part using reversible logic. It is also conceivable that the neural network may perform functions other than those of the ALU, and that the neural network may be used to obtain functionalities that are impossible for a general ALU.

[0011] According to a second aspect of this disclosure, a self-healing system architecture is provided, comprising at least a first unit and a second unit, which are primary units according to the first aspect.

[0012] In some embodiments, the first input of the second unit may be the second input of the first unit. The system architecture may be further configured to determine whether the second unit is a failed unit. If the second unit is determined to be a failed unit, the first unit may be configured to operate in a second state using the first function of the second unit as a second function of the first unit, i.e., such that the first unit can perform the task of the second unit during the other half of the clock cycle. Through this time-division multiplexing and the possibility that a unit can perform both its own task and the task of a failed unit without introducing additional timing delays, this system architecture provides improved reliability without the need for additional redundant units and additional timing delays, thereby reducing the overall required area overhead without negatively impacting throughput.

[0013] This invention relates to all possible combinations of the features cited in the claims. The objectives and features according to the first aspect can be combined with or replaced by the objectives and features described according to the second aspect, or vice versa.

[0014] Additional objectives and advantages of various embodiments of this disclosure will be described below by way of illustrative examples. Attached Figure Description

[0015] The exemplary embodiments will now be described with reference to the accompanying drawings, wherein:

[0016] Figure 1 A primary unit for a self-healing structure according to one or more exemplary embodiments of the present disclosure is illustrated schematically;

[0017] Figure 2a Functional blocks for this unit according to one or more example embodiments of the present disclosure are schematically shown, including artificial neural networks implemented using reversible logic;

[0018] Figure 2b The nodes of this neural network according to one or more example embodiments of the present disclosure are schematically shown; and

[0019] Figure 3 A self-healing system architecture comprising two or more primary units according to one or more embodiments of the present disclosure is illustrated schematically.

[0020] In the accompanying drawings, unless otherwise stated, the same reference numerals will be used for the same elements. Unless explicitly stated to the contrary, the drawings only show those elements necessary to illustrate the exemplary embodiments, while other elements may be omitted or only implied for clarity. As shown in the various drawings, the dimensions of elements and regions are exaggerated for illustrative purposes; therefore, the dimensions of layers and regions are provided to illustrate the general structure of the embodiments. Detailed Implementation

[0021] Various embodiments of the primary unit according to this disclosure will now be referred to. Figure 1 describe.

[0022] Figure 1 An embodiment of a primary unit 100 according to this disclosure is illustrated schematically. Unit 100 includes a first input 110 and a second input 112. Unit 100 also has an output 120. It is conceivable that there may be more than one output, and similarly, more than two inputs. Unit 100 also includes a function block 140, a control input 150, a clock input 152, and a memory 160 to which the function block 140 can communicate. Using a selection device 130 (such as, for example, a multiplexer), it can be determined which of the first input 110 and the second input 120 will become an input to the function block 140, so that the function block 140 uses a specific function to map the selected input to the output 120. Multiple such functions may, for example, be pre-stored in the memory 160, and the function block 140 may select which function to use based on a signal received on the control input 150. It is also conceivable that the function to be used by the function block 140 may be provided via the control input 150, and the memory 160 may, for example, be updated accordingly for future use with this function. The control input 150 can also instruct the selection device 130 which of the two inputs 110 and 112 it will select.

[0023] As an example, unit 100 can be instructed (configured) to operate in a first state. This instruction can be provided to unit 100, for example, via control input 150. It is also conceivable that function block 140 itself can determine which state unit 100 should operate in. When it is determined that unit 100 should operate in the first state, unit 100 can use function block 140 to set output 120 based on first input 110 using a first function (e.g., stored in memory 160 or as one of a plurality of functions received, for example, on control input 150). Function block 140 can use the first function for a period of time. This period of time can, for example, correspond to the clock cycle of a clock signal received on clock input 152.

[0024] Unit 100 can also be instructed (configured) to operate in a second state different from the first state. This instruction can also be provided to unit 100, for example, via control input 150 or in another manner, such as identified by function block 150 of unit 100. When it is determined that unit 100 is to operate in the second state, time-division multiplexing can be used so that during only a portion of the clock cycle (e.g., the first half of the clock cycle), selection device 130 selects the first input 110 for function block 140, so that function block 140 can use the first function to map the first input 110 to output 120. Then, during another portion of the clock cycle (e.g., the remainder, such as the second half of the clock cycle), selection device 130 can instead select the second input 112 for function block 140, so that function block 140 can instead use the second function to instead map the second input 112 to output 120. The second function may be stored, for example, in memory 160, and function block 140 may know which function to use based on a signal received on control input 150, or receive the second function, for example, via control input 150 itself. Therefore, if unit 100 is operating in the second state, unit 100 may first perform its "normal task" of using the first function to map its first input 110 to output 120, and then perform another task by using another function to map the second input 112 to output 120. As will be described below, this other / secondary function may be a function normally used by another unit to perform its task, and if that other unit fails (i.e., malfunctions), unit 100 may take over the responsibilities of that other unit and perform both its own task and the task of the failed unit during the same clock cycle, thereby without causing any decrease in computational throughput. For example, if the clock signal received at clock input 152 is a square wave, it is conceivable that unit 100 and function block 140 use a first function to perform a first task when triggered by a first slope (i.e., rising or falling), and use a second function to perform a second task when triggered by a second slope different from the first (i.e., falling or rising). Other possibilities, depending on how precisely the clock signal is generated, are of course also possible. Although shown as a single arrow, it is conceivable here that control input 150 may include several signals for various parts of control unit 100. Control input 150 may, for example, accept one or more control signals provided by one or more control units external to unit 100.

[0025] Although referred to herein as a control “input,” it is conceivable that control input 150 could also be a bidirectional control input / output, enabling it to also be used to send one or more signals from unit 100 to, for example, other units or one or more control units external to unit 100. In other words, for example… Figure 1The various inputs, outputs, and arrows in the diagram are illustrative and only represent the functionality of unit 100 and its components, not the explicit physical location of one or more physical outputs / inputs.

[0026] In unit 100 and other units described herein, the input / output or other connections between two or more components of the unit (although shown as single lines / single arrows) may also include multiple signals to enable, for example, the simultaneous reception / output / transfer of multiple bits.

[0027] In some embodiments of unit 100, function block 140 may be, for example, an arithmetic logic unit (ALU), including combinational logic necessary to implement one or more arithmetic and / or logical operations / functions (such as ADD, SUBTRACT, AND, OR, XOR, NAND, NOR, XNOR, NOT, data buffer, etc.). The ALU may have access to one or more data registers that it can use to perform a specific function. The data registers may be located, for example, in memory 160 or stored elsewhere, such as within function block 140 itself.

[0028] To reduce power consumption, functional block 140 is implemented at least partially using reversible logic. By using appropriate gates, the function performed by functional block 140 can make a specific output match only one specific input, i.e., make a 1:1 correspondence between the input and the output. Examples of suitable gates that can be used to achieve this reversible behavior include, for example, NOT gates, CNOT gates, Input Toffoli gates, Peres gates, double Peres gates, etc. Other gates required (such as, for example, OR gates or similar gates) can be made reversible by adding additional, auxiliary, and / or useless inputs and outputs as necessary. It is conceivable that although such additional inputs / outputs may increase area overhead, the savings relative to power consumption outweigh the increased area. In general, this disclosure provides a primary cell in which such trade-offs between various variables to be optimized are carefully considered to simultaneously optimize the power-area-delay (PAD) product.

[0029] At least a portion of the various structures and devices envisioned herein can be implemented using, for example, VHDL (or other equivalents) and one or more field-programmable gate arrays (FPGAs). For validation purposes, this implementation of a particular ALU device was performed for both the primary cell disclosed herein and for standard architectures using typical (non-reversible) logic gates in functional blocks. It has been shown that despite the increase in area overhead (9% for the typical logic gate version and 11% for the primary cell disclosed herein), the power consumption is reduced by nearly 20% (79mW for the typical logic gate version and 64mW for the primary cell disclosed herein). Thus, it has been shown that a small increase in area overhead can lead to even greater power consumption reductions, thereby validating the advantages of the primary cell disclosed herein.

[0030] Other examples of function blocks will now be referenced. Figure 2a and 2b To describe.

[0031] Figure 2a An example embodiment of functional block 200 according to this disclosure is illustrated schematically. Functional block 200 has an input 210, an output 220, and further includes a neural network 230. Neural network 230 includes an input layer 240, one or more hidden layers 250, and an output layer 260. Each layer of neural network 230 may contain a different number of nodes 270 and includes connections 280 interconnecting the nodes 270 in different layers. The exact number of nodes in each layer and the exact connections existing between different layers can be specified depending on the type of neural network to be used and the required functionality of the neural network. There may also be more than one input 210 and more than one output 220. It is conceivable that the number of nodes in the input layer 240 and the output layer 260 respectively is such that these nodes provide at least these numbers of inputs and outputs. For example, for a single input 210, the input layer 240 includes at least one node 270. For two inputs 210, the input layer includes at least two nodes 270, and so on. The same applies to output layer 260, so that there are at least as many nodes in output layer 260 as in output layer 220.

[0032] Figure 2b An example of node 270 is illustrated schematically. Node 270 is assumed to be the j-th node in a particular layer and receives one or more inputs x. m , where m is an integer between 1 and M, and M is an integer equal to the total number of inputs to node 270. Inputs can, for example, originate from another layer, i.e., nodes in the layer preceding the layer to which the j-th node 270 belongs. A bias b may also be provided, for example. For each input x... m Assign node 270 and have the input x mThe specific weight w associated with the connection between another node as its input. m In multiplier box 270, each input x m All of them are associated with their corresponding weights w m Multiplication. In subsequent adder block 272, the product of the weights and the input is added together (along with a bias b, if present) to form a sum. In the final nonlinear block 273, the sum a j The output of the node is passed through a nonlinear function σ (e.g., the sigmoid function) to determine whether the node's output is activated. Finally, the result of this function provides the output o of the j-th node, 270. j =σ(a j ).

[0033] After one or more inputs 210 have been propagated through layers 240, 250, 260 of neural network 230, one or more outputs 220 from output layer 260 can be compared with the desired result, and the deviation between the outputs 220 and the desired result can be used to train the network. This training can be performed by updating the weights (i.e., the connections between different layers) using, for example, backpropagation, until neural network 230 is determined to be ready for practical use. With the network already trained, neural network 230 knows how to estimate the desired function, i.e., the desired mapping between one or more inputs 210 and one or more outputs 220. Neural network 230 can thus be used, for example, to simulate the behavior of the ALU or to perform other functions as needed.

[0034] Here, it can be envisioned that each of the blocks 271, 272, and 273 of node 270 is implemented at least partially using reversible logic. As a result, less information is lost, and the power consumption of the network can be reduced (see, for example, Landauer's principle, which states that losing one bit of information will generate approximately k*T*ln(2) joules of heat energy (where k is the Boltzmann constant and T is the calculated absolute temperature).

[0035] For verification purposes, implementations of specific artificial neural network devices were performed for both the reversible logic cases disclosed herein and standard architectures using typical (non-reversible) logic gates. A power consumption reduction of approximately 17% has been demonstrated (96W for the typical logic gate version and 79W for the reversible logic cases disclosed herein).

[0036] Reference Figure 3 Various embodiments of the self-healing system architecture will now be described in more detail.

[0037] Figure 3An embodiment of a self-healing system architecture 300 according to this disclosure is schematically illustrated. Architecture 300 includes at least a first primary unit 310 and a second primary unit 320. Both units 310 and 320 are, for example, referenced in [reference missing]. Figure 1 , 2a The primary unit described in 2b. The first unit 310 is connected to the second unit 320 such that the first input 311 of the first unit 310 is also the second input 322 of the second unit 320, and the second input 312 of the first unit 310 is also the first input 321 of the second unit 320. The outputs 313 and 323 of the first unit 310 and the second unit 320 are further connected to the first inputs 331 and 341 and the second inputs 332 and 342 of the additional units 330 and 340, respectively, as shown in... Figure 3 As shown in the figures. Additional units 330 and 340 also have corresponding outputs 333 and 343.

[0038] In the appendix Figure 3 With the unit configuration shown, it is conceivable that during normal operation of units 310 and 320, the first unit 310 may perform its “own” task, namely, using a first function to map its first input 311 to its output 313, as previously described herein. This is achieved by using its selection device 314 to select the first input 311 as an input to its function block 315. As mentioned above, control inputs and clock signals may also be provided to various units, and the first unit 310 may, for example, perform its own task during the entire clock cycle. This posture, when the unit operates as intended, may be referred to as the “first state.”

[0039] It is also conceivable that if, for example, the second unit 320 is determined to be malfunctioning (i.e., the unit has failed or malfunctioned), the first unit 310 can be configured to operate in a second state, different from the first state. In this second state, the first unit 310 can perform either its own function or the function of the failed second unit 320. The selection device 314 is used to select the appropriate input to the function block 315 depending on whether the first unit 310 will perform its own function or the function of the second unit 320. For example, when in the second state, the first unit 310 can, for example, first perform its own task during a portion of the full clock cycle, and then also perform the task of the failed second unit 320 during another portion of the full clock cycle. By providing the first input 321 of the second unit 320 as the second input 312 of the first unit 310 and by using the first function of the second unit 320 as the second function of the first unit 310, the first unit 310 can take over the responsibilities of the second unit 320 during that other portion of the full clock cycle. By using this time-division multiplexing, a failure of the second unit 320 can be compensated by the first unit 310 without adding additional timing delays and thus without further reducing throughput. The exact order in which the first unit 310 performs its own tasks and the tasks of the failed second unit 320 can be communicated to the first unit 310, for example, using control inputs, as discussed earlier herein.

[0040] The failure of the second unit 320 can be evaluated, for example, by the unit 320 itself or by one or more additional controllers (not shown), using various test schemes or similar schemes. The failure of the second unit 320 can be assessed using control inputs (such as those previously referred to...). Figure 1 The control input 150 is communicated to the first unit 310.

[0041] During normal operation, the output 323 of the second unit 320 is provided as the first input 331 of the auxiliary unit 330. During a failure of the second unit 320, the output 323 of the second unit 320 will instead correspond to (or be replaced by) the output 313 of the first unit 310. To compensate for this as well, it is conceivable that during a failure of the second unit 320, i.e., when the first unit 310 is operating in the second state, the auxiliary unit 330 will be instructed (e.g., by the control unit via a control input) to use its second input 332 as an input to its function blocks, since this second input 332 is connected to the output 313 of the first unit 310 (e.g., ...). Figure 3(As shown). Thus, normal operation of the entire architecture can be maintained, for example, in the event of a failure of the second unit 320. In other cases, such as during the failure of units other than the second unit 320, additional instructions can be sent to the various remaining units so that one of these remaining units can take over the responsibilities of the failed unit and that the outputs are properly routed so that the unit that would have been processing the outputs of the failed unit now receives the corresponding output from another unit at another of its inputs.

[0042] In summary, by combining this self-healing architecture, which does not introduce additional timing delays, with various functional blocks that implement primary units using reversible logic, this disclosure provides a solution that simultaneously optimizes multiple parameters in a manner that improves the overall power-area-delay (PAD) product. As described above, this is achieved through a combination of the following:

[0043] a) The self-healing architecture provides improved reliability, where one unit can perform its own task as well as the task of another unit without additional timing delays. This eliminates the need for redundant units, thus reducing area overhead; and

[0044] b) Use reversible logic to reduce power consumption, where the auxiliary and / or useless inputs and outputs required for this reversible logic increase the area overhead, but the overall benefit of reduced power consumption still outweighs this increase.

[0045] Although features and elements may be described above in specific combinations, each feature or element may be used alone without other features and elements, or in various combinations with or without other features and elements.

[0046] Furthermore, other variations of the disclosed embodiments may be understood and implemented by those skilled in the art from a study of the drawings, this disclosure, and the appended claims when carrying out the claimed invention. In the claims, the word "comprising" does not exclude other elements, and the indefinite articles "a" or "an" do not exclude a plural. The mere fact that certain features are recited in mutually different dependent claims does not indicate that combinations of these features cannot be advantageously used.

Claims

1. A primary unit (100) for a self-healing system architecture, the primary unit (100) comprising at least a first input (110) and a second input (112), at least one output (120), and functional blocks (140, 200) configured to use one of a plurality of functions to set the at least one output (120) based on at least one of the first input (110) and the second input (112). The primary unit (100) can be configured to operate in a first state or a second state different from the first state, and: If operating in the first state, then: the function blocks (140, 200) are used to set the at least one output (120) based on the first input (110) during the entire single clock cycle using the first function of the plurality of functions, and If operating in the second state and using time-division multiplexing, then: the function blocks (140, 200) are used to set the at least one output (120) based on the first input (110) during only a portion of the single clock cycle triggered by the first slope, and the second function of the plurality of functions is used to set the at least one output (120) based on the second input (112) during another portion of the same single clock cycle triggered by a second slope different from the first. The aforementioned functional blocks (140, 200) are implemented using reversible logic.

2. The primary unit (100) as claimed in claim 1, comprising a multiplexer (130) for selecting between the first input and the second input as inputs to the function block.

3. The primary unit (100) as claimed in claim 2, wherein the multiplexer is implemented using reversible logic.

4. The unit as claimed in claim 1, wherein the functional block includes an arithmetic logic unit (ALU).

5. The unit as claimed in claim 1, wherein the functional block includes a neural network (230).

6. A self-healing system architecture (300) comprising at least a first unit (310) and a second unit (320), both of which are primary units (100) as described in any one of claims 1 to 3.

7. The system architecture of claim 6, wherein the first input (321) of the second unit (320) is the second input (312) of the first unit (310), and wherein the system architecture is further configured to: Determine whether the second unit (320) is a failed unit, and If it is determined that the second unit (320) is a failed unit, the first unit is configured to operate in the second state by using the first function of the second unit (320) as the second function of the first unit (310).

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