Non-volatile memory device and storage device

Abstract

A non-volatile memory device and a memory device are disclosed. The non-volatile memory device includes an array of memory cells including strings of cells, a row decoder connected with a ground select transistor of each of the strings of cells through a ground select line, connected with a memory cell of each of the strings of cells through a word line, and connected with a string select transistor of each of the strings of cells through a string select line, and a page buffer connected with the strings of cells through a bit line. In a first period of an inspection operation, the page buffer applies a first bias voltage to the bit line, and the row decoder applies an off voltage to the ground select line, applies an on voltage to the string select line, and applies a first inspection voltage to the word line. In a second period of the inspection operation, the page buffer senses a first change in voltage of the bit line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0121631, filed on September 21, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments disclosed herein relate to electronic devices, and more particularly to non-volatile memory devices for detecting failures and storage devices including the non-volatile memory devices. Background Technology

[0004] Storage devices are devices that store data under the control of host devices (such as computers, smartphones, or tablets). Storage devices include devices that store data on disks (such as hard disk drives, HDDs) or devices that store data in semiconductor memory (specifically, non-volatile memory, such as solid-state drives, SSDs, or memory cards).

[0005] Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0006] With the development of semiconductor manufacturing technology, the integration and capacity of storage devices are constantly increasing. Higher integration makes it possible to reduce the cost of manufacturing storage devices. However, this increased integration leads to the miniaturization and structural changes of storage devices, introducing various new problems. These problems can corrupt the data stored in the storage device, thus reducing its reliability. Therefore, there is a persistent need for methods and devices to improve the reliability of storage devices. Summary of the Invention

[0007] Embodiments of this disclosure provide a non-volatile memory device for checking whether a fault has occurred at a non-volatile memory location in a vertical structure, and a storage device including the non-volatile memory device.

[0008] According to an example embodiment, a non-volatile memory device includes: a memory cell array including cell strings, wherein each cell string includes a ground select transistor, a memory cell, and a string select transistor stacked in a direction perpendicular to a substrate; a row decoder connected to the ground select transistor of each cell string via a ground select line, connected to the memory cell of each cell string via a word line, and connected to the string select transistor of each cell string via a string select line; and a page buffer connected to the cell strings via bit lines. During a first period of the check operation, the page buffer applies a first bias voltage to the bit lines. During the first period of the check operation, the row decoder applies a turn-off voltage to the ground select line, a turn-on voltage to the string select line, and a first check voltage to the word lines. During a second period of the check operation, the page buffer senses a first change in the voltage of the bit lines. During the second period of the check operation, in response to sensing the first change in the voltage of the bit lines, a status fault signal is output.

[0009] According to an example embodiment, a storage device includes: a non-volatile memory device including cell strings, wherein each cell string includes a ground select transistor, a memory cell, and a string select transistor stacked on a substrate in a direction perpendicular to the substrate; and a controller that transmits a command to the non-volatile memory device. The non-volatile memory device performs a check operation in response to the command. The check operation includes: applying a bias voltage to a bit line connected to the cell strings, applying a turn-off voltage to a ground select line connected to the ground select transistor of each cell string, applying a turn-on voltage to a string select line connected to the string select transistor of each cell string, and a first time period applying a check voltage to a word line connected to the memory cell of each cell string, and a second time period sensing a change in the voltage of the bit lines.

[0010] According to an example embodiment, a non-volatile memory device includes a peripheral region and a memory cell region. The memory cell region includes a first metal pad and a memory cell array, the memory cell array including cell strings, wherein each cell string includes a ground select transistor, a memory cell, and a string select transistor stacked on the substrate in a direction perpendicular to the substrate. The peripheral region includes: a second metal pad; a row decoder connected to the ground select transistor of each cell string via a ground select line, connected to the memory cell of each cell string via a word line, and connected to the string select transistor of each cell string via a string select line; and a page buffer connected to the cell strings via bit lines. The peripheral region is perpendicularly connected by the first and second metal pads. During a first period of the check operation, the page buffer applies a bias voltage to the bit lines. During the first period of the check operation, the row decoder applies a turn-off voltage to the ground select line, an turn-on voltage to the string select line, and a check voltage to the word lines. During a second period of the check operation, the page buffer senses a change in the voltage of the bit lines. During the second period of the check operation, in response to sensing a change in the voltage of the bit lines, a status fault signal is output. Attached Figure Description

[0011] The above and other objects and features of this disclosure will become apparent from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating a non-volatile memory device according to an exemplary embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A circuit diagram of an example memory block within a memory block.

[0014] Figure 3 yes Figure 2 A three-dimensional diagram of the structure of a portion of a memory block.

[0015] Figure 4 An example of a non-volatile memory device performing a check operation is shown.

[0016] Figure 5 A first example of the voltage applied to a memory block during an inspection operation is shown.

[0017] Figure 6 A second example of the voltage applied to a memory block during an inspection operation is shown.

[0018] Figure 7 An example is shown in which a non-volatile memory device performs a check operation by distinguishing between a threshold voltage error and a short-circuit channel error in a ground selection transistor.

[0019] Figure 8 An example of the voltage applied to the memory block during the second phase of the inspection operation is shown.

[0020] Figure 9 A storage device according to an example embodiment of the present disclosure is shown.

[0021] Figure 10 This illustrates a first example of how a storage device operates.

[0022] Figure 11 A second example of how to operate a storage device is shown.

[0023] Figure 12 A third example of how a storage device is operated is shown.

[0024] Figure 13 A fourth example of how a storage device is operated is shown.

[0025] Figure 14 The fifth example of how a storage device is operated is shown.

[0026] Figure 15 A sixth example of how a storage device is operated is shown.

[0027] Figure 16 This is a schematic diagram illustrating a memory device according to an example embodiment of the present disclosure. Detailed Implementation

[0028] Below, exemplary embodiments of this disclosure will be described in detail and clearly to the extent that those skilled in the art can readily implement this disclosure.

[0029] Figure 1 This is a block diagram illustrating a non-volatile memory device 100 according to an exemplary embodiment of the present disclosure. Reference Figure 1 The non-volatile memory device 100 includes a memory cell array 110, a line decoder 120, a page buffer 130, a pass / fail check block (PFC) 140, data input and output circuitry 150, a buffer 160, and / or control logic 170.

[0030] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block in BLK1 to BLKz includes multiple memory cells. Each memory block in BLK1 to BLKz can be connected to line decoder 120 via (multiple) ground select lines GSL, word lines WL, and (multiple) serial select lines SSL. Some of the word lines WL can be used as dummy word lines. Each memory block in BLK1 to BLKz can be connected to page buffer 130 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be connected to multiple bit lines BL in a common manner.

[0031] In the example embodiment, each of the multiple memory blocks BLK1 to BLKz can be a unit of erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz can be erased simultaneously. As another example, each of the multiple memory blocks BLK1 to BLKz can be divided into multiple sub-blocks. Each of the multiple sub-blocks can correspond to a unit of erase operation.

[0032] The row decoder 120 is connected to the memory cell array 110 via the ground select line GSL, the word line WL, and the serial select line SSL. The row decoder 120 operates under the control of the control logic 170.

[0033] The line decoder 120 can decode the line address received from the buffer 160 and can control the voltage to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded line address.

[0034] Page buffer 130 is connected to memory cell array 110 via multiple bit lines BL. Page buffer 130 is connected to data input and output circuit 150 via multiple data lines DL. Page buffer 130 operates under the control of control logic 170.

[0035] During programming operations, page buffer 130 can store data to be written to memory cells. Page buffer 130 can apply voltages to multiple bit lines BL based on the stored data. During read operations or verification read operations performed during programming or erasing operations, page buffer 130 can sense the voltages on bit lines BL and store the sensing results.

[0036] In a verification read operation associated with a programming or erasing operation, pass / fail check block 140 can verify the sensing results of page buffer 130. For example, in a verification read operation associated with a programming operation, pass / fail check block 140 can count the number of values ​​(e.g., "0") corresponding to on-cells that are not programmed to a target threshold voltage or higher.

[0037] In the verification read operation associated with the erase operation, the pass / fail check block 140 can count the number of values ​​(e.g., "1") corresponding to off-cells that were not erased to a target threshold voltage or lower. When the count result is the threshold or higher, the pass / fail check block 140 can output a failure signal to the control logic 170. When the count result is less than the threshold, the pass / fail check block 140 can output a pass signal to the control logic 170. Depending on the verification result of the pass / fail check block 140, a programming loop for programming operations can be further executed, or an erase loop for erasing operations can be further executed.

[0038] Data input / output circuitry 150 is connected to page buffer 130 via multiple data lines DL. Data input / output circuitry 150 can receive column address CA from buffer 160. Data input / output circuitry 150 can output data read from page buffer 130 to buffer 160 based on column address CA. Data input / output circuitry 150 can provide data received from buffer 160 to page buffer 130 based on column address CA.

[0039] Buffer 160 can receive commands CMD and addresses ADDR from external devices via the first channel CH1, and can exchange data "DATA" with external devices. Buffer 160 can operate under the control of control logic 170. Buffer 160 can provide commands CMD to control logic 170. Buffer 160 can provide the row address RA of address ADDR to row decoder 120, and can provide the column address CA of address ADDR to data input and output circuit 150. Buffer 160 can exchange data "DATA" with data input and output circuit 150.

[0040] Control logic 170 can exchange control signals CTRL from external devices via the second channel CH2. Control logic 170 can allow buffer 160 to route commands CMD, addresses ADDR, and data "DATA". Control logic 170 can decode commands CMD received from buffer 160 and can control non-volatile memory device 100 based on the decoded commands.

[0041] Control logic 170 may include a short channel detector 171. The short channel detector 171 can perform a check operation in response to a specified command. The check operation can be performed to check for a short channel fault. In response to detecting a short channel fault, control logic 170 can output a status fault signal. The status fault signal can be output as data "DATA" or as a control signal CTRL.

[0042] In an example embodiment, the non-volatile memory device 100 can be fabricated in a bonding manner. The memory cell array 110 can be fabricated on a first wafer, and the line decoder 120, page buffer 130, data input and output circuitry 150, buffer 160, and control logic 170 can be fabricated on a second wafer. The non-volatile memory device 100 can be implemented by coupling the first and second wafers such that the upper surfaces of the first and second wafers face each other.

[0043] In another example, the non-volatile memory device 100 can be fabricated in a cell-over-periphery (COP) configuration. Peripheral circuitry, including a row decoder 120, page buffer 130, data input and output circuitry 150, buffer 160, and / or control logic 170, can be implemented on the substrate. The memory cell array 110 can be implemented on the peripheral circuitry. The peripheral circuitry and the memory cell array 110 can be connected using through-vias.

[0044] Figure 2 yes Figure 1 A circuit diagram of an example memory block BLKa from memory blocks BLK1 to BLKz. (Refer to...) Figure 2 Multiple cell strings (CS) can be arranged in rows and columns on the substrate SUB. These multiple cell strings (CS) can be commonly connected to a common source line (CSL) formed on (or within) the substrate SUB. Figure 2 In the diagram, the location of the substrate SUB is shown as an example to help understand the structure of the memory block BLKa.

[0045] The cell string CS in each row can be connected to the ground select line GSL in a common manner, and can also be connected to the corresponding string select line in the first and second string select lines SSL1a, SSL1b, SSL2a, and SSL2b. The cell string CS in each column can be connected to the corresponding bit line in the first bit line BL1 and the second bit line BL2.

[0046] Each cell string CS may include at least one ground select transistor GST connected to the ground select line GSL and multiple memory cells MC1 to MC8 connected to multiple word lines WL1 to WL8 respectively. The first row of cell string CS may also include string select transistors SSTa and SSTb connected to the first string select lines SSL1a and SSL1b respectively. The second row of cell string CS may also include string select transistors SSTa and SSTb connected to the second string select lines SSL2a and SSL2b respectively.

[0047] In each cell string CS, the ground selection transistor GST, memory cells MC1 to MC8, and string selection transistors SSTa and SSTb can be connected in series in a direction perpendicular to the substrate SUB, and can be stacked sequentially in the same direction. In each cell string CS, at least one memory cell from MC1 to MC8 can be used as a dummy memory cell. The dummy memory cell can be unprogrammed (e.g., can be disabled for programming) or can be programmed differently from the remaining memory cells in MC1 to MC8.

[0048] In the example embodiment, memory cells placed at the same height and associated with string select lines SSL1a and SSL1b or SSL2a and SSL2b can form a physical page. Memory cells within a physical page can be connected to a subword line. Subword lines of physical pages placed at the same height can be commonly connected to a word line.

[0049] Figure 3 yes Figure 2 A three-dimensional diagram of the structure of a portion of the memory block BLKa. (Reference) Figure 2 and Figure 3 A common source region CSR is provided on the substrate SUB, extending in a first direction and spaced apart from each other in a second direction.

[0050] The common source region (CSR) can be publicly connected to form a common source line (CSL). In an example embodiment, the substrate (SUB) may include a P-type semiconductor material. The common source region (CSR) may include an N-type semiconductor material. For example, a conductive material for increasing the conductivity of the common source line (CSL) may be disposed on the common source region (CSR).

[0051] Between the common source regions (CSRs), insulating layers 112 and 112a are sequentially stacked on the substrate SUB in a third-party orientation perpendicular to the substrate SUB. Insulating layers 112 and 112a may be spaced apart from each other in the third-party orientation. In an example embodiment, insulating layers 112 and 112a may comprise silicon oxide or silicon nitride. In an example embodiment, the thickness (e.g., in the third-party orientation) of the insulating layer 112a that contacts the substrate SUB may be less than the thickness (e.g., in the third-party orientation) of each of the remaining insulating layers 112.

[0052] Pillars PL are provided between the common source regions CSR, configured to be spaced apart from each other in a first direction and a second direction, and extending through insulating layers 112 and 112a in a third direction. In an example embodiment, the pillars PL can contact the substrate SUB through insulating layers 112 and 112a. Each of the pillars PL may include an internal material 114, a channel layer 115, and / or a first insulating layer 116.

[0053] The internal material 114 may include an insulating material or an air gap. The channel layer 115 may include a P-type semiconductor material or an intrinsic semiconductor material. The first insulating layer 116 may include one or more insulating layers (e.g., different insulating layers), such as a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0054] Between the common source regions CSR, a second insulating layer 117 is provided on the upper and lower surfaces of insulating layers 112 and 112a, as well as on the exposed outer surface of the pillar PL. The second insulating layer 117 disposed on the upper surface of the insulating layer at the highest height among insulating layers 112 and 112a can be removed.

[0055] In each of the pillars PL, when the first insulating layer 116 and the second insulating layer 117 are coupled adjacent to each other, the first insulating layer 116 and the second insulating layer 117 can form an information storage layer. For example, the first insulating layer 116 and the second insulating layer 117 can include oxide-nitride-oxide (ONO) or oxide-nitride-alumina (ONA). The first insulating layer 116 and the second insulating layer 117 can form a tunneling insulating layer, a charge trapping layer, and a barrier insulating layer.

[0056] Conductive materials CM1 to CM11 are provided on the exposed outer surface of the second insulating layer 117 between the common source regions CSR and between insulating layers 112 and 112a. The conductive materials CM1 to CM11 may include metallic conductive materials. A drain 118 is provided on the pillar PL. In an example embodiment, the drain 118 may include an N-type semiconductor material (e.g., silicon). In an example embodiment, the drain 118 may be in contact with the upper surface of the channel layer of the pillar PL.

[0057] Bit lines BL2 and BL3, extending in a second direction and spaced apart from each other in a first direction, are disposed on the drain 118. Bit lines BL2 and BL3 are connected to the drain 118. In an example embodiment, the drain 118 and the bit lines (e.g., BL2 and BL3) may be connected via a contact plug. Bit lines BL2 and BL3 may comprise a metallic conductive material.

[0058] The pillar PL, together with the first insulating layer 116 and the second insulating layer 117 and the conductive materials CM1 to CM11, forms a cell string CS. Each of the pillars PL, together with the first insulating layer 116 and the second insulating layer 117 and the adjacent conductive materials CM1 to CM11, forms a cell string. The first conductive material CM1 may form a ground selection transistor GST together with the first insulating layer 116, the second insulating layer 117 and the adjacent channel layer 115. The first conductive material CM1 may extend in a first direction to form a ground selection line GSL.

[0059] The second conductive material CM2 to the ninth conductive material CM9 can be together with the first insulating layer 116, the second insulating layer 117, and the adjacent channel layer 115 to form the first memory cell MC1 to the eighth memory cell MC8. The second conductive material CM2 to the ninth conductive material CM9 can extend in a first direction to form the first word line WL1 to the eighth word line WL8, respectively.

[0060] The tenth conductive material CM10 can form a string select transistor SSTa together with the adjacent first insulating layer 116, second insulating layer 117, and channel layer 115. The tenth conductive material CM10 can extend in a first direction to form string select lines SSL1a and SSL2a.

[0061] The eleventh conductive material CM11 can form a series select transistor SSTb together with the adjacent first insulating layer 116, second insulating layer 117, and channel layer 115. The eleventh conductive material CM11 can extend in a first direction to form series select lines SSL1b and SSL2b.

[0062] When the first conductive material CM1 to the eleventh conductive material CM11 are stacked upwards on the third side, in each cell string CS, the ground selection transistor GST, memory cells MC1 to MC8, and string selection transistors SSTa and SSTb can be stacked upwards on the third side.

[0063] Since the channel layer 115 is shared by the first conductive material CM1 to the eleventh conductive material CM11 in each of the pillars PL, the ground selection transistor GST, memory cells MC1 to MC8, and string selection transistors SSTa and SSTb can be connected in series in the third direction in each cell string CS. For example, the channel layer 115 thus shared can form a vertical body.

[0064] Since the first conductive material CM1 to the ninth conductive material CM9 are connected to a common ground, the ground selection line GSL and the first word line WL1 to the eighth word line WL8 can be considered to be connected to a common ground in the cell string CS.

[0065] Memory blocks BLKa can be provided at a three-dimensional (3D) memory array. The 3D memory array is monolithically formed in one or more physical layers of a memory cell MC array, each memory cell MC having an active region disposed above a silicon substrate and circuitry associated with the operation of those memory cells MC. The circuitry associated with the operation of the memory cell MC can be located on or within such a substrate. The term "monolithic" means that each layer of the array is directly deposited on the layer of each bottom layer of the 3D memory array.

[0066] In an exemplary embodiment of this disclosure, the 3D memory array includes vertically oriented vertical cell strings (or NAND strings) such that at least one memory cell is situated on top of another memory cell. At least one memory cell may include a charge trapping layer. Each cell string may also include at least one selection transistor disposed on the memory cell MC. The at least one selection transistor may have the same structure as the memory cell MC and may be formed consistent with the memory cell MC.

[0067] Suitable configurations of three-dimensional memory arrays are described by reference to the following patent documents incorporated herein by reference, wherein the three-dimensional memory array is configured as multiple levels with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0068] like Figure 3 As shown, the channel layer 115 and the conductive materials CM1 to CM11 are separated by a first insulating layer 116 and a second insulating layer 117. In an example embodiment where the first insulating layer 116 and the second insulating layer 117 are degraded, the channel layer 115 and the conductive materials CM1 to CM11 may be short-circuited. For example, the first insulating layer 116 and the second insulating layer 117 may be degraded due to iterative write and erase operations.

[0069] In an example embodiment where the channel layer 115 is short-circuited to one of the conductive materials CM1 to CM11, the voltage of the channel layer 115 may follow the voltage of the short-circuited conductive material among the conductive materials CM1 to CM11. This short circuit may cause abnormal operation of the non-volatile memory device 100 that performs write, read, and erase operations based on the voltage of the channel layer 115.

[0070] Figure 4 An example of a non-volatile memory device 100 performing a check operation is shown. The non-volatile memory device 100 can check for channel faults that occur when the channel is short-circuited by performing the check operation.

[0071] refer to Figure 1 , Figure 2 and Figure 4 In operation S110, the page buffer 130 can be subjected to a first bias voltage VBA (refer to...). Figure 5 ) to line BL. In operation S120, the line decoder 120 can apply a turn-off voltage VOFF (reference) Figure 5 The line selector line GSL is connected to the ground selection line. In operation S130, the line decoder 120 can apply a turn-on voltage VON (reference). Figure 5 The serial select lines SSL1a, SSL1b, SSL2a, and SSL2b are connected. During operation S140, the line decoder 120 can apply a check voltage VCK (reference...). Figure 5 (From word lines WL1 to WL8. Operations S110 to S140 can constitute the first time period of the inspection operation.)

[0072] In operation S150, page buffer 130 can detect (or sense) a change in the voltage of bit line BL. In an example embodiment, page buffer 130 can float bit line BL for a preset time period and then detect the voltage of bit line BL. Page buffer 130 can detect whether the voltage of bit line BL changes from a first bias voltage VBA. Operation S150 of detecting a change in the voltage of bit line BL can constitute a second time period of the inspection operation.

[0073] In response to the detection of a change in the voltage of bit line BL, the non-volatile memory device 100 may report a status fault in operation S160. For example, the non-volatile memory device 100 may output a status fault signal in the form of data "DATA" or control signal CTRL.

[0074] In response to no change in the voltage of bit line BL, the non-volatile memory device 100 can report a normal status during operation S170. For example, the non-volatile memory device 100 can report a normal status by not outputting a status fault signal. The non-volatile memory device 100 can terminate the check operation.

[0075] Figure 5 A first example of the voltage applied to memory block BLKa during a check operation is shown. (Reference) Figure 1 , Figure 4 and Figure 5The bias voltage VBA applied to bit lines BL1 and BL2 can be a positive voltage. The turn-off voltage VOFF applied to the ground select line GSL can be a voltage sufficient to turn off the ground select transistor GST. The turn-on voltage VON applied to the string select lines SSL1a, SSL1b, SSL2a, and SSL2b can be a voltage sufficient to turn on the string select transistors SSTa and SSTb. The check voltage VCK applied to word lines WL1 through WL8 can be a voltage sufficient to turn on memory cells MC1 through MC8, and can be less than the bias voltage VBA.

[0076] In an example embodiment where a channel fault exists, such that a short circuit is present, the voltages of bit lines BL1 and BL2 can be reduced from the bias voltage VBA to the check voltage VCK. Page buffer 130 can determine that a short-circuited channel, i.e., a channel fault exists, based on the reduction of the voltages of bit lines BL1 and BL2 from the bias voltage VBA to the check voltage VCK.

[0077] In an example embodiment, a check operation can be performed when memory cells MC1 to MC8 of memory block BLKa are in an erase state. The threshold voltage of memory cells MC1 to MC8 in the erase state can be less than the ground voltage. The row decoder 120 can apply the ground voltage as the check voltage VCK. The page buffer 130 can detect whether the voltage of bit line BL drops to the ground voltage. The control logic 170 can determine a short-circuit channel, i.e., a channel fault, based on the voltage of bit lines BL1 and BL2 dropping to the ground voltage.

[0078] In the example embodiment, the turn-on voltage VON can be 5V or higher. The bias voltage VBA can be 1V or higher. The turn-off voltage VOFF can be ground. The check voltage VCK can be a positive voltage (e.g., 0.5V or lower) or a negative voltage (e.g., -0.5V or higher).

[0079] Figure 6 A second example of the voltage applied to memory block BLKa during a check operation is shown. (Reference) Figure 1 , Figure 4 and Figure 6 The bias voltage VBA applied to bit lines BL1 and BL2 can be ground voltage (e.g., 0V). The turn-off voltage VOFF applied to the ground select line GSL can be a voltage sufficient to turn off the ground select transistor GST. The turn-on voltage VON applied to the string select lines SSL1a, SSL1b, SSL2a, and SSL2b can be a voltage sufficient to turn on the string select transistors SSTa and SSTb. The check voltage VCK applied to word lines WL1 through WL8 can be a voltage sufficient to turn on memory cells MC1 through MC8 and can be greater than the bias voltage VBA.

[0080] In an example embodiment where a channel fault exists, such that a short circuit is present, the voltages of bit lines BL1 and BL2 can be increased from the bias voltage VBA to the check voltage VCK. Page buffer 130 can determine that a short-circuited channel, i.e., a channel fault exists, based on the increase in the voltages of bit lines BL1 and BL2 from the bias voltage VBA to the check voltage VCK.

[0081] In an example embodiment, a check operation can be performed when memory cells MC1 to MC8 of memory block BLKa are in an erase state. The threshold voltage of memory cells MC1 to MC8 in the erase state can be less than the ground voltage. The row decoder 120 can apply a positive voltage of 1V or higher as the check voltage VCK. The page buffer 130 can detect whether the voltage of bit line BL increases to the check voltage VCK. The control logic 170 can determine a short-circuit channel, i.e., a channel fault, based on the increase in the voltage of bit lines BL1 and BL2 to the check voltage VCK.

[0082] In the example embodiment, the turn-on voltage VON can be 5V or higher. The turn-off voltage VOFF can be ground voltage. The bias voltage VBA can be a positive voltage (e.g., 0.5V or lower) or a negative voltage (e.g., -0.5V or higher) close to ground voltage.

[0083] Channel layer 115 (reference) Figure 3 The voltage change may occur due to abnormal operation of the ground select transistor GST and short-circuited channel. For example, in an example embodiment where the threshold voltage of a particular ground select transistor GST is less than the turn-off voltage VOFF, the voltage of the channel layer 115 corresponding to that particular ground select transistor GST may change to the voltage of the common source line CSL.

[0084] Because memory cells and word lines of the same height are controlled by a common ground, a short-circuit channel can cause large-scale errors in word line cells. In contrast, a threshold voltage error of the ground select transistor GST may cause an error limited to a single cell string CS11, CS12, CS21, or CS22, and can be corrected by error-correcting codes. Therefore, the non-volatile memory device 100 according to an exemplary embodiment of this disclosure can distinguish between short-circuit channel errors and threshold voltage errors of the ground select transistor GST, and can omit the status fault report associated with the threshold voltage error of the ground select transistor GST.

[0085] Figure 7 An example is shown in which a non-volatile memory device 100 performs a check operation by distinguishing between a threshold voltage error and a short-circuit channel error in the ground selection transistor GST. Reference Figure 1 , Figure 2 and Figure 7During operation S210, the non-volatile memory device 100 can perform a first stage of a check operation. For example, the first stage of the check operation may include... Figure 4 The following operations: Apply reference Figure 5 and Figure 6 The voltage described is used to detect changes in the voltage of the bit line, and the state of fault or normal is determined in response to the detection result.

[0086] In operation S220, the pass / fail check block 140 of the non-volatile memory device 100 can count the number of bit lines whose voltage changes, as a first count. The pass / fail check block 140 can provide the first count to the control logic 170.

[0087] In operation S230, the non-volatile memory device 100 can perform the second phase of the check operation. (Refer to...) Figure 8 The second phase is described below. In operation S240, the pass / fail check block 140 of the non-volatile memory device 100 can count the number of bit lines whose voltage changes, as a second count. The pass / fail check block 140 can provide the second count to the control logic 170.

[0088] In operation S250, control logic 170 can determine whether the first count and the second count are not equal. In response to the first count and the second count being not equal, in operation S260, control logic 170 can determine a status fault. For example, control logic 170 can output a status fault signal as data "DATA" or control signal CTRL.

[0089] In response to the first count and the second count being equal, in operation S270, control logic 170 can determine that the state is normal. Control logic 170 can report the state as normal by omitting the output of the state fault signal.

[0090] In an example embodiment, the first count may indicate a combination of a short-circuit channel error and a threshold voltage error of the ground select transistor GST. The second count may indicate a threshold voltage error of the ground select transistor GST. In an example embodiment where the first and second counts are equal, a change in the voltages of bit lines BL1 and BL2 detected in the first phase of the check operation may originate from a threshold voltage error of the ground select transistor GST. Therefore, control logic 170 can determine that the state is normal.

[0091] Figure 8 An example of the voltage applied to memory block BLKa during the second phase of the inspection operation is shown. In the example embodiment, reference is made to... Figure 4 The bias voltage of the described memory block BLKa can be applied equivalently to Figure 8 The memory block BLKa. Besides the reference... Figure 4 In addition to the given description, during the second phase of the inspection operation, the common source line voltage VCSL can also be applied to the common source line CSL.

[0092] The second phase of the check operation may include a third and a fourth time period. In the third time period, the page buffer 130 may apply a bias voltage VBA to bit lines BL1 and BL2. The row decoder 120 may apply a check voltage VCK to word lines WL1 through WL8. The check voltage VCK may be a voltage sufficient to turn on memory cells MC1 through MC8, and the level of the check voltage VCK may be the same as or similar to the level of the bias voltage VBA.

[0093] The line decoder 120 can apply an on-state voltage VON to the series select lines SSL1a, SSL1b, SSL2a, and SSL2b. The line decoder 120 can apply an off-state voltage VOFF to the ground select line GSL. The common-source voltage VCSL can be applied to the common-source line CSL. The common-source voltage VCSL can be different from the bias voltage VBA.

[0094] During the fourth time period, page buffer 130 can detect changes in the voltages of bit lines BL1 and BL2. For example, the voltage of the bit line connected to the cell string where a short-circuit channel error has occurred can correspond to the check voltage VCK. Because the check voltage VCK is the same as the bias voltage VBA, the bit line voltage associated with the short-circuit channel error can remain unchanged.

[0095] The voltage of the bit line connected in series with the cell where the threshold voltage error of the ground select transistor GST occurs can correspond to the common source line voltage VCSL. Because the common source line voltage VCSL is different from the bias voltage VBA, the voltage of the bit line connected to the threshold voltage error of the ground select transistor GST may change to the common source line voltage VCSL.

[0096] As described above, the non-volatile memory device 100 according to the exemplary embodiments of this disclosure can distinguish between short-circuit channel errors and threshold voltage errors of the ground select transistor GST. Therefore, the occurrence of bad blocks due to threshold voltage errors of the ground select transistor GST can be reduced or prevented. This can mean that the reduction in the capacity of the non-volatile memory device 100 can be reduced or minimized.

[0097] refer to Figure 7 An example is described that uses the comparison between a first count from the first stage of an inspection operation and a second count from the second stage of an inspection operation to determine whether a state is faulty or normal. However, a state fault or normal can be determined by adjusting the voltage level instead of comparing the counts.

[0098] Table 1 below shows examples of the voltages applied in the first and second stages of the inspection operation.

[0099] [Table 1]

[0100]

[0101]

[0102] refer to Figure 5 As per Table 1 above, in the first stage of the check operation, page buffer 130 can apply the power supply voltage VDD as the bias voltage VBA. Line decoder 120 can apply the ground voltage VSS as the check voltage VCK. The voltage (e.g., normal voltage) of the bit line connected to the cell string where a short-circuit channel error or a threshold voltage error of the ground select transistor GST does not exist can be the power supply voltage VDD. The voltage (e.g., error voltage) of the bit line connected to the cell string where a short-circuit channel error or a threshold voltage error of the ground select transistor GST exists can be the ground voltage VSS. Page buffer 130 can latch the voltages of bit lines BL1 and BL2.

[0103] In the second stage, page buffer 130 can apply a bias voltage VBA based on the detection results of the first stage. For example, a voltage change can be detected relative to the error bit line BL in which an error voltage was detected in the first stage. Page buffer 130 can apply a power supply voltage VDD to the normal bit line BL in which a normal voltage was detected in the first stage. Page buffer 130 can apply a ground voltage VSS to the error bit line BL in which an error voltage was detected in the first stage. The line decoder 120 can apply the ground voltage VSS as a check voltage VCK. The power supply voltage VDD can be applied as the common source line voltage VCSL.

[0104] In the first stage, the voltage of the bit line connected to the cell string where there is no short-circuit channel error and the threshold voltage error of the ground select transistor GST (e.g., the error-free bit line) can be detected as the supply voltage VDD. In the second stage, a bias voltage VBA of the supply voltage VDD can be applied to the error-free bit line. In the second stage, because the voltage of the error-free bit line remains constant, the supply voltage VDD can be detected.

[0105] In the first stage, the voltage of the bit line connected in series with the cell where the threshold voltage error of the ground selection transistor GST exists (e.g., a first-type error bit line) can be detected as the ground voltage VSS. In the second stage, a bias voltage VBA of the ground voltage VSS can be applied to the first-type error bit line. In the second stage, because the voltage of the first-type error bit line changes to the power supply voltage VDD, the power supply voltage VDD can be detected.

[0106] In the first stage, the voltage of the bit line connected to the cell string where the short-circuit channel error exists (e.g., the second type of error bit line) can be detected as the ground voltage VSS. In the second stage, a bias voltage VBA of the ground voltage VSS can be applied to the second type of error bit line. In the second stage, because the voltage of the second type of error bit line does not change, the ground voltage VSS can be detected.

[0107] For reference Figure 5 As per Table 1 above, in the first stage of the inspection operation, the voltage of the bit line connected to the cell string where short-circuit channel errors and threshold voltage errors of the ground select transistor GST exist can be set to the ground voltage VSS. In the second stage of the inspection operation, the voltage of the bit line connected to the cell string where threshold voltage errors of the ground select transistor GST exist can be set to the power supply voltage VDD.

[0108] Therefore, when performing the first and second phases of the inspection operation, the voltage of the bit line connected to the cell string where only a short-circuit channel error exists can be set to the ground voltage VSS, and the voltage of the remaining bit lines can be set to the power supply voltage VDD. That is, if no count is performed in the first phase and no count is performed in the second phase, a state fault can be determined when a bit line corresponding to the ground voltage VSS exists after performing the first and second phases.

[0109] [Table 2]

[0110]

[0111] refer to Figure 6 As per Table 2 above, in the first stage of the check operation, page buffer 130 can apply ground voltage VSS as bias voltage VBA. Line decoder 120 can apply power supply voltage VDD as check voltage VCK. The voltage (e.g., normal voltage) of the bit lines connected to cell strings where a short-circuit channel error or a threshold voltage error of the ground select transistor GST does not exist can be ground voltage VSS. The voltage (e.g., error voltage) of the bit lines connected to cell strings where a short-circuit channel error or a threshold voltage error of the ground select transistor GST exists can be power supply voltage VDD. Page buffer 130 can latch the voltages of bit lines BL1 and BL2.

[0112] In the second stage, page buffer 130 can apply a bias voltage VBA based on the detection results of the first stage. For example, a voltage change can be detected relative to the error bit line BL in which an error voltage was detected in the first stage. Page buffer 130 can apply a ground voltage VSS to the normal bit line BL in which a normal voltage was detected in the first stage. Page buffer 130 can apply a power supply voltage VDD to the error bit line BL in which an error voltage was detected in the first stage. The line decoder 120 can apply the power supply voltage VDD as a check voltage VCK. The ground voltage VSS can be applied as the common source line voltage VCSL.

[0113] In the first stage, the voltage of the bit line connected to the cell string where neither short-circuit channel error nor threshold voltage error of the ground select transistor exists (e.g., the error-free bit line) can be detected as the ground voltage VSS. In the second stage, a bias voltage VBA of the ground voltage VSS can be applied to the error-free bit line. In the second stage, because the voltage of the error-free bit line remains constant, the ground voltage VSS can be detected.

[0114] In the first stage, the voltage of the bit line connected in series with the cell where the threshold voltage error of the ground selection transistor exists (e.g., a first-type error bit line) can be detected as the supply voltage VDD. In the second stage, a bias voltage VBA of the supply voltage VDD can be applied to the first-type error bit line. In the second stage, because the voltage of the first-type error bit line changes to the ground voltage VSS, the ground voltage VSS can be detected.

[0115] In the first stage, the voltage of the bit line connected to the cell string where a short-circuit channel error exists (e.g., a type-two error bit line) can be detected as the supply voltage VDD. In the second stage, a bias voltage VBA of the supply voltage VDD can be applied to the type-two error bit line. In the second stage, because the voltage of the type-two error bit line does not change, the supply voltage VDD can be detected.

[0116] For reference Figure 6 As described in Table 2 above, in the first stage of the inspection operation, the voltage of the bit line connected to the cell string where a short-circuit channel error and a threshold voltage error of the ground select transistor GST exist can be set to the power supply voltage VDD. In the second stage of the inspection operation, the voltage of the bit line connected to the cell string where a threshold voltage error of the ground select transistor GST exists can be set to the ground voltage VSS.

[0117] Therefore, when performing the first and second phases of the inspection operation, the voltage of the bit line connected to the cell string where only a short-circuit channel error exists can be set to the power supply voltage VDD, and the voltage of the remaining bit lines can be set to the ground voltage VSS. That is, without performing the counting in the first and second phases, a state fault can be determined when a bit line corresponding to the power supply voltage VDD exists after performing the first and second phases.

[0118] In the above example embodiment, a description is given of a non-volatile memory device 100 checking for short-circuit channel errors in a memory block. Furthermore, the non-volatile memory device 100 can also be configured to specify the word line where a short-circuit channel error occurs.

[0119] For example, in reference Figure 5 In the described example embodiment, a check voltage VCK less than the bias voltage VBA can be applied to word lines selected from word lines WL1 to WL8 for short-circuit channel checking. The bias voltage VBA can be applied to word lines not selected for short-circuit channel checking. An example embodiment of a change in the voltage of bit lines BL1 and BL2 can be considered as a short-circuit channel error occurring at the relevant word line, or a threshold voltage error of the ground select transistor GST occurring at the relevant cell string. Whether the change in the bit line voltage corresponds to a short-circuit channel error can then be determined by... Figure 8 The second stage is determined.

[0120] Reference Figure 6 In the described example embodiment, a check voltage VCK greater than the bias voltage VBA can be applied to word lines WL1 through WL8 selected for short-circuit channel checking. The bias voltage VBA can be applied to word lines not selected for short-circuit channel checking. An example embodiment of a change in the voltage of bit lines BL1 and BL2 can be considered as a short-circuit channel error occurring at the relevant word line, or a threshold voltage error of the ground select transistor GST occurring at the relevant cell string. Whether the change in the bit line voltage corresponds to a short-circuit channel error can then be determined by... Figure 8 The second stage is determined.

[0121] Control logic 170 can specify (multiple) word lines associated with short-circuit channel errors when sequentially selecting word lines WL1 to WL8. Control logic 170 can output information about the position of the word lines along with a status fault signal, or it can output information about the position of the word lines in response to a status read command received from an external source.

[0122] In Tables 1 and 2 above, the terms "Power Supply Voltage VDD" and "Ground Voltage VSS" are used to describe the first and second phases of the inspection operation. However, the voltage level applied to the memory block BLKa is not limited by the terms "Power Supply Voltage VDD" and "Ground Voltage VSS". The Power Supply Voltage VDD can be interchanged with a first voltage identified as a first logic level, and the Ground Voltage VSS can be interchanged with a second voltage that is less than the first voltage and identified as a second logic level.

[0123] Figure 9 A storage device 200 according to an example embodiment of the present disclosure is shown. Reference Figure 9 The storage device 200 may include a non-volatile memory device 210, a memory controller 220, and / or an external buffer 230. The non-volatile memory device 210 may include multiple memory cells. Each of the multiple memory cells may store two bits or more.

[0124] For example, non-volatile memory device 210 may include at least one of various non-volatile memory devices such as flash memory devices, phase-change memory devices, ferroelectric memory devices, magnetic memory devices, and resistive memory devices. Non-volatile memory device 210 may include references. Figures 1 to 8 The non-volatile memory device 100 is described. The non-volatile memory device 210 can perform a check operation in response to a specified command.

[0125] The memory controller 220 can receive various requests from an external host device to write data to or read data from the non-volatile memory device 210. The memory controller 220 can store (or buffer) user data exchanged with the external host device in an external buffer 230, and can also store metadata for managing the storage device 200 in the external buffer 230.

[0126] The memory controller 220 can access the non-volatile memory device 210 through the first channel CH1 and the second channel CH2. For example, the memory controller 220 can send commands and addresses to the non-volatile memory device 210 through the first channel CH1. The memory controller 220 can exchange data with the non-volatile memory device 210 through the first channel CH1.

[0127] The memory controller 220 can send a first control signal to the non-volatile memory device 210 via the second channel CH2. The memory controller 220 can also receive a second control signal from the non-volatile memory device 210 via the second channel CH2.

[0128] In an example embodiment, memory controller 220 may be configured to control two or more non-volatile memory devices. Memory controller 220 may provide a first different channel and a second different channel for each of the two or more non-volatile memory devices.

[0129] In another example, memory controller 220 may share a first channel for two or more non-volatile memory devices. Memory controller 220 may also share a portion of a second channel CH2 for two or more non-volatile memory devices, and may provide the remainder separately.

[0130] External buffer 230 may include random access memory. For example, external buffer 230 may include at least one of dynamic random access memory, phase change random access memory, ferroelectric random access memory, magnetic random access memory, or resistive random access memory.

[0131] The memory controller 220 may include a bus 221, a host interface 222, an internal buffer 223, a processor 224, a buffer controller 226, a memory manager 227, and / or an error correction code (ECC) block 228.

[0132] Bus 221 provides a communication channel between components in memory controller 220. Host interface 222 can receive various requests from external host devices and can parse the received requests. Host interface 222 can store the parsed requests in internal buffer 223.

[0133] Host interface 222 can send various responses to external host devices. Host interface 222 can exchange signals with external host devices according to a given communication protocol. Internal buffer 223 may include random access memory. For example, internal buffer 223 may include static random access memory or dynamic random access memory.

[0134] Processor 224 can drive the operating system or firmware used to drive memory controller 220. Processor 224 can read parsed requests stored in internal buffer 223 and can generate commands and addresses for controlling non-volatile memory device 210. Processor 224 can transmit the generated commands and addresses to memory manager 227.

[0135] Processor 224 can store various metadata used for managing storage device 200 into internal buffer 223. Processor 224 can access external buffer 230 through buffer controller 226. Processor 224 can control buffer controller 226 and memory manager 227 so that user data stored in external buffer 230 is sent to non-volatile memory device 210.

[0136] Processor 224 can control host interface 222 and buffer controller 226 to send data stored in external buffer 230 to external host device. Processor 224 can control buffer controller 226 and memory manager 227 to store data received from non-volatile memory device 210 into external buffer 230. Processor 224 can control host interface 222 and buffer controller 226 to store data received from external host device into external buffer 230.

[0137] Under the control of processor 224, buffer controller 226 can write data to or read data from external buffer 230. Memory manager 227 can communicate with non-volatile memory device 210 through first channel CH1 and second channel CH2 under the control of processor 224.

[0138] Error correction code block 228 can perform error correction encoding on data to be sent to non-volatile memory device 210 by using error correction code ECC. Error correction code block 228 can perform error correction decoding on data received from non-volatile memory device 210 by using error correction code ECC.

[0139] Processor 224 may include short-channel check controller 225. When a specified command is issued to non-volatile memory device 210, short-channel check controller 225 may further issue a check command directing a check operation. The specified command may include a write command, an erase command, or a read command. Alternatively, when a specified command is issued to non-volatile memory device 210, short-channel check controller 225 may add a descriptor / argument or opcode directing the check operation to the specified command. In an example embodiment, short-channel check controller 225 may periodically transmit check commands, descriptors, or opcodes to non-volatile memory device 210 when a count corresponding to a random number passes, or whenever a specified command is issued.

[0140] The non-volatile memory device 210 may perform a check operation in response to a check command or in response to a descriptor or opcode pointing to a check operation. Alternatively, the non-volatile memory device 210 may perform a check operation in response to a specified command. The specified command may include a write command, an erase command, or a read command. The non-volatile memory device 210 may perform the check operation periodically when a count corresponding to a random number passes, or whenever a specified command is received.

[0141] In the example embodiment, the storage device 200 may not include the external buffer 230 and the buffer controller 226. When the external buffer 230 and the buffer controller 226 are not included in the storage device 200, the functions described above for the external buffer 230 and the buffer controller 226 can be performed by the internal buffer 223.

[0142] Figure 10 A first example of how the storage device 200 operates is shown. (Reference) Figure 9 and Figure 10 During operation S310, the memory controller 220 can generate specified commands. These commands can be generated based on requests from external host devices or on an internal schedule. Specified commands can include write commands, erase commands, or read commands.

[0143] In response to generating the specified command, in operation S320, the memory controller 220 can transmit the check command to the non-volatile memory device 210. In response to the check command, in operation S330, the non-volatile memory device 210 can execute the check command. In operation S340, the non-volatile memory device 210 can transmit the result of the check operation as status information to the memory controller 220.

[0144] In the example embodiment, when a short-circuit channel error is detected during the check operation, the non-volatile memory device 210 can transmit a status fault signal as status information to the memory controller 220. When no short-circuit channel error is detected during the check operation, the non-volatile memory device 210 can transmit a normal status signal as status information to the memory controller 220, or the output of status information can be omitted. In the example embodiment, the memory controller 220 can be configured to read status information from the non-volatile memory device 210 via a status read operation after transmitting the check command.

[0145] When operation S350 determines that the status information indicates a status fault, operation S360 is executed. In operation S360, the memory controller 220 can designate the memory block where a short-circuit channel error occurs as a bad region. Alternatively, when multiple word lines where short-circuit channel errors occur are identified, the memory controller 220 can designate the word lines where short-circuit channel errors occur as bad regions, or it can designate the multiple word lines where short-circuit channel errors occur and their adjacent word lines as bad regions. In operation S370, the memory controller 220 can report the bad region information to the external host device. Afterwards, the process associated with the check command and the designation command can be terminated.

[0146] If, in operation S350, it is determined that the status information does not indicate a status fault, in operation S380, the memory controller 220 may transmit a specified command to the non-volatile memory device 210. In response to the specified command, in operation S390, the non-volatile memory device 210 may execute the specified operation. The specified operation may include a write operation, an erase operation, or a read operation. When the specified operation is completed, the process associated with the check command and the specified command may be terminated.

[0147] As described above, when a specified command is issued, the memory controller 220 can instruct the non-volatile memory device 210 to perform a check operation via a check command, and then the specified command can be transmitted to the non-volatile memory device 210. For example, the specified command could be the first write command to a memory block in an erased state, including memory cells in an erased state. The non-volatile memory device 100 can perform the check operation before writing data to the memory block containing the erased memory cells for the first time.

[0148] Figure 11 A second example of the operation method of the storage device 200 is shown. (Reference) Figure 9 and Figure 11 In operation S410, the memory controller 220 can generate specified commands. These commands can be generated based on requests from external host devices or on an internal schedule. The specified commands can include write commands, erase commands, or read commands.

[0149] In operation S420, the memory controller 220 can transmit a specified command to the non-volatile memory device 210. In response to the specified command, in operation S430, the non-volatile memory device 210 can perform a specified operation. The specified operation may include a write operation, an erase operation, or a read operation.

[0150] In response to the completion of the specified command, in operation S440, the memory controller 220 can transmit the check command to the non-volatile memory device 210. In response to the check command, in operation S450, the non-volatile memory device 210 can execute the check command. In operation S460, the non-volatile memory device 210 can transmit the result of the check operation as status information to the memory controller 220. Operation S460 can be combined with... Figure 10 The operation is the same as S340. Therefore, additional descriptions will be omitted to avoid redundancy.

[0151] When the status information indicates a status fault in operation S470, operation S480 is executed. In operation S480, the memory controller 220 can specify the bad region. Operation S480 can be combined with... Figure 10 The operation S360 is the same. Therefore, additional descriptions will be omitted to avoid redundancy. In operation S490, the memory controller 220 can report information about bad areas to the external host device.

[0152] When it is determined in operation S470 that the status information does not indicate a status fault, the memory controller 220 may terminate the process associated with the specified command and the check command.

[0153] As described above, when a specified command is issued, the memory controller 220 can instruct the non-volatile memory device 210 to perform a specified operation via the specified command, and then instruct the non-volatile memory device 210 to perform a check operation via a check command. For example, the specified command could be an erase command for erasing memory cells of a memory block. The non-volatile memory device 210 can erase the memory cells of the memory block, and then perform a check operation.

[0154] Figure 12 A third example of the operation method of storage device 200 is shown. (Reference) Figure 9 and Figure 12 In operation S510, the memory controller 220 can generate specified commands. These commands may be generated based on requests from external host devices or on an internal schedule. Specified commands may include write commands, erase commands, or read commands. Specified commands may include descriptors / arguments or opcodes indicating check operations.

[0155] In operation S520, the memory controller 220 can transmit a specified command to the non-volatile memory device 210. In response to the specified command, in operation S530, the non-volatile memory device 210 can perform a check operation. In operation S540, the non-volatile memory device 210 can transmit the result of the check operation as status information to the memory controller 220. Operation S540 can be combined with... Figure 10The operation is the same as S340. Therefore, additional descriptions will be omitted to avoid redundancy.

[0156] When the status information indicates a status fault in operation S550, operation S560 is executed. In operation S560, the memory controller 220 can specify the bad region. Operation S560 can be combined with... Figure 10 The operation S360 is the same. Therefore, additional descriptions will be omitted to avoid redundancy. In operation S570, the memory controller 220 can report information about bad regions to the external host device. Afterwards, the process associated with the specified command can be terminated.

[0157] If it is determined in operation S550 that the status information does not indicate a status fault, the process associated with the inspection operation is terminated. Parallel to operation S550, in operation S580, if the status information indicates a status fault, the process associated with the specified command is terminated. If it is determined in operation S580 that the status information does not indicate a status fault, operation S590 is executed.

[0158] In operation S590, in response to the completion of the check operation initiated according to the specified command, the non-volatile memory device 210 may execute the specified operation. The specified operation may include a write operation, an erase operation, or a read operation. Afterwards, the memory controller 220 may terminate the process associated with the specified command and the check command.

[0159] As described above, when a specified command is issued, the memory controller 220 may include a descriptor / argument or opcode indicating a check operation in the specified command. In response to the specified command including the descriptor / argument or opcode indicating a check operation, the non-volatile memory device 210 may perform the check operation; if no error is detected in the check operation, the non-volatile memory device 210 may perform the specified operation. For example, the specified command may be the first write command to a memory block including erased memory cells. The non-volatile memory device 210 may perform the check operation before the first write of data to the memory block including erased memory cells.

[0160] Figure 13 A fourth example of the operation method of storage device 200 is shown. (Reference) Figure 9 and Figure 13 During operation of S610, the memory controller 220 can generate specified commands. These commands may be generated based on requests from external host devices or on an internal schedule. Specified commands may include write commands, erase commands, or read commands. Specified commands may include descriptors / arguments or opcodes indicating check operations.

[0161] In operation S620, the memory controller 220 can transmit a specified command to the non-volatile memory device 210. In response to the specified command, in operation S630, the non-volatile memory device 210 can perform a specified operation. The specified operation may include a write operation, an erase operation, or a read operation.

[0162] In operation S640, in response to the completion of the specified operation initiated according to the specified command, the non-volatile memory device 210 can perform a check operation. In operation S650, the non-volatile memory device 210 can transmit the result of the check operation as status information to the memory controller 220. Operation S650 can be combined with... Figure 10 The operation is the same as S340. Therefore, additional descriptions will be omitted to avoid redundancy.

[0163] When the status information indicates a status fault in operation S660, operation S670 is executed. In operation S670, the memory controller 220 can specify the bad region. Operation S670 can be combined with... Figure 10 The operation S360 is the same. Therefore, additional descriptions will be omitted to avoid redundancy. In operation S680, the memory controller 220 can report information about bad regions to the external host device. Afterward, the process associated with the specified command is terminated.

[0164] When it is determined in operation S660 that the status information does not indicate a status fault, the process associated with the specified command can be terminated.

[0165] As described above, when a specified command is issued, the memory controller 220 may include a descriptor / argument or opcode indicating a check operation in the specified command. In response to the specified command including the descriptor / argument or opcode indicating a check operation, the non-volatile memory device 210 may perform the specified operation and may perform the check operation. For example, the specified command may be an erase command for erasing memory cells of a memory block. The non-volatile memory device 210 may erase the memory cells of the memory block and then perform the check operation.

[0166] Figure 14 This illustrates a fifth example of how the storage device 200 operates. (See reference) Figure 9 and Figure 14 In operation of S710, the memory controller 220 can generate specified commands. These commands may be generated based on requests from external host devices or on an internal schedule. Specified commands may include write commands, erase commands, or read commands. Specified commands may include descriptors / arguments or opcodes indicating check operations.

[0167] In operation S720, the memory controller 220 can transmit a specified command to the non-volatile memory device 210. In response to the specified command, in operation S730, the non-volatile memory device 210 can execute the first part of the specified operation. The specified operation may include a write operation, an erase operation, or a read operation.

[0168] In operation S740, in response to the completion of the first part of the specified operation initiated according to the specified command, the non-volatile memory device 210 can perform a check operation. In operation S750, the non-volatile memory device 210 can transmit the result of the check operation as status information to the memory controller 220. Operation S750 can be combined with... Figure 10 The operation is the same as S340. Therefore, additional descriptions will be omitted to avoid redundancy.

[0169] When the status information indicates a status fault in operation S760, operation S770 is executed. In operation S770, the memory controller 220 can specify the bad region. Operation S770 can be combined with... Figure 10 The operation S360 is the same. Therefore, additional descriptions will be omitted to avoid redundancy. In operation S780, the memory controller 220 can report information about bad regions to the external host device. Afterwards, the process associated with the specified command is terminated.

[0170] In parallel with operation S760, in operation S790, when the status information indicates a status fault, the process associated with the specified command is terminated. When it is determined in operation S790 that the status information does not indicate a status fault, operation S800 is executed.

[0171] In operation S800, in response to the completion of the check operation initiated according to the specified command, the non-volatile memory device 210 can execute the second part of the specified operation. Afterwards, the memory controller 220 can terminate the process associated with the specified command and the check command.

[0172] As described above, when a specified command is issued, the memory controller 220 may include a descriptor / argument or opcode indicating a check operation in the specified command. In response to the specified command including the descriptor / argument or opcode indicating a check operation, the non-volatile memory device 210 may execute a first part of the specified operation, execute the check operation, and execute a second part of the specified operation.

[0173] Figure 15 A sixth example of the operation method of storage device 200 is shown. (Reference) Figure 1 , Figure 2 , Figure 9 and Figure 15The non-volatile memory device 100 can receive write commands as specified commands. Write commands can be received along with address and data.

[0174] In operation S810, the non-volatile memory device 100 can load received data onto the page buffer 130. Operation S810 can be a write operation.

[0175] In operation S820, page buffer 130 can be based on loaded data bias bit lines BL1 and BL2. For example, page buffer 130 can apply a second logic level voltage (e.g., ground voltage) to the bit line corresponding to the memory cell to be programmed. Page buffer 130 can apply a first logic level voltage (e.g., power supply voltage) to the bit line corresponding to the memory cell to be disabled from programming. Operation S820 can be a write operation. Furthermore, operation S820 can correspond to the operation of applying bias voltage VBA in a check operation.

[0176] In operation S830, the row decoder 120 can apply a turn-off voltage to the ground select line GSL. The row decoder 120 can apply a pass voltage to the serial select lines SSL1a, SSL1b, SSL2a, and SSL2b. The row decoder 120 can apply a pass voltage to the word lines WL1 to WL8. The pass voltage can be a voltage sufficient to turn on memory cells MC1 to MC8 and serial select transistors SSTa and SSTb. Operation S830 can be a write operation. Furthermore, operation S830 can correspond to the operation of applying a turn-on voltage VON, a turn-off voltage VOFF, and a check voltage VCK in a check operation. Operations S820 and S830 can constitute the first phase of the check operation.

[0177] In operation S840, the page buffer 130 can sense the voltages of bit lines BL1 and BL2. In operation S850, the control logic 170 can determine whether the voltages of bit lines BL1 and BL2 have changed. Operations S840 and S850 can constitute the second phase of the inspection operation. Operations S820 to S850 can correspond to the first phase of the inspection operation.

[0178] In response to the determination result in operation S850 indicating that the voltages of bit lines BL1 and BL2 have not changed, in operation S860, the row decoder 120 can apply a programming voltage to the selected word line. Operation S860 can be a write operation.

[0179] In operation of S870, the non-volatile memory device 100 can perform a verification operation. Page buffer 130 can precharge bit lines BL1 and BL2 to a positive voltage, and then float bit lines BL1 and BL2. Row decoder 120 can apply a read pass voltage to the unselected word line, ground select line GSL, and serial select lines SSL1a, SSL1b, SSL2a, and SSL2b. The read pass voltage can be a voltage sufficient to turn on the ground select transistor GST, serial select transistors SSTTa and SSTb, and the unselected memory cell. Row decoder 120 can apply a verification voltage to the selected word line. After the development time has elapsed, page buffer 130 can latch the voltages of bit lines BL1 and BL2.

[0180] In operation S880, control logic 170 can determine whether the memory cell of the selected word line has been successfully programmed. Control logic 170 can determine success when the threshold voltage of the selected memory cell is the verification voltage or higher. In response to determining programming failure, non-volatile memory device 100 can re-execute operation S860. In response to determining programming success, the write operation process can be terminated.

[0181] In response to a voltage change in at least one of the bit lines BL1 and BL2 indicated by the determination result in operation S850, the non-volatile memory device 100 may terminate the write operation in operation S890. For example, the non-volatile memory device 100 may further perform a reference... Figure 8 The second phase of the described inspection operation. When a short-circuit channel error is determined to have occurred, in operation S900, the non-volatile memory device 100 can report a status fault to the memory controller 220. Afterwards, the process associated with the write operation can be terminated.

[0182] Figure 16 This illustrates a memory device according to an example embodiment of the present disclosure. References Figure 16 The memory device 1400 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then bonding the upper and lower chips together. For example, the bonding method may include electrically connecting bonding metals formed on the uppermost metal layer of the upper chip and bonding metals formed on the uppermost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding method may be a Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten.

[0183] Each of the peripheral circuit region PERI and cell region CELL of memory device 1400 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0184] The Peripheral Circuit Area (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In an example embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten, which has relatively high resistance, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper, which has relatively low resistance.

[0185] exist Figure 16 In the illustrated example embodiment, although first metal layers 1230a, 1230b, and 1230c and second metal layers 1240a, 1240b, and 1240 are shown and described, the first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240 are not limited thereto, and one or more metal layers may be further formed on the second metal layers 1240a, 1240b, and 1240c. At least a portion of the one or more metal layers formed on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum or the like, which have a lower resistivity than copper, which forms the second metal layers 1240a, 1240b, and 1240c.

[0186] An interlayer insulating layer 1215 may be disposed on a first substrate 1210 and may cover multiple circuit elements 1220a, 1220b and 1220c, first metal layers 1230a, 1230b and 1230c and second metal layers 1240a, 1240b and 1240c. The interlayer insulating layer 1215 may include an insulating material such as silicon oxide or silicon nitride.

[0187] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b in the cell region CELL in a bonding manner, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum, copper, tungsten, etc.

[0188] Furthermore, the upper bonding metals 1371b and 1372b in the cell region CELL can be referred to as the first metal pads, and the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be referred to as the second metal pads.

[0189] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 810, an interlayer insulating layer 1315, and a common source line 1320. Multiple word lines 1331 to 1338 (e.g., 1330) may be stacked on the second substrate 1310 in a direction perpendicular to the upper surface of the second substrate 1310 (e.g., the Z-axis direction). A serial select line and a ground select line may be arranged above and below the multiple word lines 1330, respectively, and the multiple word lines 1330 may be disposed between the serial select line and the ground select line.

[0190] The widths of the multiple word lines 1330 can vary along the X-axis. As the distance from the first substrate 1210 of the peripheral circuit region PERI to the corresponding word line among the multiple word lines 1300 increases, the width of the corresponding word line among the multiple word lines 1300 increases. Similarly, as the distance from the second substrate 1310 of the cell region CELL to the corresponding word line among the multiple word lines 1300 increases, the width of the corresponding word line among the multiple word lines 1300 decreases.

[0191] In the bit line bonding area (BLBA), the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 1310 and can pass through multiple word lines 1330, serial select lines, and ground select lines. The channel structure CH may include a data memory layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact point, and the second metal layer 1360c can be a bit line. In an example embodiment, the bit line 1360c can extend in a first direction (e.g., the Y-axis direction) parallel to the upper surface of the second substrate 1310.

[0192] An interlayer insulating layer 1315 may be disposed on the second substrate 1310 and may cover the common source line 1320, multiple word lines 1330, multiple unit contact plugs, first metal layers 1350a, 1350b and 1350c, and second metal layers 1360a, 1360b and 1360c. The interlayer insulating layer 1315 may include an insulating material, such as silicon oxide, silicon nitride, etc.

[0193] exist Figure 16In the example embodiment shown, the region where the channel structure CH, bit line 1360c, etc., are arranged can be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 1360c can be electrically connected to circuit element 1220c that provides page buffer 1393 in peripheral circuit region PERI. For example, bit line 1360c can be connected to upper bonding metals 1371c and 1372c in cell region CELL, and upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c that are connected to circuit element 1220c of page buffer 1393.

[0194] In the word line bonding area (WLBA), multiple word lines 1330 may extend in a second direction (e.g., the X-axis direction) parallel to the upper surface of the second substrate 1310 and may be connected to multiple cell contact plugs 1341 to 1347 (e.g., 1340). The word lines 1330 and cell contact plugs 1340 may be connected to each other in pads provided by at least a portion of the multiple word lines 1330 extending at different lengths in the second direction. A first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portion of each of the cell contact plugs 1340 connected to the word lines 1330. The cell contact plug 1340 may be connected to the circuit region PERI via upper bonding metals 1371b and 1372b of the cell region CELL and lower bonding metals 1271b and 1272b of the peripheral circuit region PERI in the word line bonding area (WLBA).

[0195] The unit contact plug 1340 can be electrically connected to circuit element 1220b that provides line decoder 1394 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 1220b providing line decoder 1394 may differ from the operating voltage of circuit element 1220c providing page buffer 1393. For example, the operating voltage of circuit element 1220c providing page buffer 1393 may be greater than the operating voltage of circuit element 1220b providing line decoder 1394.

[0196] A common source contact 1380 can be disposed in the external pad bonding region PA. The common source contact 1380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a can be sequentially stacked on the upper part of the common source contact 1380. For example, the area where the common source contact 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed can be defined as the external pad bonding region PA.

[0197] Input / output pads 1205 and 1305 can be set in the external pad bonding area PA. (See reference) Figure 16 A lower insulating film 1201 covering the lower surface of the first substrate 1210 can be formed below the first substrate 1210, and a first input / output pad 1205 can be formed on the lower insulating film 1201. The first input / output pad 1205 can be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI via a first input / output contact plug 1203, and can be separated from the first substrate 1210 via the lower insulating film 1201. In addition, a side insulating film can be provided between the first input / output contact plug 1203 and the first substrate 1210 to electrically isolate the first input / output contact plug 1203 from the first substrate 1210.

[0198] refer to Figure 16 An upper insulating film 1301 covering the upper surface of the second substrate 1310 can be formed on the second substrate 1310, and a second input / output pad 1305 can be disposed on the upper insulating film 1301. The second input / output pad 1305 can be connected to at least one of a plurality of circuit elements 1220a, 1220b and 1220c disposed in the peripheral circuit region PERI via the second input / output contact plug 1303 and the lower bonding metals 1271a and 1272a in the peripheral circuit region PERI.

[0199] According to the example embodiment, the second substrate 1310 and the common source line 1320 may not be located in the area where the second input / output contact plug 1303 is provided. Additionally, the second input / output pad 1305 may not overlap with the word line 1330 in a third direction (e.g., the Z-axis direction). Reference Figure 16 The second input / output contact plug 1303 can be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and can pass through the interlayer insulation layer 1315 of the cell region to connect to the second input / output pad 1305.

[0200] According to the example embodiment, the first input / output pad 1205 and the second input / output pad 1305 can be selectively formed. For example, the memory device 1400 may include only the first input / output pad 1205 disposed on the first substrate 1210 or the second input / output pad 1305 disposed on the second substrate 1310. Alternatively, the memory device 1400 may include both the first input / output pad 1205 and the second input / output pad 1305.

[0201] In each of the external pad bonding area PA and bit line bonding area BLBA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, a metal pattern in the top metal layer can be provided as a pseudo pattern or the top metal layer may not exist.

[0202] In the external pad bonding region PA, in the uppermost metal layer of the peripheral circuit region PERI, the memory device 1400 may include a lower metal pattern 1273a, which corresponds to the upper metal pattern 1372a formed in the uppermost metal layer of the cell region CELL and has the same shape as the upper metal pattern 1372a of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact point. As described above, in the external pad bonding region PA, an upper metal pattern can be formed in the uppermost metal layer of the cell region CELL, which corresponds to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern of the peripheral circuit region PERI.

[0203] Lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL via a bonding scheme.

[0204] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 1392 can be formed in the uppermost metal layer of the cell region CELL. This metal pattern 1392 corresponds to the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit region PERI, and has the same shape as the lower metal pattern 1252f of the peripheral circuit region PERI. No contact points may be formed on the upper metal pattern 1392 formed in the uppermost metal layer of the cell region CELL.

[0205] In the above example embodiments, the components according to this disclosure are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish the components from each other and do not limit this disclosure. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0206] In the above exemplary embodiments, components according to exemplary embodiments of this disclosure are described using blocks. These blocks can be implemented using various hardware devices such as integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driving the hardware devices, software such as applications, or a combination of hardware devices and software. Furthermore, these blocks can include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0207] According to this disclosure, a non-volatile memory device can detect whether a channel fault has occurred. Therefore, a non-volatile memory device with improved reliability and a storage device including the non-volatile memory device are provided.

[0208] Although this disclosure has been described with reference to exemplary embodiments disclosed herein, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: an array of memory cells including cell strings, wherein each of the cell strings includes a ground select transistor, a memory cell, and a string select transistor stacked in a direction perpendicular to a substrate; a row decoder connected with the ground select transistor of each of the cell strings through a ground select line, with the memory cell of each of the cell strings through a word line, and with the string select transistor of each of the cell strings through a string select line; and a page buffer connected with the cell strings through a bit line, wherein, in a first period of an inspection operation, the page buffer is configured to apply a first bias voltage to the bit line, wherein, in the first period of the inspection operation, the row decoder is configured to apply an off voltage to the ground select line, an on voltage to the string select line, and a first inspection voltage to the word line, wherein, in a second period of the inspection operation, the page buffer is configured to sense a first change in voltage of the bit line, wherein, in the second period of the inspection operation, in response to sensing the first change in voltage of the bit line, output a state failure signal, wherein, in a third period of the inspection operation, the page buffer applies a second bias voltage to the bit line, wherein, in the third period of the inspection operation, the row decoder applies the off voltage to the ground select line, the on voltage to the string select line, and a second inspection voltage to the word line, wherein, in a fourth period of the inspection operation, the page buffer senses a second change in voltage of the bit line, and wherein, in response to a number of first bit lines among the bit lines that make the first change being equal to a number of second bit lines among the bit lines that make the second change, the output of the state failure signal is omitted.

2. The non-volatile memory device of claim 1, wherein, the first bias voltage is a positive voltage, and wherein the first inspection voltage is less than the first bias voltage.

3. The nonvolatile memory device of claim 2, wherein, In the second period of the inspection operation, the page buffer outputs the state failure signal in response to a decrease in voltage of the bit line.

4. The nonvolatile memory device of claim 2, wherein, In the second period of the inspection operation, the page buffer floats the bit line during a preset period of time and then senses the first change in voltage of the bit line.

5. The nonvolatile memory device of claim 1, wherein, the first inspection voltage is greater than the first bias voltage.

6. The nonvolatile memory device of claim 5, wherein, In the second period of the inspection operation, the non-volatile memory device outputs the state failure signal in response to an increase in voltage of the bit line.

7. The nonvolatile memory device of claim 1, wherein, In response to no change in voltage of the bit line, the inspection operation is terminated without the output of the state failure signal.

8. The nonvolatile memory device of claim 1, wherein, the second inspection voltage is equal to the second bias voltage.

9. A memory device, comprising: a non-volatile memory device including cell strings, wherein each of the cell strings includes a ground select transistor, a memory cell, and a string select transistor stacked on a substrate in a direction perpendicular to the substrate; and a controller configured to transmit a command to the non-volatile memory device, wherein the non-volatile memory device performs a check operation in response to the command, wherein the check operation comprises: applying a bias voltage to a bit line connected to the string of cells, applying an off voltage to a ground select line connected to a ground select transistor of each of the string of cells, applying an on voltage to a string select line connected to a string select transistor of each of the string of cells, and applying a check voltage to a word line connected to a memory cell of each of the string of cells for a first period; and sensing a change in voltage of the bit line for a second period, wherein, in a case where the command is a write command, the non-volatile memory device receives write data with the command, applies a voltage comprising the bias voltage to the bit line based on the write data, applies a pass voltage as the check voltage to the word line, suspends a write operation according to the write command in response to a change in voltage of the bit line to which the bias voltage is applied, and applies a program voltage to a word line selected from the word line in response to no change in voltage of the bit line to which the bias voltage is applied.

10. The storage device of claim 9, wherein, in response to sensing the change in voltage of the bit line, the non-volatile memory device transmits a status fault signal to the controller.

11. The storage device of claim 9, wherein, the controller is further configured to transmit the command to the non-volatile memory device prior to transmitting a specified command to the non-volatile memory device, and wherein the specified command comprises at least one of a write command, a read command, or an erase command.

12. The storage device of claim 9, wherein, the controller is further configured to transmit the command to the non-volatile memory device after transmitting a specified command to the non-volatile memory device, and wherein the specified command comprises at least one of a write command, a read command, or an erase command.

13. The storage device of claim 9, wherein, the command is one of a write command, a read command, or an erase command, and wherein, in response to the command, the non-volatile memory device performs the check operation and then performs the operation specified by the command among a write operation, a read operation, or an erase operation.

14. The storage device of claim 9, wherein, the command is one of a write command, a read command, or an erase command, and wherein, in response to the command, the non-volatile memory device performs the operation specified by the command among a write operation, a read operation, or an erase operation and then performs the check operation.

15. The storage device of claim 9, wherein, the command is one of a write command, a read command, or an erase command, and wherein, in response to the command, the non-volatile memory device performs a portion of the operation specified by the command among a write operation, a read operation, or an erase operation, then performs the check operation, and then performs a remaining portion of the specified operation.

16. A non-volatile memory device, comprising: a peripheral region; and a memory cell region, wherein the memory cell region comprises: a first metal pad; and an array of memory cells comprising a string of cells, wherein each of the string of cells comprises a ground select transistor, a memory cell, and a string select transistor stacked on a substrate in a direction perpendicular to the substrate, wherein the peripheral region comprises: a second metal pad; a row decoder connected with a ground select transistor of each of the strings of cells through a ground select line, with a memory cell of each of the strings of cells through a word line, and with a string select transistor of each of the strings of cells through a string select line; a page buffer connected with the strings of cells through bit lines, wherein the peripheral region is connected vertically through the first metal pad and the second metal pad, wherein, in a first period of an inspection operation, the page buffer is configured to apply a bias voltage to the bit lines, wherein, in the first period of the inspection operation, the row decoder is configured to apply an off voltage to the ground select line, an on voltage to the string select line, and an inspection voltage to the word line, wherein, in a second period of the inspection operation, the page buffer is configured to sense a first change in voltage of the bit lines, wherein, in the second period of the inspection operation, in response to sensing the first change in voltage of the bit lines, a state failure signal is outputted, wherein, in a third period of the inspection operation, the page buffer applies a second bias voltage to the bit lines, wherein, in the third period of the inspection operation, the row decoder applies the off voltage to the ground select line, the on voltage to the string select line, and a second inspection voltage to the word line, wherein, in a fourth period of the inspection operation, the page buffer senses a second change in voltage of the bit lines, and wherein, in response to a number of first bit lines among the bit lines that make the first change being equal to a number of second bit lines among the bit lines that make the second change, an output of the state failure signal is omitted.

17. The nonvolatile memory device of claim 16, wherein, the row decoder is connected with the ground select line, the string select line, and the word line through a first portion of the first metal pad and a first portion of the second metal pad, and wherein the page buffer is connected with the bit lines through a second portion of the first metal pad and a second portion of the second metal pad. a second metal pad; a row decoder connected with a ground select transistor of each of the strings of cells through a ground select line, with a memory cell of each of the strings of cells through a word line, and with a string select transistor of each of the strings of cells through a string select line; a page buffer connected with the strings of cells through bit lines, wherein the peripheral region is connected vertically through the first metal pad and the second metal pad, wherein, in a first period of an inspection operation, the page buffer is configured to apply a bias voltage to the bit lines, wherein, in the first period of the inspection operation, the row decoder is configured to apply an off voltage to the ground select line, an on voltage to the string select line, and an inspection voltage to the word line, wherein, in a second period of the inspection operation, the page buffer is configured to sense a first change in voltage of the bit lines, wherein, in the second period of the inspection operation, in response to sensing the first change in voltage of the bit lines, a state failure signal is outputted, wherein, in a third period of the inspection operation, the page buffer applies a second bias voltage to the bit lines, wherein, in the third period of the inspection operation, the row decoder applies the off voltage to the ground select line, the on voltage to the string select line, and a second inspection voltage to the word line, wherein, in a fourth period of the inspection operation, the page buffer senses a second change in voltage of the bit lines, and wherein, in response to a number of first bit lines among the bit lines that make the first change being equal to a number of second bit lines among the bit lines that make the second change, an output of the state failure signal is omitted. the row decoder is connected with the ground select line, the string select line, and the word line through a first portion of the first metal pad and a first portion of the second metal pad, and wherein the page buffer is connected with the bit lines through a second portion of the first metal pad and a second portion of the second metal pad.

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