Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive layer and an amorphized layer on the first conductive layer in the first dielectric layer, wherein the material of the amorphized layer is the material of the amorphous first conductive layer; forming a second dielectric layer on the first dielectric layer and the amorphized layer; forming a first opening in the second dielectric layer, wherein the first opening exposes a portion of the surface of the amorphized layer; forming a second opening in the amorphized layer at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is within the projection range of the second opening on the substrate. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active areas, between transistors, or between metal lines of different layers, and complete the transmission and control of signals. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of semiconductor devices and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of each semiconductor device, a multi-layer interconnection structure is usually required.

[0003] Generally, in the back-end interconnection process of the semiconductor device manufacturing process, the first metal layer (M1) needs to form an electrical connection with the active device structure (including the source and drain regions and the gate structure region) of the lower layer. Therefore, before forming the first metal layer, it is usually necessary to pre-form a local interconnection structure (Local Interconnect) of the semiconductor device. The local interconnection structure includes: a zeroth metal layer (M0) electrically connected to the source and drain regions of the lower layer, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the semiconductor structure with the local interconnection structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive layer and an amorphous layer located on the first conductive layer in the first dielectric layer, the material of the amorphous layer is the material of the amorphous first conductive layer; forming a second dielectric layer on the first dielectric layer and the amorphous layer; forming a first opening in the second dielectric layer, the first opening exposing a portion of the surface of the amorphous layer; forming a second opening in the amorphous layer at the bottom of the first opening, the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is located within the projection range of the second opening on the substrate.

[0007] Optionally, before forming the first conductive layer in the first dielectric layer and the amorphous layer on the first conductive layer, the method further includes: forming an initial first conductive layer in the first dielectric layer.

[0008] Optionally, the method for forming the first conductive layer and the amorphous layer includes: performing an amorphization treatment on a portion of the initial first conductive layer to form the first conductive layer and the amorphous layer located on the first conductive layer.

[0009] Optionally, the method of performing amorphization treatment on a portion of the initial first conductive layer includes: performing plasma gas bombardment treatment on a portion of the initial first conductive layer to form the amorphization layer.

[0010] Optionally, the method of performing an amorphization treatment on a portion of the initial first conductive layer includes: performing an oxidation treatment on a portion of the initial first conductive layer to form an oxide layer; and performing a reduction treatment on the oxide layer to form an amorphization layer.

[0011] Optionally, the gas of the gas oxidation process includes a gas containing oxygen or ozone; the reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

[0012] Optionally, the method of performing an amorphization treatment on a portion of the initial first conductive layer includes: performing a nitridation treatment on a portion of the initial first conductive layer to form a nitride layer; and performing a reduction treatment on the nitride layer to form an amorphization layer.

[0013] Optionally, the nitridation process includes a gas nitridation process, and the gas of the gas nitridation process includes a gas containing nitrogen; the reduction process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

[0014] Optionally, the method for forming the amorphous layer includes: removing a portion of the initial first conductive layer to form a first conductive layer; and forming the amorphous layer on the first conductive layer.

[0015] Optionally, the process of removing part of the initial first conductive layer includes a wet etching process.

[0016] Optionally, the process of forming the amorphization layer on the first conductive layer includes a selective deposition process.

[0017] Optionally, the method for forming the initial first conductive layer includes: forming a first mask layer on the first dielectric layer; etching the first dielectric layer using the first mask layer as a mask until the substrate surface is exposed, thereby forming a groove in the first dielectric layer; forming a transitional first conductive layer in the groove; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer.

[0018] Optionally, the thickness of the amorphous layer ranges from 2 nanometers to 10 nanometers.

[0019] Optionally, the method for forming the first opening includes: forming a second mask layer on the second dielectric layer; etching the second dielectric layer using the second mask layer as a mask until the surface of the amorphized layer is exposed, thereby forming the first opening in the second dielectric layer.

[0020] Optionally, the method for forming the second opening includes: removing a portion of the amorphized layer exposed by the first opening to form a transitional second opening in the amorphized layer; and laterally etching the amorphized layer exposed by the transitional second opening to form the second opening in the amorphized layer.

[0021] Optionally, the process of etching the second dielectric layer includes an anisotropic dry etching process; and the process of removing a portion of the amorphized layer exposed by the first opening to form the transitional second opening includes an anisotropic dry etching process.

[0022] Optionally, the process of performing lateral etching on the amorphized layer exposed by the transitional second opening includes an isotropic wet etching process.

[0023] Optionally, after forming the first opening and the second opening, a first annealing treatment is performed on the amorphized layer to crystallize the amorphized layer into a second conductive layer.

[0024] Optionally, after performing the first annealing treatment on the amorphized layer, the method further includes: forming a third conductive layer in the first opening and the second opening.

[0025] Optionally, the method for forming the third conductive layer includes: forming an initial third conductive layer in the first opening and the second opening; forming a stop layer on the initial third conductive layer; forming a buffer layer on the stop layer; and planarizing the buffer layer, the stop layer and the initial third conductive layer to form a third conductive layer.

[0026] Optionally, the buffer layer and the initial third conductive layer are made of the same material.

[0027] Optionally, the material of the buffer layer and the initial third conductive layer includes metal, and the metal includes tungsten.

[0028] Optionally, the process of forming the initial third conductive layer in the first opening and the second opening includes a selective deposition process; process parameters of the selective deposition process include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0029] Optionally, the process of planarizing the buffer layer, the stop layer and the initial third conductive layer includes a chemical mechanical polishing process.

[0030] Optionally, the material of the first conductive layer includes metal, and the metal includes crystalline cobalt.

[0031] Optionally, before forming the first dielectric layer on the substrate, the method further includes: forming a gate structure on the substrate; forming source-drain doped regions in the substrate on both sides of the gate structure; the first dielectric layer is located on the sidewalls of the gate structure, and the first conductive layer is located on the source-drain doped regions.

[0032] Optionally, the substrate includes: a base and a fin structure located on the base; the gate structure spans the fin structure, and the source and drain doped regions are located in the fin structure on both sides of the gate structure.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] The method for forming a semiconductor structure in the technical solution of the present invention forms an amorphous layer on a first conductive layer, wherein the material of the amorphous layer is the material of the amorphous first conductive layer, and then forms a first opening in a second dielectric layer, and forms a second opening in the amorphous layer at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate. Since the amorphous layer is an amorphous material and the structure of the amorphous material is relatively loose, the amorphous layer is easy to etch during the etching process of forming the second opening, so that the morphology of the second opening is easy to control, so that the projection area of ​​the formed first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, so that in the subsequent process of forming the third conductive layer in the first opening and the second opening, the third conductive layer located in the second opening can protect the second conductive layer and the first conductive layer, and prevent the second conductive layer and the first conductive layer from being damaged during the process of forming the third conductive layer, thereby improving the performance of the semiconductor structure.

[0035] Furthermore, the amorphous layer can be crystallized into the second conductive layer through the first annealing treatment, so that the resistance of the second conductive layer is reduced and the conductive effect of the second conductive layer can be improved.

[0036] Furthermore, the process of forming an initial third conductive layer in the first opening and the second opening includes a selective deposition process, which can form a densely structured initial third conductive layer in an opening with a large aspect ratio, so that the subsequently formed third conductive layer has a smaller resistance and a better conductive effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 3 is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment;

[0038] Figures 4 to 11is a schematic cross-sectional structure diagram of a semiconductor structure forming process in an embodiment of the present invention;

[0039] Fig.12 and Fig.13 FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0040] As described in the background art, the manufacturing process of the semiconductor structure with the local interconnection structure in the prior art is complicated, and the performance of the formed semiconductor structure needs to be further improved. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0041] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0042] Please refer to Figure 1 , providing a substrate 100; forming a gate structure 101 on the substrate 100; forming source-drain doped regions 102 in the substrate on both sides of the gate structure 101; forming a first dielectric layer 103 on the substrate; forming a conductive layer 104 in the dielectric layer 103, wherein the conductive layer 104 is electrically connected to the source-drain doped regions 102; forming a second dielectric layer 105 on the first dielectric layer 103 and the conductive layer 104; forming a first opening 106 in the second dielectric layer 105, wherein the first opening 106 exposes the surface of the conductive layer 104; and forming a second opening 110 in the first conductive layer at the bottom of the first opening 106.

[0043] Please refer to Figure 2 , forming an initial connection layer 107 in the first opening 106 and the second opening 110 ; forming a seed layer (not shown) on the surface of the initial connection layer 107 and the surface of the second dielectric layer 105 ; and forming a connection material layer 108 on the seed layer.

[0044] Please refer to Figure 3 , planarizing the connection material layer 108 , the seed layer, the initial connection layer 107 and a portion of the second dielectric layer 105 to form the connection layer 109 .

[0045] During the formation of the semiconductor structure, the material of the initial connection layer 107 includes metal tungsten, the material of the conductive layer 104 includes metal crystalline cobalt, and the process of forming the initial connection layer 107 in the opening 106 includes a selective deposition process. The material growth of the initial connection layer 107 formed by the selective deposition process has a certain directionality, so the initial connection layer 107 is not completely tightly combined with the second dielectric layer 105, and there is a gap between the initial connection layer 107 and the second dielectric layer 105. In addition, since the material growth of the initial connection layer 107 formed by the selective deposition process has a certain directionality, the top surface of the initial connection layer 107 formed is often higher than the surface of the second dielectric layer 105, and the initial connection layer 107 needs to be planarized to form a connection layer 109. Before planarizing the initial connection layer 107, a seed layer and a connection material layer 108 located on the seed layer are formed on the surface of the initial connection layer 107 and the surface of the second dielectric layer 105, so that the starting plane of the planarization process is relatively flat, so as to control the stop position of the planarization later.

[0046] The planarization process generally adopts a chemical mechanical polishing process, and the polishing liquid of the chemical mechanical polishing process is an acidic solution. Since there is a gap between the initial connection layer 107 and the second dielectric layer 105, the polishing liquid of the chemical mechanical polishing process will enter the conductive layer 104 along the gap between the initial connection layer 107 and the second dielectric layer 105, causing damage to the lattice of the conductive layer 104, thereby increasing the resistance of the conductive layer 104, thereby affecting the performance of the semiconductor structure.

[0047] In order to reduce the influence of the polishing liquid on the conductive layer 104, in this embodiment, an initial second opening (not shown) is formed in the first conductive layer 104 at the bottom of the first opening 106, and then the bottom of the initial second opening is laterally etched to form a second opening 110, so that the size of the second opening 110 in the conductive layer 104 is larger than the size of the first opening 106. Therefore, when the polishing liquid flows into the conductive layer 104 along the gap between the initial connection layer 107 and the second dielectric layer 105, the initial connection layer 107 in the second opening 110 will block the polishing liquid, thereby reducing the damage of the polishing liquid to the conductive layer 104.

[0048] However, since the conductive layer 104 is transformed into a crystalline state after annealing, the crystalline conductive layer 104 is denser and has grain boundaries. When the wet etching process is used to laterally etch the bottom of the initial second opening, the etching direction of the etching solution in the wet etching process is easily guided by the grain boundaries and deviates from the preset direction, making the etching process difficult to control, and thus making it difficult to make the side walls of all the second openings 110 formed to be concave into the first dielectric layer 104 relative to the first opening 106 (e.g., Figure 3 Therefore, the subsequent planarization process for forming the connection layer 109 will still damage part of the conductive layer 104, affecting the performance of the formed semiconductor structure.

[0049] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by forming an amorphous layer on a first conductive layer, the material of the amorphous layer is the material of the amorphous first conductive layer, then forming a first opening in a second dielectric layer, and forming a second opening in the amorphous layer at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate. Since the material of the amorphous layer is the material of the amorphous first conductive layer, the etching process of the amorphous material when forming the second opening is easy to control, so that the projection area of ​​the formed first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, so that in the subsequent process of forming the third conductive layer in the first opening and the second opening, the third conductive layer located in the second opening can protect the second conductive layer and the first conductive layer, and prevent the second conductive layer and the first conductive layer from being damaged in the process of forming the third conductive layer, thereby improving the performance of the semiconductor structure.

[0050] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] Figures 4 to 11 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0052] Please refer to Figure 4 , providing a substrate 200.

[0053] In this embodiment, the material of the substrate 200 is silicon.

[0054] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0055] Please continue to refer to Figure 4 , a gate structure 201 is formed on a substrate 200 ; source-drain doped regions 202 are formed in the substrate 200 on both sides of the gate structure 201 ; a first dielectric layer 203 is formed on the substrate 200 , and the first dielectric layer 203 is located on the sidewall of the gate structure 201 .

[0056] The source-drain doping region 202 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

[0057] The material of the first dielectric layer 203 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first dielectric layer 203 includes silicon oxide.

[0058] The gate structure 201 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0059] In this embodiment, the material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate layer includes polysilicon.

[0060] In other embodiments, the gate structure further includes a work function layer, and the work function layer is located between the gate dielectric layer and the gate layer.

[0061] In other embodiments, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0062] In other embodiments, the method for forming the gate structure includes: forming a dummy gate structure on a substrate; forming source-drain doped regions in the substrate on both sides of the dummy gate structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is located on the side wall of the dummy gate structure; removing the dummy gate structure, forming a gate opening in the first dielectric layer; and forming a gate structure in the gate opening.

[0063] In this embodiment, the substrate 200 is a planar substrate.

[0064] In other embodiments, the substrate includes: a base and a fin structure located on the base; the gate structure spans the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

[0065] Please refer to Figure 5 , an initial first conductive layer 204 is formed in the first dielectric layer 203 , and the initial first conductive layer 204 is located on the source-drain doped region 202 .

[0066] The initial first conductive layer 204 is used for subsequently forming a first conductive layer.

[0067] The material of the initial first conductive layer 204 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, crystalline cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0068] In this embodiment, the material of the initial first conductive layer 204 includes crystalline cobalt. The metallic crystalline cobalt has a relatively low resistivity, which is beneficial to improving the conductive efficiency of the subsequent first conductive layer and improving the performance of the semiconductor structure.

[0069] The method for forming the initial first conductive layer 204 includes: forming a first mask layer (not shown) on the first dielectric layer 203; etching the first dielectric layer 203 using the first mask layer as a mask until the surface of the source-drain doped region 202 is exposed, and forming a groove (not shown) in the first dielectric layer 203; forming a transitional first conductive layer (not shown) in the groove; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer 204.

[0070] The method for forming a transitional first conductive layer in a groove includes: forming an adhesion layer (not shown) on the bottom surface and sidewall surface of the groove and the first dielectric layer 203; forming a conductive material layer (not shown) on the adhesion layer; and planarizing the conductive material layer and the adhesion layer until the surface of the first dielectric layer 203 is exposed to form the transitional first conductive layer.

[0071] The adhesion layer is used to form a conductive material layer in the groove and on the first dielectric layer 203 .

[0072] The material of the adhesion layer includes one or both of metal and metal compound; the metal includes one or more combinations of copper, aluminum, tungsten, crystalline cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0073] In this embodiment, the material of the adhesion layer includes titanium nitride.

[0074] The process of forming the conductive material layer includes an electroplating process, a chemical plating process, a physical vapor deposition process, an atomic layer deposition process or a selective deposition process.

[0075] In this embodiment, the process of forming the conductive material layer includes an electroplating process.

[0076] The second annealing process is used to crystallize the amorphous transitional first conductive layer into a crystalline initial first conductive layer 204 .

[0077] Please refer to Figure 6A first conductive layer 205 and an amorphous layer 206 located on the first conductive layer 205 are formed in the first dielectric layer 203 . The material of the amorphous layer 206 is the material of the first conductive layer 205 in an amorphous state.

[0078] The amorphous layer 206 is an amorphous material with a relatively loose structure. Therefore, the amorphous layer 206 is easy to etch in the subsequent etching process of forming the second opening, so that the morphology of the second opening is easy to control, so that the projection area of ​​the first opening formed subsequently on the substrate 200 is smaller than the projection area of ​​the second opening on the substrate 200. Therefore, in the process of continuing to form the third conductive layer in the first opening and the second opening, the third conductive layer located in the second opening can protect the second conductive layer and the first conductive layer, and avoid the second conductive layer and the first conductive layer from being damaged in the process of forming the third conductive layer, thereby improving the performance of the semiconductor structure.

[0079] In this embodiment, the method for forming the first conductive layer 205 and the amorphous layer 206 includes: performing an amorphization treatment on a portion of the initial first conductive layer 204 to form the first conductive layer 205 and the amorphous layer 206 located on the first conductive layer 205 .

[0080] In this embodiment, the method of amorphizing a portion of the initial first conductive layer 204 includes: oxidizing a portion of the initial first conductive layer 204 to form an oxide layer (not shown); and reducing the oxide layer to form an amorphized layer 206 .

[0081] The oxidation treatment process includes a gas oxidation process, and the gas of the gas oxidation process includes a gas containing oxygen or ozone.

[0082] The reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

[0083] In other embodiments, the method of performing an amorphization treatment on a portion of the initial first conductive layer 204 includes: performing a nitridation treatment on a portion of the initial first conductive layer to form a nitride layer; and performing a reduction treatment on the nitride layer to form an amorphization layer.

[0084] The nitridation treatment process includes a gas nitridation process, and the gas of the gas nitridation process includes a gas containing nitrogen; the reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

[0085] In another embodiment, the method of performing amorphization treatment on a portion of the initial first conductive layer includes: performing plasma gas bombardment treatment on a portion of the initial first conductive layer to form the amorphization layer.

[0086] In this embodiment, the thickness of the amorphized layer 206 is in the range of 2 nanometers to 10 nanometers. If the thickness of the amorphized layer 206 is too thick, i.e., greater than 10 nanometers, the process conditions of the amorphization treatment will be strengthened, resulting in process waste; if the thickness of the amorphized layer 206 is too thin, i.e., less than 2 nanometers, when the second opening is subsequently formed in the amorphized layer 206, the second opening is also located in part of the first conductive layer 205, thereby increasing the difficulty of the etching process for forming the second opening, which is not conducive to forming the second opening within a preset size range.

[0087] Please refer to Figure 7 A second dielectric layer 207 is formed on the first dielectric layer 203 and the amorphous layer 206 .

[0088] The material of the second dielectric layer 207 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0089] In this embodiment, the material of the second dielectric layer 207 includes silicon oxide.

[0090] Please continue to refer to Figure 7 A first opening 208 is formed in the second dielectric layer 207 , wherein the first opening 208 exposes a portion of the surface of the amorphized layer 206 .

[0091] The method for forming the first opening 208 includes: forming a second mask layer (not shown) on the second dielectric layer 207 ; etching the second dielectric layer 207 using the second mask layer as a mask until the surface of the amorphized layer 206 is exposed, thereby forming the first opening 208 in the second dielectric layer 207 .

[0092] The process of etching the second dielectric layer 207 includes an anisotropic dry etching process or a wet etching process.

[0093] In this embodiment, the process of etching the second dielectric layer 207 includes an anisotropic dry etching process. The anisotropic dry etching process has high directional selectivity and can form a first opening 208 with smooth sidewalls and good morphology.

[0094] Please refer to Figure 8 A second opening 209 is formed in the amorphous layer 206 at the bottom of the first opening 208 , the projection area of ​​the first opening 208 on the substrate 200 is smaller than the projection area of ​​the second opening 209 on the substrate 200 , and the projection of the first opening 208 on the substrate 200 is within the projection range of the second opening 209 on the substrate 200 .

[0095] The method for forming the second opening 209 includes: removing part of the amorphous layer 206 exposed by the first opening 208 to form a transitional second opening (not shown) in the amorphous layer 206 ; and laterally etching the amorphous layer 206 exposed by the transitional second opening to form the second opening 209 in the amorphous layer 206 .

[0096] In this embodiment, the process of removing the portion of the amorphized layer 206 exposed by the first opening 208 to form the transitional second opening includes an anisotropic dry etching process. The anisotropic dry etching process facilitates controlling the depth of the transitional second opening.

[0097] The etching gas of the anisotropic dry etching process includes a mixed gas of carbon tetrafluoride, monofluoromethane and oxygen.

[0098] The process of performing lateral etching on the amorphized layer 206 exposed by the transitional second opening includes an isotropic wet etching process. The isotropic wet etching process has a high etching selectivity for the second dielectric layer 207 and the amorphized layer 206, so that the sidewall of the formed second opening 209 is recessed into the first dielectric layer 204 relative to the sidewall of the first opening 208, so that the projected area of ​​the first opening 208 on the substrate 200 is smaller than the projected area of ​​the second opening 209 on the substrate 200.

[0099] The etching solution of the isotropic wet etching process includes a mixed solution of hydrogen peroxide, hydrofluoric acid and water.

[0100] Since the amorphous material structure of the amorphous layer 206 is relatively loose, the amorphous layer 206 is easy to etch during the etching process of forming the second opening 209, so that the morphology of the second opening 209 is easy to control, so that the projected area of ​​the first opening 208 formed on the substrate 200 is smaller than the projected area of ​​the second opening 209 on the substrate 200, so that in the subsequent process of forming the third conductive layer in the first opening 208 and the second opening 209, the third conductive layer located in the second opening 209 can protect the second conductive layer and the first conductive layer 205, and avoid the second conductive layer and the first conductive layer 205 from being damaged during the process of forming the third conductive layer, thereby improving the performance of the semiconductor structure.

[0101] Please refer to Fig. 9 After forming the first opening 208 and the second opening 209 , a first annealing treatment is performed on the amorphous layer 206 to crystallize the amorphous layer 206 into a second conductive layer 210 .

[0102] The parameters of the first annealing treatment are: temperature of 200 degrees Celsius to 500 degrees Celsius, and time of 50 seconds to 500 seconds.

[0103] The amorphous layer 206 can be crystallized into the second conductive layer 210 through the first annealing process, so that the resistance of the second conductive layer 210 is reduced and the conductive effect of the second conductive layer 210 is improved.

[0104] Next, after the amorphous layer 206 is subjected to the first annealing treatment, the process further includes: forming a third conductive layer 214 in the first opening 208 and the second opening 209. The formation process of the third conductive layer 214 is shown in FIG. Fig.10 and Fig.11 .

[0105] Please refer to Fig.10 , an initial third conductive layer 211 is formed in the first opening 208 and the second opening 209 ; a stop layer 212 is formed on the initial third conductive layer 211 and the second dielectric layer 207 ; and a buffer layer 213 is formed on the stop layer 212 .

[0106] The buffer layer 213 and the initial third conductive layer 211 are made of the same material.

[0107] The buffer layer 213 and the initial third conductive layer 211 are made of metal, and the metal includes tungsten.

[0108] The material of the stop layer 212 includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0109] In this embodiment, the material of the stop layer 212 includes titanium nitride. The stop layer 212 is used to form a buffer layer 212 on the second dielectric layer 207 and also serves as a stop layer for subsequently planarizing the buffer layer 213 , the stop layer 212 and the initial third conductive layer 211 .

[0110] The process of forming the initial third conductive layer 211 in the first opening 208 and the second opening 209 includes a selective deposition process. The process parameters of the selective deposition process include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0111] The process of forming the initial third conductive layer 211 in the first opening 208 and the second opening 209 includes a selective deposition process, which can form a densely structured initial third conductive layer 211 in the opening with a large aspect ratio, so that the subsequently formed third conductive layer has a smaller resistance and a better conductive effect.

[0112] Please refer to Fig.11 , planarizing the buffer layer 213 , the stop layer 212 and the initial third conductive layer 211 to form a third conductive layer 214 .

[0113] The process of planarizing the buffer layer 213 , the stop layer 212 and the initial third conductive layer 211 includes a chemical mechanical polishing process, and the polishing liquid of the chemical mechanical polishing process is an acidic solution.

[0114] Since the projection area of ​​the first opening 208 on the substrate 200 is smaller than the projection area of ​​the second opening 209 on the substrate 200, during the process of forming the third conductive layer 214 in the first opening 208 and the second opening 209, the third conductive layer 214 located in the second opening 209 can protect the second conductive layer 210 and the first conductive layer 205, thereby preventing the polishing liquid of the chemical mechanical polishing process from flowing into the second conductive layer 210 and the first conductive layer 205 along the gap between the initial third conductive layer 211 and the second dielectric layer 207 during the process of planarizing the buffer layer 213, the stop layer 212 and the initial third conductive layer 211, causing the second conductive layer 210 and the first conductive layer 205 to be damaged, thereby improving the performance of the semiconductor structure.

[0115] Fig.12 and Fig.13 FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0116] Please refer to Fig.12 , Fig.12 For Figure 5 A schematic structural diagram of a base, wherein a portion of the initial first conductive layer 204 is removed to form a first conductive layer 305 .

[0117] The process of removing a portion of the initial first conductive layer 204 includes a wet etching process or a dry etching process.

[0118] In this embodiment, the process of removing part of the initial first conductive layer 204 includes a wet etching process. The wet etching process has a relatively high etching selectivity for the initial first conductive layer 204, and can completely remove part of the initial first conductive layer 204, and at the same time can obtain a first conductive layer 305 with a good surface appearance, so that the subsequently formed amorphous layer 306 has good contact with the first conductive layer 305.

[0119] Please refer to Fig.13 , an amorphous layer 306 is formed on the first conductive layer 305 , and the material of the amorphous layer 306 is the material of the amorphous first conductive layer 305 .

[0120] In the present embodiment, the process of forming the amorphization layer 306 on the first conductive layer 305 includes a selective deposition process.

[0121] The selective deposition process can form an amorphous layer 306 with a dense structure on the first conductive layer 305 of the metal material, so that the resistance of the second conductive layer formed subsequently is small and the conductive effect is good.

[0122] Next, it also includes: forming a second dielectric layer on the first dielectric layer 203 and the amorphized layer 306; forming a first opening in the second dielectric layer; forming a second opening in the amorphized layer 306 at the bottom of the first opening, wherein the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is within the projection range of the second opening on the substrate; after forming the first opening and the second opening, performing a first annealing treatment on the amorphized layer 306 to crystallize the amorphized layer 306 into a second conductive layer; after performing the first annealing treatment on the amorphized layer 306, it also includes: forming a third conductive layer in the first opening and the second opening. For methods, processes and materials in forming the above structure, please refer to Figures 7 to 11 , I will not go into details here.

[0123] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive layer and an amorphous layer on the first conductive layer in the first dielectric layer, wherein the material of the amorphous layer is the material of the amorphous first conductive layer; forming a second dielectric layer on the first dielectric layer and the amorphized layer; forming a first opening in the second dielectric layer, wherein the first opening exposes a portion of the surface of the amorphized layer; A second opening is formed in the amorphous layer at the bottom of the first opening, the projection area of ​​the first opening on the substrate is smaller than the projection area of ​​the second opening on the substrate, and the projection of the first opening on the substrate is within the projection range of the second opening on the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first conductive layer and the amorphous layer on the first conductive layer in the first dielectric layer, the method further includes: forming an initial first conductive layer in the first dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the first conductive layer and the amorphous layer comprises: performing an amorphous treatment on a portion of the initial first conductive layer to form the first conductive layer and the amorphous layer located on the first conductive layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method of performing amorphization treatment on a portion of the initial first conductive layer includes: performing plasma gas bombardment treatment on a portion of the initial first conductive layer to form the amorphization layer.

5. The method for forming a semiconductor structure according to claim 3, wherein: The method of performing amorphization treatment on a part of the initial first conductive layer comprises: performing oxidation treatment on a part of the initial first conductive layer to form an oxide layer; and performing reduction treatment on the oxide layer to form an amorphization layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: The oxidation treatment process includes a gas oxidation process, and the gas of the gas oxidation process includes a gas containing oxygen or ozone; the reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

7. The method for forming a semiconductor structure according to claim 3, wherein: The method of performing amorphization treatment on a part of the initial first conductive layer comprises: performing nitridation treatment on a part of the initial first conductive layer to form a nitride layer; and performing reduction treatment on the nitride layer to form an amorphization layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The nitridation treatment process includes a gas nitridation process, and the gas of the gas nitridation process includes a gas containing nitrogen; the reduction treatment process includes a gas reduction process, and the gas of the gas reduction process includes a gas containing hydrogen.

9. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the amorphous layer includes: removing a portion of the initial first conductive layer to form a first conductive layer; and forming an amorphous layer on the first conductive layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of removing part of the initial first conductive layer includes a wet etching process.

11. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the amorphization layer on the first conductive layer includes a selective deposition process.

12. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the initial first conductive layer includes: forming a first mask layer on a first dielectric layer; etching the first dielectric layer using the first mask layer as a mask until the substrate surface is exposed, thereby forming a groove in the first dielectric layer; forming a transitional first conductive layer in the groove; and performing a second annealing treatment on the transitional first conductive layer to form the initial first conductive layer.

13. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the amorphous layer ranges from 2 nanometers to 10 nanometers.

14. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening includes: forming a second mask layer on the second dielectric layer; etching the second dielectric layer using the second mask layer as a mask until the surface of the amorphized layer is exposed, thereby forming a first opening in the second dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the second opening includes: removing a portion of the amorphized layer exposed by the first opening to form a transitional second opening in the amorphized layer; and performing side etching on the amorphized layer exposed by the transitional second opening to form the second opening in the amorphized layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The process of etching the second dielectric layer includes an anisotropic dry etching process; and the process of removing a portion of the amorphized layer exposed by the first opening to form a transitional second opening includes an anisotropic dry etching process.

17. The method for forming a semiconductor structure according to claim 15, wherein: The process of performing lateral etching on the amorphized layer exposed by the transitional second opening includes an isotropic wet etching process.

18. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first opening and the second opening, a first annealing treatment is performed on the amorphized layer to crystallize the amorphized layer into a second conductive layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: After performing the first annealing treatment on the amorphized layer, the method further includes: forming a third conductive layer in the first opening and the second opening.

20. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the third conductive layer includes: forming an initial third conductive layer in a first opening and a second opening; forming a stop layer on the initial third conductive layer; forming a buffer layer on the stop layer; and planarizing the buffer layer, the stop layer and the initial third conductive layer to form a third conductive layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: The buffer layer and the initial third conductive layer are made of the same material.

22. The method for forming a semiconductor structure according to claim 21, wherein: The material of the buffer layer and the initial third conductive layer includes metal, and the metal includes tungsten.

23. The method for forming a semiconductor structure according to claim 20, wherein: The process of forming the initial third conductive layer in the first opening and the second opening includes a selective deposition process; the process parameters of the selective deposition process include: a temperature of 300 degrees Celsius to 400 degrees Celsius, and a reaction gas of a mixed gas of hydrogen and tungsten hexafluoride.

24. The method for forming a semiconductor structure according to claim 20, wherein: The process of planarizing the buffer layer, the stop layer and the initial third conductive layer includes a chemical mechanical polishing process.

25. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first conductive layer includes metal, and the metal includes crystalline cobalt.

26. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first dielectric layer on the substrate, the method also includes: forming a gate structure on the substrate; forming source-drain doped regions in the substrate on both sides of the gate structure; the first dielectric layer is located on the sidewall of the gate structure, and the first conductive layer is located on the source-drain doped regions.

27. The method for forming a semiconductor structure according to claim 26, wherein: The substrate comprises: a base and a fin structure located on the base; the gate structure spans across the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

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