A method for manufacturing a semiconductor device

Abstract

This invention discloses a method for fabricating a semiconductor device, relating to the field of semiconductor manufacturing technology, to increase the top width of the active region of a semiconductor device. The method includes: providing a substrate; forming a patterned hard mask layer on the substrate, the patterned hard mask layer having at least one trench; and filling the at least one trench with a semiconductor material to form an active region. The semiconductor device fabrication method provided by this invention is used in semiconductor device fabrication.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] In the process of manufacturing semiconductor devices, active regions are typically fabricated on the wafer. These active regions are usually formed using an etching process.

[0003] However, as the design size of semiconductor devices continues to shrink, the active region formed by traditional etching processes has a positive slope, resulting in a smaller top width of the active region of the semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device to increase the top width of the active region of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device. The method for fabricating the semiconductor device includes:

[0006] Provide a substrate;

[0007] A patterned hard mask layer is formed on the substrate, the patterned hard mask layer having at least one trench;

[0008] The at least one trench is filled with semiconductor material to form an active region.

[0009] Compared to existing technologies, the semiconductor device fabrication method provided by this invention first forms a patterned hard mask layer with trenches on a substrate, and then fills the trenches to form an active region. In this process, the shape and size of the trenches define the shape and size of the active region. Compared to active regions formed by etching the substrate using methods such as etching, which are narrow at the top and wide at the bottom, the active region formed by etching the hard mask layer to form trenches and then filling the trenches has a top width greater than or equal to the designed size. Based on this, the problem of reduced top width of the active region can be avoided, thereby increasing the contact area between the active region and the upper circuitry, reducing contact resistance, and improving the performance of the semiconductor device. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0011] Figure 1 A schematic diagram of the silicon substrate state is provided when fabricating the active region for related technologies; wherein, a is a three-dimensional schematic diagram and b is a side view schematic diagram;

[0012] Figure 2 A schematic diagram of the state of the photoresist layer when fabricating the active region for related technologies; where a is a three-dimensional schematic diagram and b is a side view schematic diagram;

[0013] Figure 3 A schematic diagram showing the formation of a photoresist pattern when creating an active region for related technologies; where a is a three-dimensional schematic diagram and b is a side view schematic diagram;

[0014] Figure 4 A schematic diagram of the etching state of a silicon substrate when fabricating an active region for related technologies; where a is a three-dimensional schematic diagram and b is a side view schematic diagram;

[0015] Figure 5 A schematic diagram showing the state of removing the photoresist pattern at the top of the active region when fabricating the active region for related technologies; where a is a three-dimensional schematic diagram and b is a side view schematic diagram;

[0016] Figure 6 This is a schematic diagram of a substrate being raised during the fabrication of a semiconductor device according to an embodiment of the present invention; wherein, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram;

[0017] Figure 7 This is a schematic diagram showing the formation of a hard mask material layer and a photoresist layer during the fabrication of a semiconductor device according to an embodiment of the present invention; wherein, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram;

[0018] Figure 8 This is a schematic diagram showing the formation of a photoresist pattern and a patterned hard mask layer during the fabrication of a semiconductor device according to an embodiment of the present invention; wherein, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram;

[0019] Figure 9 This is a schematic diagram showing the state of removing the photoresist layer to form a filling portion during the fabrication of a semiconductor device according to an embodiment of the present invention; wherein, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram;

[0020] Figure 10 This is a schematic diagram showing the state of the filling portion other than the trench during the fabrication of a semiconductor device according to an embodiment of the present invention; wherein, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram;

[0021] Figure 11 This is a schematic diagram showing the state of the active region being released when the light-blocking portion of the patterned hard mask layer is removed during the fabrication of a semiconductor device according to an embodiment of the present invention. In the diagram, a is a three-dimensional schematic diagram, b is a side view schematic diagram, and c is a top view schematic diagram.

[0022] Figures 12-17 This is a schematic diagram of each stage of the DRAM active region fabrication process provided in an embodiment of the present invention.

[0023] Figure label:

[0024] Figures 1-5 In the diagram, 11-silicon substrate, 12-photoresist layer, 13-photoresist pattern, 14-active region, and 15-groove.

[0025] Figures 6-17 In the diagram, 21-substrate, 22-hard mask material layer, 23-photoresist layer, 24-photoresist pattern, 25-patterned hard mask layer, 251-trench, 252-light-shielding part, 26-filling part, 27-active region. Detailed Implementation

[0026] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0027] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0028] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0029] In the process of manufacturing semiconductor devices, active regions are typically fabricated on a wafer first, and then these active regions are used to fabricate semiconductor devices such as transistors and memory devices. Subsequently, other semiconductor devices or circuits can be fabricated on top of the fabricated semiconductor devices.

[0030] In related technologies, dry etching processes are commonly used to fabricate active regions on wafers. The following uses a silicon substrate as an example to illustrate the process of fabricating active regions on a silicon substrate. It should be understood that the following description is for illustrative purposes only and not as a limitation. Methods for fabricating active regions provided by related technologies generally include:

[0031] like Figure 1 As shown, a silicon substrate 11 is provided. The specific structure and dimensions of the silicon substrate 11 can be determined according to the actual working conditions, and are not specifically limited here.

[0032] like Figure 2 As shown, a photoresist layer 12 is deposited on a silicon substrate 11. The material of the photoresist layer 12 is a photoresist material.

[0033] like Figure 3 As shown, the photoresist layer 12 can be patterned using a photolithography process to form a photoresist pattern 13.

[0034] like Figure 4 As shown, under the masking of the photoresist pattern 13, the silicon substrate 11 is etched to form a plurality of spaced grooves 15. Doping the silicon substrate 11 between two adjacent grooves 15 can form an active region 14. For example, when using a plasma etching process to etch the silicon substrate 11 downwards to form the grooves 15, the amount of plasma actually involved in the etching gradually decreases as the depth of the grooves 15 gradually increases. In other words, the amount of plasma actually involved in the etching at the groove opening of the groove 15 is greater than the amount of plasma actually involved in the etching at any other point in the downward direction. Therefore, the amount of silicon substrate 11 material etched away at the groove opening of the groove 15 is greater than the amount of silicon substrate 11 material etched away at any other point in the downward direction, resulting in a groove 15 with a "wider at the top and narrower at the bottom" structure. The grooves 15 with this "wider at the top and narrower at the bottom" structure form a "narrower at the top and wider at the bottom" columnar structure. When the above columnar structure is ion-doped to form the active region 14, the top width of the active region 14 is smaller than the bottom width. Therefore, when a corresponding portion of the active region 14 comes into contact with the bit line contact or the storage contact, the contact area becomes smaller compared to the active region which is either equal in width at the top and bottom or wider at the top and narrower at the bottom, resulting in a larger contact resistance. This will reduce the operating performance of the semiconductor device.

[0035] like Figure 5 As shown, after the active region 14 is formed, the photoresist pattern 13 on top of the active region 14 can be removed by dry etching or wet etching process.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a method for fabricating a semiconductor device. It should be noted that this method for fabricating a semiconductor device can be applied to various semiconductor device fabrication processes. The semiconductor device can be a semiconductor memory device, a crystal diode, a CMOS transistor, etc., and is not limited to these.

[0037] Taking a semiconductor memory device as an example, when fabricating a semiconductor memory device, an active region can first be fabricated on a wafer using the semiconductor device fabrication method provided in this embodiment of the invention. Then, buried trench transistors and capacitors are fabricated on the active region, and metal wiring is performed.

[0038] The method for fabricating a semiconductor device provided in this embodiment of the invention includes:

[0039] like Figure 6 As shown, a semiconductor substrate 21 is provided. The substrate 21 can be a common semiconductor substrate such as silicon, gallium arsenide, silicon germanium, ceramic, or semiconductor-on-insulator, or it can be a substrate on which a semiconductor device has already been formed, and is not limited to these. When the substrate 21 is a silicon substrate, it can be a single-crystal silicon substrate or a polycrystalline silicon substrate. In one embodiment of the present invention, the substrate 21 is preferably a bulk silicon substrate.

[0040] like Figure 7 As shown, a hard mask material layer 22 and a photoresist layer 23 are formed sequentially from bottom to top on the substrate 21.

[0041] For example, any of the following processes can be used to form a hard mask material layer 22 on the substrate 21 from bottom to top: thin film deposition, spin coating, electroplating, etc. When the hard mask material layer 22 is formed by chemical vapor deposition, in order to form a high-quality thin film, processes such as enhanced plasma chemical vapor deposition, high-density plasma chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, and molecular beam epitaxy can be used.

[0042] The material of the aforementioned hard mask material layer 22 can be one or more of silicon oxide, silicon nitride, and amorphous carbon. Furthermore, the hard mask material layer 22 can also comprise multiple layers, for example, a stack of at least two of oxides, nitrides, amorphous carbon (ACL), tetraethyl orthosilicate (TEOS), a bottom antireflective layer (BARC), and a dielectric antireflective layer (DARC). For example, a stack of oxides and nitrides from bottom to top, or a stack of tetraethyl orthosilicate, amorphous carbon, and a bottom antireflective layer from bottom to top.

[0043] The thickness of the hard mask material layer 22 defines the height of the active region. Therefore, when designing and fabricating the hard mask material layer 22, the thickness of the hard mask material layer 22 can be designed according to the height of the active region to be fabricated. For example, when an active region with a height of 100 nm is required, a hard mask material layer 22 with a thickness of 100 nm can be formed on the substrate 21. Of course, a hard mask material layer 22 with a thickness greater than 100 nm, such as 110 nm, 130 nm, or 150 nm, can also be formed on the substrate 21.

[0044] The photoresist layer 23 can be formed on the hard mask material layer 22 using any of the following processes: thin film deposition, spin coating, electroplating, etc.

[0045] For example, the material of the photoresist layer 23 is photoresist. Specifically, photoresist of the type of phenol-formaldehyde resin, polyvinyl alcohol laurate, etc., can be used.

[0046] The main function of photoresist layer 23 is to copy the design pattern of the active area onto photoresist layer 23, and then use etching and other processes to copy the design pattern of the active area on photoresist layer 23 onto hard mask material layer 22. During the process of copying the design pattern of the active area onto hard mask material layer 22, in order to prevent the photoresist layer 23 from being rapidly etched, leading to over-etching of the top of hard mask material layer 22, in practical applications, a photoresist material with an etching rate lower than that of hard mask material layer 22 should be used to form photoresist layer 23.

[0047] like Figure 8 As shown, the design pattern of the active region is copied to the photoresist layer 23 to form a photoresist pattern 24.

[0048] In practical applications, photolithography can be used to copy the design pattern of the active area on the photomask onto the photoresist layer. The photoresist pattern 24 formed by the above process has a light-shielding portion 252 and at least one trench 251. Each trench 251 corresponds to a design pattern of an active area.

[0049] like Figure 8 As shown, the hard mask material layer 22 is processed to form a patterned hard mask layer 25. The method for processing the hard mask material layer 22 can be wet etching or dry etching. When using a dry etching process to process the hard mask material layer 22, any of the following processes can be used: plasma etching, ion milling, reactive ion etching, etc.

[0050] In practical applications, under the masking effect of the photoresist pattern 24, the hard mask material layer 22 is processed to form a patterned hard mask layer 25. The process of processing the hard mask material layer 22 is essentially the process of copying the pattern (design pattern of the active area) on the photoresist pattern 24 to the hard mask material layer 22. At this time, the pattern on the patterned hard mask layer 25 is identical to the pattern on the photoresist pattern 24; that is, the patterned hard mask layer 25 has a light-shielding portion 252 and at least one trench 251.

[0051] When the hard mask material layer 22 comprises two layers, from top to bottom, the two hard mask material layers 22 can be defined as the first hard mask material layer and the second hard mask material layer, respectively. In this case, the design pattern of the active area on the photoresist pattern 24 can be copied onto the first hard mask material layer first by etching, and then the design pattern of the active area can be copied onto the second hard mask material layer by etching.

[0052] like Figure 9 As shown, the photoresist pattern 24 is removed, and the trench 251 is filled with semiconductor material to form a filling portion 26. The removal of the photoresist pattern 24 can be performed using either wet etching or dry etching processes. Each trench 251 corresponds to a design pattern for an active region; therefore, filling the trench 251 with semiconductor material can form an active region 27 defined by the shape and size of the trench 251.

[0053] The aforementioned semiconductor materials can be any of silicon, gallium arsenide, silicon germanium, or ceramics, but are not limited to these. In practical applications, the semiconductor material used for filling can be either polycrystalline or single-crystal.

[0054] For example, when the semiconductor material is silicon, the trench 251 can be filled with either monocrystalline silicon or polycrystalline silicon. When the filler is polycrystalline silicon, at least one trench 251 is filled with polycrystalline silicon material to obtain a polycrystalline silicon filled portion 26. Then, the polycrystalline silicon filled portion is heat-treated to form a monocrystalline silicon filled portion. When the filler is monocrystalline silicon, at least one trench 251 is filled with monocrystalline silicon material to form a monocrystalline silicon filled portion.

[0055] During the process of filling the trenches 251 with the aforementioned semiconductor material, the number of trenches 251 filled can be one, two, five, ten, one hundred, or even more. The number of filled trenches 251 is the number of active regions 27 formed.

[0056] When filling trench 251 with semiconductor material, the semiconductor material can be filled into trench 251 using an epitaxial growth process or a deposition process. Specifically, the deposition process can be atmospheric pressure or low pressure vapor phase deposition, atomic layer deposition, or plasma deposition, etc. The epitaxial growth process can be vapor phase epitaxy or molecular beam epitaxy, etc.

[0057] After the filling portion 26 is formed, it can be processed to form the active region 27. In practical applications, the filling portion 26 can be processed by ion doping, so that the semiconductor material filling the trench 251 is called a doped semiconductor material, thereby forming the active region 27. For example, when the semiconductor material filling the trench 251 is silicon, ion doping of the single-crystal silicon filling portion can form the active region 27.

[0058] The aforementioned semiconductor material can also be a doped semiconductor material. During the process of filling trench 251 with semiconductor material, the doped material and the semiconductor material are simultaneously filled into trench 251, that is, the filling process and the doping process are performed simultaneously, which can also obtain the active region 27. In this process, an in-situ doping process can be used to fill trench 251 with semiconductor material to form the active region 27.

[0059] like Figure 10 As shown, the filler portion 26 outside the trench 251 is removed. Alternatively, the filler portion 26 outside the trench 251 can be removed first, leaving the filler portion 26 with the required height, and then the filler portion 26 within the trench 251 can be processed to form the active region 27. In practical applications, wet etching or dry etching processes can be used to remove excess filler portion 26 and photoresist pattern 24.

[0060] like Figure 11 As shown, the light-blocking portion 252 of the patterned hard mask layer 25 is removed, releasing the active region 27.

[0061] In practical applications, wet etching or dry etching processes can be used to remove the light-shielding portion 252 of the patterned hard mask layer 25.

[0062] As can be seen from the above, the semiconductor device fabrication method provided in this embodiment of the invention first forms a patterned hard mask layer 25 with trenches 251 on a substrate 21, and then fills the trenches 251 to form an active region 27. In this process, the shape and size of the trenches 251 define the shape and size of the active region 27. Compared to an active region 27 formed by etching the substrate 21 using methods such as etching, which is narrow at the top and wide at the bottom, the active region 27 formed by etching the hard mask layer to form the trenches 251 and then filling the trenches 251 has a top width greater than or equal to the designed size. Based on this, the problem of reduced top width of the active region 27 can be avoided, thereby increasing the contact area between the active region 27 and the upper circuit, reducing contact resistance, and improving the performance of the semiconductor device.

[0063] In one embodiment of the present invention, the above-described method for forming an active region can be applied to the fabrication of fins in a FinFET.

[0064] The manufacturing method provided in this invention can also be applied to the manufacturing of dynamic random access memory (DRAM). This invention provides a method for manufacturing active regions in DRAM. The manufacturing method will be described in detail below with reference to the accompanying drawings.

[0065] like Figure 12 As shown, a semiconductor material substrate 21 is first provided.

[0066] like Figure 13 As shown, a hard mask material layer 22 and a photoresist layer 23 are formed sequentially from bottom to top on the substrate 21. In practical applications, the hard mask material layer 22 and the photoresist layer 23 can be fabricated using any of the following processes: thin film deposition, spin coating, or electroplating. The photoresist layer 23 is made of photoresist.

[0067] like Figure 14 As shown, the design pattern of the active region is copied to the photoresist layer 23 using photolithography to form a photoresist pattern 24. This photoresist pattern 24 has a light-shielding portion 252 and at least one trench 251. Each trench 251 corresponds to a design pattern of an active region.

[0068] like Figure 14 As shown, under the cover of the photoresist pattern 24, the hard mask material layer 22 is etched to form a patterned hard mask layer 25. At this time, the design pattern of the active region is copied onto the hard mask material layer 22. The patterned hard mask layer 25 has a light-shielding portion 252 and at least one trench 251.

[0069] like Figure 15 As shown, the photoresist pattern 24 is removed, and the trenches 251 of the patterned hard mask layer 25 are filled with semiconductor material to form a filling portion 26. After forming the filling portion 26, the filling portion 26 can be processed by a doping process to form an active region 27.

[0070] like Figure 16 As shown, the active region 27 outside the trench 251 is removed by processes such as wet etching.

[0071] like Figure 17 As shown, the light-blocking portion 252 of the patterned hard mask layer 25 is removed by wet etching or dry etching process, releasing the active region 27.

[0072] This invention also provides a semiconductor memory device. The semiconductor memory device includes at least one active region, each active region being an active region fabricated using the method described above for manufacturing the semiconductor device.

[0073] Compared with the prior art, the beneficial effects of the semiconductor memory device provided by the embodiments of the present invention are the same as the beneficial effects of the semiconductor device manufacturing method described in the above technical solutions, and will not be repeated here.

[0074] This invention also provides an electronic device. This electronic device includes the aforementioned semiconductor memory device. This electronic device can be a communication device, a mobile terminal, etc.

[0075] Compared with the prior art, the beneficial effects of the electronic device provided by the embodiments of the present invention are the same as the beneficial effects of the semiconductor device manufacturing method described in the above technical solutions, and will not be repeated here.

[0076] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0077] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide a substrate; A patterned hard mask layer is formed on the substrate, the patterned hard mask layer having at least one trench and a light-shielding portion; The at least one trench is filled with semiconductor material, the filling portion outside the trench is removed, and the filling portion inside the trench is processed to form an active region; wherein the top width of the active region formed by filling the trench is greater than or equal to the design size; After the active region is formed, the light-blocking portion of the patterned hard mask layer is removed to release the active region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming a patterned hard mask layer on the substrate includes: A hard mask material layer is formed on the substrate; The hard mask material layer is processed to form the patterned hard mask layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming a patterned hard mask layer on the substrate includes: A hard mask material layer and a photoresist layer are formed sequentially from bottom to top on the substrate; The photoresist layer is processed to form a photoresist pattern; The hard mask material layer is processed under the cover of the photoresist pattern to form the patterned hard mask layer.

4. The method for fabricating a semiconductor device according to claim 2 or 3, characterized in that, The material of the hard mask layer is one or more of silicon oxide, silicon nitride, and amorphous carbon.

5. The method for fabricating a semiconductor device according to claim 2 or 3, characterized in that, Processing the hard mask material layer to form the patterned hard mask layer includes: The hard mask material layer is processed by wet etching or dry etching to form the patterned hard mask layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Filling the at least one trench with a semiconductor material to form an active region includes: The at least one trench is filled with polycrystalline silicon material to obtain a polycrystalline silicon filled portion; Heat treatment of the polycrystalline silicon filling portion forms a monocrystalline silicon filling portion; The single-crystal silicon filling portion is processed to form an active region.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Processing the single-crystal silicon filling portion to form an active region includes: The single-crystal silicon filling portion is ion-doped to form the active region.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Filling the at least one trench with a semiconductor material to form an active region includes: The at least one trench is filled with a doped semiconductor material to form an active region.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, Filling the at least one trench with a semiconductor material to form an active region includes: The at least one trench is filled using an epitaxial growth process or a deposition process to form an active region.

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