Split-gate flash memory cell having a grooved select gate

Abstract

The present invention relates to a split-gate flash memory cell having a trench-shaped select gate, and discloses a structure for a split-gate flash memory cell and a method of forming the structure for a split-gate flash memory cell. A trench is formed in a semiconductor substrate. First and second source / drain regions are formed in the semiconductor substrate. A first gate is laterally located between the trench and the second source / drain region, and the second gate includes a portion within the trench. The first source / drain region is located in the semiconductor substrate below the trench. A dielectric layer is located between the portion of the second gate within the trench and the semiconductor substrate.

Description

Technical Field

[0001] The present invention generally relates to integrated circuits and semiconductor device manufacturing, and more particularly, to a structure for a split gate flash memory cell and a method of forming a structure for a split gate flash memory cell. Background Art

[0002] Non-volatile memory is used for general storage and transfer of data in various electronic products. When the storage cell is not powered on, the stored data is retained by the non-volatile storage device. The data storage persistence of non-volatile storage devices is in contrast to volatile storage technologies, such as static random access memory (SRAM) devices, where the stored data will eventually be lost when the storage cell is not powered on, and dynamic random access memory (DRAM) devices, where the stored data will be lost when the storage cell is not refreshed regularly.

[0003] Flash memory is a special type of non-volatile memory that can be reprogrammed and erased. Embedded flash memory can be used to store configuration settings, program code, application parameters, and other types of data in consumer electronics, industrial electronics, and automotive electronics. The storage cell of flash memory is similar to a standard metal-oxide-semiconductor field-effect transistor, but is equipped with a pair of gates instead of a single gate. The current in the trench region between the source and drain is controlled by the cooperation between the floating gate and the control gate. The control gate is similar to a standard transistor gate. However, the floating gate is surrounded and wrapped by a tunneling oxide layer. The floating gate is located between the control gate and the trench region. Charge is transferred to and removed from the floating gate by tunneling through the tunneling oxide layer. The charge stored on the floating gate affects the device threshold voltage, thereby providing different storage logic states. In the split gate flash memory cell design, the control gate partially overlaps with the floating gate and partially overlaps with the trench region, which can significantly improve the data erase time.

[0004] There is a need for an improved structure for a split gate flash memory cell and a method of forming a structure for a split gate flash memory cell. Summary of the Invention

[0005] In one embodiment, a structure for a split gate flash memory cell is provided. The structure includes a semiconductor substrate having a trench, a first source / drain region and a second source / drain region in the semiconductor substrate, a first gate laterally located between the trench and the second source / drain region, and a second gate having a portion within the trench. The first source / drain region is located below the trench. A dielectric layer is located between the portion of the second gate within the trench and the semiconductor substrate.

[0006] In one embodiment, a method of forming a split-gate flash memory cell structure is provided. The method includes forming a trench in a semiconductor substrate, forming a first source / drain region and a second source / drain region in the semiconductor substrate, forming a first gate laterally between the trench and the second source / drain region, forming a dielectric layer within the trench, and forming a second gate including a portion within the trench. The first source / drain region is located in the semiconductor substrate below the trench, and the dielectric layer is located between a portion of the second gate within the trench and the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings included in and constituting a part of this specification illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals are used to indicate like features in different views.

[0008] Figure 1 FIG. is a cross-sectional view of the structure of a split-gate flash memory cell according to embodiments of the present invention.

[0009] Figure 2 FIG. is a cross-sectional view taken along line 2-2 of Figure 1 FIG.

[0010] Figures 3 to 6 FIG. is a cross-sectional view of the structure of a successive manufacturing stage following Figure 2 FIG.

[0011] Figures 7 to 10 FIG. is a cross-sectional view of the structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0012] Referring to Figure 1 and Figure 2 , according to an embodiment of the present invention, a structure 10 for a split-gate flash memory cell includes a plurality of layers 14, 16, 18 formed in a layer stack on a top surface 11 of a semiconductor substrate 12. The semiconductor substrate 12 may be composed of a single-crystalline semiconductor material such as single-crystalline silicon and may be lightly doped to have p-type conductivity. The layers 14 and 18 may be composed of a dielectric material such as silicon dioxide deposited by chemical vapor deposition, and the layer 16 may be composed of an electrical conductor such as doped polysilicon, which is deposited by chemical vapor deposition. In an alternative embodiment, the layer 16 may include a dielectric material such as silicon nitride.

[0013] A hard mask 20 is laid and patterned by photolithography and etching processes to define an opening at a predetermined position of a subsequently formed trench isolation region 22. An etching process, such as a reactive ion etching process, is used to form a trench at the position of the opening in the hard mask 20, and the opening extends completely through layers 14, 16, 18 and extends to a shallower depth of the semiconductor substrate 12. Then the trench is filled with a dielectric material and planarized by chemical mechanical polishing to define the trench isolation region 22. The dielectric material including the trench isolation region 22 can be, for example, silicon dioxide. The hard mask 20 can be removed, and then the trench isolation region 22 can be recessed. The trench isolation region 22 surrounds the active region of the semiconductor substrate 12.

[0014] The formation of the trench isolation region 22 divides layers 14, 16, 18 into several segments for subsequent use in forming the floating gate of the structure 10. The segmentation of layers 14, 16, 18 eliminates the need for a chemical mechanical polishing process to planarize the floating gate material during the formation of the floating gate.

[0015] Reference Figure 3 , in which the same reference numerals denote Figure 2 the same features in , in a subsequent manufacturing stage of the processing method, a trench 24 is formed that extends completely through layers 14, 16, 18 and into the semiconductor substrate 12. The trench 24 can be formed by patterning through photolithography and etching processes. The trench 24 is located in the active region of the semiconductor substrate 12 surrounded by the trench isolation region 22. The trench 24 has a bottom 23 and sidewalls 25 extending to the bottom 23 in the semiconductor substrate 12. The trench 24 is partially located in the semiconductor substrate 12 and partially located between different segments of layers 14, 16, 18.

[0016] A well 26 is formed in a portion of the semiconductor substrate 12 surrounding the trench 24. In one embodiment, the well 26 can be formed by introducing dopants into the semiconductor substrate 12 near the bottom 23 and sidewalls 25 of the trench 24 by ion implantation under given implantation conditions, as indicated by the single arrow. A patterned implantation mask can be formed to define a selected region exposed for implantation. The implantation mask covers a masked region of the semiconductor substrate 12, and the masked region of the semiconductor substrate 12 surrounds the unmasked region around the trench 24. The implantation mask can include a material layer, such as an organic photoresist, which is laid and patterned lithographically such that the vicinity of the trench 24 is not masked. The implantation mask can have a sufficient thickness and blocking ability to prevent the semiconductor substrate 12 under the masked region from receiving the dose of implanted ions.

[0017] The injection conditions (e.g., ion species, dose, kinetic energy, angle of incidence) can be selected to adjust the electrical and physical characteristics of the well 26. In one embodiment, the well 26 can be injected with a p-type dopant (e.g., boron) to provide a semiconductor material with p-type conductivity. In an alternative embodiment, the well 26 can be injected with an n-type dopant (e.g., phosphorus and / or arsenic) to provide a semiconductor material with n-type conductivity. The well 26 can provide doping for the trench region of the structure 10.

[0018] Reference Figure 4 , where like reference numerals represent Figure 3 the same features in Figure 3 ), a doped region 28 is formed in the semiconductor substrate 12 at the bottom 23 of the trench 24 during a subsequent manufacturing stage of the processing method. In one embodiment, the doped region 28 can be formed by introducing a dopant into the semiconductor substrate 12 by ion implantation under given injection conditions, as indicated by the single-headed arrow. The patterned injection mask used to form the well 26 can also be used to form the doped region 28. The doped region 28 extends in the semiconductor substrate 12 along the length of the trench 24. In one embodiment, the doped region 28 can extend in the semiconductor substrate 12 along the entire length of the trench 24.

[0019] The injection conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical characteristics of the doped region 28. The doped region 28 is doped to have a conductivity type opposite to that of the well 26. In one embodiment, the doped region 28 can comprise a semiconductor material doped with an n-type dopant (e.g., phosphorus and / or arsenic) to provide n-type conductivity. In an alternative embodiment, the doped region 28 can comprise a semiconductor material doped with a p-type dopant (e.g., boron) to provide p-type conductivity. The doped region 28 can provide a source for the structure 10.

[0020] Reference Figure 5 , where like reference numerals represent Figure 4 the same features in

[0021] The tunneling oxide layer 32 is formed to conformally cover the sidewalls 25 and the bottom 23 of the trench 24 Figure 3) dielectric layer. A conductor layer 34 is deposited over the tunneling oxide layer 32, and the conductor layer 34 includes a portion filling the trench 24 not occupied by the tunneling oxide layer 32. The tunneling oxide layer 32 is composed of a dielectric material having a high resistivity, and the conductor layer 34 is composed of a conductive material having a low resistivity. In one embodiment, the tunneling oxide layer 32 may be composed of silicon dioxide deposited by atomic layer deposition, and the conductor layer 34 may be composed of doped polysilicon (i.e., doped polycrystalline silicon) deposited by chemical vapor deposition.

[0022] Reference Figure 6 , where like reference numerals represent Figure 5 the same features in, in subsequent manufacturing stages of the processing method, the tunneling oxide layer 32 and the conductor layer 34 are patterned by forming an etch mask using photolithography and then etching using an etching process (e.g., a reactive ion etching process). The patterning of the conductor layer 34 defines the select gate 36. A portion of the select gate 36 extends over the floating gate 30, and another portion of the select gate 36 is located within the trench 24. The portion of the select gate 36 located within the trench 24 extends along the length of the trench 24 at a level above the doped region 28. The floating gate 30 is surrounded by the dielectric materials of the layers 14, 18 and the dielectric material of the tunneling oxide layer 32. The floating gate 30 surrounds a portion of the select gate 36.

[0023] A portion of the tunneling oxide layer 32 is located between the floating gate 30 and the select gate 36. Another portion of the tunneling oxide layer 32 is located within the trench 24 above the doped region 28 and is laterally located between the select gate 36 and the semiconductor substrate 12. Another portion of the tunneling oxide layer 32 is located at the bottom 23 of the trench 24 above the doped region 28 and is located between the doped region 28 and the select gate 36.

[0024] A double-layer spacer 37 is formed that extends around the periphery of the upper portion of the select gate 36. A double-layer spacer 38 is also formed that extends around the periphery of the floating gate 30. The double-layer spacers 37, 38 can be formed by conformally depositing a stack of dielectric material layers and etching the layer stack using a directional or anisotropic etching process (e.g., reactive ion etching).

[0025] A doped region 40 is formed in the semiconductor substrate 12 and is laterally offset with respect to the gates 30, 36 and the trench 24. The doped region 40 is also laterally offset with respect to the gates 30, 36 and the doped region 28. The doped region 40 may have the same conductivity type as the doped region 28. In one embodiment, the semiconductor material of the doped region 40 may be heavily doped with an n-type dopant (e.g., phosphorus and / or arsenic) to provide n-type conductivity. In an alternative embodiment, the semiconductor material of the doped region 40 may be heavily doped with a p-type dopant (e.g., boron) to provide p-type conductivity. The doped region 40 may be formed by implanting ions (e.g., ions of an n-type dopant) into the semiconductor substrate 12 in the presence of an implantation mask over the structure 10. The implantation mask defines the intended location of the doped region 40 in the semiconductor substrate 12.

[0026] A channel region is defined in the semiconductor substrate 12 between the doped region 40 and the doped region 28. The doped region 40 may provide a drain for the structure 10, and the doped region 28 may provide a source for the structure 10 that is laterally spaced from the drain.

[0027] A middle-of-line (MOL) process and a back-end-of-line (BEOL) process are then performed, which include forming an interconnect structure coupled to the structure 10. The interconnect structure may include individual contacts coupled to the select gate 36 and the doped regions 28, 40. The floating gate 30 is not contacted by the contacts of the middle-of-line portion of the interconnect structure but is electrically isolated.

[0028] In use, the structure 10 may be programmed by applying a positive voltage to the select gate 36 and the doped region 40 and applying a current to the doped region 28 to inject electrons in the current flowing through the channel region into the floating gate 30. For example, to program the structure 10, 1.5 volts may be applied to the select gate 36, 8 volts may be applied to the doped region 40, and a current of 1 microampere may be applied to the doped region 28. The floating gate 30 is negatively charged when in the programmed state. The structure 10 may be erased by applying a high positive voltage (e.g., 12 volts) to the select gate 36 and applying a ground potential to the doped regions 28, 40 to induce electrons to tunnel from the floating gate 30 to the select gate 36. The floating gate 30 is positively charged when in the erased state. The structure 10 may be read by applying a positive voltage to the select gate 36 and the doped region 40, applying a ground potential to the doped region 28, and sensing the current. For example, to read the structure 10, a voltage of 2.5 volts may be applied to the select gate 36, a voltage of 0.8 volts may be applied to the doped region 40, and the doped region 28 may be grounded.

[0029] The select gate 36 serves as both an erase gate and a word line in the structure 10 lacking a control gate. The dual-functional select gate 36 can be biased to program the structure and biased to erase the structure 10, which simplifies construction as no individual erase gate is required. Placing a portion of the select gate 36 within the trench 24 facilitates reduction in the size of the structure 10 and an increase in device density relative to conventional split-gate flash memory cells.

[0030] Reference Figure 7 , where like reference numerals denote Figure 6 like features in, according to an embodiment of the present invention, a portion of layer 18 and a portion of layer 14 can be removed by a selective isotropic etching process and replaced by a deposited portion of the tunneling oxide layer 32. A portion of the select gate 36 overlaps or overhangs a portion of the floating gate 30, and only the tunneling oxide layer 32 provides an insulating spacer of dielectric material between these overlapping portions. Another portion of the select gate 36 that also overlaps the floating gate 30 remains separated from the floating gate 30 by an insulating spacer of dielectric material provided by the combination of layer 18 and the tunneling oxide layer 32.

[0031] Reference Figure 8 , where like reference numerals denote Figure 6 like features in, according to an embodiment of the present invention, the structure 10 can be modified by dividing the select gate 36 into a section 42 and a section 44 to provide a fully decoded device. To this end, a photolithography and etching process can be used to pattern the select gate 36 to define an opening in the tunneling oxide layer 32 that extends through the select gate 36 to above the doped region 28 at the bottom 23 of the trench 24, and a double-layer spacer 46 can be formed within the opening. In one embodiment, the double-layer spacer 46 can be formed when forming the double-layer spacers 37, 38 and includes the same dielectric material. The double-layer spacer 46 provides isolation pillars that electrically isolate the section 42 from the section 44 such that the select gate sections 42, 44 can be contacted individually. In an alternative embodiment, an overhang of each select gate section 42, 44 having a floating gate 30 can be provided by removing a portion of layer 18 prior to depositing the tunneling oxide layer 32, as described in connection with Figure 7 that which is described.

[0032] Reference Figure 9 , where like reference numerals denote Figure 6 like features in, according to an embodiment of the present invention, the select gate 36 can be coplanar or substantially coplanar with the top surface 11 of the semiconductor substrate 12 and located both on and below the top surface 11 of the semiconductor substrate 12. The select gate 36 can be recessed after patterning to provide a setting that is completely below the top surface 11 within the trench 24.

[0033] Reference Figure 10, wherein like reference numerals denote Figure 9 like features in Figure 9 . According to an embodiment of the present invention, both the select gate 36 and the floating gate 30 may be entirely located below the top surface 11 of the semiconductor substrate 12. In particular, they may be disposed between the select gate 36 and the top surface 11 of the semiconductor substrate 12.

[0034] The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer having multiple unpackaged chips), as bare chips, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier having leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnects or buried interconnects). In any case, the chip may be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0035] References in this document to terms such as "vertical," "horizontal," etc. are established as a frame of reference by way of example and not as a limitation. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0036] Terms modified by approximate language as used in this document, such as "about," "approximately," and "substantially," are not limited to the specified exact value. The approximate language may correspond to the precision of the instrument used to measure the value and may represent + / - 10% of the specified value unless otherwise dependent on the precision of the instrument.

[0037] A feature "connected" or "coupled" to another feature may be directly connected or coupled to the other feature or coupled with the other feature, or there may be one or more intermediate features. If there are no intermediate features, a feature may be "directly connected" or "directly coupled" to the other feature or together with the other feature. If there is at least one intermediate feature, a feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature "on" or "in contact with" another feature may be directly on the other feature or in direct contact with the other feature, or conversely, there may be one or more intermediate features. If there are no intermediate features, a feature may be "directly" on the other feature or in "direct contact" with the other feature. If there is at least one intermediate feature, a feature may be "indirectly" on the other feature or in "indirect contact" with the other feature.

[0038] The description of the various embodiments of the present invention is provided for illustrative purposes but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a flash memory cell, the structure comprising: a semiconductor substrate including a trench; a first source / drain region and a second source / drain region located in the semiconductor substrate, the first source / drain region being located below the trench, and the second source / drain region being laterally spaced from the first source / drain region; a well located in a portion of the semiconductor substrate surrounding the trench, wherein the well provides a trench region disposed between the first source / drain region and the second source / drain region; a first gate laterally located between the trench and the second source / drain region; a second gate including a first portion within the trench and a second portion above the first portion, the second portion of the second gate extending laterally to overlap with the first gate; a first dielectric layer including a first portion within the trench and a second portion located between the second portion of the second gate and the first gate, the first portion of the first dielectric layer being located between the first portion of the second gate and the semiconductor substrate; and a second dielectric layer located between the first gate and the second portion of the first dielectric layer.

2. The structure according to claim 1, wherein the second gate is configured to be biased to program the flash memory cell and to be biased to erase the flash memory cell.

3. The structure according to claim 1, wherein the first portion of the second gate and the first portion of the first dielectric layer completely fill the space within the trench.

4. The structure according to claim 3, wherein the second dielectric layer completely covers the first gate.

5. The structure according to claim 1, wherein the first portion of the second gate includes a first section and a second section, and further includes: an isolation pillar located between the first section and the second section of the second gate, the isolation pillar being composed of a dielectric material.

6. The structure according to claim 1, wherein the semiconductor substrate has a top surface, and the first gate is located above the top surface of the semiconductor substrate.

7. The structure according to claim 1, wherein the first source / drain region extends along the entire length of the trench and the first portion of the second gate.

8. The structure according to claim 1, wherein the semiconductor substrate has a top surface, and the first portion of the second gate is completely located below the top surface of the semiconductor substrate.

9. The structure according to claim 1, wherein the semiconductor substrate has a top surface, and the second portion of the second gate is located above the top surface of the semiconductor substrate.

10. The structure according to claim 1, wherein the first gate surrounds the second portion of the second gate.

11. The structure according to claim 1, wherein the first portion of the second gate includes a first section and a second section, and further includes: an insulating spacer located between the first section and the second section of the second gate.

12. A method for forming a structure of a flash memory cell, the method comprising: forming a trench in a semiconductor substrate; forming a first source / drain region and a second source / drain region in the semiconductor substrate; forming a well in a portion of the semiconductor substrate surrounding the trench, wherein the well provides a trench region disposed between the first source / drain region and the second source / drain region; forming a first gate laterally between the trench and the second source / drain region; forming a second gate including a first portion within the trench and a second portion above the first portion, wherein the second portion of the second gate extends laterally to overlap with the first gate; forming a first dielectric layer including a first portion within the trench and a second portion between the second portion of the second gate and the first gate; and forming a second dielectric layer between the first gate and the second portion of the first dielectric layer; wherein the first source / drain region is located below the trench, the second source / drain region is laterally spaced from the first source / drain region, and the first portion of the first dielectric layer is located between the first portion of the second gate and the semiconductor substrate.

13. The method according to claim 12, wherein, forming the first gate laterally between the trench and the second source / drain region includes: patterning a layer stack including a layer composed of a material to form the first gate.

14. The method according to claim 12, wherein, forming the first source / drain region and the second source / drain region in the semiconductor substrate includes: ion implanting the semiconductor substrate below the bottom of the trench to form the first source / drain region.

15. The method according to claim 12, wherein, forming the second gate including the portion within the trench includes: after forming the first dielectric layer, depositing a material on the first dielectric layer to fill the trench; and patterning the material to form the second gate.

16. The method according to claim 13, wherein, when the material is patterned, the second dielectric layer located above the first gate is patterned.

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