Semiconductor-on-insulator wafer with cavity structure

Abstract

The present disclosure relates to semiconductor structures, and more particularly to semiconductor-on-insulator substrates with cavity structures and methods for fabricating the same. The structure includes a bulk substrate having at least one linear cavity structure; an insulator material encapsulating the at least one linear cavity structure; and a buried insulator layer located on the bulk substrate and above the at least one linear cavity structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to semiconductor-on-insulator wafers with cavity structures and methods of manufacturing the same. Background Art

[0002] When formed using bulk semiconductor wafers, device structures such as radio frequency switches are susceptible to high capacitance and body-to-body leakage. To mitigate these issues, silicon-on-insulator (SOI) wafers can be used instead of bulk wafers. SOI wafers include a buried insulator layer disposed between the bulk of the device structure, which provides the active device region, and the bulk of the substrate below the buried insulator layer. Another measure to mitigate the effects of high capacitance and body-to-body leakage is to provide triple-well isolation surrounding the active device region of the device structure. Summary of the Invention

[0003] In one aspect of the present disclosure, a structure includes a bulk substrate having at least one rectilinear cavity structure; an insulator material that seals the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and above the at least one rectilinear cavity structure.

[0004] In one aspect of the present disclosure, a structure includes: a bulk substrate of single crystal material; a buried insulator layer located on the bulk substrate; and at least one linear cavity structure located within the bulk substrate and having a top surface that is the buried insulator layer.

[0005] In one aspect of the present disclosure, a method includes forming an amorphous region at a first depth within a bulk substrate below a buried oxide layer of a semiconductor-on-insulator (SOI) technology; forming a vent hole through the buried oxide layer to expose the amorphous region; removing the amorphous region through the vent hole to form at least one cavity structure at the first depth within the bulk substrate; lining the at least one cavity structure with an insulator material; and forming a single crystalline semiconductor material on the buried oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0007] Figure 1 A semiconductor-on-insulator substrate and corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0008] Figure 2An amorphous region in a bulk wafer of a semiconductor-on-insulator substrate and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0009] Figure 3 Shown are additional amorphous regions in a bulk wafer and corresponding fabrication processes according to aspects of the present disclosure, among other features.

[0010] Figure 4 Shown are trenches exposing an amorphous region and corresponding fabrication processes, among other features, according to aspects of the present disclosure.

[0011] Figure 5 Shown are, among other features, a cavity structure in a bulk wafer beneath an insulator material and a corresponding fabrication process according to aspects of the present disclosure.

[0012] Figure 6 Shown are, among other features, a groove sealed with a material and a corresponding manufacturing process according to some aspects of the present disclosure.

[0013] Figure 7 Shown are, among other features, a cavity structure lined with an insulator material and a corresponding fabrication process according to aspects of the present disclosure.

[0014] Figure 8 An alternative embodiment is shown in which the electrodes are used in a microfluidic MEMS application.

[0015] Figure 9A A top view of a structure having a device over a cavity structure according to further aspects of the present disclosure is shown.

[0016] Figure 9B and Figure 9C Shown Figure 9A Different cross-sectional views of the structure. DETAILED DESCRIPTION

[0017] The present disclosure relates to semiconductor structures, and more particularly to semiconductor-on-insulator wafers having cavity structures (e.g., voids) and methods for their fabrication. More specifically, the present disclosure relates to linear cavity structures (e.g., voids) in bulk wafers of semiconductor-on-insulator (SOI) technology. Advantageously, the present disclosure provides tightly controlled cavity structures in SOI technology.

[0018] In an embodiment, a cavity structure is provided in a bulk wafer of SOI technology, below an insulator layer. The cavity structure is well-formed in all dimensions (e.g., X, Y, and Z dimensions). For example, the cavity structure is a linear structure below a buried oxide layer (e.g., BOX) of the SOI technology. The cavity structure may include thermally oxidized sidewalls. In an embodiment, the cavity structure may be implemented in a switch or microfluidic application (e.g., MEMS microfluidic application).

[0019] As described in more detail herein, the cavity structure can be formed by an implantation process and a subsequent etching process. For example, an implantation of a heavy species through an oxide layer can be used to form amorphous regions that are subsequently removed by a selective etching process. In an embodiment, the implantation process can be an argon implantation process that is used to control the depth of the cavity structure within the bulk wafer of SOI technology. A photolithography process can be used to control the position of the cavity structure. Compared to known isotropic etching processes that have high variability, the use of an implantation process is well controlled, thereby forming a cavity structure that is tightly controlled (e.g., width and height control).

[0020] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, these methods and tools are used to form structures with micrometer and nanometer dimensions. The methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted from integrated circuit (IC) technology. For example, these structures are constructed on a wafer and are realized in a patterned material film by performing a photolithography process on top of the wafer. In particular, the manufacture of these structures uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) selectively etching the film to the mask.

[0021] Figure 1 A substrate and corresponding manufacturing process according to some aspects of the present disclosure are shown. More specifically, Figure 1 The structure 10 shows an SOI technology including a bulk wafer 12, an insulator layer 14, and a semiconductor material 12a located on the insulator layer 14. In an embodiment, the semiconductor material 12a can be composed of any suitable bulk substrate material, such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In a preferred embodiment, the semiconductor material 12a and the bulk wafer 12 include any suitable single crystal orientation (such as (100), (110), (111) or (001) crystal orientation), and are preferably single crystal Si. The insulator layer 14 can be any insulator layer, preferably a buried oxide material (such as BOX).

[0022] Figure 2An amorphous region 20 and a corresponding fabrication process are shown in the bulk wafer 12. As described in more detail, the amorphous region 20 is formed in the bulk wafer 12 directly beneath the insulator layer 14 by performing an implantation process at a certain energy level. The implantation process causes damage to the bulk wafer 12, thereby forming the amorphous region 20 beneath the insulator layer 14.

[0023] More specifically, in Figure 2 In the embodiment of the present invention, a mask 16 can be formed over a semiconductor-on-insulator (SOI) wafer 10, the top semiconductor material 12a is removed using any known wet or dry etching process that exposes the BOX layer 14, and an implant is performed through the BOX layer 14 to transform the bulk wafer 12 (e.g., a crystalline substrate) into an amorphous layer 20. In an alternative embodiment, the semiconductor material 12a is not removed before the implant and is recrystallized after the implant process. In an embodiment, the recrystallization process is a rapid thermal annealing (RTA) performed at a temperature in the range of 900°C to 1100°C for up to 60 seconds. In an embodiment, the RTA is performed at 1000°C for 5 seconds.

[0024] The mask 16 is any known implantation mask and may include a layer of photosensitive material (e.g., an organic photoresist layer) applied by a spin coating process, then pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed using a chemical developer. Those skilled in the art will appreciate that the implantation mask 16 has a thickness and stopping power sufficient to prevent the masked areas from receiving a certain dose of implanted ions.

[0025] The mask 16 is patterned to form openings 18. The patterning of the mask 16 can be formed by conventional photolithography and etching methods known to those skilled in the art. For example, a resist formed on the mask 16 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to form one or more openings (patterns) 18 in the mask 16 through the openings in the resist. The resist can then be removed by a conventional oxygen ashing process or other known strippers.

[0026] Before removing the resist, an implantation process is performed through the opening 18 to form an amorphous region 20. In an embodiment, the ion implantation process includes an argon implantation process to form the amorphous region 20 within the bulk wafer 12 at a defined location within the bulk wafer 12. Depending on the energy level, the amorphous region 20 can extend to different depths. For example, at approximately 100 to 2000 KeV, the argon implantation energy level can be approximately 1E14 to 1.5E15, resulting in a depth range of approximately 0.2 μm to approximately 2.5 μm.

[0027] Figure 3An optional step is shown for providing a deeper amorphous region 20a in the bulk wafer 12, formed by another implantation process. In this implantation process, a different implantation energy (e.g., higher) and / or concentration and a patterned mask 16a are used to form the amorphous region 20a in the bulk wafer 12 at a different depth. This implantation process effectively forms a step-like feature having different dimensions (e.g., depth) than that achieved in the first implantation process. It should be understood that the position of the amorphous region 20a can be controlled by the openings 18a in the mask 16a and can therefore be separated (not shown), partially overlapped (not shown), or completely overlapped (shown) with the first amorphous region 20.

[0028] More specifically, in Figure 3 In the embodiment of the present invention, after stripping off the previous mask, a new implantation mask 16a is deposited over the insulator layer 14. The mask 16a is patterned to form openings 18a using conventional photolithography and etching methods known to those skilled in the art and described herein. After patterning, another argon ion implantation process is performed through the openings 18a to form the amorphous regions 20a. It should also be understood that by adjusting the energy level of the implantation process, the size of the amorphous regions 20a can also be adjusted, for example, making the amorphous regions 20a larger or smaller than the amorphous regions 20. In addition, by positioning the openings 18a at different locations, the amorphous regions 20a can be moved away from the amorphous regions 20. Additional amorphous depth can be added by adding additional masking and implantation steps. In an alternative embodiment, with Figure 2 As in FIG. 1 , the opening 18 a is formed over the top semiconductor material 12 a of the semiconductor-on-insulator (SOI); or, partially over the layer 12 a and partially over the exposed BOX layer 14 .

[0029] exist Figure 4 In the embodiment, after mask 16a is stripped, a vent hole is formed in the structure using conventional photolithography and etching processes described herein to expose amorphous layer 20; or layers 20 and 20a. In an embodiment, vent hole 22 extends into or at least exposes the top surface of amorphous region 20 or amorphous region 20a. In an embodiment, vent hole 22 can also be used as a shallow trench isolation feature to isolate an NFET from a PFET, such as in conventional CMOS as described herein.

[0030] Figure 5The formation of cavity structure 24 and the corresponding fabrication process are shown. In an embodiment, cavity structure 24 extends from vent 22 to below insulator layer 14 and is formed by removing amorphous regions 20, 20a using a selective etching process that is selective to the single-crystalline material of BOX layer 14 and bulk wafer 12. This etching process can be, for example, an aqueous Secco etching process performed through vent 22, using an aqueous solution of K2Cr2O7 mixed with HF; however, other aqueous and dry etching processes are contemplated. In this embodiment, cavity structure 24 is a multi-depth cavity structure due to the different implantation processes; however, those skilled in the art will appreciate that the second implantation process is optional and will result in a cavity of uniform depth.

[0031] In addition, if Figure 5 As shown, cavity structure 24 is well controlled, resulting in a linear cavity structure with strict control (e.g., width and height). In this embodiment, the linear shape has different depths due to different implantation processes, which can be controlled by ion implantation. Furthermore, the top surface of linear cavity structure 24 in bulk wafer 12 includes the top surface of insulator layer 14.

[0032] Figure 6 The vent 22 is shown hermetically sealed with a dielectric material 26. In an embodiment, the dielectric material 26 is an oxide material; however, other insulator materials are contemplated herein. For example, the dielectric material 26 can be any material used for the insulator layer 14. The dielectric material 26 can be deposited by conventional deposition methods such as chemical vapor deposition (CVD). After deposition, in an optional embodiment, any excess dielectric material 26a can be removed by a chemical mechanical planarization (CMP) process; or, as shown, the excess material can be left on the wafer. As described above, a CMP process can be performed to remove excess dielectric layer 26a, leaving dielectric layer 26b to form an STI region (not shown).

[0033] Figure 7 An alternative embodiment is shown in which the sidewalls of cavity structure 24 are coated with an oxide (e.g., SiO2) or other insulating material 30. For example, the sidewalls of cavity structure 24 are coated or lined with oxide material 24a using a conventional furnace or rapid thermal annealing oxidation process. In this embodiment, the oxidation process lines cavity structure 24 and region 24a (if present) with thermal oxide (or other insulating material). This oxidation will passivate surface states (i.e., dangling bonds) on the cavity walls and reduce RF losses during device or chip operation. Thus, insulating material 30 suppresses traps in this manner.

[0034] Figure 8An alternative embodiment is shown in which an electrode is formed. This electrode can be used, for example, as an electrode in a microfluidic MEMS application; or as an active or passive device as described below. Electrode 31 can be formed by a subtractive metal etching process (shown) or a damascene process (not shown) as is known in the art. If a damascene process is used, insulating layer 26a is planarized, if necessary, before forming the damascene trench. Figure 9A A top view of a structure having one or more devices is shown. Figure 9B Shown is a section taken along line AA Figure 9A A cross-sectional view of the structure; Figure 9C Shown is a section taken along line BB Figure 9A A cross-sectional view of the structure. Figures 9A to 9C As shown in structure 10a, cavity structures 24, 24' are optionally lined with oxide material 26a and formed in bulk wafer 12. In this embodiment, both cavity structures 24, 24' have a consistent depth and can be formed by the same masking and implantation process. It should also be understood that more than two cavity structures can be formed, depending on the patterned mask used with the implantation process; or cavities of multiple depths can be formed by using additional photomasks.

[0035] exist Figures 9B to 9C In the embodiment of the present invention, shallow trench isolation (STI) oxide 32 isolates the top silicon layer 12a of the SOI. The STI oxide 32 can be formed from the cavity sealing dielectric 26b or another dielectric deposit. In an embodiment, the STI dielectric is, for example, formed from high-density plasma chemical vapor deposition (HDPCVD) of SiO2, which is well known in the art. If the STI dielectric is formed from the cavity sealing dielectric 26b, an insulator material (e.g., thermal oxide layer 30) can be used as a thermal oxide liner for the STI trenches before the HDPCVD oxide deposition.

[0036] Still refer to Figures 9A to 9C , multiple conductive lines 31 and 31a are formed on the semiconductor material 12a above the cavity structures 124 and 124a; however, it is contemplated that one or more conductive lines may be formed above any combination of cavity structures. Furthermore, shallow trench isolation structures 32 are formed in the semiconductor material 12a, extending all the way to the underlying BOX layer 14.

[0037] In an embodiment, the conductors 31 and 31a may alternatively be any active or passive device, such as a transistor, MOS capacitor, or resistor formed by a conventional CMOS manufacturing process. For example, the FET device 31 may be formed by a gate-first or gate-last process known to those skilled in the art, so that the present disclosure may be fully understood without further explanation. These FET devices 31 include a gate dielectric material (e.g., a high-k material) and a sidewall spacer formed on the sidewalls of the gate electrode material, each of which may be implemented using the conventional CMOS manufacturing structure described herein. The source region and the drain region are formed in the substrate material using a conventional ion implantation process or an epitaxial doped material process known to those skilled in the art. Passive devices 31a, such as resistors or capacitors, are formed on top of the shallow trench isolation 32.

[0038] These structures can be utilized in system-on-chip (SoC) technology. Those skilled in the art will understand that an SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, the SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.

[0039] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a bulk substrate having at least one linear cavity structure; an insulator material that seals the at least one linear cavity structure; a buried insulator layer on the bulk substrate and above the at least one linear cavity structure; as well as a semiconductor material on the buried insulator layer and above the at least one linear cavity structure, wherein the insulator material is above and contacts the semiconductor material, wherein the at least one rectilinear cavity structure is defined by the bulk substrate and a portion of the buried insulator layer at its top surface, wherein the insulator material contacts the portion of the buried insulator layer and extends within the opening of the buried insulator layer.

2. The semiconductor structure of claim 1, wherein the at least one linear cavity structure is lined with an insulator material. The semiconductor structure of claim 2 , wherein the insulator material suppresses traps.

4. The semiconductor structure of claim 3, wherein the insulator material is thermal SiO2. 5 . The semiconductor structure of claim 1 , further comprising shallow trench isolation regions formed in the semiconductor material. The semiconductor structure according to claim 1 , wherein the at least one linear cavity structure is a plurality of cavity structures having different sizes. 7 . The semiconductor structure of claim 1 , wherein the at least one linear cavity structure is a plurality of cavity structures having the same depth within the bulk substrate. The semiconductor structure according to claim 1 , wherein the at least one linear cavity structure is a plurality of cavity structures separated from each other.

9. The semiconductor structure of claim 1, wherein the at least one linear cavity structure is a single linear cavity having different depths.

10. The semiconductor structure of claim 1, wherein the bulk substrate is a single crystalline semiconductor material.

11. The semiconductor structure of claim 1 , wherein the at least one linear cavity structure forms a portion of a microfluidic device.

12. The semiconductor structure of claim 1, wherein the at least one linear cavity structure is hermetically sealed.

13. A semiconductor structure comprising: Bulk substrate of single crystal material; a buried insulator layer located on the bulk substrate; at least one linear cavity structure located within the bulk substrate and having a top surface that is the buried insulator layer; a semiconductor material on the buried insulator layer and over the at least one linear cavity structure, wherein the at least one linear cavity structure is defined by the bulk substrate and a portion of the buried insulator layer at a top surface thereof; and A dielectric material is located over and contacts the semiconductor material and the portion of the buried insulator layer, wherein the dielectric material extends within the opening of the buried insulator layer and seals the at least one linear cavity structure.

14. The semiconductor structure of claim 13, wherein the at least one linear cavity structure is lined with an insulator material. The semiconductor structure of claim 13 , wherein the at least one linear cavity structure is a plurality of cavity structures.

16. The semiconductor structure of claim 13, wherein the at least one linear cavity structure has a stepped feature lined with an insulator material.

17. The semiconductor structure of claim 16, further comprising an electrode positioned above the at least one linear cavity forming a microfluidic device.

18. A method of manufacturing a semiconductor structure, comprising: forming an amorphous region of a first depth within a bulk substrate beneath a buried oxide layer of a semiconductor-on-insulator (SOI) technology; forming a vent hole through the buried oxide layer to expose the amorphous region; removing the amorphous region through the vent hole to form at least one cavity structure at the first depth within the bulk substrate, wherein the at least one cavity structure is defined by the bulk substrate and a portion of the buried oxide layer at a top surface thereof; lining the at least one cavity structure with an insulator material; forming a single crystalline semiconductor material on the buried oxide layer; The vent hole is sealed with a dielectric material, wherein the dielectric material is overlying and contacting the portions of the single crystalline semiconductor material and the buried oxide layer.

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