Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate includes a substrate and a plurality of transistors, and each transistor is disposed on the substrate. Among them, each transistor includes an active portion, an insulating portion, and a first gate. The active portion is disposed on the substrate. The active portion includes at least one semiconductor portion and at least one epitaxial corner portion that is connected to the semiconductor portion and protrudes from the semiconductor portion in a first direction. In the first direction, the epitaxial corner portion is located on one side of the semiconductor portion. The insulating portion is disposed on the active portion and covers the active portion. The first gate is disposed on the insulating portion, and the first gate is located above the semiconductor portion and the epitaxial corner portion. The first gate extends along the first direction. In the present application, in the first direction, by moving the epitaxial corner portion of the active portion outward, the current in which the epitaxial corner does not participate in the operation of the semiconductor portion is reduced or suppressed, avoiding the hump effect caused by different turn-on voltages, thereby improving the performance of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and particularly relates to an array substrate and a display panel. Background Art

[0002] Currently, due to the manufacturing process of thin film transistors (TFTs), after the active layer is etched, a Taper angle, that is, a sharp angle, will be formed at the edge of the active layer, resulting in poor coverage uniformity after the gate insulating layer is deposited. Generally, the gate insulating layer in the Taper angle area at the edge of the active layer is thinner than the film layer in the main area of the active layer, which causes the characteristics of the edge thin film transistors to appear earlier, resulting in a hump effect in the subthreshold region and a decrease in the performance of the device. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate and a display panel to solve the problem of the hump effect caused by different turn-on voltages.

[0004] Embodiments of the present application provide an array substrate, including:

[0005] A substrate;

[0006] A plurality of transistors, each of the transistors being disposed on the substrate; wherein, each of the transistors includes:

[0007] An active part, the active part being disposed on the substrate, the active part including a semiconductor part and at least one epitaxial sharp angle part connected to the semiconductor part and protruding from the semiconductor part in a first direction, in the first direction, the epitaxial sharp angle part is located on one side of the semiconductor part;

[0008] An insulating part, the insulating part being disposed on the active part and covering the active part;

[0009] A first gate, the first gate being disposed on the insulating part, and the first gate being located above the semiconductor part and the epitaxial sharp angle part, the first gate extending along the first direction.

[0010] Optionally, in some embodiments of the present application, the array substrate further includes a second gate, the second gate and the first gate are spaced apart and disposed on the insulating part, and the second gate is located above the semiconductor part and the epitaxial sharp angle part, the second gate extends along the first direction, and the first gate and the second gate are in series, independent or parallel.

[0011] Optionally, in some embodiments of the present application, in the first direction, the semiconductor portions of adjacent transistors are connected by an epitaxial connection portion, the first gate is located above the semiconductor portion, the epitaxial corner portion, and the epitaxial connection portion, the array substrate further includes a second gate, the second gate and the first gate are spaced apart on the insulating portion, the second gate is located above the semiconductor portion, the epitaxial corner portion, and the epitaxial connection portion, the semiconductor portion, the epitaxial corner portion, and the epitaxial connection portion provided with the first gate are spaced apart from the semiconductor portion, the epitaxial corner portion, and the epitaxial connection portion provided with the second gate.

[0012] Optionally, in some embodiments of the present application, in the first direction, the semiconductor portions of adjacent transistors are connected by an epitaxial connection portion and the epitaxial corner portion, the first gate is located above the semiconductor portion, the epitaxial corner portion, and the epitaxial connection portion.

[0013] Optionally, in some embodiments of the present application, in the first direction, the length of the epitaxial corner portion is greater than 1 micron.

[0014] Optionally, in some embodiments of the present application, the first direction intersects the second direction, in the second direction, the distance from the edge of the positive projection of the first gate on the substrate located on the epitaxial corner portion to the edge of the positive projection of the epitaxial corner portion on the substrate is 0 - 1 micron.

[0015] Optionally, in some embodiments of the present application, a through hole is provided on the active portion, the through hole is located on the epitaxial corner portion, and the through hole penetrates the epitaxial corner portion.

[0016] Optionally, in some embodiments of the present application, the aspect ratio of the semiconductor portion ranges from 1:1 to 20:1.

[0017] Optionally, in some embodiments of the present application, the array substrate further includes a source electrode and a drain electrode, the active portion further includes a conductor portion, the first direction intersects the second direction, in the second direction, the conductor portion is located on both sides of the semiconductor portion, the source electrode is provided on one of the conductor portions, and the drain electrode is provided on the other conductor portion.

[0018] Correspondingly, the present application further provides a display panel, and the display panel includes the array substrate as described above.

[0019] The present application discloses an array substrate and a display panel. The array substrate includes a substrate and a plurality of transistors, and each transistor is disposed on the substrate. Wherein, each transistor includes an active portion, an insulating portion, and a first gate. The active portion is disposed on the substrate, and the active portion includes a semiconductor portion and at least one epitaxial sharp corner portion connected to the semiconductor portion and protruding from the semiconductor portion in a first direction. In the first direction, the epitaxial sharp corner portion is located on one side of the semiconductor portion. The insulating portion is disposed on the active portion and covers the active portion. The first gate is disposed on the insulating portion and is located above the semiconductor portion and the epitaxial sharp corner portion. The first gate extends in the first direction. In the present application, in the first direction, by shifting the epitaxial sharp corner portion of the active portion outward, the current in which the epitaxial sharp corner portion does not participate in the operation of the semiconductor portion is reduced or suppressed, avoiding the hump effect caused by different turn-on voltages, thereby improving the performance of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 is a schematic plan view of an array substrate provided by the prior art.

[0022] Figure 2 is Figure 1 a schematic cross-sectional view of a transistor of the provided array substrate along line AB.

[0023] Figure 3 is Figure 1 an enlarged schematic plan view of a transistor in the provided array substrate.

[0024] Figure 4 is Figure 3 a schematic cross-sectional view of the transistor in

[0025] Figure 5 is a first schematic plan view of an array substrate provided by an embodiment of the present application.

[0026] Figure 6 is provided by an embodiment of the present application Figure 5 an enlarged schematic plan view of a transistor of the array substrate therein.

[0027] Figure 7 is a schematic diagram of the gate bias voltage and current of the epitaxial sharp corner portion of a transistor provided by the present application and the edge region of the active portion in the prior art.

[0028] Figure 8It is the second planar schematic diagram of the array substrate provided by the embodiment of the present application.

[0029] Figure 9 It is the third planar schematic diagram of the array substrate provided by the embodiment of the present application. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In the present application, "reaction" can be a chemical reaction or a physical reaction.

[0031] Please refer to Figures 1-4 . There is Figure 1 and Figure 2 It can be seen that in the prior art, for the transistors in the array substrate 10, in the first direction X, the active parts 11 of adjacent transistors are not connected, that is, the active parts 11 of adjacent transistors in the same column are not connected, and the transistors in the same column share one gate 12.

[0032] Please refer to Figure 2 . Each transistor further includes a substrate 13, a light-shielding part 14, a buffer part 15, a gate insulating part 16, a planar part 17, a passivation part 18, a source electrode 19 and a drain electrode 20. The light-shielding part 14 is disposed on the substrate 13, the buffer part 15 is disposed on the substrate 13 and the light-shielding part 14, the active part 11 is disposed on the buffer part 15, the gate insulating part 16 is disposed on the buffer part 15 and the active part 11, the gate 12 is disposed on the gate insulating part, the planar part 17 is disposed on the gate 12 and the gate insulating part, the passivation part 18 is disposed on the planar part 17, the source electrode 19 and the drain electrode 20 are disposed on the passivation part 18 in the same layer, the source electrode 19 is connected to one conductor part of the active part 11, and the drain electrode 20 is connected to the other conductor part of the active part 11.

[0033] Please refer to Figure 3 . The current of the array substrate 10 is composed of a main leakage current Ia and an edge leakage current Ic. The voltage of its gate 12 controls the movement of carriers in the channel region 11a of the active part 11, and determines the on, working and off states of the devices of the array substrate 10. Please refer to Figure 4, it can be known that after etching the edge region 11b of the active portion 11, a Taper angle, i.e., a sharp angle, will be formed, resulting in poor coverage uniformity of the gate insulating portion 16. That is, the film thickness of the gate insulating portion 16 in region II is smaller than that in region I. Under the same gate bias voltage Vg, the electric field strengths in the two regions are different, and the electric field strength in region II is greater than that in region I, resulting in the edge region 11b of the active portion 11 being turned on earlier than the channel region 11a of the active portion 11, thus generating the hump effect, that is, the hump effect caused by different turn-on voltages.

[0034] Therefore, in the array substrate 10 of the prior art, after etching the active portion 11, a Taper angle will be formed, resulting in poor coverage uniformity of the gate insulating portion 12, causing the edge region 11b of the active portion 11 to be turned on earlier than the channel region 11a of the active portion 11, thus generating the hump effect, that is, the edge of the active portion 11 is turned on in advance, resulting in the hump effect.

[0035] To solve the above problems, the present application provides an array substrate and a display panel, which can avoid the problem of the edge of the active portion in the prior art being turned on in advance, resulting in the hump effect.

[0036] The present application discloses an array substrate and a display panel. The array substrate includes a substrate and a plurality of transistors, and each transistor is disposed on the substrate. Among them, each transistor includes an active portion, an insulating portion, and a first gate. The active portion is disposed on the substrate. The active portion includes a semiconductor portion and at least one epitaxial sharp corner portion connected to the semiconductor portion and protruding from the semiconductor portion in a first direction. In the first direction, the epitaxial sharp corner portion is located on one side of the semiconductor portion. The insulating portion is disposed on the active portion and covers the active portion. The first gate is disposed on the insulating portion and is located above the semiconductor portion and the epitaxial sharp corner portion. The first gate extends in the first direction.

[0037] In the present application, in the first direction, by moving the epitaxial sharp corner portion of the active portion outward, the current in which the epitaxial sharp corner portion does not participate in the operation of the semiconductor portion is reduced or suppressed, avoiding the hump effect caused by different turn-on voltages, and thereby improving the performance of the array substrate.

[0038] Please refer to Figure 5 and Figure 6 , Figure 5 The first planar schematic diagram of the array substrate provided by the embodiment of the present application, Figure 6 The embodiment of the present application provides Figure 5 The enlarged planar schematic diagram of the transistor of the array substrate in. The present application provides an array substrate 30, including a substrate 100 and a plurality of transistors 200. The specific description is as follows.

[0039] Each transistor 200 is disposed on a substrate 100. Each transistor 200 includes an active portion 210, an insulating portion 220, and a first gate 230.

[0040] The active portion 210 is disposed on the substrate 100. The active portion 210 includes a semiconductor portion 211 and an epitaxial corner portion 212 connected to the semiconductor portion 211 and protruding from the semiconductor portion 211 in a first direction X. In the first direction X, the epitaxial corner portion 212 is located on one side of the semiconductor portion 211.

[0041] In the present application, in the first direction X, there is an epitaxial corner portion 212 that is connected to the semiconductor portion 211 and protrudes from the semiconductor portion 211 in the first direction X, such that the current in which the epitaxial corner portion 212 does not participate in the operation of the active portion 210 is reduced or suppressed. And because the epitaxial corner portion 212 protrudes from the semiconductor portion 211, the thickness of the insulating portion 220 subsequently covered is uniform on the semiconductor portion 211, so that the turn-on voltage is consistent, that is, it avoids the epitaxial corner portion 212 from turning on prior to the semiconductor portion 211, thereby avoiding the hump effect, and thus improving the performance of the array substrate 30.

[0042] Please refer to Figure 7 , Figure 7 which is a schematic diagram of the gate bias voltage and current of the epitaxial corner portion of the transistor provided in the present application and the edge region of the active portion in the prior art. A voltage of 0.1V is applied to the current of the epitaxial corner portion 212 provided in the present application and the edge region 11b of the active portion 11 in the prior art. When Vg is 0.1 - 3V, the current of the epitaxial corner portion 212 provided in the present application is less than that of the edge region 11b of the active portion 11 in the prior art; when a voltage of 10V is applied to the current of the epitaxial corner portion 212 provided in the present application and the edge region 11b of the active portion 11 in the prior art, and when Vg is 0.1 - 3V, the current of the epitaxial corner portion 212 provided in the present application is less than that of the edge region 11b of the active portion 11 in the prior art. From this, it can be seen that the transistor 200 provided in the present application reduces or suppresses the current in which the epitaxial corner portion 212 does not participate in the operation of the active portion 210, and avoids the hump effect caused by the edge region 11b (i.e., the sharp corner) of the active portion 11 in the prior art turning on prior to the channel region 11a of the active portion 11, that is, the hump effect caused by different turn-on voltages.

[0043] In one embodiment, in the first direction X, the length of the epitaxial sharp corner portion 212 is greater than 1 micron. Specifically, in the first direction X, the length of the epitaxial sharp corner portion 212 can be greater than 1 micron, 3 microns, 5 microns, 10 microns, 50 microns, 80 microns, or 1000 microns, etc. In the present application, in the first direction X, the length of the epitaxial sharp corner portion 212 is set to be greater than 1 micron, so that the edge leakage current Ic can be negligible, avoiding the epitaxial sharp corner portion 212 from turning on prior to the semiconductor portion 211, thereby avoiding the problem of the hump effect, and further improving the performance of the array substrate 30.

[0044] In one embodiment, in the first direction X, the epitaxial sharp corner portions 212 of the plurality of transistors 200 can be all on the same side or different sides, that is, the epitaxial sharp corner portions 212 can all be on the same side of the semiconductor portion 211. For example, the epitaxial sharp corner portions 212 of two adjacent transistors 200 are both located below the semiconductor portion 211, that is, the epitaxial sharp corner portion 212 of the active portion 210 of one transistor 200 is located on a side away from the epitaxial sharp corner portion 212 of the active portion 210 of the other transistor 200; or, the epitaxial sharp corner portion 212 of the active portion 210 of one transistor 200 is located on a side close to the epitaxial sharp corner portion 212 of the active portion 210 of the other transistor 200.

[0045] In one embodiment, a via hole 201 is provided on the active portion 210, the via hole 201 is located on the epitaxial sharp corner portion 212, and the via hole 201 penetrates through the epitaxial sharp corner portion 212 to expose the substrate 100. In the present application, by providing the via hole 201 on the epitaxial sharp corner portion 212, the heat dissipation efficiency of the array substrate 30 is improved, thereby the temperature of the array substrate 30 can be reduced, and thus the performance of the array substrate 30 is ensured.

[0046] In one embodiment, the planar shape of the via hole 201 can be one or a combination of several of a rectangle, an ellipse, a quadrilateral, a triangle, and an irregular shape. But it is not limited thereto.

[0047] In one embodiment, in the first direction X, epitaxial sharp corner portions 212 are provided on both sides of the semiconductor portion 211. In the present application, in the first direction X, epitaxial sharp corner portions 212 are provided on both sides of the semiconductor portion 211, further making the film thickness of the insulating portion 220 subsequently covered uniform on the semiconductor portion 211, so that the turn-on voltage is consistent, that is, avoiding the epitaxial sharp corner portion 212 from turning on prior to the semiconductor portion 211, thereby avoiding the hump effect, and thus improving the performance of the array substrate 30.

[0048] In one embodiment, the active portion 210 includes two connected semiconductor portions 211.

[0049] In one embodiment, the active portion 210 further includes a conductor portion 213. In the second direction Y, the first direction X intersects the second direction Y, and the conductor portion 213 is located on both sides of the semiconductor portion 211.

[0050] In one embodiment, the aspect ratio (W / L) of the semiconductor portion 211 ranges from 1:1 to 20:1. Specifically, the aspect ratio (W / L) of the semiconductor portion 211 can be 2:1, 6:1, 8:1, 10:1, 12:1, 18:1, 20:1, etc. In this embodiment, setting the aspect ratio (W / L) of the semiconductor portion 211 to range from 1:1 to 20:1 improves the voltage negative bias of the array substrate 30, thereby improving the performance of the array substrate 30.

[0051] In one embodiment, the array substrate 30 further includes an epitaxial connection portion 240. In the first direction X, the epitaxial corner portion 212 of the transistor 200 is connected to the semiconductor portion 211 of the adjacent transistor 200 through the epitaxial connection portion 240.

[0052] The insulating portion 220 is disposed on the active portion 210 and covers the active portion 210.

[0053] The first gate 230 is disposed on the insulating portion 220, and the first gate 230 is located above the semiconductor portion 211, the epitaxial corner portion 212, and the epitaxial connection portion 240, and the first gate 230 extends along the first direction X.

[0054] In one embodiment, in the second direction Y, the distance from the edge of the positive projection of the first gate 230 on the substrate 100 located on the epitaxial corner portion 212 to the edge of the positive projection of the epitaxial corner portion 212 on the substrate 100 is 0-1 micrometer. Specifically, in the second direction Y, the distance from the edge of the positive projection of the first gate 230 on the substrate 100 located on the epitaxial corner portion 212 to the edge of the positive projection of the epitaxial corner portion 212 on the substrate 100 can be 0 micrometer, 0.3 micrometer, 0.5 micrometer, 0.8 micrometer, or 1 micrometer, etc. When in the second direction Y, the distance from the edge of the positive projection of the first gate 230 on the substrate 100 located on the epitaxial corner portion 212 to the edge of the positive projection of the epitaxial corner portion 212 on the substrate 100 is 0 micrometer, the positive projection of the first gate 230 on the substrate 100 located on the epitaxial corner portion 212 completely coincides with the positive projection of the epitaxial corner portion 212 on the substrate 100.

[0055] In the present application, in the second direction Y, setting the distance from the edge of the positive projection of the first gate 230 on the substrate 100 located on the epitaxial corner portion 212 to the edge of the positive projection of the epitaxial corner portion 212 on the substrate 100 to 0-1 micrometer further avoids the hump effect, thereby further improving the performance of the array substrate 30.

[0056] In one embodiment, in the first direction X, the width of the first gate 230 located on the semiconductor portion 211 is the same as the width of the first gate 230 located on the epitaxial corner portion 212. In the present application, in the first direction X, the width of the first gate 230 located on the semiconductor portion 211 is set to be the same as the width of the first gate 230 located on the epitaxial corner portion 212, thereby simplifying the manufacturing method of the array substrate 30.

[0057] In one embodiment, the transistor 200 further includes a source electrode 250 and a drain electrode 260. The source electrode 250 is disposed on a conductor portion 213. The drain electrode 260 is disposed on another conductor portion 213.

[0058] It should be noted that the transistor 200 of the present application can be a multiplexing transistor and can be applied to the design of display panel integrated circuits.

[0059] In one embodiment, the array substrate 30 further includes a second gate 270. The second gate 270 and the first gate 230 are spaced apart and disposed on the insulating portion 220, and the second gate 270 is located on the semiconductor portion 211 and the epitaxial corner portion 212. The second gate 270 extends along the first direction X. The first gate 230 is in series, independent, or parallel with the second gate 270. The semiconductor portion 211, the epitaxial corner portion 212, and the epitaxial connection portion 240 provided with the first gate 230 are spaced apart from the semiconductor portion 211, the epitaxial corner portion 212, and the epitaxial connection portion 240 provided with the second gate 270.

[0060] In the present application, the transistor 200 is a double-gate transistor 200, which can improve the mobility of the device, thereby improving the performance of the array substrate 30.

[0061] Please refer to Figure 8 , Figure 8 which is the second planar schematic diagram of the array substrate 30 provided by the embodiment of the present application. It should be noted that the difference between the second planar schematic diagram and the first planar schematic diagram is that: the through hole 201 is located on the epitaxial connection portion 240, and a part of the epitaxial connection portion 240 is provided with the through hole 201.

[0062] Please refer to Figure 9 , Figure 9 which is the third planar schematic diagram of the array substrate 30 provided by the embodiment of the present application. It should be noted that the difference between the third planar schematic diagram and the second planar schematic diagram is that:

[0063] the through holes 201 are all located on the epitaxial connection portion 240. In the present application, the through holes 201 are all disposed on the epitaxial connection portion 240, thereby further improving the heat dissipation efficiency of the film layer, and further improving the performance of the array substrate 30.

[0064] The present application also provides a display panel, which includes the array substrate 30 described in the present application.

[0065] The present application discloses an array substrate 30 and a display panel. The array substrate 30 includes a substrate 100 and a plurality of transistors 200, and each transistor 200 is disposed on the substrate 100. Each transistor 200 includes an active portion 210, an insulating portion 220, and a first gate 230. The active portion 210 is disposed on the substrate 100. The active portion 210 includes a semiconductor portion 211 and at least one epitaxial corner portion 212 that is connected to the semiconductor portion 211 and protrudes from the semiconductor portion 211 in the first direction X. In the first direction X, the epitaxial corner portion 212 is located on one side of the semiconductor portion 211. The insulating portion 220 is disposed on the active portion 210 and covers the active portion 210. The first gate 230 is disposed on the insulating portion 220, and the first gate 230 is located above the semiconductor portion 211 and the epitaxial corner portion 212. The first gate 230 extends along the first direction X. In the present application, in the first direction X, by moving the epitaxial corner portion 212 of the active portion 210 outward, the current in which the epitaxial corner portion 212 does not participate in the operation of the semiconductor portion 211 is reduced or suppressed, avoiding the hump effect caused by different turn-on voltages, and thereby improving the performance of the array substrate 30.

[0066] The above has introduced in detail an array substrate and a display panel provided by an embodiment of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; A plurality of transistors, each of the transistors being disposed on the substrate; wherein each of the transistors comprises: An active portion disposed on the substrate, the active portion including a semiconductor portion and at least one epitaxial sharp corner portion connected to the semiconductor portion and protruding from the semiconductor portion in a first direction, in the first direction, the epitaxial sharp corner portion being located on one side of the semiconductor portion; An insulating portion disposed on the active portion and covering the active portion; A first gate disposed on the insulating portion, and the first gate being located above the semiconductor portion and the epitaxial sharp corner portion, the first gate extending along the first direction; The array substrate further includes a second gate, the second gate being spaced from the first gate and disposed on the insulating portion, and the second gate being located above the semiconductor portion and the epitaxial sharp corner portion, the second gate extending along the first direction, the first gate being in series, independent or parallel with the second gate.

2. The array substrate according to claim 1, wherein In the first direction, the semiconductor portions of adjacent transistors are connected by an epitaxial connection portion, the first gate being located above the semiconductor portion, the epitaxial sharp corner portion and the epitaxial connection portion, the array substrate further including a second gate, the second gate being spaced from the first gate and disposed on the insulating portion, the second gate being located above the semiconductor portion, the epitaxial sharp corner portion and the epitaxial connection portion, the semiconductor portion, the epitaxial sharp corner portion and the epitaxial connection portion provided with the first gate being spaced from the semiconductor portion, the epitaxial sharp corner portion and the epitaxial connection portion provided with the second gate.

3. The array substrate according to claim 1, wherein In the first direction, the semiconductor portions of adjacent transistors are connected by an epitaxial connection portion and the epitaxial sharp corner portion, the first gate being located above the semiconductor portion, the epitaxial sharp corner portion and the epitaxial connection portion.

4. The array substrate according to claim 1, wherein In the first direction, the length of the epitaxial sharp corner portion is greater than 1 micron.

5. The array substrate according to claim 1, wherein The first direction intersects with a second direction, in the second direction, the distance from the edge of the positive projection of the first gate on the substrate located on the epitaxial sharp corner portion to the edge of the positive projection of the epitaxial sharp corner portion on the substrate is 0-1 micron.

6. The array substrate according to claim 1, wherein A through hole is provided on the active portion, the through hole being located on the epitaxial sharp corner portion and penetrating the epitaxial sharp corner portion.

7. The array substrate according to claim 1, wherein The aspect ratio of the semiconductor portion ranges from 1:1 to 20:

1.

8. The array substrate according to claim 1, wherein The array substrate further includes a source electrode and a drain electrode, the active portion further includes a conductor portion, the first direction intersects with a second direction, in the second direction, the conductor portion is located on both sides of the semiconductor portion, the source electrode is disposed on one of the conductor portions, and the drain electrode is disposed on the other conductor portion.

9. A display panel, characterized in that, The display panel includes the array substrate according to any one of claims 1-8.

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