Vertical transistors, integrated circuits, and methods for forming vertical transistors and integrated circuits.

Abstract

Embodiments of this application relate to a vertical transistor, an integrated circuit, and a method of forming the vertical transistor and the integrated circuit. A method of forming a vertical transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The method includes microwave annealing at least the channel region in a plurality of time-interval microwave annealing steps. The plurality of time-interval microwave annealing steps reduce the average concentration of elemental form H in the channel region from its state prior to the start of the plurality of time-interval microwave annealing steps. The reduced average concentration of elemental form H is from 0.005 to less than 1 atomic percentage. Structural embodiments of the invention are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to vertical transistors, integrated circuits, methods for forming vertical transistors, and methods for forming integrated circuits. Background Technology

[0002] Memory is a type of integrated circuit used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines, gate lines, or gate lines). Digital lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed using a combination of digital lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically defined as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored electrostatically within this material. Depending on the composition of the insulating material, the stored field will be volatile or non-volatile. For example, a capacitor insulating material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has at least a portion of a ferroelectric material as the insulating material. Ferroelectric materials are characterized by having two stable polarization states, and thus can be used as programmable materials for capacitors and / or memory cells. The polarization states of the ferroelectric material can be changed by applying a suitable programming voltage and remain thereafter (at least for a period of time) after the programming voltage is removed. Each polarization state has a charge storage capacitance different from the other, and ideally can be used to write (i.e., store) and read the memory state without reversing the polarization state until it is desired to reverse it. Less ideally, in some memories with ferroelectric capacitors, the act of reading the memory state may reverse the polarization. Therefore, when the polarization state is determined, the memory cell is rewritten to place the memory cell in a read-ahead state immediately after its determination. Regardless, due to the bistable nature of the ferroelectric material forming the capacitor portion, memory cells incorporating ferroelectric capacitors are ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field-effect transistors (FETs) are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, for example, ferroelectric.

[0006] Of course, capacitors and transistors can be used in integrated circuits other than memory circuits. Summary of the Invention

[0007] Describe a vertical transistor. In some instances, the vertical transistor may include: a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region; and the channel region having an average concentration of H in the form of elemental form from 0.005 to less than 1 atomic percentage.

[0008] Describing an integrated circuit. In some instances, the integrated circuit may include: a lower array comprising vertical transistors; each of the lower array vertical transistors individually including a top source / drain region, a bottom source / drain region, a lower array channel region vertically located between the top and bottom source / drain regions, and a lower array gate operatively adjacent to the lower array channel region; an upper array of vertical transistors spaced above the lower array of vertical transistors, each of the upper array vertical transistors individually including a top source / drain region, a bottom source / drain region, an upper array channel region vertically located between the top and bottom source / drain regions, and an upper array gate operatively adjacent to the upper array channel region; an insulating material vertically located between the lower and upper arrays and spaced them relative to each other; and each of the lower and upper array channel regions having an average concentration of H in the form of an element from 0.005 to less than 1 atomic percentage.

[0009] A method for forming a vertical transistor is described, wherein the vertical transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. In some instances, the method may include: microwave annealing at least the channel region in a plurality of time-interval microwave annealing steps; the plurality of time-interval microwave annealing steps reducing the average concentration of elemental form H in the channel region from its state prior to the start of the plurality of time-interval microwave annealing steps, the reduction in the average concentration of elemental form H being from 0.005 to less than 1 atomic percentage.

[0010] A method of forming an integrated circuit is described, wherein the integrated circuit includes: a lower array comprising vertical transistors; each of the lower array vertical transistors individually including a top source / drain region, a bottom source / drain region, a lower array channel region vertically located between the top and bottom source / drain regions, and a lower array gate operatively adjacent to the lower array channel region; an upper array of vertical transistors spaced above the lower array of vertical transistors, each of the lower array vertical transistors individually including a top source / drain region, a bottom source / drain region, an upper array channel region vertically located between the top and bottom source / drain regions, and an upper array gate operatively adjacent to the upper array channel region; and an insulating material vertically located between the lower and upper arrays and spaced them relative to each other. In some instances, the method may include: microwave annealing at least the upper array channel region in a series of time-interval microwave annealing steps; the series of time-interval microwave annealing steps reducing the average concentration of elemental form H in the upper array channel region from its state prior to the start of the series of time-interval microwave annealing steps, the reduction in the average concentration of elemental form H being from 0.005 to less than 1 atomic percentage. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of a portion of a substrate including a vertical transistor according to an embodiment of the present invention.

[0012] Figure 2 This is a cross-sectional view of a portion of the substrate including an integrated circuit according to an embodiment of the present invention. Detailed Implementation

[0013] Embodiments of the present invention cover methods for forming integrated circuits comprising one or more vertical transistors, and one or more vertical transistors independent of the manufacturing method. Vertical transistors manufactured according to the method embodiments may have any of the properties described herein in the structural embodiments. Figure 1 The first example of a vertical transistor 14 according to an embodiment of the invention, which is part of construction 10, is illustrated by way of example. Construction 10 includes a substrate 11 having any one or more of a conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulator (i.e., electrically) material 12. Various materials have been vertically formed above the substrate 11. The materials may be... Figure 1 The material depicted may be adjacent to, vertically inside, or vertically outside the substrate. For example, other parts of the integrated circuit or fully fabricated components may be disposed above, around, or within the substrate 11. Only one vertical transistor 14 is shown, but configuration 10 may include multiple vertical transistors of the same or different configurations, for example, fabricated as an array comprising one or more vertical transistors according to the invention.

[0014] The vertical transistor 14 includes a top source / drain region 16, a bottom source / drain region 18, a channel region 20 vertically located between the top and bottom source / drain regions 16 and 18, respectively, and a gate 22 (i.e., a conductive material) operably laterally adjacent to the channel region 20 (e.g., beside it laterally). A gate insulator 24 (e.g., silicon dioxide, silicon nitride, a high-k material, and / or a ferroelectric material) is located between the gate 22 and the channel region 20. For simplicity and clarity, the components depicted in the example are only shown in the example. Figure 1 The image is shown as a vertical cross-section. Example source / drain regions and channel regions may extend into, for example, from... Figure 1 The form of a longitudinally extending line along the plane of the page. Alternatively, and by way of example only, this may be circular, rectangular, elliptical, triangular, etc., in a horizontal cross-section (not shown). Gate insulator 24 and / or gate 22 may surround such a structure, or alternatively, by way of example only, partially surround such a structure, or only on one lateral side of a vertical cross-section (not shown). By way of example only, regions 16, 18, and 20 may comprise one or more suitably doped crystalline semiconductor materials, such as silicon, germanium, and so-called group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN), wherein source / drain regions 16 and 18 are sufficiently doped to conduct electricity, and channel region 20 is undoped or sufficiently doped to be semiconducting, to conduct in the “on” state of the transistor and not conduct in the “off” state.

[0015] The channel region 20 has an average concentration of elemental form H from 0.005 to less than 1 atomic percentage, in one embodiment not exceeding 0.5 atomic percentage, in one embodiment not exceeding 0.25 atomic percentage, in one embodiment not exceeding 0.1 atomic percentage, and in one embodiment not exceeding 0.01 atomic percentage. In one embodiment, all channel regions 20 have a concentration of elemental form H from 0.005 to less than 1 atomic percentage. In one embodiment, the channel region 20 comprises silicon. Elemental form H can be introduced in a manufacturing process in which a vertical transistor 14 is formed, for example, by a deposition gas comprising a compound or species having hydrogen atoms therein. The presence of some elemental form H may be advantageous for the operation of the vertical transistor, but a concentration of 1 atomic percentage or more is disadvantageous, and in any case, undesirable void spaces may be created in the channel region 20 upon heating.

[0016] Any other attributes or aspects that may be used in the embodiments shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described above.

[0017] Embodiments of the present invention cover integrated circuits, for example, as per [reference to...] Figure 2 Construction 10a is illustrated in the diagram. The same numbers from the embodiments described above have been used as appropriate, with some differences from construction 10 indicated by the suffixes “a,” “L,” “U,” or by different numbers. Construction 10a includes an example stack 26, which includes layers 28, 30, and 32. Construction 10a may have more layers than shown. The integrated circuit of construction 10a includes a lower array 34, which includes vertical transistors 14L. Each of these transistors individually includes a top source / drain region 16L, a bottom source / drain region 18L, a lower array channel region 20L vertically located between the top and bottom source / drain regions, and a lower array gate 22L operatively adjacent to the lower array channel region 20L. Regions 18L, 16L, 20L, and 22L of the lower array vertical transistors 14L may accordingly have any of the properties described above with respect to 18, 16, 20, and 22.

[0018] The integrated circuit of configuration 10a includes an upper array 36 of vertical transistors 14U spaced above a lower array 34 of vertical transistors 14L. Each of the upper array vertical transistors 14U includes a top source / drain region 16U, a bottom source / drain region 18U, an upper array channel region 20U vertically located between the top and bottom source / drain regions, and an upper array gate 22U operatively adjacent to the upper array channel region 20U. Regions 18U, 16U, 20U, and 22U of the upper array vertical transistors 14U may accordingly have any of the properties described above with respect to 18, 16, 20, and 22. An insulating material 38 (e.g., silicon dioxide and / or silicon nitride) is vertically located between the lower array 34 and the upper array 36 and spaces them apart (e.g., as a layer 30 separating layers 28 and 32). Instance levels 28 and 32 are shown to include insulating material 40, which may be a composition that is the same as or different from insulating material 38.

[0019] The lower array channel region 20L and the upper array channel region 20U each have an average concentration of H in the form of the element, ranging from 0.005 to less than the atomic percentage of the number 1.

[0020] In one embodiment, the integrated circuit configured 10a includes a lower array gate insulator 24L laterally between a lower array channel region 20L and a lower array gate 22L. Furthermore, the lower array 34 includes a capacitor 45, each capacitor 45 individually including a lower array capacitor insulator 50 (e.g., silicon dioxide, silicon nitride, a high-k material, and / or a ferroelectric material) between a pair of lower array capacitor electrodes 52, 54. In this embodiment, the integrated circuit includes at least one of (a) and (b), wherein:

[0021] (a) At least one of the lower array vertical transistors, having a lower array gate insulator comprising a metal oxide, wherein the metal is one or more of Pb, Zr, Hf, Ru, and Ti; and

[0022] (b) at least one of the lower array capacitors having a lower array capacitor insulator comprising a metal oxide. In one embodiment, the integrated circuit includes (a), in another embodiment it includes (b), and in yet another embodiment it includes both (a) and (b).

[0023] In one embodiment, the integrated circuit configured 10a includes an upper array gate insulator 24U lateral between an upper array channel region 20U and an upper array gate 22U. Furthermore, the upper array 36 includes a capacitor 55, each capacitor 55 individually comprising an upper array capacitor insulator 60 between a pair of upper array capacitor electrodes 62, 64. The upper array capacitor 55 may have the same configuration as the lower array capacitor 45 or a different configuration. In any case, in this embodiment, the integrated circuit includes at least one of (c) and (d), wherein:

[0024] (c) at least one of the upper array vertical transistors, having an upper array gate insulator comprising a metal oxide; and

[0025] (d) At least one of the arrayed capacitors having an arrayed capacitor insulator comprising a metal oxide. In one embodiment, the integrated circuit includes (c), in another embodiment it includes (d), and in yet another embodiment it includes both (c) and (d).

[0026] In one embodiment, the lower array channel region 20L comprises a metal oxide, wherein the metal is one or more of In, Ga, and Zn, and in one embodiment is substantially composed of this metal oxide. In one embodiment, the upper array channel region 20U comprises a metal oxide, and in one embodiment is substantially composed of this metal oxide.

[0027] In one embodiment, the lower array 34 includes at least a number of electronic components, said electronic components comprising at least one of metal oxides, metal nitrides, or metal chalcogenides other than metal oxides, wherein the metal of said metal oxide, metal nitride, or metal chalcogenide is one or more of Zr, Hf, Al, Ta, Nb, Ni, Co, In, Ge, Sb, Be, Ti, Zn, and Ga. Such electronic components can be any existing or future-developed components, such as transistors, capacitors, diodes, thyristors, memristors, etc. Figure 2One or more of the transistors and / or capacitors shown in the diagram. In one embodiment, the upper array 36 also includes at least some electronic components, including at least one of metal oxides, metal nitrides, or metal chalcogenides other than metal oxides.

[0028] In one embodiment, the upper array vertical transistor 14U and the lower array vertical transistor 14L each include a memory cell. For example, and by way of example only, one of the capacitor electrodes 52 or 54 may be directly electrically coupled to one of the source / drain regions 18L or 16L (not shown) to form an individual memory cell (not shown) comprising a capacitor and a transistor. This also applies to the upper array vertical transistor 14U and the capacitor electrodes 52 or 54, as well as the source / drain regions 18U or 16U. Alternatively, and by way of example only, the gate insulator of one or both of the transistors 14L and 14U may be ferroelectric, and a non-volatile memory cell may be formed, for example, without any separate / additional capacitors.

[0029] The various components described above may be interconnected relative to each other within and / or between layers (not shown), and conductive paths (not shown) may extend through one or more of such layers to connect to circuitry above and / or below (not shown).

[0030] Any or any of the other properties or aspects shown and / or described in this document with respect to other embodiments may be used.

[0031] Embodiments of the present invention include a method for forming an integrated circuit including a vertical transistor, and include a method for forming a vertical transistor. A vertical transistor formed according to a method embodiment may have any of the properties described above with respect to structural embodiments. A structural embodiment of a vertical transistor may have any of the properties described below with respect to method embodiments. In one embodiment, the method includes forming a vertical transistor (e.g., 14) including a top source / drain region (e.g., 16), a bottom source / drain region (e.g., 18), a channel region (e.g., 20) vertically located between the top and bottom source / drain regions, and a gate (e.g., 22) operatively adjacent to the channel region 20. A microwave annealing step is performed at multiple time intervals to microwave anneal at least the channel region. The microwave annealing step at multiple time intervals reduces the average concentration of elemental form H in the channel region from its state before the start of the microwave annealing step at multiple time intervals. The average concentration reduction of elemental form H is from 0.005 to less than 1 atomic percentage.

[0032] Those skilled in the art can select suitable microwave power levels and the number of time interval steps to achieve a reduction in the concentration of elemental H to 0.005 to less than 1 atomic percentage. The time interval microwave annealing steps may be at the same power level relative to each other, or may be at two or more different power levels relative to each other. Furthermore, the power level need not be constant in the time interval microwave annealing steps. The time interval microwave annealing steps may have the same time length relative to each other, or may have two or more different time lengths relative to each other. Furthermore, the time between the stated microwave annealing steps may be the same relative to each other or may have two or more different time lengths relative to each other. In some embodiments, the microwave power between adjacent time interval microwave annealing steps is still applied, but reduced from the time interval microwave annealing step, and in another embodiment, the microwave power between adjacent time interval microwave annealing steps is 0 watts. As an example only, the microwave power during cyclic microwave annealing is from 100 watts to 20,000 watts, the time length between adjacent annealing steps is from 1 second to 1 hour, and the microwave power between adjacent annealing steps is from 0 watts to a value lower than the minimum power during the adjacent annealing steps (e.g., less than 100 watts between adjacent annealing steps).

[0033] In one embodiment, the channel region is exposed upwards during microwave annealing steps at multiple time intervals (e.g., before the material has formed the upper source / drain region 16). Alternatively, as an example, the top of the channel region is covered by material during microwave annealing steps at multiple time intervals, for example, until after the material has formed the upper source / drain region 16.

[0034] In one embodiment, the temperature of the channel region and the material below the channel region never exceeds 450°C during all the microwave annealing steps at multiple time intervals; in one embodiment, the temperature never drops below 300°C during all the annealing steps at multiple time intervals (i.e., after initially reaching 300°C, if the substrate is below the temperature at the start of the annealing step); and in one embodiment, the temperature ranges from 300°C to 450°C during all the microwave annealing steps at multiple time intervals.

[0035] In one embodiment, the concentration of elemental form H in the channel region is reduced by at least 10%, in one embodiment by at least 2 times, in one embodiment by at least 10 times, in one embodiment by at least 100 times, and in one embodiment by at least 200 times.

[0036] Any or any of the other properties or aspects shown and / or described in this document with respect to other embodiments may be used.

[0037] In one embodiment, a method includes forming an integrated circuit including a lower array (e.g., 34) comprising vertical transistors (e.g., 14L), each vertical transistor individually including a top source / drain region (e.g., 16L), a bottom source / drain region (e.g., 18L), a lower array channel region (e.g., 20L) vertically located between the top and bottom source / drain regions of the lower array, and a lower array gate (e.g., 22L) operatively adjacent to the lower array channel region. An upper array (e.g., 36) of vertical transistors (e.g., 14U) spaced above the lower array of vertical transistors is also formed. Each upper array vertical transistor includes a top source / drain region (e.g., 16U), a bottom source / drain region (e.g., 18U), an upper array channel region (e.g., 20U) vertically located between the top and bottom source / drain regions of the upper array, and an upper array gate (e.g., 22U) operatively adjacent to the upper array channel region. An insulating material (e.g., 38) is vertically positioned between the lower and upper arrays and spaced apart from each other. The method also includes microwave annealing at least the upper array channel region in a series of time-interval microwave annealing steps. The time-interval microwave annealing steps reduce the average concentration of elemental form H in the upper array channel region from its state prior to the start of the time-interval microwave annealing steps, wherein the average reduction in the concentration of elemental form H is from 0.005 to less than 1 atomic percentage. Such time-interval annealing steps can also be applied to the lower array channel region. Any and several other properties or aspects shown and / or described herein with reference to other embodiments may be used.

[0038] The aforementioned processing or construction can be viewed relative to an array of components formed as a single stack or single layer of such components above or as part of an underlying substrate, or within such a single stack or single layer, or within two stacks or two layers of such components (although each of the single stack / layer and / or two stacks / layers may have multiple levels). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the completed construction, and in some embodiments, may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, the arrays of components may be the same or different from each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses from each other. Intermediate structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Similarly, the different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / layers can be manufactured substantially simultaneously.

[0039] The assemblies and structures discussed above can be used in integrated circuits and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting equipment, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0040] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means a direction along the general surface of the substrate (i.e., within 10 degrees) and relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to horizontal. The reference to “fully horizontal” is a direction along the surface of the substrate (i.e., not at an angle) and relative to the direction in which the substrate is processed during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the substrate’s orientation in three-dimensional space. Additionally, “vertically extending” and “extending vertically” refer to a direction deviating at least 45° from fully horizontal. Furthermore, with respect to field-effect transistors, “extending vertically,” “extending vertically,” “extending horizontally,” “extending horizontally,” and the like refer to the orientation of the transistor’s channel length along which current flows between the source and drain regions during operation. For bipolar junction transistors, "extending vertically," "extending vertically," "extending horizontally," and the like are orientations that refer to the length of the substrate along which current flows between the emitter and collector during operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of the vertical.

[0041] Furthermore, "directly above," "directly below," and "directly under" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, using "directly above" without the preceding "directly" only requires that a portion of the area / material / component above another area / material / component is vertically outside of that other area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "directly" only requires that a portion of the area / material / component below / under another area / material / component is vertically inside that other area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0042] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any material overlying them. Where one or more example compositions are provided for any material, the material may comprise, consist substantially of, or be composed of such one or more compositions. Furthermore, unless otherwise stated, any suitable existing or future-developed technique may be used to form each material, examples of which include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0043] Furthermore, “thickness” itself (without a directional adjective previously) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions of different compositions through a given material or region. Additionally, the various materials or regions described herein may have substantially constant or variable thicknesses. If variable thickness is present, then thickness refers to the average thickness, unless otherwise indicated, and this material or region will have a minimum and a maximum thickness due to the variable thickness. As used herein, “different compositions” only requires that the portions of two said materials or regions that can directly contact each other are chemically and / or physically different (e.g., if such materials or regions are not homogeneous). If two said materials or regions are not directly contacting each other, then “different compositions” only requires that the portions of two said materials or regions that are closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, when a material, region, or structure has at least some physical contact with each other, the material, region, or structure “directly contacts” the other. In contrast, the words “above,” “on,” “adjacent to,” “alongside,” and “against” without the preceding “direct” encompass “direct contact” and constructions in which (some) intermediate materials, (some) areas, or (some) structures cause the materials, areas, or structures to be in contact with each other without physical contact.

[0044] In this paper, if, during normal operation, current can flow continuously from one zone-material-component to another, and this flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” to each other. Another electronic component can be electrically coupled between and to a zone-material-component. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0045] In this document, the terms "row" and "column" are used for convenience in distinguishing one series or orientation of features from another series or orientation of features along which components have been or may be formed. "Row" and "column" are used synonymously with any series of areas, components, and / or features and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect each other at 90° or one or more other angles (i.e., other than right angles).

[0046] Combinations of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds, or combinations thereof.

[0047] In this document, any use of "selective" in relation to etching, removal, deposition, and / or forming is an action in which one material is acted relative to another(s) of said materials at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective forming is the deposition, growth, or formation of a material relative to another(s) of said materials at a rate of at least 2:1 by volume for at least the first 75 angstroms.

[0048] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0049] in conclusion

[0050] In some embodiments, the vertical transistor includes a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region. The channel region has an average concentration of H in the form of elemental form from 0.005 to less than 1 atomic percentage.

[0051] In some embodiments, the integrated circuit includes a lower array comprising vertical transistors. Each lower array vertical transistor includes a top source / drain region, a bottom source / drain region, a lower array channel region vertically located between the top and bottom source / drain regions, and a lower array gate operatively adjacent to the lower array channel region. An upper array of vertical transistors is spaced above the lower array of vertical transistors. Each upper array vertical transistor includes a top source / drain region, a bottom source / drain region, an upper array channel region vertically located between the top and bottom source / drain regions, and an upper array gate operatively adjacent to the upper array channel region. An insulating material is vertically positioned between the lower and upper arrays and spaced apart from each other. The lower and upper array channel regions each have an average concentration of H in the form of 0.005 to less than 1 atomic percentage.

[0052] In some embodiments, a method of forming a vertical transistor, the vertical transistor including a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, the method comprising microwave annealing at least the channel region in a plurality of time-interval microwave annealing steps. The plurality of time-interval microwave annealing steps reduce the average concentration of elemental form H in the channel region from its state prior to the start of the plurality of time-interval microwave annealing steps. The average concentration reduction of elemental form H is from 0.005 to less than 1 atomic percentage.

[0053] In some embodiments, a method of forming an integrated circuit includes forming a lower array comprising vertical transistors. Each lower array vertical transistor includes a top source / drain region, a bottom source / drain region, a lower array channel region vertically located between the top and bottom source / drain regions, and a lower array gate operatively adjacent to the lower array channel region. An upper array of vertical transistors is spaced above the lower array of vertical transistors. Each upper array vertical transistor includes a top source / drain region, a bottom source / drain region, an upper array channel region vertically located between the top and bottom source / drain regions, and an upper array gate operatively adjacent to the upper array channel region. An insulating material is vertically positioned between the lower and upper arrays and spaced relative to each other. The method includes microwave annealing at least the upper array channel region in a plurality of time-interval microwave annealing steps. The plurality of time-interval microwave annealing steps reduce the average concentration of elemental form H in the upper array channel region from its state prior to the start of the plurality of time-interval microwave annealing steps. The average concentration of the elemental form H decreased from 0.005 to less than 1 atomic percentage.

[0054] In accordance with regulations, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the means disclosed herein include exemplary embodiments. Therefore, the claims should be given their full scope literally and should be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. A vertical transistor, comprising: A top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region; and The channel region has an average concentration of H in the form of elements ranging from 0.005 to less than 1 atomic percentage.

2. The vertical transistor of claim 1, wherein the average concentration of elemental form H does not exceed 0.5 atomic percentages.

3. The vertical transistor of claim 2, wherein the average concentration of elemental form H does not exceed 0.25 atomic percentages.

4. The vertical transistor of claim 3, wherein the average concentration of elemental form H does not exceed 0.1 atomic percentage.

5. The vertical transistor of claim 4, wherein the average concentration of elemental form H does not exceed 0.01 atomic percentage.

6. The vertical transistor of claim 1, wherein all said channel regions have a concentration of H in the form of element from 0.005 to less than 1 atomic percentage.

7. The vertical transistor of claim 1, wherein the channel region comprises silicon.

8. An integrated circuit, comprising: The lower array includes vertical transistors; Each of the lower array vertical transistors includes a top source / drain region of the lower array, a bottom source / drain region of the lower array, a lower array channel region vertically located between the top and bottom source / drain regions of the lower array, and a lower array gate operatively adjacent to the lower array channel region. An upper array of vertical transistors, spaced above the lower array of vertical transistors, each of the upper array vertical transistors includes a top source / drain region of the upper array, a bottom source / drain region of the upper array, an upper array channel region located vertically between the top and bottom source / drain regions of the upper array, and an upper array gate operatively adjacent to the upper array channel region. An insulating material, which is vertically positioned between the lower array and the upper array and spaced apart from each other; and The lower array channel region and the upper array channel region each have an average concentration of H in the form of element from 0.005 to less than 1 atomic percentage.

9. The integrated circuit according to claim 8, comprising: A lower array gate insulator is located between the lower array channel region and the lower array gate laterally. The lower array includes capacitors, each of which individually includes a lower array capacitor insulator between a pair of lower array capacitor electrodes; and At least one of (a) and (b), wherein: (a): At least one of the lower array vertical transistors has a lower array gate insulator comprising a metal oxide, wherein the metal is one or more of Pb, Zr, Hf, Ru and Ti; and (b): At least one of the lower array capacitors has a lower array capacitor insulator comprising the metal oxide.

10. The integrated circuit according to claim 9, comprising (a).

11. The integrated circuit according to claim 9, comprising (b).

12. The integrated circuit according to claim 9, comprising (a) and (b).

13. The integrated circuit of claim 9, comprising: An upper array gate insulator is located between the upper array channel region and the upper array gate laterally; The upper array includes capacitors, each of which individually includes an upper array capacitor insulator between a pair of upper array capacitor electrodes; and At least one of (c) and (d), wherein: (c): At least one of the upper array vertical transistors has an upper array gate insulator comprising the metal oxide; and (d): At least one of the upper array capacitors has an upper array capacitor insulator comprising the metal oxide.

14. The integrated circuit according to claim 9, comprising (c).

15. The integrated circuit according to claim 9, comprising (d).

16. The integrated circuit according to claim 9, comprising (c) and (d).

17. The integrated circuit of claim 8, wherein the lower array channel region comprises a metal oxide, wherein the metal is one or more of In, Ga, and Zn.

18. The integrated circuit of claim 17, wherein the lower array channel region is substantially composed of the metal oxide.

19. The integrated circuit of claim 17, wherein the upper array channel region comprises the metal oxide.

20. The integrated circuit of claim 19, wherein the upper array channel region is substantially composed of the metal oxide.

21. The integrated circuit of claim 8, wherein the lower array comprises at least some electronic components, the electronic components comprising at least one of a metal oxide, a metal nitride, or a metal chalcogenide other than a metal oxide; wherein the metal in the metal oxide, metal nitride, or metal chalcogenide is one or more of Zr, Hf, Al, Ta, Nb, Ni, Co, In, Ge, Sb, Be, Ti, Zn, and Ga.

22. The integrated circuit of claim 21, wherein the upper array comprises at least some electronic components, the electronic components comprising at least one of the metal oxide, the metal nitride, or the metal chalcogenide other than the metal oxide.

23. The integrated circuit of claim 21, wherein at least some of the electronic components include the lower array of vertical transistors.

24. The integrated circuit of claim 8, wherein the upper array vertical transistor and the lower array vertical transistor each include a memory cell.

25. A method of forming a vertical transistor, the vertical transistor including a top source / drain region, a bottom source / drain region, a channel region vertically located between the top and bottom source / drain regions, and a gate operatively adjacent to the channel region, the method comprising: In the microwave annealing steps at multiple time intervals, at least the channel region is microwave annealed; The microwave annealing steps at multiple time intervals reduce the average concentration of elemental form H in the channel region from its state before the start of the microwave annealing steps at multiple time intervals to 0.005 to less than 1 atomic percentage.

26. The method of claim 25, wherein the microwave power between adjacent microwave annealing steps in the time interval is 0 watts.

27. The method of claim 25, wherein the channel region is exposed upward during the microwave annealing steps of the plurality of time intervals.

28. The method of claim 25, wherein during the microwave annealing steps at the plurality of time intervals, the top of the channel region is covered with material.

29. The method of claim 28, wherein the material comprises the top source / drain region.

30. The method of claim 25, wherein during the microwave annealing steps of all the plurality of time intervals, the temperature of the channel region and the material below the channel region never exceeds 450°C.

31. The method of claim 25, wherein during the microwave annealing steps of all the plurality of time intervals, the temperature of the channel region and the material below the channel region is never lower than 300°C.

32. The method of claim 25, wherein during the microwave annealing steps of all the plurality of time intervals, the temperature of the channel region and the material below the channel region ranges from 300°C to 450°C.

33. The method of claim 25, wherein the average concentration of elemental form H is reduced by at least 10%.

34. The method of claim 33, wherein the average concentration of elemental form H is reduced by at least two times.

35. The method of claim 34, wherein the average concentration of elemental form H is reduced by at least 10-fold.

36. The method of claim 35, wherein the average concentration of elemental form H is reduced by at least 100 times.

37. The method of claim 36, wherein the average concentration of elemental form H is reduced by at least 200 times.

38. A method of forming an integrated circuit, the integrated circuit comprising: The lower array includes vertical transistors; Each of the lower array vertical transistors includes a top source / drain region of the lower array, a bottom source / drain region of the lower array, a lower array channel region vertically located between the top and bottom source / drain regions of the lower array, and a lower array gate operatively adjacent to the lower array channel region. An upper array of vertical transistors is spaced above the lower array of vertical transistors, each of the lower array vertical transistors including a top source / drain region of the upper array, a bottom source / drain region of the upper array, an upper array channel region vertically located between the top and bottom source / drain regions of the upper array, and an upper array gate operatively adjacent to the upper array channel region. An insulating material is vertically positioned between the lower array and the upper array and spaced apart from each other; the method includes: In the microwave annealing steps at multiple time intervals, at least the upper array channel region is microwave annealed; The microwave annealing steps at multiple time intervals reduce the average concentration of elemental form H in the upper array channel region from its state before the start of the microwave annealing steps at multiple time intervals to 0.005 to less than 1 atomic percentage.

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