ADC Chip Test Circuit, Method, Test Equipment and Storage Medium

Abstract

An embodiment of the present invention discloses an ADC chip test circuit, method, test device, and storage medium. The multi-channel ADC chip test method includes obtaining a plurality of analog test signals after voltage division, inputting the plurality of analog test signals one by one into a plurality of ADC branches of an ADC chip to be detected, collecting the output signals of each ADC branch, and determining whether the ADC chip to be detected is a good product according to the plurality of output signals and a preset first test standard value range. The above solution solves the technical problem of low test efficiency of ADC chips in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of ADC chip testing, and in particular, to an ADC chip testing circuit, method, testing device, and storage medium. Background Art

[0002] An ADC (Analog-to-Digital Convertor) is an extremely crucial component of current electrical signal acquisition systems. With the rapid development of SOC technology and the electricity metering industry in recent years, the performance and quality requirements for ADCs have become increasingly high. ADCs for electricity metering, which can meet the performance requirements of wide voltage, high precision, and high reliability simultaneously, have been widely used in power and energy storage fields such as smart electricity meters, charging piles, and energy controllers.

[0003] How to evaluate the quality of such devices through a fast and effective testing method, achieving both cost savings in testing and meeting the test coverage rate, has become one of the most concerned focuses for ADC manufacturers and producers. For ADC chips, their design and manufacturing costs already account for a large portion. If the testing time cannot be guaranteed to be short enough during chip testing, the total cost will increase significantly. Therefore, in order to improve the reliability of products and considering the testing cost, the current biggest obstacle lies in the lack of an effective fast testing method for multi-channel high-precision ADCs. Summary of the Invention

[0004] The present invention provides an ADC chip testing circuit, method, testing device, and storage medium, which are used to solve the technical problem of low testing efficiency of ADC chips in the prior art.

[0005] To achieve the above object, the present application provides a multi-channel ADC chip testing method, which includes:

[0006] Obtaining a plurality of divided analog test signals;

[0007] Inputting the plurality of analog test signals one by one into a plurality of ADC branches of the ADC chip to be detected;

[0008] Collecting the output signals of each ADC branch;

[0009] Determining whether the ADC chip to be detected is a good product according to the plurality of output signals and a preset first test standard value range.

[0010] Optionally, the step of obtaining a plurality of divided analog test signals includes:

[0011] Obtaining an original test signal;

[0012] Input the original test signal into a voltage division network to obtain multiple analog test signals with equal phases.

[0013] Optionally, the step of determining whether the ADC chip to be detected is a good product according to the multiple output signals and a preset first test standard value range includes:

[0014] Arbitrarily select one of the output signals and determine whether the output signal is within a preset first test standard value range;

[0015] When the current output signal is within the preset first test standard value range, take the ratios of the remaining output signals to the current output signal respectively;

[0016] When the ratio of each output signal to the current output signal satisfies a second test standard value range, determine that the current ADC chip to be detected is a good product.

[0017] Optionally, after the step of arbitrarily selecting one of the output signals and determining whether the output signal is within a preset first test standard value range, the following steps are further included:

[0018] When the current output signal does not meet the preset first test standard value range, determine that the current ADC chip to be detected is a defective product.

[0019] Optionally, after the step of taking the ratios of the remaining output signals to the current output signal respectively when the current output signal is within the preset first test standard value range, the following steps are further included:

[0020] When the ratio of any one of the output signals to the current output signal does not satisfy the second test standard value range, determine that the current ADC chip to be detected is a defective product.

[0021] To achieve the above object, the present application also proposes a storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the ADC chip testing method as described above in the claims.

[0022] To achieve the above object, the present application also proposes an ADC chip testing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The feature is that when the processor executes the computer program, it implements the ADC chip testing method as described above.

[0023] To achieve the above object, the present application further provides an ADC chip test circuit for testing an ADC chip to be tested. The ADC chip to be tested has multiple ADC branches, and each ADC branch has an input end and an output end. The ADC chip test circuit is characterized in that it includes:

[0024] A signal input end for accessing an original test signal;

[0025] A voltage dividing circuit having an input end and multiple output ends. The input end of the voltage dividing circuit is connected to the signal input end, and the multiple output ends of the voltage dividing circuit are connected to the input ends of the ADC branches of multiple ADC chips to be tested one by one;

[0026] The voltage dividing circuit is used to divide the original test signal to obtain multiple analog test signals with equal phases, and input each analog test signal into the corresponding ADC branch to test the ADC branch of the corresponding ADC chip to be tested;

[0027] A control circuit. The control circuit has multiple test ends. The test ends of the control circuit are connected to the output ends of the ADC branches of multiple ADC chips, and are used to obtain the output signal of each ADC branch, and determine whether the ADC chip to be detected is a good product according to each output signal and a preset first test standard value range.

[0028] Optionally, the voltage dividing circuit includes multiple resistor branches connected in parallel. The signal input end includes a positive input end and a negative input end. The resistor branch includes a positive voltage input end, a negative voltage input end, and a test signal output end. The positive voltage input end of the resistor branch is connected to the positive input end, the negative voltage input end of each resistor branch is connected to the negative input end, and the test signal output ends of multiple resistor branches are connected to the input ends of the ADC branches of the ADC chip to be tested.

[0029] Optionally, the resistor branch includes multiple resistors, and a test signal output end is provided between any two resistors. The test signal output ends of each resistor branch are connected to the input ends of the ADC branches of the ADC chip to be tested one by one.

[0030] Optionally, at least one switch module is provided in the resistor branch. The resistor branch further includes a first access end and a second access end. The input end of the switch module is connected to the first access end of the resistor branch, the output end of the switch module is connected to the second access end of the resistor branch, and the controlled end of the switch module is connected to the control circuit.

[0031] Optionally, the switch module is a relay or a switch.

[0032] Optionally, the ADC chip test circuit further includes a signal source generation circuit, and an output end of the signal source generation circuit is the signal input end.

[0033] Optionally, output ends of the plurality of voltage dividing circuits are set as a plurality of test points, and each test point is set corresponding to an input pin of an ADC branch of the ADC chip to be tested.

[0034] To achieve the above object, the present application further provides an ADC chip test device, and the ADC chip test device includes the ADC chip test circuit as described above.

[0035] Implementing the embodiments of the present invention will have the following beneficial effects:

[0036] After adopting the above ADC chip test method, the multi-channel ADC chip test method first obtains a plurality of analog test signals after voltage division, and then inputs the plurality of analog test signals one by one into a plurality of ADC branches of the ADC chip to be detected. Then, output signals of each ADC branch are collected, and it is determined whether the ADC chip to be detected is a good product according to the plurality of output signals and a preset first test standard value range. Since the plurality of analog test signals are voltage-divided at this time, the consistency of the input analog test signals can be ensured. In addition, the plurality of analog test signals can cover the voltage points to be tested by the plurality of ADC branches of the plurality of ADC chips after voltage division. Then, according to the current plurality of output signals and the preset first test standard value range, it can be determined whether the ADC chip to be detected is a good product. Therefore, the technical solution of the present application can reduce the number of tests required for linear testing of each ADC branch, reduce the test time, and thus solve the technical problem of low test efficiency of ADC chips in the prior art. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Among them:

[0039] Figure 1 is a schematic flowchart of a multi-channel ADC chip test method in an embodiment;

[0040] Figure 2 is a schematic flowchart of a multi-channel ADC chip test method in an embodiment;

[0041] Figure 3 Schematic diagram of analog test signals and output signals of corresponding ADC branches during the test of the multi-channel ADC chip test method in one embodiment;

[0042] Figure 4 Circuit schematic diagram of the multi-channel ADC chip test circuit in one embodiment. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] In the exemplary technology, a multi-channel ADC chip generally integrates multiple relatively independent ADC circuits internally. Due to the influence of the discreteness of the semiconductor process itself, there may be deviations in the ADC conversion accuracy fed into each channel. At the same time, during the analog-to-digital conversion process of each channel, the errors introduced by different analog input quantities are different. These non-linear errors directly affect the performance and quality of the ADC product and need to be screened out during the chip test process. The current common test method in the industry is to input different signals into each channel, and then use the amplitude distribution histogram method to test each input voltage point corresponding to each output bit of the ADC once.

[0045] This method, because the signals input into each channel are relatively discrete, there are deviations in the amplitude and phase of the signals; it will cause differences in the outputs of each channel of the ADC. For high-precision ADC chips, due to high quality requirements, such differences are likely to cause the chip specifications to exceed the test standard range and be judged as defective products, thereby reducing the product yield and increasing the cost.

[0046] In addition, within the ADC input voltage range, each voltage interval needs to be tested one by one, which will also lead to too long test time and increased cost.

[0047] In one embodiment, as Figure 1 shown, a multi-channel ADC chip test method, the multi-channel ADC chip test method includes;

[0048] S1. Obtain a plurality of analog test signals after voltage division;

[0049] Among them, multiple analog test signals after voltage division can be achieved through a single-channel original test signal input, and then the single-channel signal is input into a voltage division network for voltage division. By obtaining multiple analog test signals after voltage division, it is possible to eliminate the deviation caused by different input signal sources in multi-channel ADC tests, resulting in different ADC channel outputs, thereby reducing the misjudgment and misplacement in testing.

[0050] S2. Input the multiple analog test signals one by one into multiple ADC branches of the ADC chip to be detected;

[0051] Among them, a single analog test signal is only input into one ADC branch, so as to ensure the singularity of the analog test signal input into each ADC branch. It should be noted that at this time, the ADC branches of the ADC chip are the ADC channels of the ADC chip.

[0052] S3. Collect the output signals of each ADC branch;

[0053] At this time, the output signals of each ADC branch can be separately collected through a control circuit, a test circuit, a sampling circuit, etc.

[0054] S4. Determine whether the ADC chip to be detected is a good product according to the multiple output signals and a preset first test standard value range.

[0055] In the above embodiment, by using a single original test signal input for voltage division through a resistor network, since multiple analog test signals are voltage-divided at this time, the consistency of the input analog test signals can be ensured. In addition, multiple analog test signals after voltage division can cover the voltage points to be tested of multiple ADC branches of multiple ADC chips, and then according to the current multiple output signals and a preset first test standard value range, it can be determined whether the ADC chip to be detected is a good product. Therefore, the technical solution of the present application can reduce the number of tests required for linear testing of each ADC branch, reduce the testing time, and thus solve the technical problem of low testing efficiency of ADC chips in the prior art.

[0056] In one embodiment, the step of obtaining multiple analog test signals after voltage division includes:

[0057] Obtain an original test signal;

[0058] The original test signal at this time can be sent by a tester, a waveform generator or a signal source.

[0059] Input the original test signal into a voltage division network to obtain multiple analog test signals with equal phases.

[0060] In the above solution, using a single original test signal to input a voltage division network and perform voltage division through the voltage division network can ensure the consistency of the input signal. In addition, according to the voltage division characteristics of the resistors, the sizes of the resistors can be adjusted to adjust the input voltage amplitudes of different ADC branches / channels to cover the ADC input voltage range; in this way of multi-point coverage, the test time cost can be greatly reduced. Additionally, through multi-channel voltage division and adjusting the input voltage amplitudes of different channels so that the voltage amplitude of the analog test signal covers multiple voltage points simultaneously, the number of ADC channel linearity tests can be reduced by covering multiple voltage points simultaneously, thereby reducing the test time.

[0061] As Figure 3 shown, the ADC input voltage range is 0 - Vref (Vref is the ADC reference voltage), and this method can test n voltage points at one time (n is the number of channels of the multi-channel ADC to be tested).

[0062] In one embodiment, as Figure 2 shown, the step of determining whether the ADC chip to be detected is a good product according to the multiple output signals and a preset first test standard value range includes:

[0063] S41. Arbitrarily select one of the output signals and determine whether the output signal is within the preset first test standard value range;

[0064] The following takes the voltage division network as a resistor voltage division network as an example to illustrate the principle of this solution. Taking the Figure 1 shown resistor voltage division network as an example, the resistor voltage division network generally consists of multiple groups of resistor voltage division circuits. The test machine AWG module or signal source generates an analog signal, which is connected to the test system through the Vin+ and Vin- two ports; after passing through each resistor voltage division circuit, it is finally converted into electrical signals with equal phases and different amplitudes and output to the input ends of each ADC; for any one of the ADCs, the input voltage value satisfies:

[0065]

[0066] (n represents the corresponding number of the probability ADC branch / channel)

[0067] And for the output of this ADC branch:

[0068]

[0069] Among them: m is the number of bits of the ADC; VIN is the effective value of the input signal; Vref is the ADC reference voltage;

[0070] When targeting the output of this ADC path, since the input voltage value of the current ADC branch is fixed, therefore, by comparing the theoretical output range (standard range) calculated through the ADC conversion formula with the actual output value of the ADC branch, the theoretical output range (standard range) at this time is the preset first test standard value range, which can be preset after calculation through the above formula. If they match after comparison, it is determined that the output signal actually output by the ADC branch is within the preset first test standard value range, that is, the output signal of the current ADC branch / channel is qualified, and whether the deviation between channels meets the standard.

[0071] S42. When the current output signal is within the preset first test standard value range, take the ratio of the remaining output signals to the current output signal respectively;

[0072] Since the resistor voltage division circuits of each path are relatively discrete, by combining the resistor values of the voltage division circuits of each ADC channel, multiple voltage points within the ADC input range can be covered simultaneously, achieving the purpose of rapid testing;

[0073] For any two ADCs: that is

[0074] The outputs of the a ADC branch and the b ADC branch are as follows:

[0075]

[0076] Taking the ratio of the remaining output signals to the current output signal respectively, since in the previous step, any one of the output signals was randomly selected as the current output signal, therefore, this kind of ratio-taking can be applied to any two output signals.

[0077] S43. When the ratio of each output signal to the current output signal all meets the second test standard value range, determine that the current ADC chip to be detected is a good product.

[0078] In the above embodiment, first, according to the output signal of any one ADC branch / channel of the ADC chip, it is judged whether the current ADC branch / channel is qualified; then, through the proportional relationship between the output signals of each ADC branch / channel and the corresponding voltage division values, that is

[0079]

[0080] According to whether the ratio is within the second test standard value range, it can be determined whether the deviation between the two channels exceeds the standard; since the resistance values Ra-1, Ra-2, Ra-3, Rb-1, Rb-2, and Rb-3 are all known, only the ratio Ka_b of the output data of a and b needs to be measured. At this time, the data ratio Ka_b is controlled within the second test standard value range, that is, by controlling the data ratio Ka_b within a range, samples with excessive channel deviation can be screened out. The second test standard value range at this time is preset by the user in advance, and can be set to the value predicted according to experimental data, or the deviation standard value range obtained by the user through other means.

[0081] In an embodiment, after the step of arbitrarily selecting one of the output signals and determining whether the output signal is within a preset first test standard value range, the following steps are further included:

[0082] When the current output signal does not meet the preset first test standard value range, it is determined that the current ADC chip to be detected is a defective product.

[0083] When targeting the output signal of this ADC, since the input voltage value of the current ADC branch is fixed, therefore, the theoretical output range (standard range) calculated by the ADC conversion formula is compared with the actual output value of the ADC branch. The theoretical output range (standard range) at this time is the preset first test standard value range. If they do not match after comparison, it is determined that the output signal of the actual output of the ADC branch is not within the preset first test standard value range, that is, the output signal of the current ADC branch / channel is unqualified, and the channel deviation does not meet the standard.

[0084] In an embodiment, after the step of taking the ratio of the remaining output signals to the current output signal when the current output signal is within the preset first test standard value range, the following steps are further included:

[0085] When the ratio of any one of the output signals to the current output signal does not meet the second test standard value range, it is determined that the current ADC chip to be detected is a defective product.

[0086] Among them, whether the ratio of one output signal to the current output signal does not meet the second test standard value range, it is determined that the current ADC chip to be detected is a defective product. Thus, the process of each measurement modeling is converted into a process of judgment by ratio. At this time, only one channel needs to be measured once, which greatly shortens the detection time, and there is no need to measure and confirm each ADC branch / channel by means of an amplitude distribution histogram. Moreover, ensuring the coverage of each voltage point can achieve accurate detection of the ADC chip, which can facilitate the confirmation of each voltage point to be tested and is more convenient for industrial unified standard measurement.

[0087] The present application also provides a storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the ADC chip testing method as described above.

[0088] It should be noted that since the storage medium of the present application includes all the steps of the above ADC chip testing method, the storage medium can also implement all the solutions of the ADC chip testing method and has the same beneficial effects, which will not be elaborated here.

[0089] The present application also provides an ADC chip testing device, including a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the computer program, it implements the ADC chip testing method as described above.

[0090] It should be noted that since the ADC chip testing device of the present application includes all the steps of the above ADC chip testing method, the ADC chip testing device can also implement all the solutions of the ADC chip testing method and has the same beneficial effects, which will not be elaborated here.

[0091] The present application also provides an ADC chip testing circuit, as Figure 4 shown, for testing an ADC chip to be tested. The ADC chip to be tested U1 has a plurality of ADC branches, and each ADC branch has an input end and an output end. The ADC chip testing circuit includes a signal input end, a voltage dividing circuit 20, and a control circuit 10. The signal voltage dividing circuit 20 has an input end and a plurality of output ends. The input end of the voltage dividing circuit 20 is connected to the signal input end, and the plurality of output ends of the voltage dividing circuit 20 are connected to the input ends of the ADC branches of the plurality of ADC chips U1 to be tested one by one. The control circuit 10 has a plurality of test ends, and the test ends of the plurality of control circuits 10 are connected to the output ends of the ADC branches of the plurality of ADC chips.

[0092] Among them, the original test signal is input through the signal input end. The voltage dividing circuit 20 divides the original test signal to obtain a plurality of analog test signals with equal phases, and inputs each analog test signal into the corresponding ADC branch to test the ADC branch of the corresponding ADC chip U1 to be tested. The control circuit 10 obtains the output signal of each ADC branch and determines whether the ADC chip to be detected is a good product according to each output signal and a preset first test standard value range. In the above embodiment, by using a single original test signal to be divided by the voltage dividing circuit 20, since a plurality of analog test signals are divided at this time, the consistency of the input analog test signals can be ensured.

[0093] In addition, if the voltage division value of the voltage division circuit is debugged, the output signals of multiple analog test signals after voltage division can cover the voltage points to be tested of multiple ADC branches of multiple ADC chips. Then, according to the current multiple output signals and the preset first test standard value range, it can be determined whether the ADC chip to be detected is a good product. Therefore, the technical solution of the present application can reduce the number of tests required for linear testing of each ADC branch, reduce the testing time, and thus solve the technical problem of low testing efficiency of ADC chips in the prior art.

[0094] Further, the control circuit 10 is further configured to determine that the ADC chip to be detected is a good product according to whether the ratio of any two output signals satisfies the second test standard value range.

[0095] In the above embodiment, first, according to the output signal of any one ADC branch / channel of the ADC chip, it is determined whether the current ADC branch / channel is qualified; then, through the proportional relationship between the output signals of each ADC branch / channel and the corresponding voltage division values, that is

[0096]

[0097] According to whether the ratio falls within the second test standard value range, it can be accurately determined whether the deviation between channels exceeds the standard; since the resistance values Ra-1, Ra-2, Ra-3, Rb-1, Rb-2, Rb-3 are all known, only the ratio Ka_b of the output data of a and b needs to be measured. At this time, the data ratio Ka_b is controlled within the second test standard value range, that is, by controlling the data ratio Ka_b within a range, samples with excessive inter-channel deviation can be screened out.

[0098] In one embodiment, the voltage division circuit 20 includes a plurality of resistor branches 201 arranged in parallel. The signal input end includes a positive input end Vin+ and a negative input end Vin-. The resistor branch 201 includes a positive voltage input end, a negative voltage input end, and a test signal output end. The positive voltage input end of the resistor branch 201 is connected to the positive input end Vin+, the negative voltage input end of each resistor branch 201 is connected to the negative input end Vin-, and the test signal output ends of the plurality of resistor branches are connected to the input end of the ADC branch of the ADC chip U1 to be tested.

[0099] At this time, through the above connection method, the effective output of the test signal output end of the resistor branch 201 can be realized. Moreover, since the calculation of the resistor branch 201 is simple, when changing the divided voltage amplitude, only the resistance value needs to be changed to change the amplitudes of multiple analog test signals, so as to cover multiple voltage points simultaneously, reduce the number of linearity tests of the ADC branch / channel, and thus reduce the test time.

[0100] In one embodiment, the resistor branch 201 includes a plurality of resistors, and a test signal output end is arranged between any two resistors. The test signal output ends of each resistor branch are connected to the input ends of the ADC branches of the ADC chip U1 to be tested one by one.

[0101] In the above solution, using a single original test signal input to be divided by the signal voltage division circuit 20 can ensure the consistency of the input signal. In addition, according to the voltage division characteristics of the resistor, the size of the resistor can be adjusted to adjust the input voltage amplitudes of different ADC branches / channels to cover the ADC input voltage range. Such a multi-point coverage method can greatly reduce the test time cost. In addition, through multi-channel voltage division and adjusting the input voltage amplitudes of different channels so that the voltage amplitudes of the analog test signals cover multiple voltage points simultaneously, the number of linearity tests of the ADC channels can be reduced by covering multiple voltage points simultaneously, thereby reducing the test time.

[0102] In one embodiment, at least one switch module is arranged in the resistor branch 201. The resistor branch 201 further includes a first access end and a second access end. The input end of the switch module is connected to the first access end of the resistor branch 201, the output end of the switch module is connected to the second access end of the resistor branch 201, and the controlled end of the switch module is connected to the control circuit 10.

[0103] At this time, the resistor branch 201 can be set to a multi-group mode. By controlling the output end of the resistor branch 201 with a switch, the voltage division of the resistor branch 201 can be adjusted by switching the resistor branch 201.

[0104] Optionally, the switch module is a relay or a switch.

[0105] In one embodiment, the ADC chip test circuit further includes a signal source generation circuit, and the output end of the signal source generation circuit is the signal input end.

[0106] By generating a signal through the signal source generation circuit, the original test signal can be adjusted as needed. Among them, the signal source generation circuit can be a test machine or a signal generation circuit or an off-the-shelf signal source.

[0107] In one embodiment, the output ends of the plurality of voltage dividing circuits 20 are set as a plurality of test points, and each test point is set corresponding to the input pin of the ADC branch of the ADC chip U1 to be tested.

[0108] By setting the test points, the connection between the ADC chip U1 to be tested and the ADC chip test circuit during testing can be facilitated, thereby reducing the test preparation time.

[0109] In one embodiment, as Figure 4 shown, each of the ADC branches includes a first positive voltage input end and a first negative voltage input end, and each of the resistor branches 201 includes a positive test signal output end and a negative test signal output end. The first positive voltage input end of the ADC branch is connected to the positive test signal output end of the corresponding resistor branch 201, and the first negative voltage input end of the ADC branch is connected to the negative test signal output end of the corresponding resistor branch 201.

[0110] At this time, through the above connection method, the effective output of the test signal output end of the resistor branch 201 can be realized. Moreover, since the calculation of the resistor branch 201 is simple, only one analog test signal is output by one branch at this time, and the calculation is simple. When changing the divided voltage amplitude, only the resistance value needs to be changed to realize the change of the amplitudes of multiple analog test signals, so as to cover multiple voltage points at the same time. The number of linearity tests of the ADC branch / channel is reduced, thereby reducing the test time.

[0111] The present application also proposes an ADC chip test device, and the ADC chip test device includes the ADC chip test circuit as described above.

[0112] It should be noted that since the ADC chip test device of the present application includes all the steps of the above ADC chip test circuit, therefore, the ADC chip test device can also implement all the solutions of the ADC chip test circuit and has the same beneficial effects, which will not be elaborated here.

[0113] The above-disclosed are only the preferred embodiments of the present invention. Of course, the scope of the rights of the present invention cannot be limited thereby. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope covered by the present invention.

Claims

1. A method for testing a multi-channel ADC chip, characterized in that, The method for testing the multi-channel ADC chip includes; Obtain a plurality of analog test signals that have been voltage-divided; Input the plurality of analog test signals one by one into a plurality of ADC branches of the ADC chip to be detected; Collect the output signals of each ADC branch; Determine whether the ADC chip to be detected is a good product according to the plurality of output signals and a preset first test standard value range; The step of determining whether the ADC chip to be detected is a good product according to the plurality of output signals and a preset first test standard value range includes: Arbitrarily select one of the output signals and determine whether the output signal is within a preset first test standard value range; When the current output signal is within the preset first test standard value range, take the ratios of the remaining output signals to the current output signal respectively; When the ratio of each output signal to the current output signal satisfies the second test standard value range, determine that the current ADC chip to be detected is a good product.

2. The method for testing a multi-channel ADC chip according to claim 1, characterized in that, The step of obtaining a plurality of analog test signals that have been voltage-divided includes: Obtain an original test signal; Input the original test signal into a voltage-dividing network to obtain a plurality of analog test signals with equal phases.

3. The method for testing a multi-channel ADC chip according to claim 1, characterized in that, After the step of arbitrarily selecting one of the output signals and determining whether the output signal is within a preset first test standard value range, the following is further included: When the current output signal does not meet the preset first test standard value range, determine that the current ADC chip to be detected is a defective product.

4. The method for testing a multi-channel ADC chip according to claim 1, characterized in that, After the step of, when the current output signal is within the preset first test standard value range, taking the ratios of the remaining output signals to the current output signal respectively, the following is further included: When the ratio of any one of the output signals to the current output signal does not meet the second test standard value range, determine that the current ADC chip to be detected is a defective product.

5. A storage medium, characterized in that, The storage medium stores a computer program, and when the computer program is executed by a processor, it implements the ADC chip testing method according to any one of claims 1 to 4.

6. An ADC chip testing device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The feature is that when the processor executes the computer program, it implements the ADC chip testing method according to any one of claims 1 to 4.

7. An ADC chip testing circuit for testing a to-be-tested ADC chip, the to-be-tested ADC chip having a plurality of ADC branches, each of the ADC branches having an input end and an output end, characterized in that, The ADC chip testing circuit includes: A signal input terminal for accessing an original test signal; A voltage-dividing circuit having an input terminal and a plurality of output terminals. The input terminal of the voltage-dividing circuit is connected to the signal input terminal, and the plurality of output terminals of the voltage-dividing circuit are connected one by one to the input terminals of the ADC branches of a plurality of ADC chips to be tested; The voltage-dividing circuit is used to voltage-divide the original test signal to obtain a plurality of analog test signals with equal phases, and input each analog test signal into the corresponding ADC branch to test the ADC branch of the corresponding ADC chip to be tested; A control circuit, the control circuit having a plurality of test terminals, the test terminals of the plurality of control circuits being connected to the output terminals of the ADC branches of the plurality of ADC chips, and being configured to acquire the output signal of each ADC branch, and determine whether the ADC chip to be tested is a good product according to each output signal and a preset first test standard value range; wherein, the step of determining whether the ADC chip to be tested is a good product according to each output signal and the preset first test standard value range includes: Arbitrarily select one of the output signals, and determine whether the output signal is within a preset first test standard value range; When the current output signal is within the preset first test standard value range, take the ratio of the remaining output signals of the current ADC chip to be tested to the current output signal respectively; When the ratio of each output signal to the current output signal satisfies the second test standard value range, determine that the current ADC chip to be tested is a good product.

8. The ADC chip testing circuit according to claim 7, characterized in that, The voltage dividing circuit includes a plurality of resistor branches arranged in parallel, the signal input terminal includes a positive input terminal and a negative input terminal, the resistor branch includes a positive voltage input terminal, a negative voltage input terminal and a test signal output terminal, the positive voltage input terminal of the resistor branch is connected to the positive input terminal, the negative voltage input terminal of each resistor branch is connected to the negative input terminal, and the test signal output terminals of the plurality of resistor branches are connected to the input terminal of the ADC branch of the ADC chip to be tested.

9. The ADC chip testing circuit according to claim 8, characterized in that, At least one switch module is provided in the resistor branch, the resistor branch further includes a first access terminal and a second access terminal, the input terminal of the switch module is connected to the first access terminal of the resistor branch, the output terminal of the switch module is connected to the second access terminal of the resistor branch, and the controlled terminal of the switch module is connected to the control circuit.

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