Partial immersion cooling of data center cooling systems

Abstract

Local immersion cooling of data center cooling systems is disclosed, specifically systems and methods for cooling data centers are disclosed. In at least one embodiment, a cold plate has an opening and a cavity such that the cold plate can be hermetically sealed around at least one computing component at the cavity and such that the cold plate can include a fluid to immerse at least a portion of the at least one computing component.

Description

Technical Field

[0001] At least one embodiment relates to a cooling system, including systems and methods for operating those cooling systems. In at least one embodiment, such a cooling system can be used in a data center containing one or more racks or computing servers. Background Technology

[0002] Data center cooling systems use fans to circulate air within server components. Some supercomputers or other high-capacity computers may use water or other cooling systems instead of air cooling systems to draw heat from the server components or racks within the data center to areas outside the data center. Cooling systems can include coolers within the data center area, which may extend to areas outside the data center itself. Additionally, areas outside the data center may include cooling towers or other external heat exchangers that receive heated coolant from the data center and dissipate the heat into the environment (or external cooling medium) through forced air or other means. The cooled coolant is then recirculated back into the data center. Coolers and cooling towers together constitute a cooling facility. Attached Figure Description

[0003] Figure 1 An exemplary data center cooling system subjected to the improvements described in at least one embodiment is shown;

[0004] Figure 2 Server-level features associated with localized immersion cooling of a data center cooling system according to at least one embodiment are illustrated;

[0005] Figure 3 Rack-level features associated with localized immersion cooling of a data center cooling system according to at least one embodiment are shown;

[0006] Figure 4 Data center-level features associated with localized immersion cooling of a data center cooling system according to at least one embodiment are illustrated;

[0007] Figure 5 The diagram illustrates a relationship according to at least one embodiment. Figures 2-4 Methods associated with data center cooling systems;

[0008] Figure 6 A distributed system according to at least one embodiment is shown;

[0009] Figure 7 An exemplary data center according to at least one embodiment is shown;

[0010] Figure 8 A client-server network according to at least one embodiment is shown;

[0011] Figure 9 A computer network is shown in accordance with at least one embodiment;

[0012] Figure 10A A networked computer system is shown in accordance with at least one embodiment;

[0013] Figure 10B A networked computer system is shown in accordance with at least one embodiment;

[0014] Figure 10C A networked computer system is shown in accordance with at least one embodiment;

[0015] Figure 11 One or more components of a system environment in which services can be offered as third party network services are shown in accordance with at least one embodiment;

[0016] Figure 12 A cloud computing environment is shown in accordance with at least one embodiment;

[0017] Figure 13 A set of functional abstraction layers offered by a cloud computing environment is shown in accordance with at least one embodiment;

[0018] Figure 14 A supercomputer at the chip level is shown in accordance with at least one embodiment;

[0019] Figure 15 A supercomputer at the rack module level is shown in accordance with at least one embodiment;

[0020] Figure 16 A supercomputer at the rack level is shown in accordance with at least one embodiment;

[0021] Figure 17 A supercomputer at the entire system level is shown in accordance with at least one embodiment;

[0022] Figure 18A Inference and / or training logic is shown in accordance with at least one embodiment;

[0023] Figure 18B Inference and / or training logic is shown in accordance with at least one embodiment;

[0024] Figure 19 Training and deployment of a neural network is shown in accordance with at least one embodiment;

[0025] Figure 20 An architecture of a network system is shown in accordance with at least one embodiment;

[0026] Figure 21 An architecture of a network system is shown in accordance with at least one embodiment;

[0027] Figure 22 A control plane protocol stack is shown, in accordance with at least one embodiment;

[0028] Figure 23 A user plane protocol stack is shown, in accordance with at least one embodiment;

[0029] Figure 24 Components of a core network are shown, in accordance with at least one embodiment;

[0030] Figure 25 Components of a system that supports network function virtualization (NFV) are shown, in accordance with at least one embodiment;

[0031] Figure 26 A processing system is shown, in accordance with at least one embodiment;

[0032] Figure 27 A computer system is shown, in accordance with at least one embodiment;

[0033] Figure 28 A system is shown, in accordance with at least one embodiment;

[0034] Figure 29 An exemplary integrated circuit is shown, in accordance with at least one embodiment;

[0035] Figure 30 A computing system is shown, in accordance with at least one embodiment;

[0036] Figure 31 An APU is shown, in accordance with at least one embodiment;

[0037] Figure 32 A CPU is shown, in accordance with at least one embodiment;

[0038] Figure 33 An exemplary accelerator integration slice is shown, in accordance with at least one embodiment;

[0039] Figures 34A-34B An exemplary graphics processor is shown, in accordance with at least one embodiment;

[0040] Figure 35A A graphics core is shown, in accordance with at least one embodiment;

[0041] Figure 35B A GPGPU is shown, in accordance with at least one embodiment;

[0042] Figure 36A A parallel processor is shown, in accordance with at least one embodiment;

[0043] Figure 36B A processing cluster is shown, in accordance with at least one embodiment;

[0044] Figure 36C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0045] Figure 37 A software stack of a programming platform is shown in accordance with at least one embodiment;

[0046] Figure 38 A CUDA implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0047] Figure 39 A ROCm implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0048] Figure 40 An OpenCL implementation of the software stack of Figure 37 is shown in accordance with at least one embodiment;

[0049] Figure 41 Software supported by a programming platform is shown in accordance with at least one embodiment; and

[0050] Figure 42 Compiled code for execution on a programming platform of Figures 37-40 is shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0051] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0052] In at least one embodiment, a data center cooling system can respond to sudden high heat requirements caused by changes in computing load in today’s computing components. In at least one embodiment, since these requirements vary or tend to range from minimum to maximum different cooling requirements, appropriate cooling systems must be used to meet these requirements in an economical way. In at least one embodiment, for medium to high cooling requirements, a liquid cooling system can be used.

[0053] In at least one embodiment, high cooling requirements are economically met by local immersion cooling. In at least one embodiment, these different cooling requirements also reflect different thermal signatures of a data center. In at least one embodiment, heat generated from these components, servers, and racks is collectively referred to as a thermal signature or cooling requirement, since the cooling requirement must fully address the thermal signature.

[0054] In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses thermal features in associated computing or data center equipment, such as a graphics processing unit (GPU), a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). In at least one embodiment, these components can be referred to herein as high heat density computing components. Further, in at least one embodiment, the associated computing or data center equipment can be a processing card with one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPUs, switches, and CPUs can be heat generating features of a computing device. In at least one embodiment, a GPU, CPU, or switch can have one or more cores, and each core can be a heat generating feature.

[0055] In at least one embodiment, reliably removing heat from high heat density computing components can not be economically addressed by liquid cooling or whole server level immersion cooling. In at least one embodiment, server level immersion cooling can have special requirements of a rack and its requirements can be complex, but can also not yield an economic cooling as a solution. In at least one embodiment, in a single cold plate design, the benefits herein are realized from both liquid cooling and local immersion cooling.

[0056] In at least one embodiment, a direct contact cold plate can be provided with a cavity and an opening. In at least one embodiment, the cavity can be adapted to include (or be filled with) a fluid, such as an immersion fluid. In at least one embodiment, the immersion fluid has been designed and manufactured and has dielectric properties. In at least one embodiment, the engineering properties are such that the fluid is not naturally occurring, but rather developed to support immersion cooling. In at least one embodiment, the fluid is a dielectric engineered fluid that is different than a coolant or refrigerant. In at least one embodiment, the fluid is an oil or other dielectric fluid. In at least one embodiment, the immersion fluid, simply referred to as fluid, has properties that allow it to be in direct contact with electronic devices of a computing component. In at least one embodiment, direct contact refers to the immersion fluid or liquid being in direct contact with electronic components that are heat generating parts. In at least one embodiment, the fluid has cooling capabilities to remove a high percentage of heat generated from heat generating parts in a data center server.

[0057] In at least one embodiment, the fluid can be introduced through at least one self-sealing port when the sealed cold plate is assembled to the component (or around the component). In at least one embodiment, the at least one self-sealing port enables local submersion cooling of the high heat density component by at least maintaining the fluid within the cavity of the cold plate. In at least one embodiment, the fluid can be provided by a fluid source that can be cooled using an air-cooled condenser or a liquid-cooled heat exchanger interfaced with the fluid source. In at least one embodiment, a heat exchanger can be provided within the cold plate. In at least one embodiment, the heat exchanger has a coolant or refrigerant from an auxiliary cooling loop or from a refrigerant loop passing therethrough. In at least one embodiment, the coolant can be from a coolant distribution unit (CDU) and the refrigerant can be from a refrigeration unit.

[0058] In at least one embodiment, local submersion cooling is achieved through direct contact enabled by the submersion cold plate between the fluid provided in the cavity of the cold plate and directly contacting at least a portion of the computing component hermetically sealed within the cold plate. In at least one embodiment, the fluid can be circulated after a determined period of time. In at least one embodiment, the fluid can be cooled by a heat exchanger within the cavity that allows a coolant or refrigerant to pass through the fluid to cool the fluid. In at least one embodiment, the submersion cold plate allows the fluid therein to be in direct contact with the electronic component. In at least one embodiment, a region between the opening of the cold plate (and thus, the cold plate) and the component or around the component at the cavity opening is provided hermetically sealed.

[0059] In at least one embodiment, as described above, a submersion cold plate can be utilized as Figure 1An exemplary data center 100 is shown, having a cooling system subject to improvements described herein. In at least one embodiment, the data center 100 can be one or more rooms 102 having racks 110 and ancillary equipment for housing one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside of the data center 100. In at least one embodiment, the cooling tower 104 dissipates heat from within the data center 100 by acting on a primary cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling loop 106 and a secondary or auxiliary cooling loop 108 to enable heat to be extracted from the secondary or auxiliary cooling loop 108 to the primary cooling loop 106. In at least one embodiment, the auxiliary cooling loop 108 can access different pipes into the server trays as needed throughout, in one aspect. In at least one embodiment, the loops 106, 108 are shown as line diagrams, but one of ordinary skill will recognize that one or more pipe features can be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with associated piping to move fluid along each of the loops 106, 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the loops 106, 108 to enable the coolant to move according to temperature sensors in different locations, including in the room, in one or more racks 110, and / or in server cabinets or server trays within the racks 110.

[0060] In at least one embodiment, the coolant in the primary cooling loop 106 and the auxiliary cooling loop 108 can be at least water and an additive, such as ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling loop and the auxiliary cooling loop has its own coolant. In at least one embodiment, the coolant in the auxiliary cooling loop can be dedicated to the requirements of the components in the server trays or racks 110. In at least one embodiment, the CDU 112 is capable of complex control of the coolant in the loops 106, 108 independently or simultaneously. In at least one embodiment, the CDU can be adapted to control flow rates so that the coolant is properly distributed to draw heat generated within the racks 110. In at least one embodiment, more flexible tubing 114 is provided from the auxiliary cooling loop 108 to enter each server tray and provide coolant to electrical and / or computing components.

[0061] In at least one embodiment, electrical and / or computing components are used interchangeably to refer to heat-generating components that benefit from a data center cooling system with partial submersion cooling. In at least one embodiment, tubing 118 forming part of secondary cooling loop 108 can be referred to as a room manifold. Separately, in at least one embodiment, tubing 116 extending from tubing 118 can also be part of secondary cooling loop 108, but can be referred to as a row manifold. In at least one embodiment, tubing 114 enters a rack as part of secondary cooling loop 108, but can be referred to as a rack cooling manifold. In at least one embodiment, row manifold 116 extends along a row in data center 100 to all racks. In at least one embodiment, plumbing of secondary cooling loop 108 including manifolds 118, 116, and 114 can be improved by at least one embodiment herein. In at least one embodiment, chiller 120 can be provided in a primary cooling loop within data center 102 to support cooling prior to a cooling tower. In at least one embodiment, to the extent that additional loops exist in a primary control loop, one of ordinary skill in the art, upon reading at least one embodiment herein, will recognize that these additional loops provide cooling outside of a rack and outside of a secondary cooling loop; and can be incorporated with a primary cooling loop for the present invention.

[0062] In at least one embodiment, in operation, heat generated within a server tray of rack 110 can be transferred via flexible tubing of row manifold 114 of secondary cooling loop 108 to coolant exiting rack 110. In at least one embodiment, second coolant from CDU 112 for cooling rack 110 (in secondary cooling loop 108) moves toward rack 110. In at least one embodiment, second coolant from CDU 112 is transferred from one side of room manifold having tubing 118 via row manifold 116 to one side of rack 110 and via tubing 114 through one side of a server tray. In at least one embodiment, used or returning second coolant (or exiting second coolant taking heat away from computing components) exits from another side of a server tray (such as entering a left side of a rack for a server tray after circulating through the server tray or through components on the server tray and exiting a right side of the rack). In at least one embodiment, used secondary coolant exiting a server tray or rack 110 comes out from a different side (such as an outlet side) of tubing 114 and moves to a parallel also outlet side of row manifold 116. In at least one embodiment, used second coolant moves from row manifold 116 in a parallel portion of row manifold 118, travels in an opposite direction from incoming second coolant (which can also be newer secondary coolant), and toward CDU 112.

[0063] In at least one embodiment, the used auxiliary coolant exchanges its heat with the main coolant in the main cooling circuit 106 via CDU 112. In at least one embodiment, the used auxiliary coolant can be refreshed (e.g., when relatively cooled compared to the temperature of the used auxiliary coolant stage) and prepared for recirculation through the auxiliary cooling circuit 108 to the computing unit. In at least one embodiment, various flow and temperature control features in CDU 112 enable control of the heat exchange from the used auxiliary coolant or the inflow and outflow of auxiliary coolant from CDU 112. CDU 112 may also be able to control the flow of the main coolant in the main cooling circuit 106.

[0064] In at least one embodiment, such as Figure 2 The server-level feature 200 shown can be associated with a local immersion cooling system of a data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or enclosure 202. In at least one embodiment, the server tray or enclosure 202 includes one or more coolant or refrigerant cold plates 210A-C and one or more immersion fluid cold plates 250, 270, each associated with one or more computing or data center components or devices 220A-D. In at least one embodiment, the server tray or enclosure 202 includes a server manifold 204, which is intermediately coupled between the cold plates 210A-C of the auxiliary cooling loop and the rack manifold.

[0065] In at least one embodiment, the server manifold distributes auxiliary coolant or refrigerant to the cold plates. In at least one embodiment, a rack manifold is mounted on a rack that may also house server trays or cases 202. In at least one embodiment, the server manifold 204 may also act as an intermediary between the immersion fluid source and the immersion cooling plates 250, 270. In at least one embodiment, channels within the server manifold 204 isolate the immersion fluid from the auxiliary coolant or refrigerant. In at least one embodiment, this isolation allows the same server manifold 204 to also distribute immersion fluid to the immersion cold plates 250, 270. In at least one embodiment, the server tray or case 202 includes multiple server manifolds. In at least one embodiment, at least one server manifold is used for immersion fluid and at least one other server manifold is used for coolant or refrigerant.

[0066] In at least one embodiment, one or more server level cooling loops 214A, B are provided between server manifold 204 and cold plates 210A-C; 250, 270. In at least one embodiment, server level cooling loops 214A, B are part of secondary cooling loops. In at least one embodiment, each server level cooling loop 214A; B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when there are cold plates 210A, B in a series configuration, then an intermediate line 216 can be provided. In at least one embodiment, one or more cold plates can be immersion cold plates, such as immersion cold plates 250, 270. In at least one embodiment, a fluid for immersion cold plates, different from secondary coolant, can be provided via a passageway of server manifold 204, via inlet and outlet 208A, 208B and line 292. In at least one embodiment, line 292 isolates immersion fluid from secondary coolant that can pass through its respective passageway within server manifold 204, and from different inlet and outlet 206A, 206B.

[0067] In at least one embodiment, immersion cold plates 250, 270 have two parts. In at least one embodiment, first part 250 includes a cavity 264 to hold fluid, while second part 270 enables an air-tight seal with first part 250 so that fluid is retained within the cold plate. In at least one embodiment, first part 250 is shown in an enlarged manner relative to receiver plate 270, but the receiver plate is installed and thus has a corresponding scaling to enable installation. In at least one embodiment, unless otherwise specified, reference to a cold plate in connection with its immersion features means reference to an immersion cold plate. In at least one embodiment, cold plate 210B, 250 can be configured to work alongside secondary coolant cold plates 210A-C. In at least one embodiment, secondary coolant cold plates 210A-C allow at least secondary coolant to pass through, even with illustrative similarities to receiver plate 270. In at least one embodiment, different from secondary coolant cold plates 210A-C, receiver plate 270 is an open structure to which a first part 250 of a cold plate is attached and forms an air-tight seal.

[0068] In at least one embodiment, two types of cold plates, whether auxiliary coolant cold plates 210A-C or immersion cold plates 250, 270, receive at least auxiliary coolant. In at least one embodiment, auxiliary coolant cold plates 210A-C receive auxiliary coolant for cooling associated computing devices 220A-C. In at least one embodiment, immersion cold plates 250, 270 receive auxiliary coolant to cool immersion fluid therein. In at least one embodiment, each type of cold plate 210A-C; 250, 270 receives a different auxiliary coolant or refrigerant from a respective auxiliary cooling loop with coolant or refrigerant. In at least one embodiment, immersion cold plates 250, 270 are adapted to receive two types of fluid. In at least one embodiment, a first type of fluid is an immersion fluid, such as a dielectric engineering fluid, while a second type of fluid is auxiliary coolant from an auxiliary cooling loop that also passes through auxiliary coolant cold plates 210A-C, such as facility water and additives or refrigerant. In at least one embodiment, auxiliary coolant can be deionized water.

[0069] In at least one embodiment, component 250 including cavity 264 for a cold plate can be referred to as a cold plate body. In at least one embodiment, cold plate body 250 can be press fit around at least one computing component 220D with a receiver seal applied directly to an area of the plate surrounding at least one computing component 220B or directly on at least a portion of at least one computing component 220D. In at least one embodiment, receiver plate 270 can be a separate part in that area or on at least one computing component and include or be entirely one or more latches or other features that allow a receiver seal of cold plate body 250 to be hermetically sealed into that area. In at least one embodiment, unless otherwise specified, reference to a cold plate or cold plate body is used interchangeably herein with respect to an immersion cold plate. In at least one embodiment, gasket or seal 272 is a receiver seal that is disposed directly on an area surrounding at least one computing component (or on at least a portion of a computing component). In at least one embodiment, receiver seal 272 can be dielectric and can be a paste that forms a seal with a cavity when associated with press fit cold plate body 250. In at least one embodiment, latches or other features can be implemented to hold cold plate body 250 and achieve a hermetic seal.

[0070] In at least one embodiment, the immersion cold plate 250, 270 includes an opening 266 and a cavity 264. In at least one embodiment, the cold plate body 250 has a first seal 268 that effects an air-tight seal around at least one computing component 220 at the cavity 264. In at least one embodiment, the immersion cold plate 250, 270 is implemented to include a fluid within the cavity, and once the immersion cold plate 250, 270 is air-tightly sealed with the computing component 220D (or around the computing component 220D), is able to immerse at least a portion of the at least one computing component at the opening.

[0071] In at least one embodiment, self-sealing ports 252, 258 are associated with the immersion cold plate 250, 270 to receive immersion fluid into the cold plate and to retain the immersion fluid within the immersion cold plate 250, 270. In one embodiment, the self-sealing ports can have a seal, gasket, or valve cover 254, 260 that can be direction and pressure controlled. In at least one embodiment, the self-sealing ports 255, 258 are adapted to allow immersion fluid in or to allow immersion fluid out. In at least one embodiment, a flow controller 280 can be associated with the immersion fluid line 288 that enables immersion fluid to enter or exit the immersion cold plate 210B, 250. In at least one embodiment, a flow controller can be used as needed to the self-sealing ports as deactivating the flow controller can prevent fluid from entering or exiting the cavity and up to the inlet side of the flow controller. In at least one embodiment, the flow controller 280 enables the immersion cold plate 250, 270 to retain the immersion fluid within the cold plate for a determined amount of time.

[0072] In at least one embodiment, the immersion fluid enters the immersion fluid line 288 via dedicated immersion fluid inlet and outlet lines 208A, B. In at least one embodiment, the server manifold 204 is adapted to have channels 292 therein to support different paths to the fluid lines 288 (also 256, 262). In at least one embodiment, separate channels are provided to the remaining loops 214A, B associated with the secondary coolant inlet and outlet lines 206A, B as compared to the fluid channels 292. In at least one embodiment, a first flow can be implemented for the immersion cold plate that enables immersion fluid to enter the cavity 264 via the associated flow controller 280. In at least one embodiment, a second flow can be implemented for the immersion cold plate where cooling of the immersion fluid in the cavity 264 occurs via the secondary coolant flowing in the radiation duct 286. In at least one embodiment, the self-sealing port 252 enables fluid to enter the cavity 264 while a second self-sealing port 258 can be used to prevent fluid from exiting the cavity 264. In at least one embodiment, the self-sealing ports have valve covers 254, 260 to enable fluid in and prevent fluid out.

[0073] In at least one embodiment, associated flow controllers 294 for at least secondary coolant circuits 214A, B enable secondary coolant to flow through fluid lines 210, 216, 212 (also 278, 284) and inlet and outlet ports 282, 284. In at least one embodiment, this can represent a second flow of secondary coolant beginning to cool the immersion fluid via secondary coolant in line 286. In at least one embodiment, secondary coolant is allowed to enter the radiating ducts 286 of the cold plate 250, 270 via respective self-sealing ports 282, 284, which both maintain a distinct path between secondary coolant and immersion fluid. In at least one embodiment, immersion fluid acts as a cooling interface between the radiating ducts 286 and computing components 220D. In at least one embodiment, the radiating ducts 286 are liquid-liquid heat exchangers for immersion fluid and secondary coolant.

[0074] In at least one embodiment, a receiver plate 270 can be provided to circumvent an area on a board in a server tray or tank that requires cooling. In at least one embodiment, the area includes or is at least one computing component 220D. In at least one embodiment, the receiver plate 270 can include a gasket or seal 272. In at least one embodiment, the receiver plate 270 with gasket or seal 272 can be part of the cold plate 250 and can enable the cold plate body 250 to be hermetically sealed around the area and between the receiver plate 270 and the opening of the cold plate 266. In at least one embodiment, the receiver plate can be a collection of attachment points on a board within a server tray or tank. In at least one embodiment, the receiver plate is any aspect that allows the cold plate body 250 to be attached to the area with a gasket or seal that provides a hermetic seal for the cold plate. In at least one embodiment, the receiver plate includes or is a plurality of latches, bolts, nuts, or other features that can enable a hermetic seal. In at least one embodiment, the gasket or seal 268 of the cold plate body 250 corresponds to the gasket or seal 272 of the receiver plate 270, enabling a hermetic seal between the cold plate body 250 and the receiver plate 270. In at least one embodiment, the gasket or seal 268 of the cold plate body is within the gasket or seal 272 of the receiver plate 270. In at least one embodiment, the gasket or seal is distinct from the receiver plate 270 and can be applied to the board first, followed by the attachment points.

[0075] In at least one embodiment, the gasket or seal 268 of the cold plate body 250 is closest to the opening 266 to enable the largest area or volume of immersion fluid to be exposed to the area or computing component 220D that benefits from the localized immersion cooling provided. In at least one embodiment, the radiant pipe 286 represents a heat exchanger loop or plate within the cold plate 250 for a coolant or refrigerant to pass through the cold plate that can absorb heat from the immersion fluid. In at least one embodiment, this heat exchanger is a plate heat exchanger that sandwiches a cavity with immersion fluid to enable a wider heat exchange surface.

[0076] In at least one embodiment, the receiver plate 270 of the cold plate 250 surrounds an area of at least one computing component that is larger than the size of at least one computing device 220D. In at least one embodiment, if the computing device 220D is a card with multiple heat generating computing components, one or more of the multiple heat generating computing components can be included in the area to receive localized immersion cooling. In at least one embodiment, the receiver plate 270 can be removably sealed to the area using sealing features underneath the receiver plate 270. In at least one embodiment, the receiver plate has a first seal 272 included thereon. In at least one embodiment, the first seal 272 is adapted to receive a second seal 268 associated with the cold plate body 250. In at least one embodiment, the receiver plate 270 or the cold plate body 250 includes at least one pair of tabs 276 that form attachment points to lock the opening 266 to the receiver plate 270.

[0077] In at least one embodiment, a hermetic seal can be achieved using a band or other latch 274. In at least one embodiment, a vacuum or pressure between the gaskets or seals 268, 272 can achieve a hermetic seal. In at least one embodiment, the inlet and outlet pipes 256, 262 can be used with a vacuum system or can be used with a purge system to affect the environment in the cavity 264 after sealing. In at least one embodiment, a vacuum can be maintained via the port 252 to achieve a hermetic seal.

[0078] In at least one embodiment, there is no fluid in the cavity during the vacuuming or beginning of the hermetic seal.

[0079] In at least one embodiment, the channel through which the submerged fluid enters the cavity purifies cavity 264 and at least partially achieves an airtight seal. In at least one embodiment, once the fluid enters the cavity, it is no longer under vacuum and retains the thermodynamic properties it had when in a fluid source. In at least one embodiment, the fluid within the cavity is at the standard pressure of a data center environment. In at least one embodiment, a self-sealing port 262 opens into the cavity and prevents fluid outflow unless a suitable trigger opens the self-sealing port 262. In at least one embodiment, only one self-sealing port 252 is provided for the entry and exit of the submerged fluid. In at least one embodiment, the outflow of the submerged fluid may be by suction. In at least one embodiment, the fluid in the cavity promotes an airtight seal.

[0080] In at least one embodiment, at least one flow controller 290 may be associated with a rack hosting at least one computing component 220B or at least one server 202. In at least one embodiment, at least one flow controller 290 may enable the submerged cold plate 250 to receive submerged fluid into the submerged cold plate 250 and retain the fluid within the submerged cold plate 250 once it is hermetically sealed. In at least one embodiment, at least one flow controller 290 may be activated to deliver submerged fluid into the cold plate, and an outlet-side flow controller of at least one flow controller 290 may be activated to purge the line, but may be deactivated once the submerged fluid begins to flow gracefully out of the outlet-side flow controller. In at least one embodiment, this results in the submerged fluid being retained in the submerged cold plate between the outlet-side flow controller and the inlet-side flow controller, where there is no air, and the inlet-side flow controller may subsequently be deactivated as well.

[0081] In at least one embodiment, at least one flow controller 290 may be associated with a rack hosting at least one computing component 220D or at least one server 202. In at least one embodiment, the at least one flow controller is adapted to control a first pressure of the submerged fluid entering the cold plate or a second pressure of the submerged fluid within the cold plate. In at least one embodiment, these controls prevent damage or destruction to the hermetic seal during and after filling the cavity 264.

[0082] In at least one embodiment, such as Figure 3 The rack-level feature 300 shown can be associated with a local immersion cooling system for data center cooling systems. In at least one embodiment, the rack-level feature 300 includes a rack 302 having supports 304, 306 for suspending cooling manifolds 314A, B. In at least one embodiment, the cooling manifolds 314A, B are located in server-level feature 200 (and... Figure 3through the secondary coolant (or refrigerant) between the server tray or sled 308 and the CDU of the data center cooling system. In at least one embodiment, the same cooling manifold 314A, B has passages to pass the immersion fluid from the fluid source 330 to the immersion cold plate and to keep the immersion fluid distinct from the secondary coolant (or refrigerant). In at least one embodiment, the inlet and outlet lines 316, 318 are provided on one side or the other of the server tray or sled 308 to couple the respective cooling manifold 314A, B to the inlet side or outlet side of the server tray or sled 308.

[0083] In at least one embodiment, different cooling manifolds 314A, B are provided for the inlet side and outlet side of the data center cooling system. In at least one embodiment, a single manifold on a single of the racks 304, 306 can be used with passages therein for both the inlet side and outlet side of the server tray or sled 308 for receiving and discharging the secondary coolant for cooling the server tray or sled 308. In at least one embodiment, the single manifold can also have passages to keep the secondary coolant (or refrigerant) and the immersion fluid distinct. In at least one embodiment, the server tray or sled 308 has associated data center or computing components or devices 320 and associated cold plates 322 through which the fluid passes. In at least one embodiment, Figure 3 Also shown is an immersion cold plate that can be mounted to a computing component, to an attachment point formed or defined on a receiver plate connected to the top of the computing component. In at least one embodiment, Figure 3 Also shown is an immersion cold plate that can be mounted to a plate with a computing component, to an attachment point formed or defined on a receiver plate attached to an area surrounding the computing component.

[0084] In at least one embodiment, different (and additional) inlet and outlet lines 316, 318 from and to rack manifolds 314A, B are implemented to couple the rack manifolds (with secondary coolant) to the immersion fluid immersion cold plate 326. In at least one embodiment, inlet and outlet lines 320, 322 from and to different immersion fluid rack manifolds 314C, D to the immersion fluid immersion cold plate 326 are implemented. In at least one embodiment, if the rack manifolds 314A, B can handle both secondary coolant and immersion fluid in different channels, then flow controllers 310C, 312C in the splitter system can be used to start the immersion fluid first, and then the secondary coolant. In at least one embodiment, inlet and outlet lines 320, 322 couple respective channels of rack manifolds 314A, B that are distinctly directed to immersion fluid from a reservoir or fluid source 330 for the immersion cold plate 326, which is different than the secondary coolant for the radiation pipes within the cold plate 326. In at least one embodiment, dedicated lines 332 can couple the inlet and outlet lines 320, 322 of the rack manifolds 314A, B (or 314C, D) to the immersion fluid ports of the cold plate 326.

[0085] In at least one embodiment, at least one flow controller can be associated with a rack 302 at a rack manifold 314A, B or inlet and outlet lines 320, 322 to enable an immersion cold plate 326 to receive fluid into the immersion cold plate and retain fluid in the immersion cold plate. In at least one embodiment, at least one flow controller can be associated with a rack at a rack manifold or inlet or outlet line to control a first pressure of fluid into a cold plate or a second pressure of fluid within a cold plate. In at least one embodiment, this at least prevents overpressure from forming or damaging seals or gaskets. In at least one embodiment, at least one manifold 314A; B can be associated with a server cooling loop or a secondary cooling loop to provide secondary coolant (for radiation pipes) from a coolant distribution unit (CDU).

[0086] In at least one embodiment, auxiliary coolant enters rack 302 through manifold inlet 310, passes through inlet cooling manifold 314A, through inlet line 316, through cold plate 326, through outlet line 318, through outlet cooling manifold 314B, and through manifold outlet 312. In at least one embodiment, fluid enters rack 302 through manifold inlet 310D, passes through inlet cooling manifold 314C, through inlet line 320, and through cold plate 326 to be retained in the cold plate. In at least one embodiment, the immersion fluid can be flushed after several cooling cycles or regular time intervals. In at least one embodiment, flushing can be done through the same inlet port, line, and manifold, or through outlet line 322 and through outlet cooling manifold 314C, and through manifold outlet 312D. In at least one embodiment, when a single array of manifolds supports and maintains different auxiliary coolants (or refrigerants) and submerged fluid passages, a splitter system with one or more flow controllers 310C, 312C can be provided such that submerged fluid from submerged fluid source 330 first flows into the cold plate via lines 310B, 312B (to at least purify the cavity), and then allows auxiliary coolant for radiant ducts to flow through the cold plate via lines 310A, 312A.

[0087] In at least one embodiment, such as Figure 4 The data center-level feature 400 shown may be associated with a localized immersion cold plate for a data center cooling system. In at least one embodiment, the data center-level feature 400 may include an immersion fluid source 420 within a data center 402. In at least one embodiment, the immersion fluid source 420 may include an evaporator unit that circulates refrigerant and interfaces with a condenser unit outside the data center 402, such as on the roof of the data center 402. In at least one embodiment, the immersion fluid source 420 supports one or more racks 404. In at least one embodiment, a CDU 406 provides auxiliary coolant in an auxiliary cooling loop to circulate within the immersion cold plate and help the immersion fluid remove heat from the associated computing components. In at least one embodiment, the CDU connects the auxiliary coolant between the CDU 406 and a manifold or cooling manifold 410 via lines 412, 414.

[0088] In at least one embodiment, flow controllers 424 can be used to interface CDU 406 with the data center cooling system. In at least one embodiment, manifold 410 services racks 404 via lines 416, 418. In at least one embodiment, the primary coolant of primary cooling loop 422 travels between CDU 406 and a cooling facility 408 external to data center 402 (or data center room). In at least one embodiment, data center 402 can include another manifold 426, which can be associated with lines to direct immersion fluid from an immersion fluid source 420 to one or more immersion cold plates via one or more flow controllers. In at least one embodiment, at least one manifold 426 is then associated with a server cooling loop and can be distinct from manifold 410 associated with an auxiliary cooling loop. In at least one embodiment, this architecture enables immersion fluid from a fluid source to remain distinct from the auxiliary coolant of the CDU.

[0089] In at least one embodiment, at least one processor can interface with respective flow controllers discussed in each of Figures 2-4 In at least one embodiment, at least one processor can interface with respective flow controllers discussed in each of

[0090] In at least one embodiment, each of the at least one processor has inference and / or training logic 1815, which can include, without limitation, code and / or data memory 1801 to store forward and / or output weight and / or input / output data and / or other parameters to configure neurons or layers of a neural network, train the neural network in aspects of one or more embodiments, and / or for inferencing. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data memory 1801 to store graph code or other software to control timing and / or order, where weight and / or other parameter information can be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on a neural network architecture corresponding to such code. In at least one embodiment, code and / or data memory 1801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments, during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data memory 1801 can be included with other on-chip or off-chip data storage, including a processor’s Ll, L2, or L3 cache or system memory.

[0091] In at least one embodiment, inference and / or training logic 1815 of the at least one processor can be part of a building management system (BMS) to control flow controllers at one or more of a server level, a rack level, and a row level. In at least one embodiment, one or more neural networks of inference and / or training logic 1815 can be provided determinations to engage an immersion cold plate with an auxiliary coolant through the immersion cold plate to cause the one or more neural networks to infer which flow controllers to gracefully engage or disengage. In at least one embodiment, cooling immersion fluid by auxiliary coolant flowing through a radiation pipe in an immersion cold plate can be implemented by flow controllers controlled by inference and / or training logic 1815.

[0092] In at least one embodiment, one or more neural networks can be trained to make inferences based on previously associated thermal characteristics or cooling requirements from a computing device, server, or rack, and cooling capacity or capability indicated by the immersion coolant, along with the associated immersion fluid source 420 and CDU 406. In at least one embodiment, previous cooling requirements satisfied by an immersion cold plate, with or without an auxiliary coolant flowing through it, can cause one or more neural networks to make similar inferences about satisfying future similar cooling requirements (taking into account their minor variations) by adjusting a flow controller to submerge the immersion cold plate with the immersion fluid source, and then initiating the CDU to send (or initiate) the auxiliary coolant flow through the radiant pipe. In at least one embodiment, the immersion fluid can circulate out of the immersion cold plate after defined time intervals. In at least one embodiment, similarly, previous cooling requirements satisfied by the immersion cold plate can cause one or more neural networks to make similar inferences about future similar cooling requirements (taking into account their minor variations) by adjusting a flow controller, either alone or in conjunction with the immersion cold plate and the immersion fluid source, in combination with the CDU. In at least one embodiment, one or more neural networks may determine and send selections to a flow controller (e.g., to electronic components associated with the flow controller) to cause appropriate heat exchanger engagement or disengagement.

[0093] Figure 5 The diagram illustrates a relationship according to at least one embodiment. Figures 2-4 Method 500 is associated with a data center cooling system. In at least one embodiment, step 502 of method 500 may be providing a cold plate with openings and cavities for use in a localized immersion cooling configuration having at least one computing device. In at least one embodiment, method 400 may include step 504 for determining that the at least one computing component is to be immersion cooled within a server. In at least one embodiment, this determination may be based in part on the heat generated by the at least one computing device.

[0094] In at least one embodiment, step 506 determines whether a region surrounding at least one computing component will be associated with a cold plate. In at least one embodiment, this step may require considering the location of supports within at least one computing device and server trays or enclosures (and racks) for immersion fluid sources and associated piping to reach at least one computing device. In at least one embodiment, step 508 can then begin when the requirements of the region are determined to be solvable by local immersion cooling, when sufficient structure is provided to implement flow controllers for immersion fluid and auxiliary coolant, and when an airtight seal in the region can be achieved. In at least one embodiment, step 508 may be enabling the cold plate to be airtightly sealed to the region, such that at least one computing component (or a portion thereof) is within a cavity. In at least one embodiment, as referenced...Figures 2-4 Aspects described to implement an air-tight seal can be applied to this step. In at least one embodiment, step 510 can be performed to initiate partial immersion cooling such that a fluid within the cold plate immerses at least a portion of at least one computing component.

[0095] In at least one embodiment, method 500 can include further steps or can include sub-steps with reference to step 510 by enabling a self-sealing port of a cold plate to receive fluid into the cold plate and retain the fluid within the cold plate. In at least one embodiment, method 500 can include further steps or include sub-steps with reference to step 510 by enabling a flow controller associated with the cold plate to retain the fluid within the cold plate for a determined amount of time. In at least one embodiment, method 500 can include further steps or include sub-steps with reference to step 508 by enabling a receiver plate for at least one computing component to surround an area of the at least one computing component. In at least one embodiment, method 500 can include further steps or include sub-steps with reference to step 508 by enabling the cold plate to be air-tightly sealed around the area and between the receiver plate and an opening of the cold plate. In at least one embodiment, method 500 can include further steps or include sub-steps with reference to step 502 by providing a heat exchanger loop or plate within the cold plate to pass a coolant or refrigerant through the cold plate. In at least one embodiment, the further steps include enabling the coolant or refrigerant to absorb heat from the fluid at least in or after the step of 510.

[0096] In at least one embodiment, a step or sub-step of method 500 provides a receiver plate of a cold plate for surrounding an area of at least one computing component such that the receiver plate is removably sealed to the area by a seal beneath the receiver plate, the receiver further having a first seal thereon. In at least one embodiment, the step or sub-step further enables the first seal to receive a second seal associated with the cold plate and further enables at least one pair of tabs on the receiver plate or a body of the cold plate to lock the opening onto the receiver plate.

[0097] In at least one embodiment, method 500 can include further steps or include sub-steps with reference to step 510 for enabling the cold plate to receive fluid into the cold plate and to retain fluid within the cold plate using at least one flow controller associated with the rack or at least one server hosting at least one computing component. In at least one embodiment, method 500 can include further steps or include sub-steps to control a first pressure of fluid into the cold plate or a second pressure of fluid within the cold plate using at least one flow controller associated with the rack or with at least one server hosting at least one computing component. In at least one embodiment, method 500 can include further steps or sub-steps for providing a path between a source of fluid and the cold plate for the fluid using at least one manifold associated with the server cooling loop; and providing an auxiliary cooling manifold associated with the auxiliary cooling loop to transfer coolant or refrigerant from a coolant distribution unit (CDU) to a heat exchanger within the cold plate.

[0098] Servers and Data Centers

[0099] The following drawings illustrate but do not limit the exemplary server and data center based systems that can be used to implement at least one embodiment.

[0100] Figure 6 A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, distributed system 600 includes one or more client computing devices 602, 604, 606, and 608, which are configured to execute and operate a client application such as a web browser, proprietary client, and / or variant thereof. In at least one embodiment, server 612 can be communicatively coupled with remote client computing devices 602, 604, 606, and 608 via network 610.

[0101] In at least one embodiment, server 612 can be adapted to execute one or more services or software applications, such as services and applications that can manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, server 612 can also provide other services, or software applications, which can include non-virtual and virtual environments. In at least one embodiment, these services can be provided as web-based services or cloud services, or under a software as a service (SaaS) model to users of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices 602, 604, 606, and / or 608 can in turn utilize one or more client applications to interact with server 612 to utilize the services provided by these components.

[0102] In at least one embodiment, software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or services provided by these components can also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, users operating client computing devices can then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components can be implemented in hardware, firmware, software, or combinations thereof. It should be appreciated that various Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0103] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 can include different types of computing systems. In at least one embodiment, client computing devices can include portable handheld devices (e.g., an iPhone®, cellular telephone, an iPad®, computing tablet, a Personal Digital Assistant (PDA)) or wearable devices (e.g., a Google Glass® head-mounted display) running software such as Microsoft Windows Phone® OS, and / or a variety of mobile operating systems. In at least one embodiment, devices can support different applications, such as different Internet-related applications, email, Short Message Service (SMS) applications, and can use various other communications protocols. In at least one embodiment, client computing devices can also include general purpose personal computers including, by way of example, personal computers and / or laptop computers running various versions of Microsoft Windows and / or Apple Macintosh OS, and / or Linux operating systems. In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems. In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems. In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems. In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems.

[0104] In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems. In at least one embodiment, client computing devices can be workstation computers running one or more versions of Microsoft Windows and / or Apple Macintosh operating systems. Microsoft Xbox game console) and / or personal messaging devices. Although Figure 6 Distributed system 600 in FIG. 6 is shown with four client computing devices, but any number of client computing devices can be supported. Other devices, such as devices with sensors, etc. can interact with server 612.

[0105] In at least one embodiment, network 610 in distributed system 600 can be any type of network in which systems can communicate with one another. In at least one embodiment, network 610 can be capable of supporting communication in accordance with any one or more of numerous predefined communication protocols, such as FTP, TCP / IP, UDP, OSI, SONET, SDH, Bluetooth, Wi-Fi, AppleTalk, Firewire, Thunderbolt, and / or any of a number of other protocols. In at least one embodiment, network 610 can be a wired or wireless network that employs one or more access technologies, including but not limited to Wi-Fi, Bluetooth, near-field communication, and / or the like. In at least one embodiment, network 610 can be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., a network operating in accordance with any of Institute of Electrical and Electronics Engineers (IEEE) 802.11 suite of protocols, Bluetooth, and / or any other wireless protocol), and / or any combination of these and / or other networks.

[0106] In at least one embodiment, server 612 can be comprised of one or more general purpose computers, specialized server computers (including in at least one embodiment, PC (personal computer) servers, UNIX® servers, mid-range servers, mainframe computers, rack-mounted servers, etc.), server farms, server clusters, or any other arrangement and / or combination that can be suitable for a computing environment. In at least one embodiment, server 612 can include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization. In at least one embodiment, one or more pools of flexible logical storage devices can be virtualized for use by servers. In at least one embodiment, virtual networks can be controlled by server 612 using software-defined networking. In at least one embodiment, server 612 can be adapted to run one or more services or software applications.

[0107] In at least one embodiment, server 612 can run any operating system, and any commercially available server operating system. In at least one embodiment, server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (HyperText Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, JAVA® servers, database servers, and the like. In at least one embodiment, server 612 can also be server, database server, and / or variations thereof. In at least one embodiment, example database servers include, without limitation, those available from Oracle, Microsoft, Sybase, IBM (International Business Machine) and / or variations thereof.

[0108] In at least one embodiment, server 612 can include one or more applications for analyzing and correlating data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates can include, without limitation, those received from one or more third party information sources and continuous data streams. feeds, updates or real-time updates, which can include real-time events related to sensor data applications, financial quotes, network performance measuring tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, and / or variations thereof. In at least one embodiment, server 612 can also include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0109] In at least one embodiment, distributed system 600 can also include one or more databases 614 and 616. In at least one embodiment, a database can provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 can reside in various locations. In at least one embodiment, one or more of databases 614 and 616 can reside on a non-transitory storage medium local to (and / or resident in) server 612. In at least one embodiment, databases 614 and 616 can be remote from server 612 and in communication with server 612 via a network-based or dedicated connection. In at least one embodiment, databases 614 and 616 can reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing functions attributed to server 612 can be appropriately stored locally on server 612 and / or remotely. In at least one embodiment, databases 614 and 616 can include a relational database such as one adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0110] Figure 7 An example data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, without limitation, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0111] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0112] In at least one embodiment, the grouped computing resources 714 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. The individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0113] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0114] In at least one embodiment, such as Figure 7As shown, framework layer 720 includes, without limitation, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, framework layer 720 can include a framework that supports software 752 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 752 or applications 742 can include, respectively, web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 can be, without limitation, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that can utilize distributed file system 738 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 732 can include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 can be capable of configuring different layers, such as software layer 730 and framework layer 720 including Spark and distributed file system 738 for supporting large-scale data processing. In at least one embodiment, resource manager 736 can be capable of managing clustered or grouped computing resources mapped to or allocated for supporting distributed file system 738 and job scheduler 732. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 714 on data center infrastructure layer 710. In at least one embodiment, resource manager 736 can coordinate with resource orchestrator 712 to manage these mapped or allocated computing resources.

[0115] In at least one embodiment, software 752 included in software layer 730 can include software used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of software can include, without limitation, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0116] In at least one embodiment, one or more applications 742 included in application layer 740 can include one or more types of applications used by at least portions of node C.R.s 716(1)-716(N), grouped computing resources 714, and / or distributed file system 738 of framework layer 720. One or more types of applications can include, without limitation, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0117] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource orchestrator 712 can implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions can relieve data center operators of data center 700 from making possibly poor configuration decisions and can avoid underutilization and / or poor-performing portions of a data center.

[0118] Figure 8 A client-server network 804 formed of a plurality of network server computers 802 interconnected is shown, according to at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible by other network server computers 802 and client computers 806 and networks 808 linked to a wide area network 804. In at least one embodiment, a configuration of client-server network 804 can change over time as client computers 806 and one or more networks 808 connect and disconnect with network 804, and as one or more backbone server computers 802 are added to or removed from network 804. In at least one embodiment, a client-server network includes client computers 806 and networks 808 when they are connected with network server computers 802. In at least one embodiment, the term computer includes any device or machine that is capable of accepting data, applying prescribed processes to data, and providing results of processes.

[0119] In at least one embodiment, client-server network 804 stores information accessible to web server computers 802, remote network 808, and client computers 806. In at least one embodiment, web server computers 802 are formed from mainframe computers, minicomputers, and / or microcomputers each having one or more processors. In at least one embodiment, server computers 802 are linked together through wired and / or wireless transmission media, such as wire, fiber optic cable, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, client computers 806 access web server computers 802 through similar wired or wireless transmission media. In at least one embodiment, client computers 806 can link into client-server network 804 using modems and standard telephone communication networks. In at least one embodiment, alternative carrier systems, such as cable and satellite communication systems, can also be used to link into client-server network 804. In at least one embodiment, other private or time-shared carrier systems can be used. In at least one embodiment, network 804 is a global information network, such as the Internet. In at least one embodiment, network is a private intranet using similar protocols as the Internet but with added security measures and restricted access controls. In at least one embodiment, network 804 is a private or semi-private network using proprietary communication protocols.

[0120] In at least one embodiment, client computers 806 are any end-user computers, and can also be mainframe computers, minicomputers, or microcomputers having one or more microprocessors. In at least one embodiment, server computers 802 can sometimes act as client computers accessing another server computer 802. In at least one embodiment, remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transmission media having a fixed or changing configuration over time. In at least one embodiment, client computers 806 can link into network 804 independently or through remote network 808 and access network 804.

[0121] Figure 9A computer network 908 connecting one or more computer machines is shown in accordance with at least one embodiment. In at least one embodiment, network 908 can be any type of electrically connected computer group, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Datalink Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communications protocol. In at least one embodiment, computing devices linked to network can be desktops, servers, portable, handheld, set-top, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, network-connected devices can vary widely in processing power, internal memory, and other performance depending on their functionality.

[0122] In at least one embodiment, communications within network and to or from computing devices connected to network can be wired or wireless. In at least one embodiment, network 908 can include, at least in part, the world-wide public Internet, which typically connects multiple users according to a client-server model according to Transmission Control Protocol / Internet Protocol (TCP / IP) specifications. In at least one embodiment, a client-server network is a dominant model for communication between two computers. In at least one embodiment, a client computer (“client”) issues one or more commands to a server computer (“server”). In at least one embodiment, a server fulfills client commands by accessing available network resources and returning information to a client according to client commands. In at least one embodiment, client computer systems and network resources residing on network servers are assigned network addresses for identification during communications between elements of a network. In at least one embodiment, communications from other network-connected systems to a server will include a network address of a relevant server / network resource as part of a communication, so that an appropriate destination for data / requests is identified as a recipient. In at least one embodiment, when network 908 includes the global Internet, network addresses are IP addresses in TCP / IP format, which can route data, at least in part, to an email account, website, or other Internet tool residing on a server. In at least one embodiment, information and services residing on network servers can be available to web browsers of client computers through a domain name (e.g., www.site.com), which maps to an IP address of a network server.

[0123] In at least one embodiment, multiple clients 902, 904, and 906 are connected to network 908 via respective communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via dial-up modem connection, cable link, digital subscriber line (DSL), wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908 (e.g., personal computer (PC), workstation, dedicated terminal, personal data assistant (PDA), or other similar device). In at least one embodiment, clients 902, 904, and 906 may or may not be located in the same geographical area.

[0124] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients communicating with network 918. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, the server includes computer-readable data storage media, such as hard disk drives and RAM memory, that store program instructions and data. In at least one embodiment, servers 910, 912, and 914 run applications that respond to client commands. In at least one embodiment, server 910 may run a web server application for responding to client requests for HTML pages and may also run a mail server application for receiving and routing emails. In at least one embodiment, other applications, such as an FTP server or media server for streaming audio / video data to clients, may also run on server 910. In at least one embodiment, different servers may be dedicated to performing different tasks. In at least one embodiment, server 910 may be a dedicated web server for managing website-related resources for different users, while server 912 may be dedicated to providing email management. In at least one embodiment, the other servers may be dedicated to a combination of two or more services typically available or provided over a network, such as media (audio, video, etc.), File Transfer Protocol (FTP), or other services. In at least one embodiment, each server may be located in the same or different location as the other servers. In at least one embodiment, multiple servers may exist to perform mirroring tasks for users, thereby mitigating congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, and 914 are under the control of a web hosting provider that maintains and delivers third-party content over network 918.

[0125] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which can be referred to as a browser, requests content from servers 910, 912, 914, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which can be referred to as a user, hires the web hosting provider to maintain a network resource, such as a website, and make it available to browsers. In at least one embodiment, a user contracts with a web hosting provider to make memory space, processor capacity, and communication bandwidth available to their desired network resource according to the amount of server resources the user desires to utilize.

[0126] In at least one embodiment, in order for the web hosting provider to provide services to both clients, the application programs that manage the network resources hosted by the servers must be properly configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application program’s response to browser requests, and also at least partially define the server resources available to a particular user.

[0127] In one embodiment, intranet server 916 communicates with network 908 via a communication link. In at least one embodiment, intranet server 916 communicates with server manager 918. In at least one embodiment, server manager 918 includes a database of application program configuration parameters used in servers 910, 912, 914. In at least one embodiment, a user modifies database 920 via intranet 916, and server manager 918 interacts with servers 910, 912, 914 to modify the application program parameters so that they match the contents of the database. In at least one embodiment, a user logs into intranet 916 by connecting to intranet 916 via computer 902 and entering authentication information such as a username and password.

[0128] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that allows the user to access configuration parameters for a particular application. In at least one embodiment, the user is presented with a number of modifiable text boxes that describe aspects of the user's website or other network resource's configuration. In at least one embodiment, if the user desires to increase the amount of memory space reserved on the server for their website, the user is provided with a field in which the user specifies the desired amount of memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server, and the new parameters are used during operation of the application. In at least one embodiment, the intranet server 916 is configured to provide the user with access to configuration parameters for a hosted network resource (e.g., web page, email, FTP site, media site, etc.) that the user has contracted with a web hosting service provider.

[0129] Figure 10A A networked computer system 1000A is shown in accordance with at least one embodiment. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computers or nodes 1002 include a processor 1014, a memory 1016, a video camera 1004, a microphone 1006, a mouse 1008, a speaker 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 can each run one or more desktop servers for an internal network within a given company, or can be servers for a general-purpose network that is not limited to a particular environment. In at least one embodiment, there is one server per PC node of the network, such that each PC node of the network represents a particular network server with a particular network URL address. In at least one embodiment, each server has a default web page for the user of that server by default, which default web page can itself contain embedded URLs pointing to further sub-pages of that user on that server, or to other servers on the network or pages on other servers.

[0130] In at least one embodiment, nodes 1002, 1018, 1020, and other nodes of network are interconnected by a medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as an Integrated Services Digital Network (“ISDN”). In at least one embodiment, various nodes of a networked computer system can be connected by various communication media, including a Local Area Network (“LAN”), a Plain Old Telephone Line (“POTS”) (sometimes referred to as a Public Switched Telephone Network (“PSTN”)), and / or variations thereof. In at least one embodiment, various nodes of a network can also constitute computer system users interconnected via a network such as the Internet. In at least one embodiment, each server on a network (running from a particular node of a network at a given instance) has a unique address or identification within a network, which can be specified according to a URL.

[0131] In at least one embodiment, multiple Multipoint Conference Units (“MCUs”) can thus be used to transmit data to and from various nodes or “endpoints” of a conferencing system. In at least one embodiment, nodes and / or MCUs can be interconnected via ISDN links or through a Local Area Network (“LAN”), in addition to various other communication media, such as nodes connected through the Internet. In at least one embodiment, nodes of a conferencing system can typically be connected either directly to a communication medium such as a LAN or through an MCU, and a conferencing system can include other nodes or elements such as routers, servers, and / or variations thereof.

[0132] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, a processor of a node of networked computer system 1000A can also be a special-purpose video processor. In at least one embodiment, different peripheral devices and components of a node, such as those of node 1002, can differ from those of other nodes. In at least one embodiment, node 1018 and node 1020 can be configured the same as or differently from node 1002. In at least one embodiment, nodes can be implemented on any suitable computer system in addition to a PC system.

[0133] Figure 10BA networked computer system 1000B is shown in accordance with at least one embodiment. In at least one embodiment, system 1000B shows a network, such as LAN 1024, which can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a number of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, nodes can also connect to the LAN via a web server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, including routers, servers, and nodes for at least one embodiment.

[0134] Figure 10C A networked computer system 1000C is shown in accordance with at least one embodiment. In at least one embodiment, system 1000C shows a WWW system with communication across a backbone communication network, such as Internet 1032, which can be used to interconnect various nodes of a network. In at least one embodiment, the WWW is a set of protocols that operate on top of the Internet, and allows graphical interface systems to operate on it in order to access information over the Internet. In at least one embodiment, attached to Internet 1032 in the WWW are a number of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, nodes interface with other nodes of the WWW through WWW HTTP servers, such as servers 1034, 1036. In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although PC 1044 and server 1036 are shown separately in Figure 10C for purposes of illustration.

[0135] In at least one embodiment, the WWW is a distributed type of application, characterized by WWW HTTP, the protocol of the WWW, which operates on top of the Internet's Transmission Control Protocol / Internet Protocol ("TCP / IP"). In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) that operate on the Internet as its "backbone."

[0136] In at least one embodiment, a web browser is an application running on a node of a network in a network system of the WWW type that allows a user of a particular server or node to view such information and thus allows the user to search through graphical and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understand HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document can have different hypertext links embedded in it, and a local copy of the page is created locally at the retrieval user's machine. In at least one embodiment, when a user clicks on a hypertext link, the locally stored information related to the selected hypertext link is typically sufficient to allow the user's machine to open a connection through the Internet to the server indicated by the hypertext link.

[0137] In at least one embodiment, more than one user can be coupled to each HTTP server through a LAN such as LAN 1038, such as shown with respect to WWW HTTP server 1034. In at least one embodiment, system 1000C can also include other types of nodes or elements. In at least one embodiment, a WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server" as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server such as WWW HTTP server 1034 that provides access to a network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node of a network, each desktop PC potentially setting up a server for its user. In at least one embodiment, each server is associated with a particular network address or URL that, when accessed, provides a default web page for that user. In at least one embodiment, the web page can contain further links (embedded URLs) that point to further sub-pages of that user on that server, or to other servers on the network or to pages on other servers on the network.

[0138] Cloud computing and services

[0139] The following figures set forth, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0140] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge, understanding or control over the technology infrastructure in the “cloud” that supports them, the specialized knowledge of the technology infrastructure, or control over the technology infrastructure that can be referred to as “in the cloud.” In at least one embodiment, cloud computing converges infrastructure, platform and software as a service offering common themes that depend on the internet to meet the computing needs of users. In at least one embodiment, a typical cloud deployment, such as in a private cloud (e.g., enterprise network) or data center (DC) in a public cloud (e.g., the Internet) can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, a cloud can also consist of network services infrastructure, such as IPsec VPN hubs, firewalls, load balancers, Wide Area Network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services by connecting via a VPN tunnel, such as an IPsec VPN tunnel.

[0141] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0142] In at least one embodiment, cloud computing is characterized by on-demand self-service, wherein consumers can unilaterally provision computing capability, such as server time and network storage, as needed automatically (without requiring human interaction with each service provider). In at least one embodiment, cloud computing is characterized by broad network access, wherein capacity available to the general public or a large industry group is made available over the network and accessed through standard mechanisms that promote the use of heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, wherein the provider’s computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge over the exact location of the provided resources but can be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0143] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, in which capability can be rapidly and elastically provisioned (in some cases automatically), in some cases with little or no management effort or interaction with provider. In at least one embodiment, cloud computing is characterized by pay-per-use billing in which users are only billed for the capacity that they actually use — contributing to what is often a substantial cost savings for users. In at least one embodiment, cloud computing is characterized by measured service, in which cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage can be monitored, controlled, and reported providing transparency for both the provider and consumer of the service.

[0144] In at least one embodiment, cloud computing can be associated with various services. In at least one embodiment, cloud Software as a Service (SaaS) can refer to a paradigm for enabling on-demand access to software. In at least one embodiment, SaaS provides the consumer the ability to use an application that is running in a provider’s cloud infrastructure. In at least one embodiment, the application is accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0145] In at least one embodiment, cloud Platform as a Service (PaaS) can refer to a paradigm for enabling deployment of consumer-created or -acquired applications using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0146] In at least one embodiment, cloud Infrastructure as a Service (IaaS) can refer to a paradigm for enabling consumption of processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

[0147] In at least one embodiment, cloud computing provides a convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and client data, etc.) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. In at least one embodiment, this cloud resource can include tools delivered as a service to users that allow for the creation of a custom operating system, applications, or specific

[0148] Figure 11 One or more components of a system environment 1100, in accordance with one or more embodiments, are shown in which services can be provided as third party network services. In at least one embodiment, a third party network can be referred to as a cloud, a cloud network, a cloud computing network, and / or variations thereof. In at least one embodiment, system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third party network infrastructure system 1102 that provides third party network services, which can be referred to as cloud computing services. In at least one embodiment, third party network infrastructure system 1102 can include one or more computers and / or servers.

[0149] It is to be appreciated that the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, the third party network infrastructure system 1102 depicted in Figure 11 In at least one embodiment, an embodiment of a third party network infrastructure system is depicted. In at least one embodiment, third party network infrastructure system 1102 can have more or fewer components than those depicted in Figure 11 In at least one embodiment, an embodiment of a third party network infrastructure system is depicted. In at least one embodiment, third party network infrastructure system 1102 can have more or fewer components than those depicted in

[0150] In at least one embodiment, client computing devices 1104, 1106, and 1108 can be configured to operate a client application such as a web browser that can be used by users of client computing devices to interact with third party network infrastructure system 1102 to use services provided by third party network infrastructure system 1102. In at least one embodiment, example system environment 1100 is shown with three client computing devices, but any number of client computing devices can be supported. In at least one embodiment, other devices such as devices with sensors, etc. can interact with third party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 can facilitate communications and exchange of data between client computing devices 1104, 1106, and 1108 and third party network infrastructure system 1102.

[0151] In at least one embodiment, services provided by third party network infrastructure system 1102 can include hosting of services available on demand to users of third party network infrastructure system. In at least one embodiment, various services can also be provided including, but not limited to, online data storage and backup solutions, Web-based electronic mail services, managed office suites and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, services provided by a third party network infrastructure system can dynamically scale to meet the needs of its users.

[0152] In at least one embodiment, a particular instantiation of a service provided by third party network infrastructure system 1102 can be referred to as a “service instance.” In at least one embodiment, generally, any service available to a user from a third party network service provider system via a communication network, such as the Internet, is referred to as a “third party network service.” In at least one embodiment, in a public third party network environment, servers and systems that make up the third party network service provider system are distinct from a customer’s on-premise servers and systems. In at least one embodiment, a third party network service provider system can host an application and users can order and utilize the application on-demand via a communication network, such as the Internet.

[0153] In at least one embodiment, a service in a computer network third party network infrastructure can include protected computer network access to storage, hosted databases, hosted network servers, software applications, or other services provided to a user by a third party network vendor. In at least one embodiment, a service can include password protected access to remote storage on a third party network over the Internet. In at least one embodiment, a service can include a network service based hosted relational database and scripting language middleware engine for private use by a networked developer. In at least one embodiment, a service can include access to an email software application hosted on a website of a third party network vendor.

[0154] In at least one embodiment, third party network infrastructure system 1102 can include a suite of applications, middleware, and database service offerings that are delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, third party network infrastructure system 1102 can also provide “big data” related computing and analytics services. In at least one embodiment, the term “big data” is commonly used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by infrastructure system at many levels and at different scales. In at least one embodiment, tens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate an outside force on the data or what it represents. In at least one embodiment, these data sets can involve structured data (such as structured data in a database or otherwise organized according to a structured model) and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging capabilities of embodiments to relatively quickly focus more (or less) computing resources on a target, third party network infrastructure system can be better used to perform tasks on big data sets based on demand from businesses, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0155] In at least one embodiment, third party network infrastructure system 1102 can be adapted to automatically provide, manage and track customer subscriptions for services provided by third party network infrastructure system 1102. In at least one embodiment, third party network infrastructure system 1102 can provide third party network services via different deployment models. In at least one embodiment, services can be provided under a public third party network model in which third party network infrastructure system 1102 is owned by an organization that sells third party network services and makes services available to the general public or different industry enterprises. In at least one embodiment, services can be provided under a private third party network model in which third party network infrastructure system 1102 operates for a single organization and can provide services for one or more entities within the organization. In at least one embodiment, third party network services can also be provided under a community third party network model in which third party network infrastructure system 1102 and the services provided by third party network infrastructure system 1102 are shared by several organizations in a related community. In at least one embodiment, third party network services can also be provided under a hybrid third party network model, which is a combination of two or more different models.

[0156] In at least one embodiment, services provided by third party network infrastructure system 1102 can include one or more services provided under a Software as a Service (SaaS) category, a Platform as a Service (PaaS) category, an Infrastructure as a Service (IaaS) category, or other categories of services including hybrid services. In at least one embodiment, a customer can order one or more services provided by third party network infrastructure system 1102 via a subscription order. In at least one embodiment, third party network infrastructure system 1102 then performs processing to provide services in customer’s subscription order.

[0157] In at least one embodiment, services provided by third party network infrastructure systems 1102 can include, without limitation, application services, platform services, and infrastructure services. In at least one embodiment, application services can be provided by third party network infrastructure systems via a SaaS platform. In at least one embodiment, a SaaS platform can be configured to provide third party network services that fall into the SaaS category. In at least one embodiment, a SaaS platform can provide the capability for customers to use applications, running on third party network infrastructure systems, that are built using technologies from an integrated development and deployment platform. In at least one embodiment, a SaaS platform can manage and control the underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by utilizing the services provided by a SaaS platform, customers can no longer have to worry about acquiring and managing and supporting the hardware and software and infrastructure themselves. In at least one embodiment, customers can obtain such services from a third party network infrastructure system on either a subscription or usage basis.

[0158] In at least one embodiment, platform services can be provided by third party network infrastructure systems 1102 via a PaaS platform. In at least one embodiment, a PaaS platform can be configured to provide third party network services that fall into the PaaS category. In at least one embodiment, platform services can include, without limitation, services enabling organizations to combine existing applications with new applications built using technologies from an integrated development and deployment platform, as well as services that enable enterprises to use common infrastructure to deploy and manage existing and new applications. In at least one embodiment, a PaaS platform can manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers can acquire PaaS services from a third party network infrastructure system 1102 without the need for customers to purchase, install, and manage the underlying software and infrastructure.

[0159] In at least one embodiment, by utilizing the services provided by a PaaS platform, customers can use programming languages and tools supported by the third party network infrastructure system and also control deployed services. In at least one embodiment, platform services provided by a third party network infrastructure system can include database third party network services, middleware third party network services, and third party network services. In at least one embodiment, database third party network services can support shared services deployment models that enable organizations to pool database resources and offer customers database as a service in the form of database third party networks. In at least one embodiment, middleware third party network services can provide customers with a platform for developing and deploying various business applications, and third party network services can provide customers with a platform to deploy applications.

[0160] In at least one embodiment, various different infrastructure services can be provided by an IaaS platform in third party network infrastructure system. In at least one embodiment, infrastructure services facilitate the management and control of underlying computing resources, such as storage, networks, and other fundamental computing resources for customers utilizing services provided by SaaS and PaaS platforms.

[0161] In at least one embodiment, third party network infrastructure system 1102 can also include infrastructure resources 1130 for providing resources used to offer various services of third party network infrastructure system to customers. In at least one embodiment, infrastructure resources 1130 can include pre-integrated and optimized combinations of hardware, such as, for example, servers, storage and networking resources to execute the services provided by PaaS and SaaS platforms and other resources.

[0162] In at least one embodiment, resources in third party network infrastructure system 1102 can be shared by multiple users and dynamically re-allocated per demand. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, third party network infrastructure system 1102 can enable a first set of users in a first time zone to utilize resources of third party network infrastructure system for a specified number of hours and subsequently enable reallocation of same resources to another set of users located in a different time zone, thereby maximizing resource utilization.

[0163] In at least one embodiment, a number of internal shared services 1132 can be provided that are shared by different components or modules of third party network infrastructure system 1102 for implementing services offered by third party network infrastructure system 1102. In at least one embodiment, these internal shared services can include, but are not limited to, security and identity services, integration services, enterprise repository services, enterprise manager services, virus scanning and white list services, high availability, backup and recovery services, services for enabling third party network support, email services, notification services, file transfer services, and / or variations thereof.

[0164] In at least one embodiment, third party network infrastructure system 1102 can provide comprehensive management of third party network services (e.g., SaaS, PaaS, and IaaS services) in third party network infrastructure system. In at least one embodiment, third party network management functionality can include the ability to provision, manage and track subscriptions of customers received by third party network infrastructure system 1102 and / or variations thereof.

[0165] In at least one embodiment, as Figure 11As shown, the third party network management functionality can be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provisioning module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules can include or use one or more computers and / or servers, which can be general purpose computers, special purpose server computers, server farms, server clusters, or any other appropriate arrangement and / or combination.

[0166] In at least one embodiment, at step 1134, a customer using a client device, such as client computing device 1104, 1106, or 1108, can interact with the third party network infrastructure system 1102 by requesting and placing an order for one or more services provided by the third party network infrastructure system 1102 and a subscription to one or more services provided by the third party network infrastructure system 1102. In at least one embodiment, the customer can access third party network user interfaces (UIs), such as third party network UI 1112, third party network UI 1114, and / or third party network UI 1116, and place the order for subscription via these UIs. In at least one embodiment, order information received by the third party network infrastructure system 1102 in response to the customer placing the order can include information identifying the customer and one or more services provided by the third party network infrastructure system 1102 that the customer wants to subscribe to.

[0167] In at least one embodiment, at step 1136, the order information received from the customer can be stored in an order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, the order database 1118 can be one of several databases operated by the third party network infrastructure system 1118 and in conjunction with other system elements.

[0168] In at least one embodiment, at step 1138, the order information can be forwarded to an order management module 1120, which can be configured to perform billing and accounting functions related to the order, such as validating the order, and, upon validation, provisioning an order.

[0169] In at least one embodiment, at step 1140, information about the order can be transmitted to an order coordination module 1122 that is configured to coordinate the provisioning of services and resources for orders placed by customers. In at least one embodiment, order coordination module 1122 can use the services of an order provisioning module 1124 for provisioning. In at least one embodiment, order coordination module 1122 enables management of business processes associated with each order and applies business logic to determine whether an order should continue to be provisioned.

[0170] In at least one embodiment, at step 1142, upon receiving a new subscribed order, order coordination module 1122 sends a request to order provisioning module 1124 to allocate resources and configure resources needed to fulfill the subscribed order. In at least one embodiment, order provisioning module 1124 implements resource allocation for services ordered by customers. In at least one embodiment, order provisioning module 1124 provides a level of abstraction between third-party network infrastructure systems 1100 provided third-party network services and physical implementation layers used to provision resources for providing the requested services. In at least one embodiment, this enables order coordination module 1122 to be isolated from implementation details, such as whether services and resources are provisioned in real-time or pre-provisioned and only allocated / assigned upon request.

[0171] In at least one embodiment, at step 1144, once services and resources are provisioned, a notification can be sent to the subscribing customer indicating that the requested services are now ready for use. In at least one embodiment, information (e.g., a link) can be sent to the customer that enables the customer to begin using the requested services.

[0172] In at least one embodiment, at step 1146, orders for customers subscribing can be managed and tracked by an order management and monitoring module 1126. In at least one embodiment, order management and monitoring module 1126 can be configured to collect usage statistics about customer usage of subscribed services. In at least one embodiment, statistics can be collected for amount of storage used, amount of data transferred, number of users, and amount and / or changes in system up times and system down times.

[0173] In at least one embodiment, third party network infrastructure system 1100 can include an identity management module 1128 configured to provide identity services such as access management and authorization services in third party network infrastructure system 1100. In at least one embodiment, identity management module 1128 can control information about customers who wish to utilize services provided by third party network infrastructure system 1102. In at least one embodiment, such information can include information to authenticate identities of such customers and information describing what actions those customers are authorized to perform with respect to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, identity management module 1128 can also include managing descriptive information about each customer and descriptive information about how and by whom the descriptive information can be accessed and modified.

[0174] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, cloud computing environment 1202 includes one or more computer systems / server 1204 that are in communication with one or more computing devices, such as personal digital assistant (PDA) or cellular telephone 1206A, desktop computer 1206B, laptop computer 1206C, and / or automobile computer system 1206N, that are in communication with one or more computer systems / server 1204. In at least one embodiment, this allows infrastructure, platforms, and / or software as a service to be offered from cloud computing environment 1202 to clients, which can not need to individually maintain such resources. It should be understood that Figure 12 The types of computing devices 1206A-N shown in FIG. 12 are intended to be illustrative only and that cloud computing environment 1202 can communicate with any type of computerized device over any type of network and / or network / addressable connection (e.g., using a web browser).

[0175] In at least one embodiment, computer system / server 1204 can be operational with numerous other general purpose or special purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations that can be suitable for use with computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and / or variants thereof.

[0176] In at least one embodiment, computer system / server 1204 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, and / or the like that perform particular tasks or implement particular abstract data types. In at least one embodiment, exemplary computer system / server 1204 can be practiced in distributed cloud computing environments with remote processing devices that are linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media including memory storage devices.

[0177] Figure 13 A set of functional abstraction layers provided by cloud computing environment 1202 (FIG. 13) is shown. It should be understood that the components, layers, and functions shown in FIG. 13 are intended to be illustrative only and that components, layers, and functions can be varied. Figure 12 Figure 13 In at least one embodiment, components, layers, and functions shown in FIG. 13 are merely meant to be illustrative and that components, layers, and functions can be varied.

[0178] In at least one embodiment, hardware and software layer 1302 includes hardware and software components. In at least one embodiment, hardware components include mainframes, various RISC (Reduced Instruction Set Computer) architecture-based servers, various computing systems, supercomputers, storage devices, networks, networking components, and / or the like. In at least one embodiment, software components include network application server software, various application server software, various database software, and / or the like.

[0179] In at least one embodiment, virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities can be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and virtual clients; and / or the like.

[0180] ​In at least one embodiment, management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. In at least one embodiment, metering provides usage tracking of resources in use, for example, the usage of application software licenses. In at least one embodiment, provisioning provides a single point of management functionality that enables ubiquitous underwriting and rapid deployment of resources by orchestrating different layers of the cloud computing environment. In at least one embodiment, security provides identity verification for users and tasks, as well as protection for data and other resources. In at least one embodiment, user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that required service levels are met. In at least one embodiment, service level agreement (SLA) planning and fulfillment provides pre-arrangement for, and fulfillment of, cloud computing resources to provide desired level of service to a user.

[0181] In at least one embodiment, workload layer 1308 provides functionality for which the cloud computing environment can be utilized. In at least one embodiment, workloads and functions that can be provided from this layer include: mapping and navigation; software development and management; education services; data analysis and processing; transaction processing; and services delivery.

[0182] Supercomputing

[0183] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0184] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits significant parallelism and includes at least one chip, where the chips in the system are interconnected by a network and are placed in a hierarchically organized enclosure. In at least one embodiment, a large hardware system that fills a machine room with several racks, each containing several board / rack modules, each containing several chips all interconnected by a scalable network, is at least one embodiment of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and contains several hardware components can also be considered a supercomputer, as the amount of hardware that can be incorporated in a single chip can increase as feature sizes can decrease.

[0185] Figure 14A supercomputer at the chip level is shown, according to at least one embodiment. In at least one embodiment, within an FPGA or ASIC chip, primary computation is performed within finite state machines (1404) called thread units. In at least one embodiment, a task and synchronization network (1402) connects finite state machines and is used to dispatch threads and perform operations in correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi-level partitioned on-chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and off-chip memory network (1414) is used to access off-chip memory. In at least one embodiment, an I / O controller (1418) is used for cross-chip communication when a design does not fit on a single logic chip.

[0186] Figure 15 A supercomputer at the rack module level is shown, according to at least one embodiment. In at least one embodiment, within a rack module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that make up a main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its neighboring FPGA / ASIC chip using a wide bus on board with differential high speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high speed serial communication cable.

[0187] Figure 16 A supercomputer at the rack level is shown, according to at least one embodiment. Figure 17 A supercomputer at the entire system level is shown, according to at least one embodiment. In at least one embodiment, see Figure 16 and Figure 17Between and across racks of rack modules, a scalable, possibly incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of an accelerator is connected to a host system (1704) through a PCI-Express connection. In at least one embodiment, a host system includes a host microprocessor (1708) on which software portions of an application run, and a memory consisting of one or more host memory DRAM units (1706) that are kept coherent with memory on an accelerator. In at least one embodiment, a host system can be a separate module on one of the racks, or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cyclic topology of cube connections provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, a group contains chips A, B, C, and D on a rack module, which has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables that connect the rack module to the outside world. In at least one embodiment, chip A on a rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, the entire group {A, B, C, D} making up a rack module can form a hypercube node within a supercomputer system, with up to 2i2= 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B with an on-board differential wide bus connection. In at least one embodiment, a message arriving on link 4 destined for the group {A, B, C, D} of chips (i.e., to B) must also first be routed to the correct destination chip (A) inside the group {A, B, C, D}. In at least one embodiment, other sizes of parallel supercomputer systems can also be implemented.

[0188] Artificial intelligence

[0189] The following figures illustrate, but are not limited to, example artificial intelligence-based systems that can be used to implement at least one embodiment.

[0190] Figure 18AInference and / or training logic 1815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are described in more detail below in conjunction with FIGS. 1 A and 1 B. Figure 18A and / or Figure 18B Details regarding inference and / or training logic 1815 are provided below in conjunction with FIGS. 1 A and IB.

[0191] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1801 for storing forward and / or output weight and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1801 for storing graph code or other software to control timing and / or order where weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or use of aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache memories, or system memory.

[0192] In at least one embodiment, any portion of code and / or data storage 1801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 can be cache memory, dynamic random addressable memory (“DRAM”), static random addressable memory (“SRAM”), nonvolatile memory (e.g., Flash), or other storage. In at least one embodiment, whether code and / or code and / or data storage 1801 is internal or external to a processor, and / or the choice of including DRAM, SRAM, Flash, or some other type of storage, can depend on available storage on-chip relative to off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0193] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of a neural network that is trained in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 1815 can include or be coupled to code and / or data storage 1805 to store graph code or other software to control timing and / or sequence in which weight and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0194] In at least one embodiment, code such as graph code causes weight or other parameter information to be loaded into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, whether code and / or data storage 1805 is internal or external to a processor, or includes a choice of DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0195] In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be separate storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be combined storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 can be partially combined and partially separate. In at least one embodiment, any portion of code and / or data store 1801 and code and / or data store 1805 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0196] In at least one embodiment, inference and / or training logic 1815 can include, without limitation, one or more arithmetic logic units (“ALUs”), including integer and / or floating-point units, for performing logical and / or mathematical operations based, at least in part, on training and / or inference code (e.g., graphics code) or instructions by training and / or inference code (e.g., graphics code), results of which can produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 1820, which is a function of input / output and / or weight parameter data stored in code and / or data store 1801 and / or code and / or data store 1805. In at least one embodiment, activations stored in activation storage 1820 are generated from linear algebra and / or matrix-based mathematics performed by ALU 1810 in response to executing instructions or other code, where weight values stored in code and / or data store 1805 and / or data store 1801 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which can be stored in code and / or data store 1805 or code and / or data store 1801 or another storage on-chip or off-chip.

[0197] In at least one embodiment, one or more ALUs 1810 are included in a processor or other hardware logic or circuitry, while in another embodiment one or more ALUs 1810 can be external to a processor or other hardware logic or circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 1810 can be included within execution units of a processor or otherwise within a bank of ALUs that are accessible by execution units of a processor, either within a same processor or distributed between different types of processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1801, code and / or data storage 1805, and activation storage 1820 can share a processor or other hardware logic or circuitry, while in another embodiment they can be in different processors or other hardware logic or circuitry, or some combination thereof. In at least one embodiment, any portion of activation storage 1820 can be included with other on-chip or off-chip data storage including an LI, L2, or L3 cache of a processor or system memory. Furthermore, inference and / or training code can be stored with other code that is accessible to and used by a processor or other hardware logic or circuitry to fetch and / or process with fetch, decode, schedule, execute, retirement, and / or other logic of a processor.

[0198] In at least one embodiment, activation storage 1820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash) or other storage. In at least one embodiment, activation storage 1820 can be entirely or partially within or outside of one or more processors or other logic circuitry. In at least one embodiment, whether activation storage 1820 is internal or external to a processor, and in at least one embodiment, or the selection of whether to include DRAM, SRAM, Flash, or some other type of storage, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0199] In at least one embodiment, Figure 18A Inference and / or training logic 1815 as shown in FIG. 18A can be used in combination with a special-purpose integrated circuit (‘ASIC”) such as Google’s Tensor Processing Unit (‘TPU”), an inference processing unit (‘IPU”) from Graphcore’s AI System, or an AI Accelerator from Nvidia’s Nsight™ Collectors, an inference processing unit (‘IPU”) from Graphcore TM ​(For example, a "Lake Crest" processor. In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware such as field programmable gate array (“FPGA”)).

[0200] Figure 18B Inference and / or training logic 1815 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown can be combined with an application-specific integrated circuit (ASIC) (such as those from Google). Processing unit, from Graphcore TM Inference processing unit (IPU), or from Intel Corporation (For example, "Lake Crest") processors are used. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field-programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 18B In at least one embodiment described herein, each of code and / or data storage 1801 and code and / or data storage 1805 is associated with a dedicated computing resource (e.g., computing hardware 1802 and computing hardware 1806). In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform mathematical functions (such as linear algebra functions) on the information stored in code and / or data storage 1801 and code and / or data storage 1805, respectively, and the results are stored in active storage 1820.

[0201] In at least one embodiment, each code and / or data store 1801 and 1805 and corresponding compute hardware 1802 and 1806, respectively, correspond to different layers of a neural network, such that resulting activations from one storage / compute pair 1801 / 1802 are provided as input to the next storage / compute pair 1805 / 1806 in code and / or data store 1805 and compute hardware 1806, mirroring a conceptual organization of a neural network. In at least one embodiment, each of storage / compute pairs 1801 / 1802 and 1805 / 1806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) after or in parallel with storage / compute pairs 1801 / 1802 and 1805 / 1806 can be included in inference and / or training logic 1815.

[0202] Figure 19 Training and deployment of a deep neural network is shown, in accordance with at least one embodiment. In at least one embodiment, an untrained neural network 1906 is trained using a training dataset 1902. In at least one embodiment, training framework 1904 is a PyTorch framework, while in other embodiments, training framework 1904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1904 trains untrained neural network 1906 and enables it to train using processing resources described herein to generate a trained neural network 1908. In at least one embodiment, weights can be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0203] In at least one embodiment, an untrained neural network 1906 is trained using supervised learning, where a training dataset 1902 includes inputs paired with desired outputs for inputs, or where a training dataset 1902 includes inputs with known outputs and outputs of the neural network 1906 are manually graded. In at least one embodiment, an untrained neural network 1906 is trained in a supervised manner and inputs from a training dataset 1902 are processed and resulting outputs are compared to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 1906. In at least one embodiment, a training framework 1904 adjusts weights that control the untrained neural network 1906. In at least one embodiment, a training framework 1904 includes tools to monitor how well an untrained neural network 1906 is converging towards a model, such as a trained neural network 1908, that is suitable to generate correct answers, such as results 1914, based on input data, such as a new dataset 1912. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 repeatedly while using a loss function and adjustment algorithm, such as stochastic gradient descent, to adjust weights to refine outputs of the untrained neural network 1906. In at least one embodiment, a training framework 1904 trains an untrained neural network 1906 until the untrained neural network 1906 achieves a desired level of accuracy. In at least one embodiment, a trained neural network 1908 can then be deployed to implement any number of machine learning operations.

[0204] In at least one embodiment, an untrained neural network 1906 is trained using unsupervised learning, where an untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, an unsupervised learning training dataset 1902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, an untrained neural network 1906 can learn groupings within a training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1908 that is capable of performing operations useful in reducing a dimensionality of a new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identification of data points in a new dataset 1912 that deviate from a normal pattern of the new dataset 1912.

[0205] In at least one embodiment, semi-supervised learning can be used, which is a technique where a mix of labeled and unlabeled data is included in a training dataset 1902. In at least one embodiment, training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables a trained neural network 1908 to adapt to new datasets 1912 without forgetting knowledge that was imprinted within trained neural network 1408 during initial training.

[0206] 5G network

[0207] The following figures set forth, but are not limited to, exemplary 5G network-based systems that can be used to implement at least one embodiment.

[0208] Figure 20 An architecture of a system 2000 of a network is shown in accordance with at least one embodiment. In at least one embodiment, system 2000 is shown to include a user equipment (UE) 2002 and a UE 2004. In at least one embodiment, UEs 2002 and 2004 are shown as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but can also include any mobile or non-mobile computing device, such as personal data assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets or any computing device including a wireless communications interface.

[0209] In at least one embodiment, any of UEs 2002 and 2004 can comprise an Internet of Things (IoT) UE, which can comprise an access layer of a network designed for low-power IoT applications using short-lived connections. In at least one embodiment, an IoT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), a proximity-based service (ProSe) or device-to-device (D2D) communication, sensor networks, or IoT networks. In at least one embodiment, M2M or MTC data exchanges can be machine-initiated exchanges in which data is exchanged between members of a M2M or MTC network. In at least one embodiment, an IoT network describes interconnecting IoT UEs, which can include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections.

[0210] In at least one embodiment, UEs 2002 and 2004 can be configured to connect with a radio access network (RAN) 2016 (e.g., communicatively coupled with the RAN 2016). In at least one embodiment, the RAN 2016 can be an evolved universal mobile telecommunication system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each of which includes a physical

[0211] In at least one embodiment, UEs 2002 and 2004 can also directly exchange communication data via a ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 can alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0212] In at least one embodiment, UE 2004 is illustrated as being configured to access an access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein the AP 2010 would comprise a wireless fidelity router. In at least one embodiment, AP 2010 is illustrated as connected to the Internet without connecting to the core network, although this is not required in every embodiment. In at least one embodiment, AP 2010 can represent a Wi-Fi access point. In at least one embodiment, AP 2010 can provide communication

[0213] In at least one embodiment, RAN 2016 can include one or more access nodes 2012 and 2014 that enable the connection 2012 and 2014. In at least one embodiment, these access nodes (ANs) can be referred to as base stations, NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNBs), RAN nodes, and / or the like, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage over a geographic area, such as a cell. In at least one embodiment, RAN 2016 can include one or more RAN nodes for providing macrocells (e.g., macro RAN node 2018) and one or more RAN nodes for providing femtocells or picocells (e.g., low power (LP) RAN node 2020).

[0214] In at least one embodiment, any of the RAN nodes 2018 and 2020 can terminate the air interface protocol and can be the first point of contact for the UEs 2002 and 2004. In at least one embodiment, any of the RAN nodes 2018 and 2020 can fulfill various logical functions for the RAN 2016 including, but not limited to, RNC functionssuch as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0215] In at least one embodiment, UEs 2002 and 2004 can be configured to communicate using orthogonal frequency division multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 2018 and 2020 over a multicarrier communication channel in accordance with various communication techniques, such as, but not limited to, an orthogonal frequency division multiple access (OFDMA) communication technique (e.g., for downlink communications) or a single carrier frequency division multiple access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), and / or variants thereof. In at least one embodiment, OFDM signals can comprise orthogonal waveshapes used for transmission or reception of information.

[0216] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from any of the RAN node 2018 and 2020 to the UEs 2002 and 2004, while uplink transmissions can utilize a similar approach. In at least one embodiment, the grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. In at least one embodiment, such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one slot, i.e., a duration of 0.5 milliseconds for NR. In at least one embodiment, the smallest time-frequency unit in the resource grid is denoted as a resource element. In at least one embodiment, the resource grid comprises a number of resource blocks (RBs) in the frequency domain, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block comprises a collection of resource elements in the frequency domain. In at least one embodiment, in the frequency domain, this can represent the smallest amount of resources that can be allocated together in the downlink. In at least one embodiment, there are several different physical downlink channels that are conveyed using such resource blocks.

[0217] In at least one embodiment, a physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to the UEs 2002 and 2004. In at least one embodiment, a physical downlink control channel (PDCCH) can carry information about the transport format and resource allocations for the PDSCH channel, among other things. In at least one embodiment, it can also inform the UEs 2002 and 2004 about the transport format, resource allocation, and HARQ information for the uplink shared channel. Generally, in at least one embodiment, downlink scheduling (which allocates control and shared channel resource blocks to the UEs 2002 within a cell) can be performed by any of the RAN nodes 2018 and 2020 based on channel quality information feedback from any of the UEs 2002 and 2004. In at least one embodiment, downlink resource allocation information can be sent on the PDCCH used for each of the UEs 2002 and 2004.

[0218] In at least one embodiment, a PDCCH can use control channel elements (CCEs) to convey control information. In at least one embodiment, PDCCH complex-valued symbols can first be organized into quadruplets, then permuted using a sub-block interleaver for rate matching, in at least one embodiment, one or more of these CCEs can be used to transmit each PDCCH, where each CCE can correspond to nine sets of four resource element groups (REGs), referred to as resource element groups (REGs). In at least one embodiment, four Quadrature Phase Shift Keying (QPSK) symbols can be mapped to each REG. In at least one embodiment, depending on the Downlink Control Information (DCI) size and the channel condition, one or more CCEs can be used to send a PDCCH. In at least one embodiment, there can be four or more different PDCCH formats (e.g., aggregation level, L=l, 2, 4, or 8) defined in LTE with different number of CCEs.

[0219] In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources can be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) can be used to transmit EPDCCH. In at least one embodiment, each ECCE can correspond to nine sets of four physical resource elements called enhanced resource element groups (EREGs). In at least one embodiment, an ECCE can have other numbers of EREGs in some situations.

[0220] In at least one embodiment, the RAN 2016 is shown to be communicatively coupled to a core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, the CN 2038 can be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 2022 is split into two parts: the S1 -U interface 2026, which carries traffic data between the RAN nodes 2018 and 2020 and a serving gateway (S-GW) 2030, and the S1 -Mobility Management Entity (MME) interface 2024, which is a signaling interface between the RAN nodes 2018 and 2020 and a MME 2028.

[0221] In at least one embodiment, CN2038 includes MME2028, S-GW2030, Packet Data Network (PDN) Gateway (P-GW)2034, and Home Subscriber Server (HSS)2032. In at least one embodiment, MME2028 may functionally resemble the control plane of a legacy General Packet Radio Service (GPRS) Support Node (SGSN). In at least one embodiment, MME2028 may manage mobility aspects of access, such as gateway selection and tracking area list management. In at least one embodiment, HSS 2032 may include a database for network users, comprising subscription-related information to support network entities in handling communication sessions. In at least one embodiment, CN2038 may include one or more HSS2032s, depending on the number of mobile users, device capacity, network organization, etc. In at least one embodiment, HSS2032 may provide support for routing / roaming, authentication, authorization, naming / addressing resolution, location dependencies, etc.

[0222] In at least one embodiment, the S-GW2030 can terminate the S1 interface 2022 toward RAN2016 and route data packets between RAN2016 and CN2038. In at least one embodiment, the S-GW2030 can be a local mobility anchor for inter-RAN node handover and can also provide an anchor for inter-3GPP mobility. In at least one embodiment, other responsibilities may include lawful interception, charging, and some policy enforcement.

[0223] In at least one embodiment, P-GW2034 can terminate the SGi interface toward the PDN. In at least one embodiment, P-GW2034 can route data packets between EPC network 2038 and external networks (such as networks including application server 2040 (or application function (AF))) via Internet Protocol (IP) interface 2042. In at least one embodiment, application server 2040 can be an element that provides applications using IP bearer resources using a core network (e.g., UMTS Packet Service (PS) domain, LTE PS data service, etc.). In at least one embodiment, P-GW2034 is shown as communicatively coupled to application server 2040 via IP communication interface 2042. In at least one embodiment, application server 2040 can also be configured to support one or more communication services (e.g., Voice over Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) of UE2002 and 2004 via CN2038.

[0224] In at least one embodiment, the P-GW 2034 can also be a node for policy enforcement and charging data collection. In at least one embodiment, a Policy and Charging Enforcement Function (PCRF) 2036 is a policy and charging control element of the CN 2038. In at least one embodiment, in a non-roaming scenario, there can be a single PCRF 2036 in a Home Public Land Mobile Network (HPLMN) associated with a UE’s Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local breakout of traffic, there can be two PCRFs associated with a UE’s IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). In at least one embodiment, the PCRF 2036 can be communicatively coupled to an application server 2040 via the P-GW 2034. In at least one embodiment, the application server 2040 can signal the PCRF 2036 to indicate a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, the PCRF 2036 can provision this rule to a Policy and Charging Enforcement Function (PCEF) (not shown) with appropriate traffic flow template (TFT) and Quality of Class of Service (QCI) which commences the QoS and charging by the application server 2040.

[0225] Figure 21 An architecture of a system 2100 of a network is shown in accordance with some embodiments. In at least one embodiment, system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a user plane function (shown as UPF 2104), a data network (DN 2106), which in at least one embodiment can be operator services, Internet access, or third party services, and a 5G core network (5GC) (shown as CN 2110).

[0226] In at least one embodiment, the CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, the CN 2110 can also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0227] In at least one embodiment, UPF2104 can act as an anchor point for intra- and inter-RAT mobility, an external PDU session point interconnected to DN2106, and a branch point supporting multi-homed PDU sessions. In at least one embodiment, UPF2104 can also perform packet routing and forwarding, packet inspection, user plane portion of policy rule enforcement, lawful packet interception (UP collection), service usage reporting, performing QoS processing for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), performing uplink service verification (e.g., SDF-to-QoS flow mapping), transport-level packet marking in uplink and downlink, and downlink packet buffering and downlink data notification triggering. In at least one embodiment, UPF2104 may include an uplink classifier for supporting the routing of service flows to the data network. In at least one embodiment, DN2106 may represent various network operator services, Internet access, or third-party services.

[0228] In at least one embodiment, AUSF2114 can store data for authentication of UE2102 and handle authentication-related functions. In at least one embodiment, AUSF2114 can facilitate a common authentication framework for various access types.

[0229] In at least one embodiment, AMF2112 can be responsible for registration management (e.g., for registering UE2102, etc.), connection management, reachability management, mobility management, and lawful interception of AMF-related events, as well as access authentication and authorization. In at least one embodiment, AMF2112 can provide SM message transmission for SMF2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, AMF2112 can also provide UE2102 with SMS Functionality (SMSF) (…). Figure 21 Transmission of Short Message Service (SMS) messages between (not shown). In at least one embodiment, AMF2112 may act as a Security Anchoring Function (SEA), which may include interaction with AUSF2114 and UE2102 and receiving an intermediate key established as a result of the UE2102 authentication process. In at least one embodiment, in the case of using USIM-based authentication, AMF2112 may retrieve security material from AUSF2114. In at least one embodiment, AMF2112 may also include a Security Context Management (SCM) function, which receives from the SEA a key it uses to derive the access network-specific key. Furthermore, in at least one embodiment, AMF2112 may be the termination point (N2 reference point) of the RANCP interface, the termination point of NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0230] In at least one embodiment, the AMF 2112 can also support NAS signaling with the UE 2102 over an N3 interworking function (IWF) interface. In at least one embodiment, the N3IWF can be used to provide access to untrusted entities. In at least one embodiment, the N3IWF can be a termination point for N2 and N3 interfaces for control plane and user plane, respectively, and thus can handle N2 signaling from SMF and AMF for PDU session and QoS, encapsulate / decapsulate packets for IPSec and N3 tunneling, mark N3 user-plane packets in uplink, and enforce QoS corresponding to N3 packet marking taking into account QoS requirements associated with such marking received over N2. In at least one embodiment, the N3IWF can also relay uplink and downlink control-plane NAS (N I) signaling between the UE 2102 and AMF 2112, and relay uplink and downlink user-plane packets between the UE 2102 and UPF 2104. In at least one embodiment, the N3IWF also provides mechanisms for IPsec tunnel establishment with the UE 2102.

[0231] In at least one embodiment, the SMF 2118 can be responsible for session management (e.g., session establishment, modify, and release, including UPF and AN node selection); UE IP address allocation and management (including optional authorization); selection and control of UP function; configuration of traffic steering at UPF to route traffic to proper destination; interface termination towards policy control functions; control plane part of policy enforcement and QoS; lawful intercept (for SM events and interface to LI system); termination of SM parts of NAS messages; downlink data notification; initiator of AN specific SM information transmitted over N2 to AN via AMF; determining SSC mode of a session. In at least one embodiment, the SMF 2118 can include the following roaming functionality: handling local enforcement to apply QoS SLAs (VPLMN); charging data collection and charging interface (VPLMN); lawful intercept (in VPLMN for SM events and interface to LI system); support for interaction with external DN to transfer signaling for PDU session authorization / authentication by external DN.

[0232] In at least one embodiment, the NEF 2116 can provide means for securely exposing services and capabilities offered by 3 GPP network functions for third party, internal exposure / re exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle AFs. In at least one embodiment, the NEF 2116 can also translate information exchanged with AFs 2126 and information exchanged with internal network functions. In at least one embodiment, the NEF 2116 can translate between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2116 can also receive information from other network functions (NFs) based on exposed capabilities of other network functions. In at least one embodiment, this information can be stored at the NEF 2116 as structured data, or at a data storage NF using standardized interfaces. In at least one embodiment, the stored information can then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes such as analytics.

[0233] In at least one embodiment, the NRF 2120 can support service discovery functions, receive NF discovery requests from NF instances, and provide NF instances with information of discovered NF instances. In at least one embodiment, the NRF 2120 also maintains information of available NF instances and their supported services.

[0234] In at least one embodiment, the PCF 2122 can provide policy rules to control plane functions to enforce them, and can also support a unified policy framework to govern network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) to access subscription information related to policy decisions in a UDR of UDM 2124.

[0235] In at least one embodiment, the UDM 2124 can handle subscription-related information to support network entities handling communication sessions, and can store subscription data of UEs 2102. In at least one embodiment, the UDM 2124 can include two parts, an application FE and a user data repository (UDR). In at least one embodiment, the UDM can include a UDM FE that is responsible for processing credentials, location management, subscription management, etc. In at least one embodiment, several different front ends can service the same user in different transactions. In at least one embodiment, the UDM-FE accesses subscription information stored in the UDR and performs authentication credential processing; user identification processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, the UDM 2124 can also support SMS management, where an SMS-FE implements similar application logic as previously discussed.

[0236] In at least one embodiment, the AF 2126 can provide application influence on traffic routing, access to network capability exposure (NCE), and interaction with policy framework for policy control. In at least one embodiment, NCE can be a mechanism that allows 5GC and AFs 2126 to provide information to each other via NEF 2116, which can be used for edge computing implementations. In at least one embodiment, network operators and third party services can be hosted close to the access point of attachment of a UE 2102 for efficient service delivery with reduced end-to-end latency and load on transport networks. In at least one embodiment, for edge computing implementations, 5GC can choose a UPF 2104 close to the UE 2102 and execute traffic steering from the UPF 2104 to DN 2106 via N6 interface. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by AF 2126. In at least one embodiment, AF 2126 can influence UPF (re)selection and traffic routing. In at least one embodiment, based on operator deployment, when AF 2126 is considered a trusted entity, the network operator can allow AF 2126 to interact directly with relevant NFs.

[0237] In at least one embodiment, the CN 2110 can include an SMSF, which can be responsible for SMS subscription checking and verification, and relaying SM messages to / from the UE 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS-router. In at least one embodiment, the SMS can also interact with AMF 2112 and UDM 2124 for a notification procedure that the UE 2102 is available for SMS transfer (e.g., setting a UE not reachable flag, and notifying UDM 2124 when the UE 2102 is available for SMS).

[0238] In at least one embodiment, the system 2100 can include the following service-based interfaces: Namf: service-based interface exposed by AMF; Nsmf: service-based interface exposed by SMF; Nnef: service-based interface exposed by NEF; Npcf: service-based interface exposed by PCF; Nudm: service-based interface exposed by UDM; Naf: service-based interface exposed by AF; Nnrf: service-based interface exposed by NRF; and Nausf: service-based interface exposed by AUSF.

[0239] In at least one embodiment, system 2100 can include the following reference points: N1: Reference point between UE and AMF; N2: Reference point between (R)AN and AMF; N3: Reference point between (R)AN and UPF; N4: Reference point between SMF and UPF; and N6: Reference point between UPF and Data Network. In at least one embodiment, there can be more reference points and / or service-based interfaces between NFs, however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, a NS reference point can be between a PCF and an AF; a N7 reference point can be between a PCF and a SMF; a N11 reference point between an AMF and a SMF; and / or the like. In at least one embodiment, CN 2110 can include an Nx interface, which is an inter-CN interface between MME and AMF 2112 in order to enable interworking between CN 2110 and CN 7221.

[0240] In at least one embodiment, system 2100 can include multiple RAN nodes, such as (R)AN nodes 2108, where the Xn interface is defined between two or more (R)AN nodes 2108 connected to 5GC 410, between a (R)AN node 2108 (e.g., gNB) and an eNB (e.g., macro RAN node) connected to CN 2110, and / or between two eNBs connected to CN 2110.

[0241] In at least one embodiment, Xn interface can include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, Xn-U can provide guaranteed delivery of user plane PDUs with some exceptions and support / provide data forwarding and flow control functionality. In at least one embodiment, Xn-C can provide management and error handling functionality, functionality to manage the Xn-C interface; mobility support for UEs 2102 in a connected mode (e.g., CM-CONNECTED) including functionality to manage connected mode UE mobility between one or more (R)AN nodes 2108. In at least one embodiment, mobility support can include context transfer from an old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108; and control of user plane tunnels between old (source) serving (R)AN node 2108 to new (target) serving (R)AN node 2108.

[0242] In at least one embodiment, the Xn-U protocol stack can include a transport network layer built on top of an Internet Protocol (IP) transport layer and a GTP-U layer for carrying user plane PDUs on top of a UDP and / or one or more IP layers. In at least one embodiment, the Xn-C protocol stack can include an application layer signaling protocol, referred to as Xn Application Protocol (Xn-AP), and a transport network layer built on top of an SCTP layer. In at least one embodiment, the SCTP layer can be on top of an IP layer. In at least one embodiment, the SCTP layer provides a guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack can be the same as or similar to user plane and / or control plane protocol stacks shown and described herein.

[0243] Figure 22 is an illustration of a control plane protocol stack in accordance with some embodiments. In at least one embodiment, control plane 2200 is illustrated as a communication protocol stack between UE 2002 (or, alternatively, UE 2004), RAN 2016, and MME 2028.

[0244] In at least one embodiment, PHY layer 2202 can transmit or receive information used by MAC layer 2204 over one or more air interfaces. In at least one embodiment, PHY layer 2202 can also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as RRC layer 2210. In at least one embodiment, PHY layer 2202 can further perform error detection on the transport channels, forward error correction (FEC) coding / decoding of the transport channels, modulation / demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and Multiple Input Multiple Output (MIMO) antenna processing.

[0245] In at least one embodiment, MAC layer 2204 can perform mapping between logical channels and transport channels, multiplexing of MAC service data units (SDUs) from one or more logical channels into transport blocks (TB) to be delivered to PHY via transport channels, demultiplexing of MAC SDUs to one or more logical channels from TBs delivered via transport channels from PHY, multiplexing of MAC SDUs onto TBs, scheduling information reporting, error correction through hybrid automatic repeat request (HARQ), and logical channel prioritization.

[0246] In at least one embodiment, RLC layer 2206 can operate in multiple modes of operation, including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, RLC layer 2206 can perform transfer of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transfers, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transfers. In at least one embodiment, RLC layer 2206 can also perform re-segmentation of RLC data PDUs for AM data transfers, reordering of RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC re-establishment.

[0247] In at least one embodiment, PDCP layer 2208 can perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-sequence delivery of upper layer PDUs at re-establishment of lower layers, eliminate duplication of lower layer SDUs at re-establishment of lower layers for RLC AM mapped radio bearers, cipher and decipher control plane data, integrity protect and integrity verify control plane data, perform data

[0248] In at least one embodiment, main services and functions of RRC layer 2210 can include broadcast of system information (e.g., included in master information block (MIB) or system information blocks (SIBs) related to non-access stratum (NAS)), broadcast of system information related to access stratum (AS), paging of UEs in RRC_CONNECTED state, establishment, maintenance and release of an RRC connection between the UE and E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), setup, configuration, maintenance and release of point-to-point Radio Bearers, security functions including key management, inter-RAT mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, MIB and SIBs can include one or more information elements (IEs), which can include individual data fields or data structures.

[0249] In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., LTE-Uu interface) to exchange control plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208, and RRC layer 2210.

[0250] In at least one embodiment, a non-access stratum (NAS) protocol (NAS protocol 2212) forms a highest stratum of the control plane between UE 2002 and MME 2028. In at least one embodiment, NAS protocol 2212 supports mobility of UE 2002 and session management procedures to establish and maintain IP connectivity between UE 2002 and P-GW 2034.

[0251] In at least one embodiment, an Si application protocol (Si-AP) layer (Si-AP layer 2222) can support functions of the Si interface and include elementary procedures (EPs). In at least one embodiment, an EP is a unit of interaction between RAN 2016 and CN 2028. In at least one embodiment, S1-AP layer services can include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transfer, RAN Information Management (RIM), and configuration transfer.

[0252] In at least one embodiment, a stream control transmission protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol / internet protocol (SCTP / IP) layer) (SCTP layer 2220) can ensure reliable delivery of signaling messages between RAN 2016 and MME 2028 based, in part, on IP protocols supported by IP layer 2218. In at least one embodiment, L2 layer 2216 and L1 layer 2214 can refer to communication links (e.g., wired or wireless) used by RAN nodes and MMEs to exchange information.

[0253] In at least one embodiment, RAN 2016 and one or more MMEs 2028 can utilize an S1-MME interface to exchange control plane data via a protocol stack including L1 layer 2214, L2 layer 2216, IP layer 2218, SCTP layer 2220, and Si-AP layer 2222.

[0254] Figure 23 is a diagram of a user plane protocol stack, in accordance with at least one embodiment. In at least one embodiment, user plane 2300 is shown as a communication protocol stack between UE 2002, RAN 2016, S-GW 2030, and P-GW 2034. In at least one embodiment, user plane 2300 can utilize the same protocol layers as control plane 2200. In at least one embodiment, UE 2002 and RAN 2016 can utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including PHY layer 2202, MAC layer 2204, RLC layer 2206, PDCP layer 2208.

[0255] In at least one embodiment, a general packet radio service (GPRS) tunneling protocol (GTP-U) layer (GTP-U layer 2304) for user plane can be used to carry user data within a GPRS core network and between a radio access network and a core network. In at least one embodiment, user data transported can be packets of any size that the protocol stack is designed to handle, including IPv4, IPv6, or PPP encapsulated data. In at least one embodiment, a UDP / IP layer (UDP / IP layer 2302) can provide checksums for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication on selected data flows. In at least one embodiment, RAN 2016 and S-GW 2030 can utilize an S1-U interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, S-GW 2030 and P-GW 2034 can utilize a S5 / S8a interface to exchange user plane data via a protocol stack comprising L1 layer 2214, L2 layer 2216, UDP / IP layer 2302, and GTP-U layer 2304. In at least one embodiment, as discussed above with respect to FIG. 22, NAS protocols support mobility and session management procedures for UE 2002 to establish and maintain IP connectivity between UE 2002 and P-GW 2034. Figure 22

[0256] Figure 24 Components of a core network are shown in accordance with at least one embodiment 2400. In at least one embodiment, components of CN 2038 can be implemented in one physical node or in separate physical nodes including components to read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage mediums (described in further detail below). In at least one embodiment, a logical instantiation of CN 2038 can be referred to as a network slice 2402 (e.g., network slice 2402 is shown to include HSS 2032, MME 2028, and S-GW 2030). In at least one embodiment, a logical instantiation of a portion of CN 2038 can be referred to as a network sub-slice 2404 (e.g., network sub-slice 2404 is shown to include P-GW 2034 and PCRF 2036).

[0257] ​In at least one embodiment, NFV architecture and infrastructure can be used to virtualize one or more network functions onto one or more physical servers that include a combination of industry-standard server hardware, storage hardware, or switches, which can alternatively be replaced by virtualized or reconfigurable logic included in or coupled to one or more physical servers. In at least one embodiment, NFV systems can be used to perform virtual or reconfigurable implementations of one or more EPC components / functions.

[0258] Figure 25 FIG. 25 illustrates a block diagram of components of a system 2500 used to support network function virtualization (NFV), according to at least one embodiment. In at least one embodiment, system 2500 is shown to include a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), a virtualized network function (shown as VNF 2508), an element manager (shown as EM 2510), an NFV orchestrator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0259] In at least one embodiment, VIM 2502 manages resources of NFVI 2504. In at least one embodiment, NFVI 2504 can include physical or virtual resources and applications (including a hypervisor) used to execute system 2500. In at least one embodiment, VIM 2502 can utilize NFVI 2504 to manage life cycle of virtual resources (e.g., creation, maintenance, and tearing down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0260] In at least one embodiment, VNFM 2506 can manage VNF 2508. In at least one embodiment, VNF 2508 can be used to execute EPC components / functions. In at least one embodiment, VNFM 2506 can manage life cycle of VNF 2508 and track performance, faults, and security of virtual aspects of VNF 2508. In at least one embodiment, EM 2510 can track performance, faults, and security of functional aspects of VNF 2508. In at least one embodiment, tracking data from VNFM 2506 and EM 2510 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 can scale up / down the number of VNFs of system 2500.

[0261] In at least one embodiment, NFVO 2512 can coordinate, authorize, release, and occupy resources of NFVI 2504 in order to provide requested services (e.g., to execute EPC functions, components, or slices). In at least one embodiment, NM 2514 can provide a package of end-user functions that are responsible for managing a network that can include network elements that are VNFs, non-virtualized network functions, or both (management of VNFs can occur via EM 2510).

[0262] Computer-based system

[0263] The following figures illustrate, without limitation, exemplary computer-based systems that can be used to implement at least one embodiment.

[0264] Figure 26 A processing system 2600, in accordance with at least one embodiment, is shown. In at least one embodiment, system 2600 includes one or more processor(s) 2602 and one or more graphics processor(s) 2608, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processor(s) 2602 or processor core(s) 2607. In at least one embodiment, processing system 2600 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0265] In at least one embodiment, processing system 2600 can include, or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 2600 is a mobile phone, a smart phone, a tablet device, or a mobile internet device. In at least one embodiment, processing system 2600 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2600 is a television or set-top box device having one or more processor(s) 2602, as well as a graphical interface displayed via one or more graphics processor(s) 2608.

[0266] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 to process instructions which, when executed, perform operations such as operations for systems and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0267] In at least one embodiment, processor 2602 includes cache memory 2604. In at least one embodiment, processor 2602 can have single-level or multi-level internal caches. In at least one embodiment, cache memory is shared among multiple components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level three (L3) cache or last level cache (LLC)) (not shown), which can be shared among processor cores 2607 using known cache coherency techniques. In at least one embodiment, register file 2606 is additionally included in processor 2602, which can include different types of registers to store different kinds of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include a general register file or other registers.

[0268] In at least one embodiment, one or more processors 2602 are coupled with one or more interface buses 2610 for passing communication signals between processor 2602 and other components of system 2600. In at least one embodiment, one or more of interface buses 2610 can be versions of a Peripheral Component Interconnect (PCI) bus or PCI Express bus. In at least one embodiment, one or more of interface buses 2610 can be versions of an Industry Standard Architecture (ISA) bus, a MicroChannel Architecture (MCA) bus, an Intelll bus, a VESA local bus, an Accelerated Graphics Port (AGP) bus, a Video Electronics Standards Association (VESA) bus, or other suitable bus. In at least one embodiment, one or more of interface buses 2610 can be a bus using time-division multiplexing, a bus using Throttling, or another suitable bus structure at one or more embodiments. In at least one embodiment, one or more of interface buses 2610 can be a bus that is not standardized.

[0269] In at least one embodiment, memory device 2620 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, or a

[0270] In at least one embodiment, platform controller hub 2630 enables peripherals to connect to storage devices 2620 and processor 2602 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, audio controller 2646, network controller 2634, firmware interface 2628, wireless transceiver 2626, touch sensors 2625, data storage devices 2624 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage devices 2624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensors 2625 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware, in at least one embodiment, and can be a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 2634 can enable network connectivity to one or more wired networks. In at least one embodiment, a high-performance network controller (not shown) is coupled

[0271] In at least one embodiment, memory controller 2616 and instances of platform controller hub 2630 can be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, platform controller hub 2630 and / or memory controller 2616 can be external to one or more processor(s) 2602. In at least one embodiment, processing system 2600 can include an external memory controller 2616 and platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system-on-a-chip (SoC) configuration.

[0272] Figure 27A computer system 2700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 2700 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 2700 is formed by a processor 2702, which may include execution units for executing instructions. In at least one embodiment, the computer system 2700 may include, but is not limited to, components such as the processor 2702, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 2700 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 2700 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces may also be used.

[0273] In at least one embodiment, the computer system 2700 can be used in other devices, such as handheld devices and embedded applications. Some of the handheld devices in at least one embodiment include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor (“DSP”), a SoC, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0274] In at least one embodiment, computer system 2700 may include, but is not limited to, processor 2702, which may include, but is not limited to, one or more execution units 2708 configured to execute a Computational Unified Device Architecture (“CUDA”). a CUDA program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2700 is a single processor desktop or server system. In at least one embodiment, computer system 2700 can be a multiprocessor system. In at least one embodiment, processor 2702 can include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, in at least one embodiment. In at least one embodiment, processor 2702 can be coupled to a processor bus 2710 that can transmit data signals between processor 2702 and other components in computer system 2700.

[0275] In at least one embodiment, processor 2702 can include, without limitation, a level 1 (“Ll”) internal cache memory (“cache”) 2704. In at least one embodiment, processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, cache memory can reside in the processor 2702’s external. In at least one embodiment, processor 2702 can include a combination of internal and external caches. In at least one embodiment, register file 2706 can store different types of data within various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0276] In at least one embodiment, execution unit 2708, including, without limitation, logic to perform integer and floating point operations, also resides in processor 2702. Processor 2702 can also include microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 2708 can include logic to handle a packed instruction set 2709. In at least one embodiment, by including the packed instruction set 2709 in the instruction set of a general-purpose processor 2702, along with associated circuitry to execute the instructions, the general-purpose processor 2702 can be used to perform the operations on packed data that many multimedia applications use. In at least one embodiment, by using the full width of the processor’s data bus when performing operations on packed data, many multimedia applications can be accelerated as compared to using load / store type architectures, which can require multiple Tens of load and store operations per application.

[0277] In at least one embodiment, execution unit 2708 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 2700 can include, but not limited to, memory 2720. In at least one embodiment, memory 2720 can be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 2720 can store instructions 2719 and / or data 2721 represented by data signals that can be executed by processor 2702.

[0278] In at least one embodiment, system logic chip can be coupled to processor bus 2710 and memory 2720. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 2716, and processor 2702 can communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 can provide a high bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 can initiate data signals to and receive data signals from memory 2720 and other components in computer system 2700, and can bridge data signals between processor bus 2710, memory 2720, and system I / O 2722.

[0279] In at least one embodiment, system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2716 can be coupled to memory 2720 through high bandwidth memory path 2718, and a graphics / video card 2712 can be coupled to MCH 2716 through an Accelerated Graphics Port (“AGP”) interconnect 2714.

[0280] In at least one embodiment, computer system 2700 can use system I / O 2722 as a proprietary hub interface bus to couple MCH 2716 to I / O controller hub (“ICH”) 2730. In at least one embodiment, ICH 2730 can provide direct connections to some I / O devices and a high-speed I / O bus to connect to other I / O devices. In at least one embodiment, the high-speed I / O bus can include, without limitation, a PCI Express bus or a revved version thereof. Examples can include, without limitation, audio controller 2729, firmware hub (“Flash BIOS”) 2728, wireless transceiver 2726, data storage 2724, legacy I / O controller 2723 containing user input 2725 and keyboard interface, serial expansion port 2777 (e.g., USB), and network controller 2734. Data storage 2724 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0281] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 27 An exemplary SoC can be shown. In at least one embodiment, Figure 27 Devices shown in FIG. 27 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 are interconnected using Compute Express Link (CXL) interconnects.

[0282] Figure 28 A system 2800 according to at least one embodiment is shown. In at least one embodiment, system 2800 is an electronic device that utilizes a processor 2810. In at least one embodiment, system 2800 can be, without limitation, a laptop, a tower server, a rack server, a blade server, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0283] In at least one embodiment, system 2800 can include, without limitation, a processor 2810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 2810 is coupled using a bus or interface, such as an I 2a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 28 A system is shown that includes interconnected hardware devices or “chips.” In at least one embodiment, Figure 28 An exemplary SoC can be shown. In at least one embodiment, Figure 28 Devices shown in FIG. 26 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof.

[0284] In at least one embodiment, Figure 28 One or more components of FIG. 26 are interconnected using Compute Express Link (CXL) interconnects.

[0285] In at least one embodiment, Figure 28 may include a display 2824, a touchscreen 2825, a touchpad 2830, a near field communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, an Express Chipset (“EC”) 2835, a Trusted Platform Module (“TPM”) 2838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 2822, a DSP 2860, a solid state disk (“SSD”) or hard disk drive (“HDD”) 2820, a wireless local area network unit (“WLAN”) 2850, a Bluetooth unit 2852, a wireless wide area network unit (“WWAN”) 2856, a Global Positioning System (GPS) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB 3.0 camera), or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented in at least one embodiment in LPDDR3 standard. These components can each be implemented in any suitable manner.

[0286] In at least one embodiment, other components can be communicatively coupled to processor 2810 by components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 can be communicatively coupled to a sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 can be communicatively coupled to EC 2835. In at least one embodiment, a speaker 2863, a headphone 2864, and a microphone (“mic”) 2865 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 2864, which in turn can be communicatively coupled to a DSP 2860. In at least one embodiment, audio unit 2864 can include, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 can be communicatively coupled to a WWAN unit 2856. In at least one embodiment, components such as WLAN unit 2850 and Bluetooth unit 2852, as well as WWAN unit 2856, can be implemented in a next-generation form factor (NGFF).

[0287] Figure 29 An exemplary integrated circuit 2900, in accordance with at least one embodiment, is shown. In at least one embodiment, exemplary integrated circuit 2900 is a SoC, which can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and can additionally include an image processor 2915 and / or a video processor 2920, any of which can be a modular IP core. In at least one embodiment, integrated circuit 2900 includes peripheral or bus logic including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I 2 S / I 2 controller 2940. In at least one embodiment, integrated circuit 2900 can include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. In at least one embodiment, storage can be provided by flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 2965 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970.

[0288] Figure 30A computing system 3000 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processor(s) 3002 and system memory 3004, which communicate via an interconnection path 3005 that can include a memory hub 3005. In at least one embodiment, the memory hub 3005 can be a separate component coupled with one or more processors 3002 via individual communication links 3007A to 3007N. In at least one embodiment, memory hub 3005 can be integrated into one or more processors 3002.

[0289] In at least one embodiment, processing subsystem 3001 includes one or more parallel processor(s) 3012 coupled to memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, communication link 3013 can be one of many such links which can be implemented as standard bus, point-to-point bridges, switched networks, etc. In at least one embodiment, communication link 3013 can be a proprietary multi-pin bus, implemented with custom electronics, or a standard bus protocol (e.g., PCI, PCI Express) implemented with commodity components. In at least one embodiment, parallel processor(s) 3012 form a computationally-intensive, highly parallel processing system that can include multiple processing cores and / or clusters, each of which can execute a respective instance of a processing application in parallel with each other. In at least one embodiment, one or more parallel processor(s) 3012 form a graphics processing subsystem that can output pixels to one or more display device(s) 3010A coupled via I / O subsystem 3011. In at least one embodiment, one or more parallel processor(s) 3012 also can include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 3010B.

[0290] In at least one embodiment, system storage 3014 can connect to I / O hub 3007 to provide storage mechanisms for computing system 3000. In at least one embodiment, I / O switches 3016 can be used to provide interface mechanisms to enable connections between I / O hub 3007 and other components such as network adapter 3018 and / or wireless network adapter 3019 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 3020. In at least one embodiment, network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0291] In at least one embodiment, computing system 3000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and / or variations of the same, which can also be connected to I / O hub 3007. In at least one embodiment, communication paths interconnecting various components in Figure 30 Communication paths interconnecting various components in at least one embodiment can use any suitable protocols including, for example, PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect, or inter-integrated circuit (I2C) protocols).

[0292] In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for graphics and video processing, in at least one embodiment including video codec circuitry for a unified shader core mode, and in at least one embodiment including circuitry optimized for general purpose processing. In at least one embodiment, parallel processor(s) 3012 include circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, parallel processor(s) 3012, memory hub 3005, processor(s) 3002, and I / O hub 3007 can be integrated with one or more other system elements onto a single integrated circuit chip.

[0293] In at least one embodiment, components of computing system 3000 can be integrated into a single package to form a system in a package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 3000 can be integrated into a multichip module (MCM), which can be interconnected with other multichip modules into a modular computing system. In at least one embodiment, I / O subsystem 3011 and display device 3010B are omitted from computing system 3000.

[0294] Processing system

[0295] The following figures illustrate, without limitation, example processing systems that can be used to implement at least one embodiment.

[0296] Figure 31 An accelerated processing unit (“APU”) 3100, in accordance with at least one embodiment, is shown. In at least one embodiment, APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 3100 can be configured to execute application programs such as CUDA programs. In at least one embodiment, APU 3100 includes, without limitation, core complex 3110, graphics complex 3140, fabric 3160, I / O interface 3170, memory controllers 3180, display controllers 3192, and multimedia engines 3194. In at least one embodiment, APU 3100 can include, without limitation, any number of core complexes 3110, any number of graphics complexes 3140, any number of display controllers 3192, and any number of multimedia engines 3194, in any combination. For purposes of illustration, multiple instances of similar objects are denoted in this document with reference numerals identifying the object, and a number in parentheses identifying the instance.

[0297] In at least one embodiment, core complex 3110 is a CPU, graphics complex 3140 is a GPU, and APU 3100 is a processing unit that integrates, without limitation, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to core complex 3110, while other tasks can be assigned to graphics complex 3140. In at least one embodiment, core complex 3110 is configured to execute host executable code derived from CUDA source code, and graphics complex 3140 is configured to execute device executable code derived from CUDA source code.

[0298] In at least one embodiment, core complex 3110 includes, without limitation, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 can include, without limitation, any number of cores 3120 and any combination and number of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0299] In at least one embodiment, each core 3120 includes, without limitation, a fetch / decode unit 3122, an integer execution engine 3124, a floating point execution engine 3126, and an L2 cache 3128. In at least one embodiment, fetch / decode unit 3122 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3124 and floating point execution engine 3126. In at least one embodiment, fetch / decode unit 3122 can simultaneously dispatch one micro-instruction to integer execution engine 3124 and another micro-instruction to floating point execution engine 3126. In at least one embodiment, integer execution engine 3124 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3126 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3122 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3124 and floating point execution engine 3126.

[0300] In at least one embodiment, each core 3120(i) can access L2 cache 3128(i) included in core 3120(i), where i is an integer representing a particular instance of core 3120. In at least one embodiment, each core 3120 included in core complex 3110(j) is connected to other cores 3120 included in core complex 3110(j) via L3 cache 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, cores 3120 included in core complex 3110(j) can access all L3 caches 3130(j) included in core complex 3110(j), where j is an integer representing a particular instance of core complex 3110. In at least one embodiment, L3 cache 3130 can include, without limitation, any number of slices.

[0301] In at least one embodiment, graphics processing engine 3120 is configured to perform graphics processing operations in a highly parallel manner. In at least one embodiment, graphics processing engine 3120 is configured to perform graphics processing operations such as, but not limited to, graphics pipeline operations, pixel operations, geometry computations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics processing engine 3120 is configured to perform graphics-related operations and non-graphics-related operations.

[0302] In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of compute units 3150 and L2 cache 3142. In at least one embodiment, compute units 3150 share L2 cache 3142. In at least one embodiment, L2 cache 3142 is partitioned. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of compute units 3150 and any number (including zero) and type of cache. In at least one embodiment, graphics processing engine 3120 includes, without limitation, any number of specialized graphics hardware.

[0303] In at least one embodiment, each compute unit 3150 includes, without limitation, any number of SIMD units 3152 and shared memory 3154. In at least one embodiment, each SIMD unit 3152 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 3150 can execute any number of thread blocks, but each thread block executes on a single compute unit 3150. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3152 executes a different thread warp. In at least one embodiment, a thread warp is a group of threads (e.g., 16 threads), where each thread in a thread warp belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread warp can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3154.

[0304] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transmissions across core complex 3110, graphics complex 3140, I / O interface 3170, memory controllers 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, APU 3100 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3160 that facilitate data and control transmissions across any number and type of directly or indirectly linked components that can be internal or external to APU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3170. In at least one embodiment, peripheral devices coupled to I / O interface 3170 can include, without limitation, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0305] In at least one embodiment, display controller 3192 displays images on one or more display devices, such as liquid crystal display (“LCD”) devices. In at least one embodiment, multimedia engine 3194 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 3180 facilitate data transfers between APU 3100 and unified system memory 3190. In at least one embodiment, core complex 3110 and graphics complex 3140 share unified system memory 3190.

[0306] In at least one embodiment, APU 3100 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that can be dedicated to one component or shared among multiple components. In at least one embodiment, APU 3100 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which can be component private or shared among any number of components (e.g., core 3120, core complex 3110, SIMD unit 3152, compute unit 3150, and graphics complex 3140).

[0307] Figure 32A CPU 3200 is shown, in accordance with at least one embodiment. In at least one embodiment, CPU 3200 is developed by AMD Corporation, of Santa Clara, California. In at least one embodiment, CPU 3200 can be configured to execute application programs. In at least one embodiment, CPU 3200 is configured to execute host executable code derived from CUDA source code, and an external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 3200 issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU 3200 includes, without limitation, any number of core complexes 3210, fabric 3260, I / O interfaces 3270, and memory controllers 3280.

[0308] In at least one embodiment, core complex 3210 includes, without limitation, cores 3220(1)-3220(4) and L3 cache 3230. In at least one embodiment, core complex 3210 can include, without limitation, any number of cores 3220 and any combination and type of caches. In at least one embodiment, cores 3220 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 3220 is a CPU core.

[0309] In at least one embodiment, each core 3220 includes, without limitation, a fetch / decode unit 3222, an integer execution engine 3224, a floating point execution engine 3226, and an L2 cache 3228. In at least one embodiment, fetch / decode unit 3222 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 3224 and floating point execution engine 3226. In at least one embodiment, fetch / decode unit 3222 can dispatch one micro-instruction to integer execution engine 3224 and another micro-instruction to floating point execution engine 3226 simultaneously. In at least one embodiment, integer execution engine 3224 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 3226 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 3222 dispatches micro-instructions to a single execution engine in place of both integer execution engine 3224 and floating point execution engine 3226.

[0310] In at least one embodiment, each core 3220(i) has access to an L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a particular instance of a core 3220. In at least one embodiment, each core 3220 included in a core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via an L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, a core 3220 included in a core complex 3210(j) has access to all L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a particular instance of a core complex 3210. In at least one embodiment, an L3 cache 3230 can include, without limitation, any number of slices.

[0311] In at least one embodiment, fabric 3260 is a system interconnect that facilitates data and control transfers across core complexes 3210(1)-3210(N) (where N is an integer greater than zero), I / O interface 3270, and memory controllers 3280. In at least one embodiment, CPU 3200 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 3260 that facilitate data and control transfers across any number and type of directly or indirectly linked components that can be internal or external to CPU 3200. In at least one embodiment, I / O interface 3270 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3270. In at least one embodiment, peripheral devices coupled to I / O interface 3270 can include, without limitation, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other types of game controller, a media recording device, an external storage device, a network interface card, etc.

[0312] In at least one embodiment, memory controllers 3280 facilitate data transfers between CPU 3200 and system memory 3290. In at least one embodiment, core complex 3210 and graphics complex 3240 share system memory 3290. In at least one embodiment, CPU 3200 implements a memory subsystem that includes, without limitation, any number and type of memory controllers 3280 and memory devices that can be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 3200 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which can be private to a component or shared among any number of components (e.g., core 3220 and core complex 3210).

[0313] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, a “slice” includes a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, an accelerator integration circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines that are part of graphics acceleration modules. Graphics processing engines can each comprise a separate GPU. Alternatively, graphics processing engines can include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module can be a GPU with a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine can be a separate GPU integrated on a common package, line card, or chip as the CPU.

[0314] An application effective address space 3382 within system memory 3314 stores process elements 3383. In one embodiment, process elements 3383 are stored in response to GPU invocations 3381 from applications 3380 executing on processor 3307. Process elements 3383 contain processing state for corresponding applications 3380. A work descriptor (WD) 3384 contained in process element 3383 can be a single job requested by an application or can contain pointers to a queue of jobs. In at least one embodiment, WD 3384 is a pointer to a job request queue in application effective address space 3382.

[0315] Graphics acceleration module 3346 and / or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, there can be included infrastructure for setting up processing state and sending WDs 3384 to graphics acceleration module 3346 to start jobs in a virtualized environment.

[0316] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 3346 or individual graphics processing engines. As graphics acceleration module 3346 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owning partition and an operating system initializes the accelerator integration circuit for the owning partition when graphics acceleration module 3346 is assigned.

[0317] In operation, a WD fetch unit 3391 in accelerator integration slice 3390 fetches a next WD 3384 including an indication of work to be completed by one or more graphics processing engines of graphics acceleration module 3346. Data from WD 3384 can be stored in registers 3345 used by memory management unit (MMU) 3339, interrupt management circuit 3347, and / or environment management circuit 3348, as shown. At least one embodiment of MMU 3339 includes segment / page walk circuitry to access segment / page tables 3386 within an OS virtual address space 3385. Interrupt management circuit 3347 can handle interrupt events (INTs) 3392 received from graphics acceleration module 3346. Effective addresses 3393 produced by graphics processing engines, when executing graphics operations, are translated to real addresses by MMU 3339.

[0318] In one embodiment, a same set of registers 3345 is replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by a system hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 3390. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0319] Table 1 - Hypervisor Initialized Registers

[0320]

[0321]

[0322] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0323] Table 2 - Operating System Initialized Registers

[0324] 1 Process and thread identification 2 Effective address (EA) environment save / restoration pointer 3 Virtual address (VA) accelerator utilization record pointer 4 Virtual address (VA) storage segment table pointer 5 Authority mask 6 Work descriptor

[0325] In one embodiment, each WD 3384 is specific to a particular graphics processing module 3346 and / or a particular graphics processing engine. It contains all information the graphics processing engine needs to work or work needed, or it can be a pointer to a memory location where an application has set up a command queue of work to be done.

[0326] Figures 34A-34B An exemplary graphics processor according to at least one embodiment is shown. In at least one embodiment, any of the exemplary graphics processors can be fabricated as one or more IP cores. In addition to the graphics processors illustrated, in at least one embodiment, other logic and circuits can be included, including additional graphics processors cores or special-purpose processing cores, peripheral interface controllers or general-purpose processor cores. In at least one embodiment, graphics processor is used in a SoC implementation.

[0327] Figure 34A An exemplary graphics processor 3410 of a SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of a SoC integrated circuit, according to at least one embodiment, can be fabricated using one or more IP cores. In at least one embodiment, Figure 34A Graphics processor 3410 of FIG. 34 is a low power graphics processor core. In at least one embodiment, graphics processor 3410 is a low power graphics processor core. Figure 34B Graphics processor 3440 of FIG. 34 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be Figure 5 Variants of graphics processor 510 of FIG. 5.

[0328] In at least one embodiment, graphics processor 3410 includes a vertex processor 3405 and one or more fragment processor(s) 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D, through 3415N-1, and 3415N). In at least one embodiment, graphics processor 3410 can execute different shader programs via separate logic for vertex processing and / or for fragment / pixel processing. In at least one embodiment, vertex processor 3405 is optimized to execute operations on vertex data that frequently process complex, high-precision calculations for geometry transformations, motion blur, and dynamic shading. In at least one embodiment, one or more fragment processor(s) 3415A-3415N can be optimized to execute more SIMT-based calculations with structured general-purpose programmability. In at least one embodiment, a pinout I / O circuit 3425 is disposed on graphics processor 3410 for communicating with a system processor, memory, or other input / output devices. In at least one embodiment, graphics processor 3410 includes a display engine 3435 optimized to perform processing of multiple tiles of a tiled display in parallel. In at least one embodiment, a display engine 3435 can include memory objects in an L2 cache or system memory not explicitly specified by code in a shader program. In at least one embodiment, display engine 3435 can include one or more propagators (e.g., for stencil operations, general arithmetic operations, etc.). In at least one embodiment, a display engine 3435 can include one or more propagation units to perform gather operations on a set or multiple sets of data, propagate the gathered data through a computational unit, and scatter the results. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data in parallel. In at least one embodiment, a display engine 3435 can include a propagation unit to gather, compute on, and scatter multiple sets of data in parallel with multiple computational units.

[0329] In at least one embodiment, graphics processor 3410 additionally includes one or more MMU(s) 3420A-3420B, cache memory 3425A-3425B, and circuit interconnect 3430A-3430B. In at least one embodiment, one or more MMU(s) 3420A-3420B provide for virtual to physical address mapping for graphics processor 3410, including for vertex processor 3405 and / or fragment processor 3415A-3415N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 3425A-3425B. In at least one embodiment, one or more MMU(s) 3420A-3420B can be synchronized with other MMUs within Figure 5 one or more application processors 505, image processors 515, and / or video processors 520 such that each processor 505-520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3430A-3430B enable graphics processor 3410 to interface with other IP cores within a SoC, either via an internal bus, as shown, or via a direct connection.

[0330] In at least one embodiment, graphics processor 3440 includes Figure 34Aone or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnect 3430A-3430B of graphics processor 3410. In at least one embodiment, graphics processor 3440 includes one or more shader core(s) 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, through 3455N-1, and 3455N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a plurality of shader cores can be varied. In at least one embodiment, graphics processor 3440 includes an inter-core task manager 3445, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A-3455N and tiling unit 3458 to accelerate tiling operations for tile-based rendering in which render operations for a scene are subdivided in image space, e.g., to utilize spatial coherence within a scene or to optimize use of internal caches.

[0331] Figure 35A A graphics core 3500 according to at least one embodiment is shown. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410. Figure 24 A graphics core 3500 according to at least one embodiment is shown. In at least one embodiment, graphics core 3500 can be included within graphics processor 2410. Figure 34B In at least one embodiment, graphics core 3500 includes shared instruction cache 3502, texture unit 3518, and cache / shared memory 3520, which are common to execution resources within graphics core 3500. In at least one embodiment, graphics core 3500 can include a number of slices 3501A-3501N or partitions of each core, and graphics processor can include multiple instances of graphics core 3500. Slices 3501A-3501N can include support logic including a local instruction cache 3504A-3504N, a thread scheduler 3506A-3506N, a thread dispatcher 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, slices 3501A-3501N can include a set of additional functional units (AFUs) 3512A-3512N, floating point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address computation units (ACUs) 3513A-3513N, double precision floating point units (DPFPUs) 3515A-3515N, and matrix processing units (MPUs) 3517A-3517N.

[0332] In one embodiment, FPUs 3514A-3514N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 3515A-3515N can perform double-precision (64-bit) floating point operations. In at least one embodiment, ALUs 3516A-3516N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 3517A-3517N can also be configured for mixed precision matrix operations, including half-precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 3517A-3517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated General Matrix to Matrix multiplication (GEMM). In at least one embodiment, AFUs 3512A-3512N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0333] Figure 35B A general purpose graphics processing unit (GPGPU) 3530 in at least one embodiment is shown. In at least one embodiment, GPGPU 3530 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3530 can be configured to enable highly parallel compute operations to be performed by a GPU array. In at least one embodiment, GPGPU 3530 can be directly linked to other instances of GPGPU 3530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, host interface 3532 is a PCIe interface. In at least one embodiment, host interface 3532 can be a vendor-specific communications interface or communication structure. In at least one embodiment, GPGPU 3530 receives commands from a host processor and uses a global scheduler 3534 to dispatch execution threads associated with those commands to a group of compute clusters 3536A-3536H. In at least one embodiment, compute clusters 3536A-3536H share a cache memory 3538. In at least one embodiment, cache memory 3538 can be used as an upper level cache for cache memory within compute clusters 3536A-3536H.

[0334] In at least one embodiment, GPGPU 3530 includes memory 3544A-3544B coupled with compute clusters 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, memory 3544A-3544B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0335] In at least one embodiment, compute clusters 3536A-3536H each include a group of graphics cores, such as graphics core 3500, which can include multiple types of integer and floating point logic units that can perform compute operations at various precisions, including suitable for computations related to CUDA programs. In at least one embodiment, at least a subset of floating point units in each compute cluster 3536A-3536H can be configured to perform 16- or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. Figure 35A

[0336] In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as compute clusters. In at least one embodiment, compute clusters 3536A-3536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate over host interface 3532. In at least one embodiment, GPGPU 3530 includes I / O hub 3539 that couples GPGPU 3530 with GPU link 3540, enabling a direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a specialized GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate over a network device accessible via host interface 3532. In at least one embodiment, GPU link 3540 can be configured to enable a connection to a host processor, in addition to or in place of host interface 3532. In at least one embodiment, GPGPU 3530 can be configured to execute CUDA programs.

[0337] Figure 36A ​A parallel processor 3600 according to at least one embodiment is shown. In at least one embodiment, various components of parallel processor 3600 can be implemented using one or more integrated circuits, for example, programmable processors, application specific integrated circuits (ASICs), or FPGAs.

[0338] In at least one embodiment, parallel processor 3600 includes a parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 can be directly connected to other devices. In at least one embodiment, I / O unit 3604 connects with other devices via use of a hub or switch interface, for example, memory hub 605. In at least one embodiment, connections between memory hub 605 and I / O unit 3604 form a communication link. In at least one embodiment, I / O unit 3604 connects with a host interface 3606 and a memory crossbar 3616, where host interface 3606 receives commands directed to performing processing operations and memory crossbar 3616 receives commands directed to performing memory operations.

[0339] In at least one embodiment, when host interface 3606 receives a command buffer via I / O unit 3604, host interface 3606 can direct work operations to execute those commands to front end 3608. In at least one embodiment, front end 3608 couples with a scheduler 3610, which is configured to assign commands or other work items to processing array 3612. In at least one embodiment, scheduler 3610 ensures that processing array 3612 is properly configured and in an active state before assigning tasks to processing array 3612 of processing array 3612. In at least one embodiment, scheduler 3610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 3610 is configurable to perform complex scheduling and work distribution operations in a coarse and fine grain fashion, enabling quick preemption and context switching for threads executing on processing array 3612. In at least one embodiment, host software can prove a workload for scheduling on processing array 3612 through one of a number of graphics processing doorbells. In at least one embodiment, workload can then be automatically distributed by scheduler 3610 logic within microcontroller including scheduler 3610 on processing array 3612.

[0340] In at least one embodiment, processing array 3612 can include up to “N” processing clusters (e.g., cluster 3614A, cluster 3614B, through cluster 3614N). In at least one embodiment, each cluster 3614A-3614N of processing array 3612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 can allocate work to clusters 3614A-3614N of processing array 3612 using various scheduling and / or work distribution algorithms, which can be determined at least in part by workload arriving at processing array 3612, capacity of processing array 3612, and / or capacities of individual clusters 3614A-3614N within processing array 3612. In at least one embodiment, scheduling can be handled dynamically by scheduler 3610, or can be aided in part by compiler logic during compilation of program logic configured for execution by processing array 3612. In at least one embodiment, different clusters 3614A-3614N of processing array 3612 can be allocated for processing different types of programs or for performing different types of computations.

[0341] In at least one embodiment, processing array 3612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 is configured to perform general-purpose parallel compute operations. In at least one embodiment, processing array 3612 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0342] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 can include additional logic to support performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, tessellation logic, and other vertex processing logic. In at least one embodiment, processing array 3612 can be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel

[0343] In at least one embodiment, when parallel processing unit 3602 is used to perform graphics processing, scheduler 3610 can be configured to divide incoming workloads into tasks of approximately equal size to better enable distribution of graphics processing operations across multiple clusters 3614A-3614N of processing array 3612. In at least one embodiment, portions of processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display on a display device. In at least one embodiment, intermediate data produced by one or more of clusters 3614A-3614N can be stored in buffers to allow transmission of intermediate data between clusters 3614A-3614N for further processing.

[0344] In at least one embodiment, processing array 3612 can receive processing tasks to be executed from scheduler 3610, which receives commands defining the processing tasks from front end 3608. In at least one embodiment, a processing task can include an index into data to be processed, which can include surface (patch) data, raw data, vertex data, and / or pixel data, for example, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 3610 can be configured to fetch the index corresponding to a task, or can receive the index from front end 3608. In at least one embodiment, front end 3608 can be configured to ensure that processing array 3612 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0345] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to a parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed by the processing array 3612, as well as the I / O unit 3604, via a memory crossbar 3616. In at least one embodiment, memory crossbar 3616 can be used to transfer data between memory elements and the processing array 3612. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar. In at least one embodiment, memory crossbar 3616 can be configured to handle memory requests from a number of coherent agents. In at least one embodiment, memory crossbar 3616 can be implemented as a fully connected crossbar.

[0346] In at least one embodiment, memory units 3624A-3624N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 3624A-3624N, allowing partition units 3620A-3620N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 3622. In at least one embodiment, local instances of parallel processor memory 3622 can be excluded in favor of a unified memory design that utilizes system memory in combination with local cache memory.

[0347] In at least one embodiment, any of clusters 3614A-3614N of processing array 3612 can process data that is to be written into any of memory units 3624A-3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transmit outputs of each cluster 3614A-3614N to any partition unit 3620A-3620N or another cluster 3614A-3614N, which can perform other processing operations on the outputs. In at least one embodiment, each cluster 3614A-3614N can communicate with memory interface 3618 through memory crossbar 3616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 3616 has a connection to memory interface 3618 to communicate with I / O unit 3604, as well as a local instance of parallel processor memory 3622, to enable processing elements within different processing clusters 3614A-3614N to communicate with system memory or other memory that is not local to the parallel processing elements 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate traffic streams between clusters 3614A-3614N and partition units 3620A-3620N.

[0348] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate in coordination with each other to enable single program multi-processing (SPMP). In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate as a single unit even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0349] Figure 36B Processing cluster 3694 is shown according to at least one embodiment. In at least one embodiment, processing cluster 3694 is included in a parallel processing unit. In at least one embodiment, processing cluster 3694 is a Figure 36Aone of the processing clusters 3614A-3614N. In at least one embodiment, processing cluster 3694 can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executed by a particular group of one or more processing clusters. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with no or negligible program overhead. In at least one embodiment, Single Instruction Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster 3694.

[0350] In at least one embodiment, operation of processing cluster 3694 can be controlled via a pipeline manager 3632 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 3632 receives instructions from scheduler 3610 and manages execution of those instructions by graphics multiprocessor 3634 and / or texture unit 3636, in at least one embodiment, graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within processing cluster 3694. In at least one embodiment, one or more instances of graphics multiprocessor 3634 can be included within processing cluster 3694. In at least one embodiment, graphics multiprocessor 3634 can process data and a data crossbar 3640 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 3632 can facilitate distribution by specifying destinations for processed data as a function of the destination’s source in either a fixed function or switched fabric manner. Figure 36A

[0351] In at least one embodiment, each graphics multiprocessor 3634 within processing cluster 3694 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units (LSUs), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which instructions are issued at a first stage, passed through stages of the pipeline with each stage performing at least one instruction, and results from a last stage are used as inputs to subsequent instruction units at a subsequent stage in the pipeline. In at least one embodiment, there can be one instruction unit for every parallel thread. In at least one embodiment, each instruction unit is configured to process a single instruction and to pipeline data into that instruction unit to improve execution rates.

[0352] ​In at least one embodiment, instructions sent to the processing cluster 3694 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 3634. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 3634. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 3634. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 3634, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 3634.

[0353] In at least one embodiment, the graphics multiprocessor 3634 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 3634 may forgo the internal cache and use a cache memory within the processing cluster 3694 (e.g., L1 cache 3648). In at least one embodiment, each graphics multiprocessor 3634 may also access partition units (e.g., Figure 36A The L2 cache is located within partition units 3620A-3620N, which are shared among all processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 3634 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 3602 can be used as global memory. In at least one embodiment, the processing cluster 3694 includes multiple instances of the graphics multiprocessor 3634, which can share common instructions and data that can be stored in the L1 cache 3648.

[0354] In at least one embodiment, each processing cluster 3694 may include an MMU 3645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 3645 may reside in Figure 36AIn at least one embodiment, MMU 3645 includes a set of page table entries (PTEs) used for mapping virtual addresses into physical addresses for graphics processing unit 3600. In at least one embodiment, MMU 3645 can include address translation lookaside buffer (TLB) or cache for receiving and storing translations of virtual addresses into physical addresses in order to facilitate access to pages stored in system memory 3614. In at least one embodiment, MMU 3645 can be configured to receive address translation requests from graphics multiprocessor 3634 relating to address translations for virtual addresses that are not stored in MMU 3645.

[0355] In at least one embodiment, processing cluster 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data can be read from an internal texture Ll cache (not shown) or from an Ll cache within graphics multiprocessor 3634 and stored in L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to data crossbar 3640 in order to provide processed task data to another processing cluster 3694 for further processing or to store processed task data in an L2 cache, local parallel processor memory, or system memory via memory crossbar 3616. Figure 36A In at least one embodiment, pre-Raster Operations Unit (preROP) 3642 is configured to receive data from graphics multiprocessor 3634, direct data to ROP unit in a graphics processing pipeline, which can be located in same or different processing cluster 3694 as preROP 3642, in at least one embodiment. In at least one embodiment, preROP 3642 can be configured to perform optimizations related to color blending, organize pixel color data, and perform address translation.

[0356] Figure 36C Graphics multiprocessor 3696 is shown in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 3696 is a GPC as described herein. In at least one embodiment, graphics multiprocessor 3696 forms at least part of graphics processing cluster 3694. In at least one embodiment, graphics multiprocessor 3696 is one of a plurality of graphics processing units 3634 within a processing cluster 3694. Figure 36Bgraphics processor 3634. In at least one embodiment, graphics processor 3696 couples with the pipeline manager 3632 of processing cluster 3694. In at least one embodiment, graphics processor 3696 has an execution pipeline that includes, without limitation, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSU(s) 3666. GPGPU cores 3662 and LSUs 3666 couple with cache memory 3672 and shared memory 3670 through memory and cache interconnect 3668.

[0357] In at least one embodiment, instruction cache 3652 receives a stream of instructions 3650 to execute from pipeline manager 3632. In at least one embodiment, instructions are cached in instruction cache 3652 and dispatched for execution by instruction unit 3654. In one embodiment, instruction unit 3654 can dispatch instructions to the various functional units available on GPGPU cores 3662 including, but not limited to, integer algebraic units, floating point units, and others. In at least one embodiment, instructions are dispatched as groups, e.g., thread groups, which are executed via a thread group instruction. In at least one embodiment, thread groups are managed by thread group scheduler 3658 which receives thread groups from thread dispatcher 3660 and further manages execution of the thread groups by scheduling threads of the thread groups to the various functional units of GPGPU cores 3662. In at least one embodiment, thread group scheduler 3658 can allocate the threads of a thread group to the functional units of GPGPU cores 3662 based on various factors including but not limited to what percentage of the threads of the thread group are already executing on the functional units, load balances between functional units, and so forth.

[0358] In at least one embodiment, register file 3658 provides a set of registers for functional units of graphics processor 3696. In at least one embodiment, register file 3658 provides temporary storage for operands of the data

[0359] In at least one embodiment, GPGPU cores 3662 can each include FPUs and / or ALUs for executing instructions for graphics processing. GPGPU cores 3662 can be similar to each other in architecture or can differ from each other in architecture. In at least one embodiment, a first portion of GPGPU cores 3662 includes single precision FPUs and integer ALUs, while a second portion of GPGPU cores includes double precision FPUs. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics processor 3696 can additionally include one or more fixed function or special purpose logic units to perform specific functions or handle specific data types. In at least one embodiment, one or more of GPGPU cores 3662 can also include fixed or special function logic.

[0360] In at least one embodiment, GPGPU cores 3662 include SIMD logic capable of

[0361] In at least one embodiment, memory and cache interconnect 3668 is an interconnect network that connects each functional unit of graphics multiprocessor 3696 to register file 3658 and shared memory 3670. In at least one embodiment, memory and cache interconnect 3668 is a crossbar interconnect that allows LSUs 3666 to implement load and store operations between shared memory 3670 and register file 3658. In at least one embodiment, register file 3658 can operate at same frequency as GPGPU cores 3662, resulting in very low latency for data transfers between GPGPU cores 3662 and register file 3658. In at least one embodiment, shared memory 3670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 3696. In at least one embodiment, cache memory 3672 can be used to store data for threads executing on functional units and texture data for textures accessed by these threads. In at least one embodiment, shared memory 3670 can also be used as a program managed cache.

[0362] In at least one embodiment, parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores by a bus or other interconnect (e.g., a high speed

[0363] General Purpose Computing

[0364] The following figures illustrate, without limitation, exemplary software configurations used in general purpose computing to implement at least one embodiment.

[0365] Figure 37A software stack of a programming platform is shown, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate compute tasks. In at least one embodiment, a software developer can access a programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, a programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL TM ), SYCL, or Intel One API.

[0366] In at least one embodiment, software stack 3700 of a programming platform provides an execution environment for application 3701. In at least one embodiment, application 3701 can include any computer software capable of launching on software stack 3700. In at least one embodiment, application 3701 can include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0367] In at least one embodiment, application 3701 and software stack 3700 run on hardware 3707. In at least one embodiment, hardware 3707 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, software stack 3700 can be vendor-specific and compatible only with devices from a particular vendor, e.g., with CUDA. In at least one embodiment, software stack 3700 can be used with devices from different vendors, e.g., with OpenCL. In at least one embodiment, hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform compute tasks. In at least one embodiment, in contrast to a host within hardware 3707, which can include, but is not limited to, a CPU (but can also include a computing device) and its memory, a device within hardware 3707 can include, but is not limited to, a GPU, FPGA, AI engine, or other computing device (but can also include a CPU) and its memory.

[0368] In at least one embodiment, software stack 3700 of a programming platform includes, without limitation, a plurality of libraries 3703, a runtime 3705, and a device kernel driver 3706. In at least one embodiment, each of libraries 3703 can include data and programming code that can be used by computer programs and leveraged during software development. In at least one embodiment, libraries 3703 can include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, libraries 3703 include functions that are optimized for execution on one or more types of devices. In at least one embodiment, libraries 3703 can include, without limitation, functions for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, libraries 3803 are associated with corresponding APIs 3802, which can include one or more APIs that expose functions implemented in libraries 3803.

[0369] In at least one embodiment, application 3701 is written as source code that is compiled into executable code, as discussed in more detail below with respect to FIG. 37B. Figure 42 In at least one embodiment, executable code of application 3701 can run, at least partially, on an execution environment provided by software stack 3700. In at least one embodiment, during execution of application 3701, code can be derived that needs to run on a device (as opposed to a host). In such a case, in at least one embodiment, runtime 3705 can be invoked to load and launch the necessary code on a device. In at least one embodiment, runtime 3705 can include any technically feasible runtime system capable of supporting execution of application 3701.

[0370] In at least one embodiment, runtime 3705 is implemented as one or more runtime libraries associated with corresponding APIs (which are shown as APIs 3704). In at least one embodiment, one or more such runtime libraries can include, without limitation, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions can include, without limitation, functions for allocating, deallocating, and copying device memory, as well as transferring data between host memory and device memory. In at least one embodiment, execution control functions can include, without limitation, functions for launching functions on a device (sometimes referred to as “kernels” when functions are global functions that can be called from a host), and functions for setting attribute values in buffers maintained by a runtime library for a given function to be executed on a device.

[0371] In at least one embodiment, runtime libraries and corresponding APIs 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number) of APIs can expose a higher-level set of functions. In at least one embodiment, high-level runtime APIs can be built on top of low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of language-independent runtime APIs.

[0372] In at least one embodiment, device kernel driver 3706 is configured to facilitate communication with underlying devices. In at least one embodiment, device kernel driver 3706 can provide low-level functions relied upon by APIs such as APIs 3704 and / or other software. In at least one embodiment, device kernel driver 3706 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 3706 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a particular target device at runtime (caching compiled binary code), which is sometimes also referred to as “final” code. In at least one embodiment, doing so can allow final code to run on a target device that can not have existed when source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code can be compiled into binary code offline without requiring device kernel driver 3706 to compile IR code at runtime.

[0373] Figure 38 A CUDA implementation of software stack 3700 is shown in accordance with at least one embodiment. Figure 37 In at least one embodiment, CUDA software stack 3800 on which application 3801 can be launched includes CUDA libraries 3803, CUDA runtime 3805, CUDA driver 3807, and device kernel driver 3808. In at least one embodiment, CUDA software stack 3800 executes on hardware 3809, which can include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0374] In at least one embodiment, application 3801, CUDA runtime 3805, and device kernel driver 3808 can perform similar functions as application 3701, runtime 3705, and device kernel driver 3706, respectively, described above in connection with Figure 37CUDA Driver 3807, which includes a library (libcuda.so) that implements the CUDA Driver API 3806. In at least one embodiment, similar to the CUDA Runtime API 3804 implemented by the CUDA Runtime Library (cudart), the CUDA Driver API 3806 can expose, without limitation, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, among others. In at least one embodiment, the CUDA Driver API 3806 differs from the CUDA Runtime API 3804 in that the CUDA Runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA Runtime API 3804, in at least one embodiment, the CUDA Driver API 3806 is a low-level API that provides more granular control over a device, particularly with respect to contexts and module loading. In at least one embodiment, the CUDA Driver API 3806 can expose functions for context management that are not exposed by the CUDA Runtime API 3804. In at least one embodiment, the CUDA Driver API 3806 is also language agnostic and supports, for example, OpenCL in addition to the CUDA Runtime API 3804. Further, in at least one embodiment, development libraries including the CUDA Runtime 3805 can be considered separate from driver components, including the user-mode CUDA Driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as a “display” driver).

[0375] In at least one embodiment, CUDA Libraries 3803 can include, without limitation, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that can be utilized by parallel computing applications, such as application 3801. In at least one embodiment, CUDA Libraries 3803 can include mathematical libraries such as a cuBLAS library, which is an implementation of basic linear algebra subprograms (“BLAS”) for performing linear algebra operations; a cuFFT library for computing fast Fourier transforms (“FFTs”), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA Libraries 3803 can include deep learning libraries such as a cuDNN library for primitives of deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

[0376] Figure 39 FIG. 39 shows a block diagram of a system including a GPU 3900, in accordance with at least one embodiment Figure 37ROCm implementation of the software stack 3700. In at least one embodiment, the ROCm software stack 3900 on which the application 3901 can launch includes a language runtime 3903, a system runtime 3905, a thunk 3907, a ROCm kernel driver 3908, and a device kernel driver 3909. In at least one embodiment, the ROCm software stack 3900 executes on hardware 3909, which can include a GPU that supports ROCm, which is developed by AMD Corporation of Santa Clara, California.

[0377] In at least one embodiment, the application 3901 can perform similar functions as the application 3701 discussed above in conjunction with Figure 37 In addition, in at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform similar functions as the runtime 3705 discussed above in conjunction with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-agnostic runtime that implements the ROCr system runtime API 3904 and utilizes a Heterogeneous System Architecture (“HAS”) runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with AMD GPUs, including functions for memory management, execution control dispatching of kernels through the architecture, error handling, system and agent information, and runtime initialization and shutdown, among others. In at least one embodiment, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904 as compared to the system runtime 3905. In at least one embodiment, a language runtime API can include, without limitation, a Portable Compute Interface (“HIP”) language runtime API, a Heterogeneous Compute Compiler (“HCC”) language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with functionally similar versions of CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes functions similar to the CUDA runtime API 3804 discussed above in conjunction with Figure 38

[0378] ​In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with underlying ROCm drivers 3908. In at least one embodiment, ROCm drivers 3908 are ROCk drivers, which are a combination of AMDGPU drivers and HAS kernel drivers (amdkfd). In at least one embodiment, AMDGPU drivers are device kernel drivers for GPUs developed by AMD that perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, HAS kernel drivers are drivers that allow different types of processors to more efficiently share system resources via hardware features.

[0379] In at least one embodiment, various libraries (not shown) can be included in ROCm software stack 3900 above language runtime 3903 and provide similar functionality to CUDA libraries 3803 discussed above in connection with Figure 38 In at least one embodiment, various libraries can include, but are not limited to, math, deep learning, and / or other libraries such as a hipBLAS library that implements similar functions to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, etc.

[0380] Figure 40 An OpenCL implementation of software stack 3700 is shown in accordance with at least one embodiment. Figure 37 In at least one embodiment, OpenCL software stack 4000 on which application 4001 can be launched includes an OpenCL framework 4005, an OpenCL runtime 4006, and drivers 4007. In at least one embodiment, OpenCL software stack 4000 executes on hardware 4008 that is not vendor-specific. In at least one embodiment, because device is supported by different vendors, specific OpenCL drivers can be required to interoperate with hardware from such vendors.

[0381] In at least one embodiment, application 4001, OpenCL runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with Figure 37 In at least one embodiment, application 4001 also includes OpenCL kernels 4002 having code that is to be executed on a device. In at least one embodiment, application 4001, OpenCL runtime 4006, device kernel drivers 4007, and hardware 4008 can perform similar functions to those discussed above in connection with

[0382] In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to that host. In at least one embodiment, OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4003 and runtime API 4005. In at least one embodiment, runtime API 4005 uses a context to manage execution of kernels on a device. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 4005 can use to manage that device’s command queues, program and kernel objects, shared memory objects, etc. In at least one embodiment, platform API 4003 exposes functions that allow device contexts to be used for selecting and initializing devices, submitting work to devices via command queues, enabling data transfers to and from devices, etc. Additionally, in at least one embodiment, OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0383] In at least one embodiment, compiler 4004 is also included in OpenCL framework 4005. In at least one embodiment, source code can be compiled offline before executing an application or online during execution of an application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 4004, which is included to represent any number of compilers that can be used to compile source and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0384] Figure 41 Software supported by a programming platform is shown, according to at least one embodiment. In at least one embodiment, programming platform 4104 is configured to support various programming models 4103, middleware and / or libraries 4102, and frameworks 4101 that an application 4100 can rely on. In at least one embodiment, application 4100 can be an AI / ML application implemented using, for example, a deep learning framework (in at least one embodiment, MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIACollective Communications Library (“NCCL”), and / or NVIDIADeveloper Data Loading Library (“DALI”) CUDA libraries to provide accelerated computation on underlying hardware.

[0385] In at least one embodiment, the programming platform 4104 can be a combination of the above-described components. Figure 38 , Figure 39 and Figure 40 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 4104 supports multiple programming models 4103, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 4103 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 4103 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0386] In at least one embodiment, the library and / or middleware 4102 provides an abstract implementation of the programming model 4104. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those available from the programming platform 4104, such middleware also includes software that provides services to applications. In at least one embodiment, the library and / or middleware 4102 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 4102 may include NCCL and ROCm communication collection library (“RCCL”) libraries, which provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0387] In at least one embodiment, the application framework 4101 depends on libraries and / or middleware 4102. In at least one embodiment, each application framework 4101 is a software framework for implementing a standard structure of application software. In at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks.

[0388] Figure 42 Compilation code according to at least one embodiment is shown to be used in Figures 37-40on one of the programming platforms. In at least one embodiment, compiler 4201 receives source code 4200, which includes both host code as well as device code. In at least one embodiment, compiler 4201 is configured to convert source code 4200 into host executable code 4202 for execution on a host and device executable code 4203 for execution on a device. In at least one embodiment, source code 4200 can be compiled offline prior to execution of an application, or online during execution of an application.

[0389] In at least one embodiment, source code 4200 can include code in any programming language supported by compiler 4201, such as C++, C, Fortran, etc. In at least one embodiment, source code 4200 can be included in a single-source file that has a mix of host code and device code, with locations of device code indicated therein. In at least one embodiment, the single-source file can be a.cu file that includes CUDA code or a.hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 4200 can include multiple source code files, rather than a single-source file, with host code and device code separated.

[0390] In at least one embodiment, compiler 4201 is configured to compile source code 4200 into host executable code 4202 for execution on a host and device executable code 4203 for execution on a device. In at least one embodiment, compiler 4201 performs operations including parsing source code 4200 into an abstract syntax tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 4200 includes a single-source file, compiler 4201 can separate device code from host code in such single-source file, compile device code and host code into device executable code 4203 and host executable code 4202, respectively, and link device executable code 4203 and host executable code 4202 together in a single file, as discussed below with respect to FIG. 4B. Figure 26 discussed in more detail.

[0391] In at least one embodiment, host executable code 4202 and device executable code 4203 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 4202 can include native object code, while device executable code 4203 can include PTX intermediate representation code. In the case of ROCm, in at least one embodiment, both host executable code 4202 and device executable code 4203 can include object binary code.

[0392] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative configurations, certain preferred embodiments thereof have been shown by way of example in the drawings and have been described above in detail. It should be understood, however, that there is no intent to limit the disclosure to the particular forms disclosed but on the contrary, the intention is to cover all modifications, alternative configurations, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.

[0393] Unless otherwise stated or contradicted by context, the use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be interpreted in an inclusive rather than an exclusive sense, as that term is used in patent law. The terms "including," "has," "having," and "comprises" and variations thereof, are to be construed as open-ended terms (meaning "including, but not limited to") unless otherwise noted or contradicted by context. The term "connected" (when used without modification) is to be construed as partly or wholly encompassed in, attached to, or joined together, even if there are some intervening items. Unless otherwise indicated herein, the reference within this document to a range of values is intended merely as a shorthand way of referring individually to each numerical value falling within the range, and each individual value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, unless otherwise indicated or contradicted by context, the use of the term "set" (e.g., "set of items") or "subset" is to be construed as a non-empty set of one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but rather the subset and the corresponding set can be equal.

[0394] Unless explicitly indicated otherwise, or otherwise clearly contradicted by context, a phrase such as "at least one of A, B, and C" or "at least one of A, B, or C" is understood to generally mean that an item, term, etc. can be A, or B, or C, or any non-empty subset of the set of A, B, and C. In at least one embodiment with a set of three members, the conjunctive phrases "at least one of A, B, and C" and "at least one of A, B, or C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is generally not intended to imply that certain embodiments require the existence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise noted or as is clear from context, the term "plurality" indicates a state of multiplicity (e.g., "a plurality of items" indicates multiple items). In at least one embodiment, a plurality of items has a quantity of at least two, but can be more if explicitly indicated or indicated by context. Furthermore, unless otherwise noted or as is clear from context, the phrase "based on" means "based, at least in part, on" rather than "based solely on."

[0395] The operations of a process described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process, such as those described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions to implement the process, and the code (e.g., executable instructions, one or more computer programs or one or more applications) is executed by hardware or combinations thereof available on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, in at least one embodiment, which is non-transitory, that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues). In at least one embodiment, the code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having stored thereon executable instructions that, as a result of being executed by one or more processors of a computer system (i.e., as a result of being executed), cause a computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes multiple non-transitory computer-readable storage media, and individual non-transitory storage media of the multiple non-transitory computer-readable storage media lack all of the code, with the multiple non-transitory computer-readable storage media collectively storing the entire code. In at least one embodiment, executable instructions are executed by different processors to cause different instructions to be executed by different processors, in at least one embodiment, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit (“CPU”) executes some instructions, while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors, and different processors execute different subsets of the instructions.

[0396] Accordingly, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform operations of processes described herein, and such a computer system is configured with applicable hardware and / or software to enable implementation of operations. Moreover, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system including multiple devices operating in different manners such that the distributed computer system performs operations described herein and such that a single device does not perform all operations.

[0397] The use of any and all examples, or exemplary language (e.g., "such as") provided herein, only intends to better illuminate embodiments of the disclosure and does not pose a limitation to the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0398] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0399] In the description and in the claims, the terms "coupled" and "connected," along with derivatives thereof, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in at least one embodiment, "connected" or "coupled" is used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0400] Unless specifically stated otherwise, it can be appreciated that throughout the specification terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and / or processes of a computer or computing system, or similar electronic

[0401] In a similar manner, the term "processor" can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. As used in at least one embodiment, a "processor" can be a CPU or GPU. A "computing platform" can include one or more processors. As used herein, in at least one embodiment, a "software" process can include software and / or hardware entities such as tasks, threads, and intelligent agents that perform work over time. Also, each process can refer to multiple processes to sequentially or concurrently execute instructions, either continuously or intermittently. The terms "system" and "method" can be used interchangeably herein, as long as the system can embody one or more methods, and the method can be considered a system.

[0402] In this document, obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine can be referenced. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Providing, outputting, transmitting, sending, or presenting analog or digital data can also be referenced. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter of a function call, a parameter of an application programming interface, or an interprocess communication mechanism.

[0403] Although the above discussion discusses one implementation in at least one embodiment of the described technology, other architectures can be used to implement the described functionality and are intended to be within the scope of the present disclosure. Moreover, although specific

[0404] Further, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A data center cooling system comprising: a cold plate including an opening and a cavity, the cold plate hermetically sealed around at least one computing component at the cavity; and a receiver plate for an area around the at least one computing component, wherein the cold plate is attached to the receiver plate, the receiver plate enables the cold plate to be hermetically sealed around the at least one computing component, the cavity includes a fluid within, the cold plate includes a first heat exchanger loop inside the cold plate, the receiver plate includes a second heat exchanger loop inside the receiver plate, the first heat exchanger loop and the second heat exchanger loop include a coolant or refrigerant therein, and the second heat exchanger loop maintains a different path between the coolant or refrigerant and the fluid within the cavity.

2. The data center cooling system of claim 1, further comprising: a self-sealing port associated with the cold plate for receiving the fluid into the cold plate and for maintaining the fluid within the cold plate.

3. The data center cooling system of claim 1, further comprising: a flow controller associated with the cold plate for maintaining the fluid within the cold plate for a determined amount of time.

4. The data center cooling system of claim 1, wherein: the receiver plate enables the cold plate to be hermetically sealed around the area and between the receiver plate and the opening of the cold plate.

5. The data center cooling system of claim 1, further comprising: the first heat exchanger loop or the second heat exchanger loop for passing the coolant or refrigerant through the cold plate or the receiver plate, the coolant or refrigerant absorbs heat from the fluid, the fluid has engineered and dielectric properties.

6. The data center cooling system of claim 1, wherein: the receiver plate is removably sealed to the area and includes a first seal thereon for receiving a second seal associated with the cold plate, a body of the receiver plate or the cold plate includes at least one pair of tabs for locking the opening to the receiver plate.

7. The data center cooling system of claim 1, further comprising: at least one flow controller associated with a rack or at least one server carrying the at least one computing component, the at least one flow controller for enabling the cold plate to receive the fluid into the cold plate and for maintaining the fluid within the cold plate.

8. The data center cooling system of claim 1, further comprising: at least one flow controller associated with a rack or at least one server carrying the at least one computing component, the at least one flow controller for controlling a first pressure of the fluid into the cold plate or a second pressure of the fluid within the cold plate.

9. The data center cooling system of claim 1, further comprising: at least one manifold associated with a server cooling loop for the fluid and a fluid source maintained separately from an auxiliary coolant manifold associated with an auxiliary cooling loop for providing coolant or refrigerant from a coolant distribution unit CDU to a heat exchanger within the cold plate.

10. The data center cooling system of claim 1, further comprising: at least one flow controller associated with the cold plate for controlling a first pressure of the fluid into the cold plate or a second pressure of the fluid within the cold plate.

11. A data center cooling system, comprising: a cold plate including an opening and a cavity; a first seal that hermetically seals the cold plate at the cavity such that the cold plate includes at least one computing component in the cavity; and a receiver plate for the at least one computing component, wherein the receiver plate surrounds an area of the at least one computing component, the receiver plate and the first seal hermetically seal the cold plate, the cavity and the receiver plate both include a fluid to submerge at least a portion of the at least one computing component, the cold plate includes a first heat exchanger loop inside the cold plate, the receiver plate further includes a second heat exchanger loop inside the receiver plate, the first heat exchanger loop and the second heat exchanger loop include a coolant or refrigerant, and the second heat exchanger loop maintains a different path between the coolant or refrigerant and the fluid within the cavity and the receiver plate.

12. The data center cooling system of claim 11, further comprising: a self-sealing port associated with the cold plate for receiving the fluid into the cold plate and for maintaining the fluid within the cold plate.

13. The data center cooling system of claim 11, wherein: the receiver plate is for enabling the cold plate to be hermetically sealed around the area and between the receiver plate and the opening of the cold plate.

14. The data center cooling system of claim 11, further comprising: the first heat exchanger loop for passing a coolant or refrigerant through the cold plate, the coolant or refrigerant absorbing heat from the fluid.

15. The data center cooling system of claim 11, further comprising: at least one flow controller associated with the cold plate for enabling the cold plate to receive the fluid into the cold plate and for maintaining the fluid within the cold plate.

16. A method for a data center liquid cooling system, comprising: providing a cold plate including an opening and a cavity; determining that at least one computing component is submersibly cooled within a server; determining an area surrounding the at least one computing component associated with the cold plate; using a receiver plate for the at least one computing component to be able to surround the area; and ​ enable the cold plate to be hermetically sealed to the area by the receiver plate to enable the at least one computing component to be within the cavity and the receiver plate, wherein the cavity includes a fluid within the cavity, the cold plate includes a first heat exchanger loop located inside the cold plate, the receiver plate includes a second heat exchanger loop located inside the receiver plate, the first heat exchanger loop and the second heat exchanger loop include a coolant or refrigerant therein, and the second heat exchanger loop maintains a different path between the coolant or refrigerant and the fluid.

17. The method of claim 16, further comprising: enabling a self-sealing port of the cold plate to receive the fluid into the cold plate and to maintain the fluid within the cold plate.

18. The method of claim 16, further comprising: enabling a flow controller associated with the cold plate to maintain the fluid within the cold plate for a determined amount of time.

19. The method of claim 16, further comprising: enabling the cold plate to be hermetically sealed around the area and between the receiver plate and the opening of the cold plate.

20. The method of claim 16, further comprising: providing the first heat exchanger loop or the second heat exchanger loop to pass a coolant or refrigerant through the cold plate or the receiver plate; and causing the coolant or refrigerant to absorb heat from the fluid.

21. The method of claim 16, further comprising: enabling the receiver plate to be removably sealed to the area and including a first seal thereon; enabling the first seal to receive a second seal associated with the cold plate; and enabling at least one pair of tabs to be implemented on a body of the receiver plate or the cold plate for locking the opening onto the receiver plate.

22. The method of claim 16, further comprising: using at least one flow controller associated with a rack or with at least one server carrying the at least one computing component to enable the cold plate to receive the fluid into the cold plate and to maintain the fluid within the cold plate.

23. The method of claim 16, further comprising: using at least one flow controller associated with a rack or with at least one server carrying the at least one computing component to control a first pressure of the fluid into the cold plate or a second pressure of the fluid within the cold plate.

24. The method of claim 16, further comprising: using at least one manifold associated with a server cooling loop to provide a path between a fluid source and a cold plate for the fluid; and providing an auxiliary cooling manifold associated with an auxiliary cooling loop for passing a coolant or refrigerant from a coolant distribution unit (CDU) to a heat exchanger within the cold plate. ​ ​ ​

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