Semiconductor Devices

Abstract

The problem of the present invention is to suppress the change ΔVth of the threshold voltage in a thin film transistor (TFT) formed by an oxide semiconductor. The representative means of the present invention for solving such a problem are as follows. A semiconductor device, which has a TFT formed by an oxide semiconductor, is characterized in that the oxide semiconductor has a channel region 104, a source region 1042, a drain region 1043, and an LDD (Lightly Doped Drain) region 1041 between the channel region and the source region and the drain region, the resistivity of the LDD region 1041 is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region, the source electrode 108 is formed overlapping with the source region 1042, the drain electrode 109 is formed overlapping with the drain region 1043, and the thickness of the LDD region 1041 of the oxide semiconductor is greater than the thickness of the channel region 104.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a TFT capable of reducing fluctuation in threshold voltage (Vth). Background Art

[0002] Thin Film Transistor (TFT) is widely used in liquid crystal display devices, organic EL display devices, etc., and can also be used in micro LED display devices, electronic paper, etc. In addition, it can also be used as a switching element for sensors, etc. Most of the TFTs used in some image display devices and semiconductor devices containing sensors operate at a higher driving voltage than conventional TFTs.

[0003] In TFT, a high electric field is generated between the channel region and the drain region, and hot carriers are generated in this part. Due to the influence of hot carriers, the threshold voltage (Vth) of the TFT changes. This phenomenon can be alleviated by forming an LDD (Lightly Doped Drain) region with a resistance transition between the channel region and the drain region.

[0004] Patent document 1 describes the following structure: in a top-gate TFT, the source region and the drain region are formed by plasma treatment of an oxide semiconductor, and the LDD region is formed by contacting a SiN film. Patent document 2 describes the following structure: a top-gate oxide semiconductor TFT is composed of a first oxide semiconductor constituting a channel region, and a second oxide semiconductor constituting a source and drain region, and in the second oxide semiconductor, the portion in contact with the channel of the first oxide semiconductor has a higher resistance, and the other portions have a lower resistance. It is described that the parasitic capacitance with the gate electrode is thereby reduced. It is also described that in the second oxide semiconductor, the portion with a larger resistance is made to work as an LDD region.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2017-76785

[0008] Patent Document 2: Japanese Patent Application Publication No. 2017-135408 Summary of the invention

[0009] Problems to be solved by the invention

[0010] In TFTs using polysilicon, an LDD region is formed to solve the problem of hot carriers generated between the channel and the drain. In contrast, in TFTs using wide-gap oxide semiconductors, impact ionization and avalanche breakdown are less likely to occur, and the problem of hot carriers is less likely to occur.

[0011] However, if the driving voltage of the TFT increases, the problem of hot carriers also occurs in the oxide semiconductor. For example, in some semiconductor devices, the gate voltage of the TFT is sometimes operated at around 38 V. In such high-voltage operation, the change of Vth caused by hot carrier degradation becomes significant.

[0012] An object of the present invention is to realize a structure that suppresses variation in Vth in a TFT using an oxide semiconductor.

[0013] Means for solving problems

[0014] The present invention overcomes the above problems, and the specific means are as follows.

[0015] (1) A semiconductor device having a TFT formed of an oxide semiconductor, characterized in that the oxide semiconductor has a channel region, a source region, a drain region, and a transition region between the channel region and the source region, and a transition region between the channel region and the drain region, the resistivity of the transition region is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region, the source electrode is formed to overlap with the source region, the drain electrode is formed to overlap with the drain region, and the thickness of the transition region of the oxide semiconductor is greater than the thickness of the channel.

[0016] (2) A semiconductor device having a TFT formed of an oxide semiconductor, characterized in that the oxide semiconductor has a channel region, a source region, a drain region, and a transition region between the channel region and the source region, and a transition region between the channel region and the drain region, the resistivity of the transition region is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region, the source electrode is formed overlapping with the source region, the drain electrode is formed overlapping with the drain region, a first gate insulating film is formed covering the oxide semiconductor, a second gate insulating film is formed covering the first gate insulating film, a through hole is formed in the second gate insulating film at a portion corresponding to the transition region, and a first gate electrode is formed covering the second gate insulating film and the through hole.

[0017] (3) A semiconductor device having a TFT formed of an oxide semiconductor, characterized in that the oxide semiconductor has a channel region, a source region, a drain region, a transition region between the channel region and the source region, and a transition region between the channel region and the drain region, the resistivity of the transition region is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region, the source electrode is formed overlapping with the source region, the drain electrode is formed overlapping with the drain region, the thickness of the central portion of the channel region is less than 60 nm, and the transition region is doped with ions for improving conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [ Figure 1 ] is a cross-sectional view of a TFT formed by an oxide semiconductor.

[0019] [ Figure 2 ] is a graph showing the change ΔVth of the threshold voltage.

[0020] [ Figure 3 ] is a cross-sectional view showing a partial layer structure of a semiconductor device using a TFT formed of an oxide semiconductor.

[0021] [ Figure 4 ] is an equivalent circuit of a semiconductor device using a TFT formed by an oxide semiconductor as a switching element.

[0022] [ Figure 5 ] is a detailed cross-sectional view of a dual-gate TFT using an oxide semiconductor.

[0023] [ Figure 6 ] is a graph showing the relationship between the film thickness of the oxide semiconductor (OS) and the change ΔVth of the threshold voltage.

[0024] [ Figure 7 ] is a graph showing the relationship between the length of LDD and the change ΔVth of the threshold voltage.

[0025] [ Figure 8 ] is a cross-sectional view of the oxide semiconductor TFT based on Example 1.

[0026] [ Fig. 9 ] is a cross-sectional view of another example of an oxide semiconductor TFT based on Example 1.

[0027] [ Fig.10 ] is a cross-sectional view of another example of an oxide semiconductor TFT based on Example 1.

[0028] [ Fig.11A ] is a cross-sectional view showing the first step in the first manufacturing method.

[0029] [ Fig. 11B ] is a cross-sectional view showing the second step in the first manufacturing method.

[0030] [ Fig. 11C ] is a cross-sectional view showing the third step in the first manufacturing method.

[0031] [ Fig.11D ] is a cross-sectional view showing the fourth step in the first manufacturing method.

[0032] [ Fig.11E ] is a cross-sectional view showing the fifth step in the first manufacturing method.

[0033] [ Fig.11F ] is a cross-sectional view showing the sixth step in the first manufacturing method.

[0034] [ Fig.11G ] is a cross-sectional view showing the seventh step in the first manufacturing method.

[0035] [ Fig.11H ] is a cross-sectional view showing the 8th step in the first manufacturing method.

[0036] [ Fig. 12A ] is a cross-sectional view showing the first step in the second manufacturing method.

[0037] [ Fig. 12B ] is a cross-sectional view showing the second step in the second manufacturing method.

[0038] [ Fig. 12C ] is a cross-sectional view showing the third step in the second manufacturing method.

[0039] [ Fig.12D ] is a cross-sectional view showing the fourth step in the second manufacturing method.

[0040] [ Fig.12E ] is a cross-sectional view showing the fifth step in the second manufacturing method.

[0041] [ Fig.12F ] is a cross-sectional view showing the sixth step in the second manufacturing method.

[0042] [ Figure 12G ] is a cross-sectional view showing the seventh step in the second manufacturing method.

[0043] [ Fig.12H ] is a cross-sectional view showing the 8th step in the second manufacturing method.

[0044] [ Fig.13A ] is a cross-sectional view showing the first step in the third manufacturing method.

[0045] [ Fig. 13B] is a cross-sectional view showing the second step in the third manufacturing method.

[0046] [ Fig. 13C ] is a cross-sectional view showing the third step in the third manufacturing method.

[0047] [ Fig.13D ] is a cross-sectional view showing the fourth step in the third manufacturing method.

[0048] [ Fig.13E ] is a cross-sectional view showing the fifth step in the third manufacturing method.

[0049] [ Fig.13F ] is a cross-sectional view showing the sixth step in the third manufacturing method.

[0050] [ Fig.14A ] is a cross-sectional view showing the first step of the first mode of Example 2. [ Fig. 14B ] is a cross-sectional view showing the second step of the first mode of Example 2. [ Fig.15A ] is a cross-sectional view showing the first step of the second mode of Example 2. [ Fig. 15B ] is a cross-sectional view showing the second step of the second mode of Example 2. [ Fig.16A ] is a cross-sectional view showing the first step of the first mode of Example 3. [ Fig. 16B ] is a cross-sectional view showing the second step of the first mode of Example 3. [ Fig.17A ] is a cross-sectional view showing the first step of the second mode of Example 3. [ Fig. 17B ] is a cross-sectional view showing the second step of the second method of Example 3. DETAILED DESCRIPTION

[0051] Hereinafter, the present invention will be described in detail using examples.

[0052] Example 1

[0053] Figure 1 2 is a cross-sectional view of a general oxide semiconductor. Hereinafter, an oxide semiconductor may also be referred to as an OS (Oxide Semiconductor). Figure 1 Although this is a top-gate TFT, the following description is the same also in the case of a bottom-gate TFT. Figure 1 In the present invention, a base film 90 is formed on a TFT substrate 100 formed of glass, and an oxide semiconductor 104 is formed on the base film 90. As the base film 90, a silicon oxide film (hereinafter referred to as a SiO film) capable of supplying oxygen is used.

[0054] In the oxide semiconductor, both sides of the channel region 104 serve as a source region 1042 and a drain region 1043. The source region 1042 and the drain region 1043 are formed by, for example, performing plasma treatment or ion implantation on the oxide semiconductor.

[0055] A gate insulating film 120 is formed to cover the oxide semiconductor 104. The gate insulating film 120 is formed of a SiO film. The reason for this is that oxygen can be supplied to the oxide semiconductor 104. A gate electrode 107 is formed on the gate insulating film 120. An interlayer insulating film 130 is formed to cover the gate electrode 107. Through holes are formed in the gate insulating film 120 and the interlayer insulating film 130, which can realize the connection between the drain region 1043 of the oxide semiconductor 104 and the drain electrode 109, or the connection between the source region 1042 and the source electrode 108.

[0056] In a TFT using an n-type channel, a portion of the channel region 104 where a high electric field is generated near the boundary between the channel region 104 and the drain region 1043 generates hot carriers in this portion. During the operation of the TFT, the hot carriers are accumulated in the gate insulating film 120. Thus, the threshold voltage Vth of the TFT varies.

[0057] Figure 2 Graph showing changes in threshold voltage Vth of a TFT using an oxide semiconductor. Figure 2 In the graph, the horizontal axis is the gate voltage (Vg) and the vertical axis is the drain current (A). The vertical axis is a logarithmic scale. The drain current also changes with the drain voltage Vd. Figure 2 , the case where the drain voltage Vd is 0.1V, the case where it is 15V, and the case where it is 30V are recorded. Figure 2 In FIG. 1 , the dotted line represents the initial characteristic of the threshold voltage Vth, and the solid line represents the characteristic after the TFT is operated.

[0058] At once Figure 2 As for the dotted line, the initial threshold voltage Vth is 0V. Figure 2 The solid line shows that when the gate voltage Vg is 38V, the threshold voltage Vth changes to 28V when Vd is 0.1V and to 22V when Vd is 15V or 30V. Generally, compared with polysilicon TFTs, oxide semiconductors are less susceptible to hot carrier degradation and threshold voltage Vth changes, but if they are operated at high voltages, Figure 2 As shown, this will bring about very big changes.

[0059] The present invention solves the problem of variation in threshold voltage Vth by forming an LDD between a channel and a drain. In particular, the present invention is characterized by the configuration of the LDD. Figure 31 is a cross-sectional view showing a TFT formed of an oxide semiconductor and its adjacent layers in a semiconductor device. Figure 3 The equivalent circuit formed in is as follows Figure 4 As shown. Figure 4 In the embodiment, the TFT operates as a switching element for storing charges corresponding to a signal in the storage capacitor Cs. The storage capacitor Cs corresponds to, for example, a pixel capacitor in an imaging device.

[0060] Figure 3 In the figure, the left side is a TFT and the right side is a storage capacitor Cs. The TFT is a dual-gate TFT having gate electrodes on both the lower and upper sides of the oxide semiconductor. Figure 3 On the left side of the glass substrate 100, a gate electrode 101 is formed, a first lower gate insulating film 102 is formed by covering the gate electrode 101 with silicon nitride (hereinafter referred to as SiN), and a second lower gate insulating film 103 is formed by covering the first lower gate insulating film 102 with SiO. An oxide semiconductor 104 is formed on the second lower gate insulating film 103.

[0061] A metal source electrode 108 is stacked on one side of the oxide semiconductor 104, and a metal drain electrode 109 is stacked on the other side. The oxide semiconductor 104, the source electrode 108, and the drain electrode 109 are covered with a first upper gate insulating film 105 made of SiO, and the first upper gate insulating film 105 is covered with a second upper gate insulating film 106 made of SiN. As for the layers in contact with the oxide semiconductor 104, both the upper layer and the lower layer are formed of SiO. The reason for this is that oxygen can be supplied to the oxide semiconductor 104 from SiO. An upper gate electrode 107 is formed on the second upper gate insulating film 106.

[0062] The upper gate electrode 107 and the second upper gate insulating film 106 are covered with a planarization film 111 made of, for example, an organic film. A capacitor electrode 112 constituting one electrode of a storage capacitor is formed on the planarization film 111. In the case of a display device, it becomes a pixel electrode made of, for example, ITO (Indium Tin Oxide).

[0063] Figure 3 In the embodiment, through holes are formed in the first upper gate insulating film 105 and the second upper gate insulating film 106 to connect the relay electrode 110 to the drain electrode 109. In addition, through holes are formed in the planarizing film 111 to connect the capacitor electrode 112 to the relay electrode 111. It should be noted that the capacitor electrode 112 also extends to the upper side of the planarizing film 111. Figure 3 On the right side of , a storage capacitor Cs is formed between the common electrode 114 .

[0064] exist Figure 3On the right side of the substrate 100, the common wiring 113 extends on the substrate 100 and is connected to the common electrode 114 formed on the second lower gate insulating film 103 via the through holes formed in the first lower gate insulating film 102 and the second lower gate insulating film 103. A storage capacitor Cs is formed between the common electrode 114 and the capacitor electrode 112. Figure 3 The storage capacitor Cs is formed by sandwiching the thick planarization film 111, so it will not become a large capacitor. However, if a large capacitor is required, the storage capacitor Cs can be formed by sandwiching other insulating films.

[0065] Figure 5 This is an enlarged cross-sectional view near the TFT. Figure 5 In FIG. 1 , the lower gate insulating film 140 is simplified and described as a single SiO film. Figure 5 In the embodiment, the oxide semiconductor 104 has a double gate structure with a lower gate electrode 101 on the lower side and an upper gate electrode 107 on the upper side. A source electrode 108 formed of metal is stacked on the left side of the oxide semiconductor 104, and a drain electrode 109 formed of metal is stacked on the right side of the oxide semiconductor 104.

[0066] exist Figure 5 In the oxide semiconductor 104, the blank part in the center is the channel region 104, the shallow part is the LDD region 1401, and the deep part is the source region 1042 or the drain region 1043. As for the oxide semiconductor in the part stacked with metal, oxygen is taken away by the metal, so it becomes conductive and becomes the source region 1042 or the drain region 1043. In addition, since oxygen diffuses from the oxide semiconductor near the source region 1042 or the drain region 1043 to the drain region 1043 or the source region 1042, there is less oxygen than in the channel part. Therefore, for this part, the resistance of the oxide semiconductor is smaller than the channel and larger than the source region 1042 or the drain region 1043. That is, this area can function as LDD1041. However, if only the drain electrode 109 and the source electrode 108 are stacked on the oxide semiconductor 104, it cannot be a solution with sufficient threshold voltage variation ΔVth.

[0067] Figure 6 : is a graph showing the relationship between the film thickness of the oxide semiconductor and the change ΔVth in the threshold voltage. Figure 6 The horizontal axis is Figure 5 The corresponding oxide semiconductor (OS) film thickness (nm), the vertical axis is the change in threshold voltage Vth ΔVth (V). Figure 6 As shown, when the film thickness of the oxide semiconductor 104 exceeds 55 nm, the change ΔVth of the threshold voltage decreases sharply. When the film thickness is 85 nm or more, the change ΔVth of the threshold voltage is hardly observed.

[0068] Here, it is considered that the change ΔVth in the threshold voltage is caused by the hot carriers in the LDD region 1041 being accumulated in the gate insulating film 105. Therefore, Figure 6 The effect of the film thickness of the oxide semiconductor 104 in the LDD region 1041 can be considered to be the effect of the film thickness of the LDD region 1041. On the other hand, if the film thickness of the oxide semiconductor channel region 104 increases, the OFF current increases. Therefore, the film thickness of the oxide semiconductor in the channel region 104 cannot be large. The thickness of the channel region 104 is preferably less than 60nm.

[0069] Thus, in order to suppress the change ΔVth of the threshold voltage and suppress the increase of the OFF current, the film thickness of the oxide semiconductor can be made thinner in the channel region 104 and thicker in the LDD region 1041. Specifically, the film thickness t1 of the oxide semiconductor in the channel region 104 is made less than 60nm in consideration of the OFF current, and the film thickness t2 of the oxide semiconductor in the LDD region 1041 is made greater than 85nm in consideration of the change ΔVth of the threshold voltage. In other words, it is preferred that t2 is greater than t1 by 25nm or more. The thickness of the channel region 104 is measured at the central part of the channel region, and the thickness of the LDD region 1041 is measured at the central part of the LDD region.

[0070] The variation ΔVth of the threshold voltage is also affected by the length of the LDD region 1041 . Figure 7 : is a graph showing the relationship between the length of the LDD region 1041 and the change ΔVth in the threshold voltage. It should be noted that, in this case, the length of the LDD region 1041 can be referred to as the length in the channel length direction. Figure 7 The horizontal axis represents the length (μm) of the LDD region 1041 , and the vertical axis represents the change ΔVth (V) in the threshold voltage. Figure 7 In the embodiment, when the length of the LDD region 1041 is from 0 to 1 μm, the change ΔVth of the threshold voltage is sharply reduced. In addition, when the length of the LDD region 1041 is 2 μm or more, the change ΔVth of the threshold voltage can be suppressed to substantially zero.

[0071] Regarding the length L1 of the LDD region 1041 in Embodiment 1, for example, Figure 8 As shown, it can be defined as the distance from the end of the drain electrode 109 to the step portion where the film thickness changes between the channel region 104 and the LDD region 1041. That is, by making the length of the LDD region 1041 greater than 2 μm and making the film thickness of the LDD region 1041 greater than the film thickness of the channel region, the change ΔVth of the threshold voltage can be effectively suppressed.

[0072] Figure 8 Detailed cross-sectional view of the oxide semiconductor TFT according to Example 1. Figure 8 In the oxide semiconductor, the blank portion in the center is the channel region 104 , the shallow portion is the LDD region 1401 , and the deep portion is the source region 1042 or the drain region 1043 . Figure 8 and Figure 5 The difference lies in that the film thickness of the oxide semiconductor constituting the TFT is different in the channel region 104, the LDD region 1041, and the drain region 1043 (the same applies to the source region 1042). That is, Figure 8 In order to suppress the variation ΔVth of the threshold voltage and prevent an increase in the OFF current, the thickness of the channel region 104 of the oxide semiconductor is made smaller than the thickness of the LDD region 1041 .

[0073] Figure 8 Another feature is that the thickness t3 of the drain region 1043 (or the source region 1042) of the oxide semiconductor is greater than the thickness t2 of the LDD region 1041 of the oxide semiconductor. The difference is more than 10nm, preferably 10nm to 15nm. As for the thickness t2 of the LDD region 1041 being greater than the thickness t3 of the drain region 1043, it is caused by the LDD region 1041 being slightly etched when the drain electrode 109 covering the drain region 1043 is etched. That is, the reason is that the metal drain electrode 109 is completely removed from the LDD region 1041. The specific process for realizing this structure is described in Figure 11.

[0074] Figure 8 This is the case where the TFT is a so-called double-gate TFT. The present invention is applicable not only to the case of a double-gate type but also to the case of a top-gate type or a bottom-gate type. Fig. 9 This is the case where the TFT is a bottom-gate type. Fig.10 This is the case of a top-gate TFT. In addition to the gate electrode configuration, Fig. 9 and Fig.10 Both Figure 8 same.

[0075] FIG. 11A to FIG. 11H To illustrate the use of Figure 8 , Fig. 9 , Fig.10 104 is a cross-sectional view of a first manufacturing method for forming an oxide semiconductor near the channel region 104. In each figure, the oxide semiconductor 104 is formed on the lower gate insulating film 140. The first manufacturing method is characterized in that in order to form an oxide semiconductor having different film thicknesses in the channel region 104 and the LDD region 1041, the oxide semiconductor 104 is formed using a second process.

[0076] Fig.11AThis is a cross-sectional view showing a state in which the oxide semiconductor 104 is entirely covered on the insulating film 140 , and a resist 500 is formed on portions of the oxide semiconductor 104 corresponding to the LDD region 1041 , the source region 1042 , and the drain region 1043 . Fig. 11B This is a cross-sectional view showing a state in which the oxide semiconductor 104 is etched using the resist 500 .

[0077] Fig. 11C For the general Fig. 11B The resist 500 is peeled off and the entire surface is covered with the oxide semiconductor 104 again. Fig. 11C The dotted line indicates that Fig. 11B The oxide semiconductor 104 is initially shown to be formed in an island-like area. Fig.11D This is a cross-sectional view showing a state in which a resist 500 is formed so that only the oxide semiconductor 104 constituting the TFT remains. Fig.11E A cross-sectional view showing the following state: Fig.11D The oxide semiconductor 104 is etched in a state of being etched, and then the resist 500 is removed, thereby forming the oxide semiconductor film 104 having a locally different film thickness.

[0078] Fig.11F This is a cross-sectional view showing a state in which the metal film 150 for forming the source electrode 1042 or the drain electrode 1043 is formed. Fig.11E The oxide semiconductor 104 formed in the process is covered, and then the resist 500 is patterned to form a source electrode 1042 and a drain electrode 1043 . Fig.11G To illustrate the use Fig.11F 104 is a cross-sectional view of a state in which the metal film 150 is etched through the resist 500 formed in FIG. 104 to form the source electrode 1042 and the drain electrode 1043 .

[0079] Here, in order to reliably remove the metal film 150 from the channel region 104 and the LDD region 1041, it is necessary to slightly etch the channel region 104 and the LDD region 1041 in addition to etching the metal film 150. Since the oxide semiconductor 104 can be slightly etched using the conditions for etching the metal film 150, the oxide semiconductor 104 can be etched continuously with the etching of the metal film 150. This process results in a difference (t3-t2) between the thickness t3 of the drain region 1043 (source region 1042) of the oxide semiconductor and the film thickness t2 of the LDD region 1041.

[0080] Fig.11H To show from Fig.11G A cross-sectional view showing a state where the resist 500 has been removed. Fig.11HIn the embodiment, after a period of time and in the subsequent heat process, oxygen is taken away from the drain region 1043 and the source region 1042 of the oxide semiconductor 104 by the drain electrode 109 and the source electrode 108, and the drain region 1043 and the source region 1042 remain conductive. On the other hand, oxygen diffuses from the LDD region 1041 to the drain region 1043 or the source region 1042, and the specific resistance of the LDD region 1041 is larger than that of the drain region 1043 (source region 1042) and smaller than that of the channel region 104.

[0081] FIG. 12A to FIG. 12H To show that in order to achieve Figure 8 , Fig. 9 , Fig.10 1 and 10. In each figure, the oxide semiconductor 104 is formed on the lower gate insulating film 140. The second manufacturing method is characterized in that in order to form an oxide semiconductor with different film thicknesses in the channel region 104 and the LDD region 1041, a half-etching technique is used to form the oxide semiconductor 104 with a film thickness difference.

[0082] Fig. 12A This is a cross-sectional view showing a state in which an oxide semiconductor 104 having the same thickness as the drain region 1043 (source region 1042 ) is coated on the entire surface of the insulating film 140 , and a resist 500 is formed in portions corresponding to the LDD region 1041 , the drain region 1043 , and the source region 1042 . Fig. 12B This is a cross-sectional view showing a state in which the oxide semiconductor 104 is etched using the resist 500 until a difference in film thickness between the drain region 1043 (source region 1042 ) and the channel region 104 is reached. Fig. 12C To show from Fig. 12B The cross-sectional view of the state in which the resist 500 is removed.

[0083] Fig.12D This is a cross-sectional view showing a state in which a resist 500 is formed so that only the oxide semiconductor 104 constituting the TFT remains. Fig.12E This is a cross-sectional view showing a state in which only the oxide semiconductor 104 constituting the TFT is left and the other oxide semiconductors 104 are removed using a resist 500. In this way, the oxide semiconductor 104 having a difference in film thickness is formed.

[0084] Then, if Fig.12F , Figure 12G , Fig.12H As shown, the drain electrode 109 and the source electrode 108 are formed of metal, and the channel region 104, the LDD region 1041, the drain region 1043 and the source region 1042 are formed in the oxide semiconductor. Fig.12F , Figure 12G , Fig.12H The process shown is Fig.11F , Fig.11G , Fig.11H The processes shown are the same, so the description is omitted.

[0085] FIG. 13A to FIG. 13F To show that in order to achieve Figure 8 , Fig. 9 , Fig.10 1 and 10. In each figure, the oxide semiconductor 104 is formed on the lower gate insulating film 140. The third manufacturing method is characterized in that, in order to form oxide semiconductors with different film thicknesses in the channel region 104, the LDD region 1041, the source region 1042, and the drain region, a technique of etching the oxide semiconductor by retreating the resist 500 when forming the drain electrode 109 and the source electrode 108 is used.

[0086] Fig.13A This is a cross-sectional view showing a state where the oxide semiconductor 104 is patterned and then covered with a metal film 150 for forming a source electrode 108 and a drain electrode 109. The film thickness of the oxide semiconductor 104 in this state is the same as that of the source region 1042 and the drain region 1043 in the final TFT.

[0087] Fig. 13B This is a cross-sectional view showing a state in which patterning of the resist 500 for etching the oxide semiconductor 104 to form the channel region 104 is performed together with patterning of the source electrode 108 and the drain electrode 109 . Fig. 13C This is a cross-sectional view showing a state in which the metal 150 is etched using the resist 500 to form the source electrode 108 and the drain electrode 109 , and simultaneously, a portion of the oxide semiconductor 104 is also etched to form a channel region 104 in the oxide semiconductor 104 . Fig. 13C The thickness t11 of the channel region 104 of the oxide semiconductor in the embodiment is thicker than the final thickness t1. This is because the channel region 104 is etched again in a subsequent step.

[0088] Fig.13D A cross-sectional view showing the following state: Fig. 13C The resist 500 in a state of being removed is retreated using oxygen plasma or the like. After the resist 500 is retreated using oxygen plasma, a part of the source electrode 108 and the drain electrode 109 and the channel region 104 of the oxide semiconductor are exposed.

[0089] Fig.13EA cross-sectional view showing a state where the source electrode 1042, the drain electrode 1043, and the oxide semiconductor 104 are etched using the retreated resist 500. In this etching, the channel region 104 of the oxide semiconductor is etched to t1, which is the final thickness. In addition, after the source electrode 108 and the drain electrode 109 are etched, in order to reliably form the LDD region 1041 in the oxide semiconductor, the oxide semiconductor corresponding to the LDD region 1041 is also slightly etched. Therefore, in the oxide semiconductor, the film thickness t2 corresponding to the LDD region 1041 is smaller than the film thickness t3 corresponding to the source region 1042 and the drain region 1043. In this way, the final shapes of the oxide semiconductor 104, the drain electrode 108, and the source electrode 109 are determined.

[0090] Fig.13F For the general Fig.13E The state after the resist 500 in the electrode is peeled off. In this state, oxygen is taken away by the metal source electrode 108 and the drain electrode 109 in the drain region 1042 and the source region 1043 of the oxide semiconductor, and the oxide semiconductor is turned on. In addition, since oxygen diffuses into the source region 1042 or the drain region 1043 in the LDD region 1041, the resistivity is smaller than that of the channel region 104. However, the resistivity of the LDD region 1041 is greater than the resistivity of the source region 1042 and the drain region 1043.

[0091] Thus, according to the configuration of Example 1, the LDD region 1041 can be reliably formed in a TFT using an oxide semiconductor, and a change ΔVth in the threshold voltage can be suppressed. In addition, an increase in OFF current can also be suppressed.

[0092] Example 2

[0093] Fig.14A and Fig. 14B This is a cross-sectional view showing the first aspect of Example 2. Fig.14A This is an enlarged cross-sectional view near the TFT. Fig.14A In the embodiment, the channel region 104 of the oxide semiconductor and the drain region 1043 and the source region 1042 have the same film thickness. Except for this, until the first upper gate insulating film 105 is formed, the thickness is the same as that of the embodiment 1. Figure 8 same. Fig.14A In the embodiment, a through hole 200 is formed in the second upper gate insulating film 106 corresponding to a region where the LDD region 1041 is formed in the oxide semiconductor.

[0094] Fig. 14B It is a cross-sectional view showing a state where the second upper gate insulating film 106 and the through hole 200 are covered and the upper gate electrode 107 is formed. Fig. 14BIn the embodiment, the metal gate electrode 107 also exists in the through hole 200 formed in the second upper gate insulating film 106. Therefore, oxygen is taken from the oxide semiconductor 104 through the gate electrode 107 in the through hole 200. Thus, the resistivity of this portion is lower than that of the channel region 104. However, the resistivity of this portion is higher than that of the source region 1042 and the drain region 1043 that are in contact with the metal. That is, it can function as the LDD region 1041. The feature of this embodiment is that the range of the LDD region 1041 of the oxide semiconductor can be defined by the through hole 200 formed in the second upper gate insulating film 106.

[0095] Fig.15A and Fig. 15B This is a cross-sectional view showing a second embodiment of Example 2. This embodiment is a combination of the configurations of Embodiment 1 of Example 2 and Example 1. Fig.15A and Fig.14A The difference is that the thickness of the oxide semiconductor is different in the channel region 104, the LDD region 1041, the source region 1042, and the drain region 1043. Such an oxide semiconductor can be formed by any of the first to third steps described in the first embodiment.

[0096] Fig. 15B 2 is a cross-sectional view showing a state where the second upper gate insulating film 106 and the through hole 200 are covered to form the upper gate electrode 107. Fig. 15B As shown, the LDD region 1041 is a structure in which oxygen is removed by the upper gate electrode 107. In addition, the film thickness of the channel region 104 is smaller than the film thickness of the LDD region 1041. Therefore, both the suppression of the change ΔVth of the threshold voltage and the reduction of the leakage current can be more effectively performed. That is, the second embodiment can have the effects of the first embodiment and the effects of the first embodiment of the second embodiment at the same time.

[0097] Example 3

[0098] Example 3 is a configuration in which the LDD region 1041 is formed by ion implantation. Fig.16A and Fig. 16B This is a cross-sectional view showing the first aspect of Example 3. Fig.16A In the embodiment, after the oxide semiconductor is patterned, a resist is formed in the channel region 104, and boron (B) is doped in regions corresponding to the LDD region 1041, the source region 1042, and the drain region 1043, for example, by ion implantation.

[0099] Then, the source electrode 108 , the drain electrode 109 , the first upper gate insulating film 105 , the second upper gate insulating film 106 , and the gate electrode 107 are formed. Fig. 16B This is a cross-sectional view showing this state. Fig. 16B For Figure 5 The same shape is different in that the LDD region 1041 is formed by ion implantation. That is, when the film thickness of the oxide semiconductor 104 is reduced in a manner that can suppress the OFF current, the resistivity of the LDD region can also be controlled by the amount of ions implanted by ion implantation, thereby suppressing the increase in the change ΔVth of the threshold voltage.

[0100] Fig.17A and Fig. 17B This is a cross-sectional view showing the second aspect of Example 3. Fig.17A In the embodiment, after the oxide semiconductor is patterned, a resist 500 is formed in the channel region 104, and boron (B) is doped in regions corresponding to the LDD region 1041, the source region 1042, and the drain region 1043, for example, by ion implantation. Fig.17A The composition and Fig.16A The compositions are similar, but the thickness of the oxide semiconductor is different. Fig.16A The thickness of the oxide semiconductor 104 in the channel region 104 becomes the thickness t1, Fig.17A The thickness of the oxide semiconductor 104 in becomes the thickness t3 of the source region 1042 or the drain region 1043 .

[0101] Then, for example, the drain electrode 109, the source electrode 108, and the oxide semiconductor (104, 1041, 1042, 1043) with a film thickness difference are formed by the steps described in the third process of Example 1. Then, the first upper gate insulating film 105, the second upper gate insulating film 106, and the upper gate electrode 107 are formed. Fig. 17B This is a cross-sectional view showing this state.

[0102] Fig. 17B For Figure 8 The same shape is different in that the LDD region 1041 is formed by ion implantation. On the other hand, by having a film thickness difference between the channel region 104, the LDD region 1041, and the drain region 1043 (source region 1042), the effect described in the first embodiment can be achieved. Therefore, the second embodiment can have the effect of the first embodiment and the effect described in the first embodiment of the third embodiment at the same time.

[0103] Description of Reference Numerals

[0104] 90…base film, 100…substrate, 101…lower gate electrode, 102…first lower gate insulating film, 103…second lower gate insulating film, 104…oxide semiconductor, channel region, 105…first upper gate insulating film, 106…second upper gate insulating film, 107…upper gate electrode, 108…source electrode, 109…drain electrode, 110…relay electrode, 111…planarization film, 112…capacitor electrode, 113…common line, 114…common electrode, 115…pixel electrode, 116…alignment film, 120…upper gate insulating film, 130…interlayer insulating film, 140…lower gate insulating film, 150…metal film for source electrode or drain electrode, 200…through hole, 500…resist, 1041…LDD region (transition region), 1042…source region, 1043…drain region,

[0105] Cs…holding capacitor

Claims

1. A semiconductor device having a TFT formed of an oxide semiconductor, characterized in that: The oxide semiconductor has a channel region, a source region, a drain region, a transition region between the channel region and the source region, and a transition region between the channel region and the drain region. The resistivity of the transition region is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region. A source electrode is formed to overlap with the source region, and a drain electrode is formed to overlap with the drain region. The thickness of the transition region of the oxide semiconductor is greater than the thickness of the channel region, In the oxide semiconductor, when measured at the center of the channel region, the thickness of the channel region is 60 nm or less, and when measured at the center of the transition region, the thickness of the transition region is 85 nm or more, A first gate insulating film is formed to cover the oxide semiconductor, and a second gate insulating film is formed to cover the first gate insulating film. The second gate insulating film has a through hole formed in a portion corresponding to the transition region. A gate electrode is formed to cover the second gate insulating film and the through hole.

2. The semiconductor device according to claim 1, wherein A thickness of the source region or a thickness of the drain region of the oxide semiconductor is greater than a thickness of the transition region.

3. The semiconductor device according to claim 2, wherein: A difference between a thickness of the source region or a thickness of the drain region of the oxide semiconductor and a thickness of the transition region is 10 nm or more.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The length of the transition region in the channel length direction of the channel region is greater than or equal to 2 μm.

5. The semiconductor device according to claim 1, wherein: The TFT is of bottom gate type.

6. The semiconductor device according to claim 1, wherein: The TFT is a double-gate type having a bottom gate and a top gate.

7. The semiconductor device according to claim 1, wherein: In the transition region, ions which increase the conductivity are doped.

8. A semiconductor device having a TFT formed of an oxide semiconductor, characterized in that: The oxide semiconductor has a channel region, a source region, a drain region, a transition region between the channel region and the source region, and a transition region between the channel region and the drain region. The resistivity of the transition region is smaller than the resistivity of the channel region and larger than the resistivity of the source region or the drain region. A source electrode is formed to overlap with the source region, and a drain electrode is formed to overlap with the drain region. A first gate insulating film is formed to cover the oxide semiconductor, and a second gate insulating film is formed to cover the first gate insulating film. The second gate insulating film has a through hole formed in a portion corresponding to the transition region. A first gate electrode is formed to cover the second gate insulating film and the through hole.

9. The semiconductor device according to claim 8, characterized in that The thickness of the channel region is less than 60 nm.

10. The semiconductor device according to claim 8, wherein The length of the transition region in the channel length direction is greater than or equal to 2 μm.

11. The semiconductor device according to claim 8, wherein A third gate insulating film exists under the oxide semiconductor, and a second gate electrode exists under the third gate insulating film.

Images