Comparator hysteresis circuit

Abstract

A comparator circuit includes a first transistor (206), a second transistor (208), a first switch (210), a second switch (212), and a timing circuit. The first transistor (206) and the second transistor (208) are coupled as a differential pair and are configured to compare an input signal with a hysteresis voltage. The first switch (210) is coupled to the first transistor (206) and is configured to selectively enable the first transistor (206). The second switch (212) is coupled to the second transistor (208) and is configured to selectively enable the second transistor (208). The timing circuit is coupled to the first switch (210) and the second switch (212) and is configured to close the first switch (210) in response to a signal transition at the output of the comparator circuit and to close the second switch (212) a predetermined delay time after the first switch (210) is closed.

Description

Technical Field

[0001] The present disclosure relates generally to circuit system design, and more particularly to a comparator hysteresis circuit. Background Art

[0002] A comparator is a circuit device that compares the amplitudes of two analog input voltage or current signals and generates an output signal indicating whether one of the two analog input signals is greater than the other. In some comparators, the output changes state when the two input signals are substantially equal, which can cause the comparator output to switch between states in response to noise on the input signals. To prevent this problem, some comparators employ hysteresis to provide individual trip thresholds based on the output state, thereby reducing the incidence of noise-induced switching when the voltage levels of the input signals are very close to each other. Summary of the Invention

[0003] Disclosed herein is a comparator circuit that reduces the incidence of output transient faults caused by switching between different differential pairs based on transitions in the comparator output. In one example, a comparator circuit includes a signal input terminal, an output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, and a timing circuit. The first transistor includes a first terminal coupled to a first hysteresis voltage circuit. The second transistor includes a first terminal coupled to the signal input terminal and a second terminal coupled to the second terminal of the first transistor. The third transistor includes a first terminal coupled to the third terminal of the first transistor and a second terminal coupled to a power rail. The fourth transistor includes a first terminal coupled to the third terminal of the second transistor and a second terminal coupled to the power rail. The timing circuit includes an input terminal, a first output, a second output, and a delay circuit. The input terminal is coupled to the output terminal. The first output is coupled to the third terminal of the third transistor. The second output is coupled to the third terminal of the fourth transistor. The delay circuit includes an input terminal coupled to the first output and an output terminal coupled to the second output.

[0004] In another example, a comparator circuit includes a first transistor, a second transistor, a first switch, a second switch, and a timing circuit. The first and second transistors are coupled as a differential pair and configured to compare an input signal with a hysteresis voltage. The first switch is coupled to the first transistor and configured to selectively enable the first transistor. The second switch is coupled to the second transistor and configured to selectively enable the second transistor. The timing circuit is coupled to the first and second switches and configured to close the first switch in response to a signal transition at an output of the comparator circuit and to close the second switch a predetermined delay time after the first switch is closed.

[0005] In another example, a comparator circuit includes a signal input terminal, an output terminal, a first input circuit, a second input circuit, and a timing circuit. The first input circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first terminal coupled to a first hysteresis voltage circuit. The second transistor includes a first terminal coupled to the signal input terminal and a second terminal coupled to the second terminal of the first transistor. The third transistor includes a first terminal coupled to the third terminal of the first transistor and a second terminal coupled to a power rail. The fourth transistor includes a first terminal coupled to the third terminal of the second transistor and a second terminal coupled to the power rail. The second input circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The fifth transistor includes a first terminal coupled to a second hysteresis voltage circuit. The sixth transistor includes a first terminal coupled to the signal input terminal and a second terminal coupled to the second terminal of the fifth transistor. The seventh transistor includes a first terminal coupled to the third terminal of the fifth transistor and a second terminal coupled to the power rail. The eighth transistor includes a first terminal coupled to the third terminal of the sixth transistor and a second terminal coupled to the power rail. The timing circuit includes an input terminal, a first output, a second output, a third output, and a fourth output. The input terminal is coupled to the output terminal. The first output is coupled to the third terminal of the third transistor. The second output is coupled to the third terminal of the fourth transistor. The third output is coupled to the third terminal of the seventh transistor. The fourth output is coupled to the third terminal of the eighth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 Schematic diagram showing an example comparator circuit using two input circuits to provide accurate hysteresis;

[0008] Figure 2A and 2B A schematic diagram showing an example comparator circuit that provides accurate hysteresis while reducing output transient glitches when switching between two input circuits;

[0009] Figure 3 Shown in Figure 2A and 2B Example signal generated in the comparator circuit;

[0010] Figure 4A and 4B Show by Figure 1 The comparator circuit and Figure 2A and 2Bcomparison of the output signals generated by the comparator circuit; and

[0011] Figure 5A and 5B Shown in Figure 2A and 2B The comparator circuit provides an example of delay circuitry in a timer circuit. DETAILED DESCRIPTION

[0012] Throughout this description, the term "coupled" means an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. Furthermore, throughout this description, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, then X may be a function of Y and various other factors.

[0013] Many comparators use hysteresis to suppress noise on the input signal. The accuracy of the hysteresis applied across comparators varies widely. For example, in some comparators, the hysteresis voltage can vary by as much as 50%. Some comparators that provide accurate hysteresis use two differential pairs to generate the hysteresis, with each differential pair connected to a different reference voltage.

[0014] Figure 1 A schematic diagram of an example comparator circuit 100 that uses two input circuits to provide accurate hysteresis is shown. Comparator circuit 100 includes input circuit 102 and input circuit 104. Input circuit 102 includes transistors 106 and 108 forming a differential pair and transistors 110 and 112 used as switches to enable or disable the differential pair. Similarly, input circuit 104 includes transistors 116 and 118 forming a differential pair and transistors 120 and 122 used as switches to enable or disable the differential pair. If the voltage at output terminal 114 of comparator circuit 100 is a logic "low," input circuit 102 is enabled to compare input signal 128 with high hysteresis voltage 124, and when input signal 128 is greater than high hysteresis voltage 124, the output of comparator circuit 100 changes to a logic "high." If the voltage at the output terminal 114 of the comparator circuit 100 is a logic "high," the input circuit 104 is enabled to compare the input signal 128 with the low hysteresis voltage 126, and when the input signal 128 is less than the low hysteresis voltage 126, the output of the comparator circuit 100 changes to a logic "low." Thus, the hysteresis applied in the comparator circuit 100 is precisely determined by the difference between the high hysteresis voltage 124 and the low hysteresis voltage 126.

[0015] When input signal 128 decreases slowly and, for example, crosses low hysteresis voltage 126, the voltage at output node 130 will also change slowly. However, control signals 132 and 134 will change quickly to disable input circuit 104 and enable input circuit 102. As input circuit 102 is enabled, parasitic capacitors at the drains of transistors 106 and 108 are charged, which induces common-mode currents in transistors 110 and 112 and, in turn, causes the voltage at the drains of transistors 110 and 112 to drop. Because the signal path from the drain of transistor 112 to output node 130 is shorter than the signal path from the drain of transistor 110 to output node 130, the voltage at output node 130 will transiently increase and may cause a transient fault on output terminal 114.

[0016] Some implementations of comparator circuit 100 match the signal paths from the drains of transistors 110, 112, 120, and 122 to output node 130 to offset the effects of parasitic capacitor charging current. However, matching the timing of these paths is difficult, and even if the timing is matched, differences in parasitic capacitance at the drain terminals of transistors 106, 108, 116, and 118 can produce timing differences sufficient to cause transient glitches at output terminal 114.

[0017] Figure 2A and 2B A schematic diagram of an example comparator circuit 200 is shown that provides accurate hysteresis while reducing output transient glitches when switching between two input circuits. Rather than attempting to match path timing, comparator circuit 200 controls the enable timing of a differential pair to reduce or eliminate transient glitches at the comparator output. Comparator circuit 200 includes input circuit 202, input circuit 204, signal input terminal 242, output terminal 214, output circuitry 258, and timing circuit 232. Input circuit 202 includes transistors 206 and 208 forming a differential pair and transistors 210 and 212 acting as switches to enable or disable the differential pair. Source terminal 206S of transistor 206 is coupled to source terminal 208S of transistor 208. Gate terminal 206G of transistor 206 is coupled to hysteresis voltage circuit 238 that generates hysteresis voltage 224. Hysteresis voltage 224 sets the threshold for transitioning from a logic "low" to a logic "high." The drain terminal 206D of transistor 206 is coupled to the source terminal 210S of transistor 210. The drain terminal 210D of transistor 210 is coupled to power rail 246 and output circuitry 258.

[0018] Gate terminal 208G of transistor 208 is coupled to signal input terminal 242 for receiving input signal 228 for comparison with hysteresis voltage 224. Drain terminal 208D of transistor 208 is coupled to source terminal 212S of transistor 212. Drain terminal 212D of transistor 212 is coupled to power rail 246 and output circuitry 258.

[0019] Input circuit 204 includes transistors 216 and 218 forming a differential pair and transistors 220 and 222 used as switches to enable or disable the differential pair. Source terminal 216S of transistor 216 is coupled to source terminal 218S of transistor 218. Gate terminal 216G of transistor 216 is coupled to signal input terminal 242 for receiving input signal 228. Drain terminal 216D of transistor 216 is coupled to source terminal 220S of transistor 220. Drain terminal 220D of transistor 220 is coupled to transistor 212D, power rail 246, and output circuitry 258.

[0020] A gate terminal 218G of transistor 218 is coupled to a hysteresis voltage circuit 240 that generates a hysteresis voltage 226 for comparison with an input signal 228. A drain terminal 218D of transistor 218 is coupled to a source terminal 222S of transistor 222. A drain terminal 222D of transistor 222 is coupled to 210D of transistor 210, a power rail 246, and output circuitry 258.

[0021] Sequential circuit 232 includes an input terminal 232A coupled to output terminal 214, an output 232B coupled to input terminal 232A, an output 232C coupled to input terminal 232A, a delay circuit 234, and a delay circuit 236. Delay circuit 234 includes an input terminal 234A coupled to output 232B and an output terminal 234B coupled to output 232C of sequential circuit 232. Delay circuit 236 includes an input terminal 236A coupled to output 232D of sequential circuit 232 and an output terminal 236B coupled to output 232E of sequential circuit 232. Output 232B of sequential circuit 232 is coupled to gate terminal 210G of transistor 210. Output 232C of sequential circuit 232 is coupled to gate terminal 212G of transistor 212. Output 232D of sequential circuit 232 is coupled to gate terminal 220G of transistor 220. An output 232E of the timing circuit 232 is coupled to a gate terminal 222G of the transistor 222 .

[0022] Timing circuit 232 sequences the turning on and off of each of transistors 210, 212, 220, and 222 at each transition of comparator output signal 244 to suppress transient glitches at output terminal 214. Timing circuit 232 delays the turning on of transistor 212 relative to transistor 210 and delays the turning on of transistor 222 relative to transistor 220. The delays provided by delay circuit 234 and delay circuit 236 operate as time-domain hysteresis to prevent transient glitches at output terminal 214. The delay time provided by delay circuit 234 is at least as great as the difference in propagation delays from drain terminal 210D of transistor 210 and drain terminal 212D of transistor 212 to output node 230. Similarly, the delay time provided by delay circuit 236 is at least as great as the difference in propagation delays from drain terminal 220D of transistor 220 and drain terminal 222D of transistor 222 to output node 230. The delay ensures that the signal in the longer path arrives at the output node 230 no later than the signal in the shorter path.

[0023] Figure 3 Example signals generated in comparator circuit 200 are shown. As voltage 256 at output node 230 slowly decreases, comparator output signal 244 (Vout) switches from logic "high" to logic "low" at 302. Shortly thereafter, at time 304, sequential circuit 232 activates control signal 248 (HystA) to turn on transistor 210, and deactivates control signal 252 (HystC) and control signal 254 (HystD) to turn off transistors 220 and 222. After a delay 306, sequential circuit 232 activates control signal 250 (HystB) to turn on transistor 212.

[0024] As the voltage 256 at the output node 230 slowly rises, the comparator output signal 244 (Vout) switches from logic "low" to logic "high" at 310. Shortly thereafter, at time 312, the sequential circuit 232 activates the control signal 252 (HystC) to turn on the transistor 220, and deactivates the control signal 248 (HystA) and the control signal 250 (HystB) to turn off the transistors 210 and 212. After a delay 314, the sequential circuit 232 activates the control signal 254 (HystD) to turn on the transistor 222.

[0025] Figure 4A and 4B A comparison of the output signals produced by comparator circuit 100 and comparator circuit 200 is shown. Figure 4AInput signal 128 and input signal 228 are shown as slowly changing triangular ramps. Voltage 156 at output node 130 of comparator circuit 100 and voltage 256 at output node 230 of comparator circuit 200 switch as input signal 128 rises and falls. Figure 4A At the time scale of , the transient fault is not visible at the edge of voltage 156 or voltage 256. Figure 4B The falling edges of voltage 156 and voltage 256 are shown at a significantly higher time scale. As voltage 156 falls, transient fault 402 is caused by the difference in path delays from transistors 120 and 122. The transient fault can trigger a change in the logic signal level at output terminal 114. As voltage 256 falls, a significantly smaller transient fault 404 is generated. The level of transient fault 404 is insufficient to trigger a change in the logic level of comparator output signal 244.

[0026] Figure 5A and 5B An example of circuitry in the sequential circuit 232 of the comparator circuit 200 is shown. Figure 5A 2. Example circuitry is shown for generating control signal 248 (HystA) and control signal 250 (HystB). Inverter 502, coupled to input terminal 232A and output terminal 232B, generates control signal 248. Delay circuit 234 includes delay cell 504 and AND gate 506. Delay cell 504 delays the output of inverter 502 by delay 306, and AND gate 506 combines the output of inverter 502 with the output of delay cell 504 to generate control signal 250. Delay cell 504 can include any number of delay elements (e.g., inverters) necessary to generate delay 306.

[0027] Figure 5B Example circuitry is shown for generating control signal 252 (HystC) and control signal 254 (HystD). A non-inverting buffer 512 coupled to input terminal 232A and output 232D generates control signal 252. Delay circuit 236 includes a delay cell 514 and an AND gate 516. Delay cell 514 delays the output of non-inverting buffer 512 by delay 314, and AND gate 516 combines the output of non-inverting buffer 512 with the output of delay cell 514 to generate control signal 254. Delay cell 514 can include any number of delay elements (e.g., inverters) necessary to generate delay 314.

[0028] The described embodiments can be modified, and other embodiments are possible, within the scope of the claims.

Claims

1. A comparator circuit, comprising: Signal input terminal; Output terminals; a first transistor including a first terminal coupled to a first hysteresis voltage circuit; A second transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the second terminal of the first transistor; A third transistor comprising: a first terminal coupled to a third terminal of the first transistor; and a second terminal coupled to the power rail; a fourth transistor comprising: a first terminal coupled to a third terminal of the second transistor; and a second terminal coupled to the power rail; A sequential circuit comprising: an input terminal coupled to the output terminal; a first output coupled to a third terminal of the third transistor; a second output coupled to a third terminal of the fourth transistor; and A delay circuit comprising: an input terminal coupled to the first output; and an output terminal coupled to the second output; and a fifth transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; and The second terminal is coupled to the third output of the sequential circuit. 2 . The comparator circuit of claim 1 , wherein the third output of the sequential circuit is coupled to the input terminal of the sequential circuit.

3. The comparator circuit according to claim 1 , further comprising: a sixth transistor comprising: a first terminal coupled to the signal input terminal; a second terminal coupled to the second terminal of the first transistor; and A third terminal is coupled to the third terminal of the fifth transistor.

4. The comparator circuit according to claim 1 , further comprising: a sixth transistor comprising: a first terminal coupled to the second terminal of the third transistor; and The second terminal is coupled to the fourth output of the sequential circuit.

5. The comparator circuit according to claim 4 , further comprising: a seventh transistor comprising: a first terminal coupled to a second hysteresis voltage circuit; and a second terminal coupled to the second terminal of the first transistor; and A third terminal is coupled to the third terminal of the sixth transistor.

6. The comparator circuit according to claim 4, wherein: The delay circuit is a first delay circuit; and The sequential circuit includes a second delay circuit, which includes: an input terminal coupled to the third output; and an output terminal coupled to the fourth output.

7. A comparator circuit comprising: a first transistor and a second transistor coupled as a differential pair and configured to compare an input signal to a hysteresis voltage; a first switch coupled to the first transistor and configured to selectively enable the first transistor; a second switch coupled to the second transistor and configured to selectively enable the second transistor; a timing circuit coupled to the first switch and the second switch and configured to: closing the first switch in response to a signal transition at an output terminal of the comparator circuit; and closing the second switch at a predetermined delay time after the first switch is closed; Output circuitry is coupled to the first switch and the second switch, wherein the predetermined delay time is at least as long as a difference between a propagation delay from the first switch through the output circuitry and a propagation delay from the second switch through the output circuitry.

8. The comparator circuit according to claim 7, wherein: The signal transition is a first signal transition; and The timing circuit is configured to open the first switch and the second switch in response to a second signal transition at the output terminal of the comparator circuit. 9 . The comparator circuit of claim 8 , wherein the timing circuit is configured to turn off the first switch and the second switch without a predetermined delay between the turning off of the first switch and the turning off of the second switch.

10. The comparator circuit according to claim 7, wherein: The hysteresis voltage is a first hysteresis voltage; The comparator circuit further comprises: a third transistor and a fourth transistor coupled as a differential pair and configured to compare the input signal with a second hysteresis voltage; a third switch coupled to the third transistor and configured to selectively enable the third transistor; a fourth switch coupled to the fourth transistor and configured to selectively enable the fourth transistor; and The timing circuit is coupled to the third switch and the fourth switch and is configured to open the third switch and the fourth switch in response to the signal transition at the output terminal of the comparator circuit. 11 . The comparator circuit of claim 10 , wherein the timing circuit is configured to turn off the third switch and the fourth switch without a predetermined delay between the turning off of the third switch and the turning off of the fourth switch.

12. The comparator circuit according to claim 10, wherein: The signal transition is a first signal transition; and The sequential circuit is configured to: closing the third switch in response to a second signal transition at the output terminal of the comparator circuit; and The fourth switch is closed at the predetermined delay time after the third switch is closed.

13. A comparator circuit comprising: Signal input terminal; Output terminals; A first input circuit comprising: a first transistor including a first terminal coupled to a first hysteresis voltage circuit; A second transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the second terminal of the first transistor; A third transistor comprising: a first terminal coupled to a third terminal of the first transistor; and a second terminal coupled to the power rail; and a fourth transistor comprising: a first terminal coupled to a third terminal of the second transistor; and a second terminal coupled to the power rail; A second input circuit comprising: a fifth transistor including a first terminal coupled to a second hysteresis voltage circuit; a sixth transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the second terminal of the fifth transistor; a seventh transistor comprising: a first terminal coupled to a third terminal of the fifth transistor; and a second terminal coupled to the power rail; and an eighth transistor comprising: a first terminal coupled to the third terminal of the sixth transistor; and a second terminal coupled to the power rail; and A sequential circuit comprising: an input terminal coupled to the output terminal; a first output coupled to a third terminal of the third transistor; a second output coupled to a third terminal of the fourth transistor; a third output coupled to a third terminal of the seventh transistor; and A fourth output is coupled to the third terminal of the eighth transistor.

14. The comparator circuit according to claim 13 , wherein the sequential circuit comprises a delay circuit, the delay circuit comprising: an input terminal coupled to the first output; and an output terminal coupled to the second output.

15. The comparator circuit of claim 14 , further comprising output circuitry coupled to the third transistor and the fourth transistor, wherein the delay circuit is configured to provide a delay between the first output and the second output that is at least as long as a difference between a propagation delay from the third transistor through the output circuitry and a propagation delay from the fourth transistor through the output circuitry.

16. The comparator circuit according to claim 13, wherein the sequential circuit comprises a delay circuit, the delay circuit comprising: an input terminal coupled to the fourth output; and an output terminal coupled to the third output.

17. The comparator circuit of claim 13, wherein the timing circuit is configured to: In response to a signal transition at the output terminal: turning off the seventh transistor and the eighth transistor; turning on the third transistor; and The fourth transistor is turned on a predetermined delay time after the third transistor is turned on.

18. The comparator circuit according to claim 17, wherein: The signal transition is a first signal transition; and The sequential circuit is configured to: In response to a second signal transition at the output terminal: turning off the third transistor and the fourth transistor; turning on the seventh transistor in response to the signal transition; and The eighth transistor is turned on a predetermined delay time after the seventh transistor is turned on.

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