A driving architecture for reducing tp parasitic capacitance and a driving method thereof

Abstract

The application discloses a driving architecture and a driving method thereof for reducing TP parasitic capacitance, which comprises two or more TP units and two driving signal lines of driving IC output, the TP unit comprises four TP sensors arranged in a two-row two-column array, each TP sensor is connected to one end of a Mux circuit, and the other ends of the Mux circuits corresponding to two TP sensors of one group of different columns and different rows in each TP unit are commonly connected to one driving signal line, and the other ends of the Mux circuits corresponding to two TP sensors of another group of different columns and different rows in each TP unit are commonly connected to another driving signal line. By changing the order of the IC sending sensing pulses to the four TP sensors, the TP parasitic capacitance is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of panel display, and in particular to a driving architecture for reducing TP parasitic capacitance and a driving method thereof. BACKGROUND

[0002] Display products on the market are increasingly pursuing narrow frames, and in order to reduce the lower frame of the panel, the current method is to reduce the TP Channel of the driving IC to half of the original by using the TP mux1:2 mode without changing the number of TP Sensor of the panel, i.e., without changing the TP resolution, as shown in FIG. 1. Figure 1 As shown in FIG. 2, when Mux1 is at a high potential level, the driving IC outputs Sx1 and Sx2 to send signals to the in-panel TPs Sx11 and Sx21, and when Mux2 is at a high potential level, the driving IC outputs Sx1 and Sx2 to send signals to the in-panel TPs Sx12 and Sx22. Figure 2 When the driving IC sends a sensing pulse signal to Sx11, i.e., when Mux1 is at a high potential, the driving IC also synchronously sends a TP same-zone signal to Sx21 at this time, so as to prevent a pressure difference between the two adjacent sensors Sx11 and Sx21 and form a parasitic capacitance C p2 , and Sx12 and Sx11 are also adjacent sensors, at this time Mux2 is at a low potential and Sx12 is also at a low potential, so that there will be a parasitic capacitance C p1 between Sx11 and Sx12, affecting the TP function. SUMMARY

[0003] The present application aims to provide a driving architecture for reducing TP parasitic capacitance and a driving method thereof, to solve the problem of parasitic capacitance between TP Sensors under the TP Mux architecture of the existing TDDI type, and to achieve the purpose of reducing the number of TP Channels while ensuring the TP resolution and TP function.

[0004] The technical solution adopted by the present application is as follows:

[0005] A driving architecture for reducing TP parasitic capacitance, comprising two or more TP units and two driving signal lines of a driving IC output, the TP unit comprising a plurality of TP sensors, the TP sensors of the TP unit being arranged in an array, the TP sensors of each TP unit comprising two columns of TP sensor pairs, each column of TP sensor pairs comprising two rows of TP sensors; each TP sensor being respectively connected to one end of a Mux circuit, the other end of the Mux circuits corresponding to one group of two TP sensors of different columns and different rows of each TP unit being commonly connected to one driving signal line, and the other end of the Mux circuits corresponding to another group of two TP sensors of different columns and different rows of each TP unit being commonly connected to another driving signal line.

[0006] Further, the gates of the control switches of the four Mux circuits of the same TP unit are respectively connected to one switch signal, and the gates of the control switches of the Mux circuits corresponding to the TP sensors at the same position of different TP units are commonly connected to the same switch signal.

[0007] Further, the four switch signals are all timing signals, and the high voltage levels of the four switch signals are all the same.

[0008] Further, each TP unit comprises four TP sensors Sx11, Sx12, Sx21 and Sx22, and the four TP sensors Sx11, Sx12, Sx21 and Sx22 are respectively connected to the four Mux circuits Mux11, Mux12, Mux21 and Mux22 one by one; Sx11 and Sx12 are in the same column, Sx21 and Sx22 are in another column, Sx11 and Sx21 are in the same row, and Sx12 and Sx22 are in another row; the other end of Mux11 and Mux22 is commonly connected to the driving signal line Sx1, and the other end of Mux12 and Mux21 is commonly connected to the driving signal line Sx2.

[0009] A driving method of a driving architecture for reducing TP parasitic capacitance, changing the order of sending sensing pulses to four TP sensors Sx11 / Sx12 / Sx21 / Sx22 by a driving IC; specifically as follows:

[0010] At t1 moment: the driving IC sends a sensing pulse to Sx11, Mux11 is high; Mux12 / Mux21 is high, the driving IC sends a null signal LFD to Sx12 / Sx21; Mux22 is low, and Sx22 is low;

[0011] t2 moment: the driving IC sends a sensing pulse to Sx22, Mux22 is high potential; Mux12 / Mux21 is high potential, the driving IC sends a null signal LFD to Sx12 / Sx21, Mux11 is low potential, Sx11 is low potential;

[0012] t3 moment: the driving IC sends a sensing pulse to Sx12, Mux12 is high potential; Mux11 / Mux22 is high potential, the driving IC sends a null signal LFD to Sx11 / Sx22, Mux21 is low potential, Sx21 is low potential;

[0013] t4 moment: the driving IC sends a sensing pulse to Sx21, Mux21 is high potential; Mux11 / Mux22 is high potential, the driving IC sends a null signal LFD to Sx11 / Sx22, Mux12 is low potential, Sx12 is low potential.

[0014] The application adopts the above technical scheme, 2 TP channels (Sx1 / Sx2) of the IC output correspond to 4 TPSensors (Sx11 / Sx12 / Sx21 / Sx22) in the plane, and the architecture requires 4 mux signals (Mux11 / Mux12 / Mux21 / Mux22). Sx1 transmits signals to Sx11 / Sx22 through control signals Mux11 / Mux22 respectively, and Sx2 transmits signals to Sx12 / Sx21 through control signals Mux12 / Mux21 respectively. Meanwhile, the order of the sensing pulse sent by the IC to Sx11 / Sx12 / Sx21 / Sx22 is changed, the parasitic capacitance between the TPSensors generated under the existing TP Mux architecture of the TDDI type is solved, and the purpose of reducing the number of TP channels while ensuring the TP resolution and TP function is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0015] The application will be further described in detail below in combination with the drawings and specific embodiments.

[0016] Figure 1 It is a schematic diagram of the existing TP mux1:2 structure.

[0017] Figure 2 It is a timing diagram of the existing TP mux1:2 architecture.

[0018] Figure 3 It is a schematic diagram of the driving architecture structure for reducing TP parasitic capacitance.

[0019] Figure 4 It is a TP Mux timing diagram. DETAILED DESCRIPTION

[0020] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application.

[0021] As shown in Figure 3 The present application discloses a driving architecture for reducing TP parasitic capacitance, which comprises two or more TP units and two driving signal lines of driving IC output, the TP unit comprises a plurality of TP sensors, the TP sensors of the TP unit are arranged in an array, the TP sensors of each TP unit comprise two columns of TP sensor pairs, each column of TP sensor pairs comprises two rows of TP sensors; that is, the TP unit comprises four TP sensors arranged in a two-row and two-column array; each TP sensor is respectively connected to one end of a Mux circuit, and the other end of the Mux circuit corresponding to one group of two TP sensors of different columns and different rows in each TP unit is commonly connected to one driving signal line, and the other end of the Mux circuit corresponding to another group of two TP sensors of different columns and different rows in each TP unit is commonly connected to another driving signal line.

[0022] Further, the gates of the control switches of the four Mux circuits of the same TP unit are respectively connected to one switch signal, and the gates of the control switches of the Mux circuits corresponding to the TP sensors at the same position of different TP units are commonly connected to the same switch signal.

[0023] Further, the four switch signals are all time sequence signals, and the high voltage levels of the four switch signals are all the same.

[0024] Specifically, as shown in Figure 3 The present application proposes a TP Mux2:4 architecture to reduce the parasitic capacitance between TP sensors. As shown in Figure 3 Taking four TP sensors (Sx11 / Sx12 / Sx21 / Sx22) in a panel as an example, there will be C p1 parasitic capacitance in the existing TP Mux1:2 architecture, which affects the TP function, so a Mux2:4 architecture is proposed, that is, two TP channels (Sx1 / Sx2) of IC output correspond to four TP sensors (Sx11 / Sx12 / Sx21 / Sx22) in the panel, and this architecture requires four mux signals (Mux11 / Mux12 / Mux21 / Mux22). Sx1 transmits signals to Sx11 / Sx22 through control signals Mux11 / Mux22, respectively, and Sx2 transmits signals to Sx12 / Sx21 through control signals Mux12 / Mux21, respectively.

[0025] AsFigure 3 As shown in the figure, in the architecture of a TP Mux2:4, when the IC sends a TP sensing pulse to Sx11, because there is a parasitic capacitance C between Sx11 and Sx12 / Sx21 p1 and C p2 , the IC needs to send a LFD signal (Load Free Driving, i.e. a TP same-area signal) to Sx12 / Sx21; at this time, Sx22 cannot receive a TP Sx signal, and if Sx1 sends a sensing pulse to Sx11 and Sx22 at the same time, it will affect the judgment of the IC and cause a false touch.

[0026] Therefore, the present application proposes a driving method of a driving architecture for reducing TP parasitic capacitance, which changes the sensing pulse sending sequence of the driving IC to Sx11 / Sx12 / Sx21 / Sx22; the specific changes are as follows:

[0027] At t1 moment: the driving IC sends a sensing pulse to Sx11, Mux11 is high; Mux12 / Mux21 is high, the driving IC sends a null signal LFD to Sx12 / Sx21; Mux22 is low, Sx22 is low;

[0028] At t2 moment: the driving IC sends a sensing pulse to Sx22, Mux22 is high; Mux12 / Mux21 is high, the driving IC sends a null signal LFD to Sx12 / Sx21; Mux11 is low, Sx11 is low;

[0029] At t3 moment: the driving IC sends a sensing pulse to Sx12, Mux12 is high; Mux11 / Mux22 is high, the driving IC sends a null signal LFD to Sx11 / Sx22; Mux21 is low, Sx21 is low;

[0030] At t4 moment: the driving IC sends a sensing pulse to Sx21, Mux21 is high; Mux11 / Mux22 is high, the driving IC sends a null signal LFD to Sx11 / Sx22; Mux12 is low, Sx12 is low.

[0031] The application adopts the above technical scheme, 2 IC output TP channels (Sx1 / Sx2) correspond to 4 in-plane TPSensors (Sx11 / Sx12 / Sx21 / Sx22), and this architecture requires 4 mux signals (Mux11 / Mux12 / Mux21 / Mux22). Sx1 transmits signals to Sx11 / Sx22 through control signals Mux11 / Mux22 respectively, and Sx2 transmits signals to Sx12 / Sx21 through control signals Mux12 / Mux21 respectively. At the same time, the order of the sensing pulse sent by the IC to Sx11 / Sx12 / Sx21 / Sx22 is changed, the parasitic capacitance between the TPSensors under the existing TP Mux architecture of the TDDI type is solved, and the purpose of reducing the number of TP channels while ensuring the TP resolution and TP function is achieved.

[0032] Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

Claims

1. A driving method for a driving architecture that reduces TP parasitic capacitance, characterized in that: The driving architecture includes two or more TP units and two drive signal lines output by the driver IC. Each TP unit includes multiple TP sensors arranged in an array. Each TP unit has two columns of TP sensor pairs, and each column of TP sensor pairs has two rows of TP sensors. Each TP sensor is connected to one end of a Mux circuit. The other ends of the Mux circuits corresponding to two TP sensors in different columns and rows within each TP unit are connected to one of the drive signal lines. The other ends of the Mux circuits corresponding to two TP sensors in different columns and rows within each TP unit are connected to another drive signal line. Each TP unit includes four TP sensors: Sx11, Sx12, Sx21, and Sx22. Sensors Sx11, Sx12, Sx21, and Sx22 are connected one-to-one with the four Mux circuits Mux11, Mux12, Mux21, and Mux22, respectively. Sx11 and Sx12 are in the same column, and Sx21 and Sx22 are in another column. Sx11 and Sx21 are in the same row, and Sx12 and Sx22 are in another row. The other ends of Mux11 and Mux22 are connected to the drive signal line Sx1, and the other ends of Mux12 and Mux21 are connected to the drive signal line Sx2. The driving method involves changing the sequence of sensing pulses delivered by the driver IC to the four TP sensors (Sx11, Sx12, Sx21, and Sx22) in each TP unit, as detailed below: At time t1: The driver IC sends an induction pulse to Sx11, and Mux11 is at a high potential; Mux12 and Mux21 are at a high potential, and the driver IC sends an idle signal LFD to Sx12 and Sx21; the output signal of Mux22 is at a low potential, and Sx22 is at a low potential. At time t2: The driver IC sends an induction pulse to Sx22, and the output signal of Mux22 is at a high level; Mux12 and Mux21 are at a high level, and the driver IC sends an unloaded signal LFD to Sx12 and Sx21; Mux11 is at a low level, and Sx11 is at a low level. At time t3: The driver IC sends an induction pulse to Sx12, and Mux12 is at a high potential; the output signals of Mux11 and Mux22 are at a high potential, and the driver IC sends an unloaded signal LFD to Sx11 and Sx22; Mux21 is at a low potential, and Sx21 is at a low potential. At time t4: The driver IC sends an induction pulse to Sx21, and Mux21 is at a high potential; the output signals of Mux11 and Mux22 are at a high potential, and the driver IC sends an unloaded signal LFD to Sx11 and Sx22; Mux12 is at a low potential, and Sx12 is at a low potential.

2. The driving method for reducing TP parasitic capacitance according to claim 1, characterized in that: The gates of the control switches of the four Mux circuits in the same TP unit are each connected to a switch signal. The gates of the control switches of the Mux circuits corresponding to the TP sensors at the same position in different TP units are all connected to the same switch signal.

3. The driving method for reducing TP parasitic capacitance according to claim 2, characterized in that: All four switch signals are timing signals, and the high-level voltage of all four switch signals is the same.

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