storage device

Abstract

Embodiments provide a storage device that can improve characteristics of the storage device. According to one embodiment, a device includes a sense amplifier that senses a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror that causes a first current to flow into a first node connected to the cell and causes a second current to flow into a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second node and the third node and causing a third current to flow into the second node based on a potential of the third node.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2020-155568, filed September 16, 2020, and U.S. Patent Application No. 17 / 200966, filed March 15, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to storage devices. Background Technology

[0004] Storage devices that use variable resistive elements (e.g., magnetoresistive elements) as storage elements are known. Summary of the Invention

[0005] The embodiment provides a storage device that can improve the characteristics of the storage device.

[0006] Generally, according to one embodiment, a storage device includes: a storage cell; and a read circuit configured to sense a first signal based on first data in the storage cell, write second data into the storage cell, sense a second signal based on the second data in the storage cell, and read data in the storage cell based on a comparison result between the first signal and the second signal. The read circuit includes a first sensing amplifier configured to sense the first and second signals, and the first sensing amplifier includes: a current mirror circuit configured to allow a first current to flow into a first node connected to the storage cell, and to allow a second current to flow into a second node based on the potential of the first node; a first switching element including a first terminal connected to the second node and a second terminal connected to a third node; a first transistor including a third terminal connected to the second node and a first gate connected to the third node; a second switching element including a fourth terminal connected to the second node and a fifth terminal connected to the fourth node; and a first circuit connected to the second and third nodes and configured to allow a third current to flow into the second node based on the potential of the third node. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example configuration of a storage device according to a first embodiment.

[0008] Figure 2 This is an equivalent circuit diagram of the storage cell array of the storage device according to the first embodiment.

[0009] Figure 3 and Figure 4 These are cross-sectional views illustrating examples of the structure of a storage cell array according to a storage device based on a first embodiment.

[0010] Figure 5 is an example of a configuration of a storage element of a storage device according to the first embodiment.

[0011] Figure 6 is a block diagram showing an example of a configuration of a read circuit of a storage device according to the first embodiment.

[0012] Figure 7 and Figure 8 is an equivalent circuit diagram of a read circuit of a storage device according to the first embodiment.

[0013] Figure 9 is a flowchart showing an example of an operation of a storage device according to the first embodiment.

[0014] Figure 10 is a timing chart showing an example of an operation of a storage device according to the first embodiment.

[0015] Figure 11 and Figure 12 is a graph showing an example of an operation of a storage device according to the first embodiment.

[0016] Figure 13 , Figure 14 , Figure 15 and Figure 16 is a graph showing a characteristic of a storage device according to the first embodiment.

[0017] Figure 17 is an equivalent circuit diagram showing an example of a configuration of a storage device according to the second embodiment.

[0018] Figure 18 is a timing chart showing an example of an operation of a storage device according to the second embodiment.

[0019] Figure 19 and Figure 20 is a graph showing an example of an operation of a storage device according to the second embodiment.

[0020] Figure 21 is a graph showing an example of an operation of a storage device according to the third embodiment.

[0021] Figure 22 is a timing chart showing an example of an operation of a storage device according to the third embodiment.

[0022] Figure 23 is a graph showing an example of an operation of a storage device according to the fourth embodiment.

[0023] Figure 24 is a timing chart showing an example of an operation of a storage device according to the fourth embodiment.

[0024] Figure 25 is an equivalent circuit diagram showing an example of a configuration of a storage device according to a fifth embodiment.

[0025] Figure 26 is an equivalent circuit diagram showing an example of a configuration of a storage device according to a sixth embodiment.

[0026] Figure 27 is an equivalent circuit diagram showing an example of a configuration of a storage device according to a seventh embodiment. DETAILED DESCRIPTION

[0027] Embodiments will be described below with reference to the accompanying drawings. Note that in the following description, constituent elements having the same function and configuration are denoted by the common reference signs. In addition, a plurality of constituent elements having the common reference signs are distinguished by adding a suffix to the common reference sign. Note that when it is not necessary to distinguish a plurality of constituent elements, the plurality of constituent elements are denoted by the common reference sign without adding any suffix. In this case, the suffix includes, in addition to a subscript and a superscript, for example, an index added to the end of the common reference sign to indicate an array.

[0028] (1) First Embodiment

[0029] A storage device according to the first embodiment will be described with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 .

[0030] (1a) Configuration Example

[0031] A configuration example of a storage device according to the embodiment will be described with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 .

[0032] Figure 1 is a block diagram showing an example of a configuration of a storage device according to the embodiment.

[0033] As Figure 1As shown, for example, the storage device 1 is connected to a device (hereinafter referred to as an external device) outside the storage device 1. The external device 9 sends a command CMD, an address ADR, and a control signal CNT to the storage device 1. At the time of writing, the external device 9 sends data to be written in the storage device 1 (hereinafter referred to as write data). At the time of reading, the external device 9 receives data read out from the storage device 1 (hereinafter referred to as read data) from the storage device 1.

[0034] The storage device 1 includes a storage cell array 10, a row control circuit 11, a column control circuit 12, a write circuit 13, a read circuit 14, a voltage generation circuit 15, an input / output circuit 16, and a control circuit 17.

[0035] The storage cell array 10 includes a plurality of storage cells MC, a plurality of word lines, and a plurality of bit lines.

[0036] Each of the plurality of storage cells is associated with a corresponding pair of row and column. Each storage cell MC is connected to a corresponding word line of the plurality of word lines WL. Each storage cell MC is connected to a corresponding bit line of the plurality of bit lines BL.

[0037] The row control circuit 11 is connected to the storage cell array 10 via the word lines WL. The row control circuit 11 receives a decoding result of a row (row address) with respect to the address ADR. The row control circuit 11 controls the plurality of word lines WL based on the decoding result with respect to the address ADR. With this operation, the row control circuit 11 sets the plurality of word lines WL (the plurality of rows) in a selected state and a non-selected state. In the following description, a word line WL set in the selected state is referred to as a selected word line WL, and a word line WL other than the selected word line WL is referred to as a non-selected word line WL.

[0038] The column control circuit 12 is connected to the storage cell array 10 via the bit lines BL. The column control circuit 12 receives a decoding result of a column (column address) with respect to the address ADR. The column control circuit 12 controls the plurality of bit lines BL based on the decoding result with respect to the address ADR. With this operation, the column control circuit 12 sets the plurality of bit lines BL (the plurality of columns) in a selected state and a non-selected state. In the following description, a bit line BL set in the selected state is referred to as a selected bit line BL, and a bit line BL other than the selected bit line BL is referred to as a non-selected bit line BL.

[0039] The write circuit 13 writes data in the storage cell MC. The write circuit 13 includes, for example, a write driver (not shown).

[0040] The read circuit 14 reads data from the storage cell MC. The read circuit 14 includes, for example, a preamplifier 141 and a sense amplifier 142. The detailed configuration of the preamplifier 141 and the sense amplifier 142 will be described later.

[0041] The voltage generating circuit 15 generates voltages for various types of operations of the memory cell array 10 by using a power supply voltage supplied from the external device 9. For example, the voltage generating circuit 15 generates various types of voltages for a write operation. The voltage generating circuit 15 outputs the generated voltages to the write circuit 13. For example, the voltage generating circuit 15 generates various types of voltages for a read operation. The voltage generating circuit 15 outputs the generated voltages to the read circuit 14.

[0042] The input / output circuit 16 functions as an interface circuit for various types of signals ADR, CMD, CNT, and DT between the memory device 1 and the external device 9.

[0043] The input / output circuit 16 transfers the address ADR from the external device 9 to the control circuit 17. The input / output circuit 16 transfers the command CMD from the external device 9 to the control circuit 17. The input / output circuit 16 transfers various control signals CNT between the external device 9 and the control circuit 17. The input / output circuit 16 transfers the data DT from the external device 9 to the write circuit 13. The input / output circuit 16 transfers the data DT transferred from the read circuit 14 to the external device 9.

[0044] The control circuit (also referred to as a sequencer, a state machine, or an internal controller) 17 decodes the command CMD. The control circuit 17 controls the operations of the row control circuit 11, the column control circuit 12, the write circuit 13, the read circuit 14, the voltage generating circuit 15, and the input / output circuit 16 in the memory device 1 on the basis of the decoding result of the command CMD, the control signals CNT, and the command CMD.

[0045] The control circuit 17 decodes the address ADR. The control circuit 17 sends the address decoding result to the row control circuit 11, the column control circuit 12, and the like. Note that a circuit (command decoder) for decoding a command and a circuit (address decoder) for decoding an address can be provided outside the control circuit 17 in the memory device 1.

[0046] (1a-1) Example of Configuration of Memory Cell Array

[0047] Figure 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array of the memory device according to the embodiment. Referring to Figure 2 , the word lines WL, the bit lines BL, and the memory cells MC are distinguished by suffixes (indices).

[0048] As shown in Figure 2 , a plurality of memory cells MC are arranged in a matrix pattern in the memory cell array 10. Each memory cell MC is connected to a plurality of bit lines BL (BL<0>, BL<1>,..., BL <n-1>corresponding bit line BL and a plurality of word lines WL (WL<0>, WL<1>,..., WL <m-1>corresponding word line WL in the memory cell array 100. In this case, m and n are arbitrary integers. The memory cell MC <i,j> (0≤i≤m-1, 0≤j≤n-1) is connected to the word line WL with bit line BL <j>between.

[0049] Each memory cell MC includes a switching element 20 and a memory element (variable resistance element) 21.

[0050] The switching element 20 functions as a selection element that controls supply of current (or voltage) to the memory element 21 at the time of writing data to and reading data from the corresponding memory element 21.

[0051] When a voltage applied to a given memory cell MC is lower than a threshold voltage Vth of the switching element 20 in the memory cell MC, for example, the switching element 20 is set in an OFF state (high resistance state or insulating state). In this case, the switching element 20 cuts off current to the memory cell MC.

[0052] When a voltage applied to a given memory cell MC is equal to or higher than a threshold voltage Vth of the switching element 20 in the memory cell MC, the switching element 20 is set in an ON state (low resistance state or conducting state). In this case, the switching element 20 causes current to flow into the memory cell MC.

[0053] The switching element 20 has a function of being able to switch whether to allow current to flow to the memory cell MC depending on the magnitude of a voltage applied to the memory cell MC, regardless of the direction of flow of the current.

[0054] The switching element 20 is, for example, a two-terminal element. The switching element 20 as a two-terminal element includes a layer provided between two terminals. The switching element 20 includes a layer (also referred to as a switching layer or a resistance change layer) having a function of switching between resistance states of the layer.

[0055] When a voltage applied between the two terminals of the switching element 20 is lower than a threshold voltage of the switching element 20, the switching element 20 is in a high resistance state (OFF state). In this case, the switching element 20 is set in a non-conductive state.

[0056] When a voltage applied between the two terminals of the switching element 20 is equal to or higher than the threshold voltage, the switching element 20 is in a low resistance state (ON state). In this case, the switching element 20 is set in a non-conductive state.

[0057] Preferably, the switching element 20 has a switching function (characteristic) with respect to a voltage applied to both of a positive electrode and a negative electrode of the switching element 20. Note, however, that the switching element 20 can have a switching function (characteristic) with respect to at least one of the positive electrode and the negative electrode of the switching element 20.

[0058] For example, the storage element 21 is a variable resistance element. The resistance state of the variable resistance element 21 changes to a plurality of resistance states (e.g., a low resistance state and a high resistance state) depending on a current (or a voltage) supplied thereto controlled by the switching element 20. The storage element 21 can store data by associating the resistance state of the element 21 with data (e.g., "0" data and "1" data).

[0059] Figure 3 and Figure 4 An example for illustrating the structure of the storage cell array of the storage device according to this embodiment is shown. Figure 3 is a schematic cross-sectional view showing the cross-sectional structure of the storage array along the X direction. Figure 4 is a schematic cross-sectional view showing the cross-sectional structure of the storage array along the Y direction.

[0060] As shown in Figure 3 and Figure 4 The storage cell array 10 is provided above the upper surface of the substrate 100.

[0061] In the following description, a plane parallel to the upper surface of the substrate 100 is defined as the X-Y plane, and a direction (axis) perpendicular to the X-Y plane is defined as the Z direction (Z axis).

[0062] A plurality of conductive layers 50 is provided above the upper surface of the substrate 100 in the Z direction. The plurality of conductive layers 50 is arranged along the Y direction. Each of the conductive layers 50 extends along the X direction. The plurality of conductive layers 50 functions as, for example, a word line WL.

[0063] Figure 3 and Figure 4 A case where the plurality of conductive layers 50 is in contact with the substrate 100 is shown. Note, however, that an insulating layer (not shown) can be provided between the plurality of conductive layers 50 and the substrate 100.

[0064] A plurality of conductive layers 51 is provided above the plurality of conductive layers 50 in the Z direction. The plurality of conductive layers 51 is arranged along the X direction. Each of the conductive layers 51 extends along the Y direction. The plurality of conductive layers 51 functions as, for example, a bit line BL.

[0065] A plurality of storage cells MC is provided between the plurality of conductive layers 50 and the plurality of conductive layers 51. The plurality of storage cells MC is arranged in a matrix pattern in the X-Y plane.

[0066] A plurality of storage cells MC arranged in the X direction is provided on one of the conductive layers 50. The plurality of storage cells MC arranged in the X direction is connected to a common word line WL.

[0067] A plurality of memory cells MC arranged in the Y direction is provided under the conductive layer 51. The plurality of memory cells MC arranged in the Y direction is connected to a common bit line BL.

[0068] For example, in each memory cell MC, a storage element (variable resistance element) 21 is provided on a switching element 20 in the Z direction. In this case, the switching element 20 is provided on the conductive layer (word line) 50. The conductive layer (bit line) 51 is provided on the variable resistance element 21.

[0069] Note that the configuration of the switching element 20 and the storage element 21 in the Z direction can be opposite to the arrangement shown in FIGS. 1A and IB. Figure 3 and Figure 4 In this case, the element 20 is provided on the element 21.

[0070] Depending on the memory cell array and the memory cell configuration, the conductive layer 50 and the conductive layer 51 can be used as the bit line BL and the word line WL, respectively.

[0071] The memory cell MC is a layer stack including the switching element 20 and the storage element 21.

[0072] The switching element 20, which is a two-terminal element, includes two electrodes 201, 203 and a switching layer (resistance change layer) 202. The switching layer 202 is provided between the two electrodes 201, 203 in the Z direction.

[0073] The storage element 21 is a variable resistance element. The variable resistance element 21 can have a plurality of resistance states (resistance values). The variable resistance element 21 is used as a storage element by associating the resistance state of the variable resistance element 21 with data (e.g., 1-bit data).

[0074] For example, the storage element 21 is a magnetoresistance effect element. In this case, the storage device according to this embodiment is a magnetic memory like an MRAM (magnetoresistive random access memory).

[0075] < Magnetoresistance Effect Element >

[0076] An example of the configuration of the storage element (magnetoresistance effect element) of the storage device according to this embodiment will be described with reference to Figure 5

[0077] Figure 5 is a cross-sectional view showing an example of the configuration of the magnetoresistance effect element. Figure 5 shows an example of a cross section along a plane (e.g., an X-Z plane) parallel to the Z direction of the storage element 21 shown in FIGS. 1A and IB. Figure 3 and Figure 4 In this case, the element 20 is provided on the element 21.

[0078] ​For example, the magnetoresistive effect element 21 includes at least two magnetic layers 211, 213 and a nonmagnetic layer 212. The nonmagnetic layer 212 is provided between the two magnetic layers 211, 213 in the Z direction. For example, a plurality of layers (i.e., the magnetic layer 211, the nonmagnetic layer 212, and the magnetic layer 213) are stacked from the word line WL side to the bit line BL side in this order.

[0079] The two magnetic layers 211, 213 and the nonmagnetic layer 212 arranged in the Z direction form a magnetic tunnel junction (MTJ). In the following description, the magnetoresistive effect element 21 including the magnetic tunnel junction will be described by way of example using an MTJ element 21. The nonmagnetic layer 212 of the MTJ element 21 will be referred to as a tunnel barrier layer.

[0080] The magnetic layers 211 and 213 are each, for example, a ferromagnetic layer including cobalt, iron, and / or boron. The magnetic layers 211 and 213 can each be a single layer film or a multi-layer film (e.g., an artificial lattice film). The tunnel barrier layer 212 is, for example, an insulating film including magnesium oxide. The tunnel barrier layer can be a single layer film or a multi-layer film.

[0081] For example, the magnetic layers 211 and 213 each have perpendicular magnetic anisotropy. The easy axis direction of each magnetic layer 211, 213 is perpendicular to the layer surface (film surface) of each magnetic layer 211, 213. The magnetization direction of each magnetic layer 211, 213 is parallel to the array direction (Z direction) of the magnetic layers 211, 213. The magnetic layers 211 and 213 each have magnetization perpendicular to the layer surface of each magnetic layer 211, 213.

[0082] As described above, in this embodiment, the MTJ element 21 is a magnetoresistive effect element of the perpendicular magnetization type.

[0083] One of the two magnetic layers 211 and 213 has a variable magnetization direction, and the other magnetic layer has an unchanging magnetization direction. Depending on the relative relationship (hereinafter referred to as the magnetization alignment) between the magnetization direction of one magnetic layer and the magnetization direction of the other magnetic layer, the MTJ element 21 can have a plurality of resistance states (resistance values).

[0084] In Figure 5 In the case shown, the magnetic layer 213 has a variable magnetization direction. The magnetic layer 211 has an unchanging (fixed) magnetization direction. In the following description, the magnetic layer 213 having a variable magnetization direction is referred to as a storage layer. In the following description, the magnetic layer 211 having an unchanging (fixed) magnetization direction is referred to as a reference layer. Note that the storage layer 213 is sometimes referred to as a free layer, a magnetization free layer, or a magnetization variable layer. The magnetic layer 211 is sometimes referred to as a pin layer, a pinned layer, a magnetization unchanging layer, or a magnetization fixed layer.

[0085] In this embodiment, "the reference layer (magnetic layer) has an unchanging magnetization direction" or "the reference layer (magnetic layer) has a fixed magnetization direction" means that the magnetization direction of the reference layer does not change when a current or voltage for changing the magnetization direction of the storage layer is supplied to the magnetoresistive effect element, regardless of whether the current or voltage is supplied before or after the supply of the current / voltage.

[0086] For example, the MTJ element 21 includes two electrodes 219A and 219B. The magnetic layers 211, 213 and the tunnel barrier layer 212 are provided between the two electrodes 219A and 219B in the Z direction. The reference layer 211 is provided between the electrode 219A and the tunnel barrier layer 212. The storage layer 213 is provided between the electrode 219B and the tunnel barrier layer 212.

[0087] For example, a shift canceling layer (not shown) can be provided in the MTJ element 21. The shift canceling layer is provided between the reference layer 211 and the electrode 219A. The shift canceling layer is a magnetic layer for mitigating the influence of a stray magnetic field from the reference layer 211.

[0088] A non-magnetic layer (not shown) is provided between the shift canceling layer and the reference layer 211. The non-magnetic layer is, for example, a metal layer such as a Ru (ruthenium) layer.

[0089] The reference layer 211 is antiferromagnetically coupled to the shift canceling layer through the non-magnetic layer. This causes the layer stack including the reference layer 211 and the shift canceling layer to form a SAF (synthetic antiferromagnetic) structure. In the SAF structure, the magnetization direction of the shift canceling is opposite to the magnetization direction of the reference layer 211. In the SAF structure, the magnetization direction of the reference layer 211 is set in a fixed state.

[0090] For example, the MTJ element 21 can include at least one of a base layer (not shown) and a cap layer (not shown). The base layer is provided between the magnetic layer (in this case, the reference layer) 211 and the electrode 219A. The base layer is a non-magnetic layer (for example, a conductive composite layer). The base layer is a layer for improving the properties (for example, crystallinity and / or magnetic properties) of the magnetic layer 211 in contact with the base layer. The cap layer is a non-magnetic layer (for example, a conductive composite layer) between the magnetic layer (in this case, the storage layer) 213 and the electrode 219B. The cap layer is a layer for improving the properties (for example, crystallinity and magnetic properties) of the magnetic layer 213 in contact with the cap layer. Note that the base layer and the cap layer can be considered as constituent elements of the electrode 219 (219A and 219B).

[0091] When the magnetization direction of the storage layer 213 is the same as the magnetization direction of the reference layer 211, the state of the magnetization alignment of the MTJ element 21 is a magnetization parallel state (hereinafter referred to as a P state). When the magnetization direction of the storage layer 213 is opposite to the magnetization direction of the reference layer 211, the state of the magnetization alignment of the MTJ element 21 is a magnetization antiparallel state (hereinafter referred to as an AP state).

[0092] An example of the relationship between the state of the magnetization alignment of the MTJ element 21 and the resistance value (magnetoresistance) of the MTJ element 21 is that the resistance value of the MTJ element 21 in the P state is lower than the resistance value of the MTJ element 21 in the AP state. In this case, the resistance state of the MTJ element in the P state corresponds to a low resistance state, and the resistance state of the MTJ element in the AP state corresponds to a high resistance state.

[0093] For example, "0" data is associated with the MTJ element 21 in the P state (low resistance state), and "1" data is associated with the MTJ element 21 in the AP state (high resistance state). Note, however, that the manner in which the state of the magnetization alignment (resistance state) of the MTJ element 21 is associated with "1" / "0" data is not limited to the above case.

[0094] With these characteristics of the MTJ element 21, the MTJ element 21 is used as a storage element.

[0095] Writing data into the storage unit MC using the MTJ element 21 is performed by controlling the magnetization direction of the storage layer 213 of the MTJ element 21. When data is written, the resistance state (resistance value) of the MTJ element 21 changes depending on the state of the magnetization alignment of the MTJ element 21.

[0096] When, for example, the magnetization direction of the storage layer 213 is switched by STT (spin transfer torque), a write current IWR (IWR0, IWR1) is supplied to the MTJ element 21.

[0097] Depending on whether the write current IWR flows from the storage layer 213 to the reference layer 211 or from the reference layer 211 to the storage layer 213, the state of the magnetization alignment of the MTJ element 21 is controlled to change from the AP state to the P state or from the P state to the AP state. The current value of the write current IWR is set to be smaller than the magnetization flipping threshold value of the reference layer 211 and equal to or greater than the magnetization flipping threshold value of the storage layer 213. Note that the magnetization flipping threshold value of the storage layer 213 is preferably greater than the threshold current for setting the switching element in the low resistance state.

[0098] The write current IWR flowing in the MTJ element 21 generates a spin torque that contributes to the magnetization flipping of the storage layer 213. The generated spin torque is applied to the storage layer 213.

[0099] When the magnetization alignment state of the MTJ element 21 is changed from the AP state to the P state (hereinafter also referred to as P write), a write current IWR0 flowing from the storage layer 213 to the reference layer 211 is supplied to the MTJ element 21. This applies a spin torque of a spin (electron) in the same direction as the magnetization direction of the reference layer 211 to the magnetization of the storage layer 213. When the magnetization direction of the storage layer 213 is opposite to the magnetization direction of the reference layer 211, the magnetization direction of the storage 213 is changed to the same direction as the magnetization direction of the reference layer 211 by the applied spin torque.

[0100] Accordingly, the magnetization alignment state of the MTJ element 21 is set to the P state. In this case, the MTJ element 21 holds "0" data.

[0101] When the magnetization alignment state of the MTJ element 21 is changed from the P state to the AP state (hereinafter also referred to as AP write), a write current IWR1 flowing from the reference layer 211 to the storage layer 213 is supplied to the MTJ element 21. This applies a spin torque of a spin in the opposite direction to the magnetization direction of the reference layer 211 to the magnetization of the storage layer 213. When the magnetization direction of the storage layer 213 is the same as the magnetization direction of the reference layer 211, the magnetization direction of the storage layer 213 is changed to the opposite direction to the magnetization direction of the reference layer 211 by the applied spin torque.

[0102] Accordingly, the magnetization alignment state of the MTJ element 21 is set to the AP state. In this case, the MTJ element 21 holds "1" data.

[0103] Data is read from the memory cell MC by discriminating the magnetization alignment state (resistance value) of the MTJ element 21. At the time of data read, a current flows in the MTJ element 21 in accordance with a voltage applied to the memory cell MC. The current value of the current at the time of data read is set to a value smaller than the magnetization flip threshold value of the storage layer 213.

[0104] The resistance value (magnetization alignment state) of the MTJ element 21 is equivalently discriminated on the basis of the amplitude of an output signal (for example, current or voltage) from the MTJ element 21 at the time of application of a voltage to the memory cell MC.

[0105] With this operation, data in the memory cell MC is discriminated and read.

[0106] In this embodiment, a read operation is performed on the basis of a self-reference scheme. The read operation on the basis of the self-reference scheme will be described later in detail.

[0107] (a-2) Configuration of read circuit

[0108] Reference will be made to Figure 6 , Figure 7 and Figure 8 An example of a configuration of a read circuit of a storage device (e.g., MRAM) according to this embodiment will be described.

[0109] Figure 6 is a block diagram for explaining a configuration of a read circuit of MRAM according to this embodiment.

[0110] As shown in Figure 6 , the read circuit 14 includes one or more preamplifiers (also referred to as pre-stage sense amplifier circuits) 141 and one or more sense amplifiers (also referred to as post-stage sense amplifier circuits) 142.

[0111] For example, the preamplifiers 141 and the sense amplifiers 142 are made to correspond to bit lines BL (columns). One preamplifier 141 and one sense amplifier 142 are provided for one bit line BL. Note that one pair of a preamplifier 141 and a sense amplifier 142 can be provided for a group of two or more bit lines BL.

[0112] The preamplifier 141 is connected to the storage unit MC via the corresponding bit line BL. The preamplifier 141 can sense a signal based on data in the storage unit MC.

[0113] The preamplifier 141 is connected to the corresponding sense amplifier 142 via nodes NDe and NDf. Note that each node is a constituent element including an interconnection line, a contact point, and a terminal.

[0114] The preamplifier 141 senses and amplifies a plurality of signals (voltage or current) from the storage unit MC. The preamplifier 141 holds the sensed and amplified signals in the nodes NDe and NDf.

[0115] The sense amplifier 142 senses a signal (voltage or current) supplied to the nodes NDe and NDf, and amplifies the sensed signal.

[0116] The sense amplifier 142 distinguishes data in the storage unit MC based on the sensed and amplified signal. The data in the storage unit MC is output as signals DO and DOB to the outside of the read circuit 14.

[0117] As described above, the read circuit 14 uses the preamplifier 141 and the sense amplifier 142 to read data in the storage unit MC (storage unit array).

[0118] <Sense Amplifier>

[0119] An example of a configuration of a sense amplifier (post-stage sense amplifier circuit) of a storage device according to this embodiment will be described with reference to Figure 7

[0120] ​ Figure 7 is a circuit diagram for explaining a configuration of a sense amplifier of a storage device according to this embodiment. As shown in Figure 7 , the sense amplifier 142 includes a plurality of transistors TR1 to TR18.

[0121] The transistors TR1, TR2, TR3, TR4, TR5, and TR6 are, for example, field effect transistors (e.g., MOS transistors) having p-type conductivity. The transistors TR7, TR8, TR9, TR10, TR11, TR12, TR13, TR14, TR15, TR16, TR17, and TR18 are, for example, field effect transistors (e.g., MOS transistors) having n-type conductivity.

[0122] Each of the transistors TR1 to TR18 includes a plurality of terminals (e.g., source and drain) and a gate.

[0123] One of the terminals (one of the source and drain) of the transistor TR1 is connected to a terminal to which a voltage (e.g., a power supply voltage) VDD is applied. The voltage VDD is supplied to one of the terminals (one of the source and drain) of the transistor TR1. The terminal (or node) to which the power supply voltage VDD is applied will be hereinafter denoted as a power supply terminal (or power supply node) VDD.

[0124] The other of the terminals (the other of the source and drain) of the transistor TR1 is connected to a node ND1.

[0125] A signal LATNB is supplied to the gate of the transistor TR1. The signal LATNB is, for example, an inverted signal of a signal LATN (to be described later).

[0126] One of the terminals of the transistor TR2 is connected to the node ND1. The other of the terminals of the transistor TR2 is connected to a node ND2. The gate of the transistor TR2 is connected to a node ND3.

[0127] One of the terminals of the transistor TR3 is connected to the node ND1. The other of the terminals of the transistor TR3 is connected to the node ND3. The gate of the transistor TR3 is connected to the node ND2.

[0128] One of the terminals of the transistor TR4 is connected to the node ND3. The other of the terminals of the transistor TR4 is connected to the node ND2. A signal SEN is supplied to the gate of the transistor TR4. The signal SEN is, for example, a signal indicating the start of a process (which will be hereinafter referred to as a sensing process) of sensing the voltages supplied to the nodes NDe and NDf (activation of the sense amplifier 142).

[0129] One terminal of the transistor TR5 is connected to a power supply terminal VDD. A power supply voltage VDD is supplied to one terminal of the transistor TR5. The other terminal of the transistor TR5 is connected to a node ND2. A signal SEN is supplied to the gate of the transistor TR5.

[0130] One terminal of the transistor TR6 is connected to a voltage terminal VDD. A power supply voltage VDD is supplied to one terminal of the transistor TR6. The other terminal of the transistor TR6 is connected to a node ND3. A signal SEN is supplied to the gate of the transistor TR6.

[0131] One terminal of the transistor TR7 is connected to the node ND2. The other terminal of the transistor TR7 is connected to a node ND4. The gate of the transistor TR7 is connected to the node ND3.

[0132] One terminal of the transistor TR8 is connected to the node ND3. The other terminal of the transistor TR8 is connected to a node ND5. The gate of the transistor TR8 is connected to the node ND2.

[0133] One terminal of the transistor TR9 is connected to the node ND4. The other terminal of the transistor TR9 is connected to a terminal to which a ground voltage VSS is applied. A ground voltage VSS is supplied to one terminal of the transistor TR9. The terminal (or node) to which the ground voltage VSS is applied will be hereinafter denoted as a ground terminal (or ground node) VSS. A signal LATN is supplied to the gate of the transistor TR9. The signal LATN is, for example, a signal indicating the end of a sensing process.

[0134] One terminal of the transistor TR10 is connected to the node ND5. The other terminal of the transistor TR10 is connected to the ground terminal VSS. A signal LATN is supplied to the gate of the transistor TR10.

[0135] One terminal of the transistor TR11 is connected to the node ND4. The other terminal of the transistor TR11 is connected to a node ND6. A signal SEN2 is supplied to the gate of the transistor TR11. The signal SEN2 is, for example, a signal indicating the start of a sensing process together with the signal SEN.

[0136] One terminal of the transistor TR12 is connected to the node ND5. The other terminal of the transistor TR12 is connected to a node ND7. A signal SEN2 is supplied to the gate of the transistor TR11.

[0137] One terminal of the transistor TR13 is connected to the node ND6. The other terminal of the transistor TR13 is connected to the ground terminal VSS. The ground voltage VSS is supplied to the other terminal of the transistor TR13. The gate of the transistor TR13 is connected to the node NDe. The signal (voltage) VSMPL from the preamplifier 141 is supplied to the gate of the transistor TR13 via the node NDe. The gate of the transistor TR13 becomes one input terminal of the sense amplifier 142. The transistor TR13 functions as an input unit for the signal (voltage VSMPL) from the preamplifier 141 to the sense amplifier 142.

[0138] One terminal of the transistor TR14 is connected to the node ND7. The other terminal of the transistor TR14 is connected to the ground terminal VSS. The ground voltage VSS is supplied to the other terminal of the transistor TR14. The gate of the transistor TR14 is connected to the node NDf. The signal (voltage) VEVAL from the preamplifier 141 is supplied to the gate of the transistor TR14 via the node NDf. The gate of the transistor TR14 becomes the other input terminal (input unit) of the sense amplifier 142. The transistor TR14 functions as an input unit for the signal (voltage VEVAL) from the preamplifier 141 to the sense amplifier 142.

[0139] One terminal of the transistor TR15 is connected to the node ND6. The other terminal of the transistor TR15 is connected to one terminal of the transistor TR16. The signal SHFTDOB is supplied to the gate of the transistor TR15. The signal SHFTDOB is, for example, a signal indicating whether the sense amplifier 142 senses the value corresponding to the voltage VSMPL of the node NDe with an offset (bias) of the value.

[0140] The other terminal of the transistor TR16 is connected to the ground terminal VSS. The voltage VSHFTa is supplied to the gate of the transistor TR16. The voltage VSHFTa is, for example, a signal voltage indicating the offset value (bias amount) of the voltage VSMPL of the node NDe (or the value corresponding to the voltage VSMPL).

[0141] One terminal of the transistor TR17 is connected to the node ND7. The other terminal of the transistor TR17 is connected to one terminal of the transistor TR18. The signal SHFTDO is supplied to the gate of the transistor TR17. The signal SHFTDO is an inverted signal of the signal SHFTDO. The signal SHFTDO is, for example, a signal indicating whether the sense amplifier 142 senses the voltage VEVAL of the node NDf (or the value corresponding to the voltage VEVAL) with an offset (bias).

[0142] The other terminal of the transistor TR18 is connected to the ground terminal VSS. The voltage VSHFTb is supplied to the gate of the transistor TR18.

[0143] The voltage VSHFTb is a voltage indicating an offset value of a value corresponding to the voltage VEVAL of the node NDf.

[0144] The output terminal OT1 of the sense amplifier 142 is connected to the node ND2. A signal DO is output from the output terminal OT1 to the outside of the sense amplifier 142.

[0145] The output terminal OT2 of the sense amplifier 142 is connected to the node ND3. A signal DOB is output from the output terminal OT2 to the outside of the sense amplifier 142. The signal DOB is an inverted signal of the signal DO.

[0146] In this embodiment, the transistors TR15 and TR16 function as the offset circuit 72a.

[0147] The offset circuit 72a including the transistors TR15 and TR16 adds a given offset value (offset current) to the output (current) from the transistor TR13 according to the voltage VSMPL of the node NDe. This makes it possible to equivalently offset the value of the voltage VSMPL within the sense amplifier 142. The amount of offset to be added by the offset circuit 72a is set according to the voltage value of the signal VSHFT.

[0148] In this embodiment, the transistors TR17 and TR18 function as the offset circuit 72b.

[0149] The offset circuit 72b including the transistors TR17 and TR18 adds a given offset value to the output (current) from the transistor TR14 corresponding to the voltage VEVAL of the node NDf. This makes it possible to equivalently offset the value of the voltage VEVAL within the sense amplifier 142. The amount of offset to be added by the offset circuit 72b is set according to the voltage value of the signal VSHFT.

[0150] Figure 7 The sense amplifier 142 in the preamplifier 140 can compare the amplitude of the voltage VSMPL of the node NDe with the amplitude of the voltage VEVAL of the node NDf.

[0151] The sense amplifier 142 can output a signal based on the comparison result as the signals DO and DOB to the output terminals OT1 and OT2, respectively.

[0152] <Pre-amplifier>

[0153] An example of the configuration of the pre-amplifier (pre-stage sense amplifier circuit) of the storage device according to this embodiment will be described with reference to Figure 8 ​

[0154] Figure 8 is a circuit diagram for illustrating an example of a configuration of a preamplifier of an MRAM according to this embodiment.

[0155] With the configuration in Figure 8 , the preamplifier 141 can sense, amplify, and hold a signal from the memory cell MC based on data (resistance state of the MTJ element) in the memory cell as a sensing result.

[0156] As shown in Figure 8 , the sense amplifier 142 includes a plurality of transistors TRa, TRb, TRc, TRd, TRe, TRf, TRg, TRh, TRi, TRp, and TRq. The transistors TRa, TRb, TRe, TRf, TRh, TRp, and TRq are, for example, field effect transistors (e.g., MOS transistors) having n-type conductivity. The transistors TRc, TRd, TRg, and TRi are, for example, field effect transistors (e.g., MOS transistors) having p-type conductivity.

[0157] Each of the transistors TRa, TRb, TRc, TRd, TRe, TRf, TRg, TRh, TRi, TRp, and TRq includes a plurality of terminals (source and drain) and a gate.

[0158] One terminal of the transistor TRa is connected to the bit line BL via the node DNa. The other terminal of the transistor TRa is connected to the node NDb. The signal REN is supplied to the gate of the transistor TRa. The signal REN is, for example, a signal indicating the start and end of a data read operation from the memory cell MC.

[0159] One terminal of the transistor TRb is connected to the node NDb. The other terminal of the transistor TRb is connected to the node NDc. The signal VCLMP is supplied to the gate of the transistor TRb. The signal VCLMP is, for example, a signal for regulating (clamping) a voltage applied to the memory cell MC via the transistors TRa and TRb to a predetermined amplitude.

[0160] One terminal of the transistor TRc is connected to the node NDc. The other terminal of the transistor TRc is connected to the power supply terminal VDD. The gate of the transistor TRc is connected to the node NDc.

[0161] One terminal of the transistor TRd is connected to the power supply terminal VDD. The other terminal of the transistor TRd is connected to the node NDd. The gate of the transistor TRd is connected to the node NDc.

[0162] The transistors TRc and TRd serve as a current mirror circuit 70. The current mirror circuit 70 including the transistors TRc and TRd is configured to cause a current (hereinafter also referred to as a mirror current or a replica current) Imr corresponding to a current (hereinafter also referred to as a cell current) Icell flowing in the memory cell MC to flow into the node NDd when a read operation is performed.

[0163] A current ratio between the mirror current Imr and the cell current Icell in the current mirror circuit 70 is set in accordance with a ratio between gate sizes (e.g., gate widths) of the two transistors TRc and TRd. In this embodiment, for example, the gate width of the transistor TRd is set to a substantially same gate width as the gate width of the transistor TRc. In this case, the amplitude of the mirror current Imr is substantially the same as the amplitude of the cell current.

[0164] One terminal of the transistor TRe is connected to the node NDd. The other terminal of the transistor TRe is connected to the ground terminal VSS. The gate of the transistor TRe is connected to the node NDe. When the transistors TRg and TRf (to be described later) are in the ON state, the gate of the transistor TRe is electrically connected to the node NDd (and one terminal of the transistor TRe) via the transistors TRg and TRf in the ON state. In this case, the transistor TRe is diode-connected to the node NDd. The transistor TRe will also be referred to as a diode-connected transistor TRe.

[0165] One terminal of the transistor TRf is connected to the node NDd. The other terminal of the transistor TRf is connected to the node NDe. The signal S1 is supplied to the gate of the transistor TRf.

[0166] One terminal of the transistor TRg is connected to the node NDd. The other terminal of the transistor TRg is connected to the node NDe. The signal S1b is supplied to the gate of the transistor TRg. The signal S1b is an inverse signal of the signal S1.

[0167] The transistors TRg and TRf serve as a MOS switch (switching element) SW1. The MOS switch SW1 controls electrical connection and electrical disconnection between the node NDd and the node NDe. The transistors TRg and TRf can be controlled to be simultaneously set in the ON state or the OFF state by the signals S1 and S1b having a complementary relationship.

[0168] One terminal of the transistor TRh is connected to the node NDd. The other terminal of the transistor TRh is connected to the node NDf. The signal S2 is supplied to the gate of the transistor TRf.

[0169] One terminal of the transistor TRi is connected to the node NDd. Another terminal of the transistor TRi is connected to the node NDf. The signal S2b is supplied to the gate of the transistor TRi. The signal S2b is an inverted signal of the signal S2.

[0170] The transistors TRh and TRi function as a MOS switch SW2. The MOS switch SW2 controls electrical connection and electrical disconnection between the node NDd and the node NDf. The transistors TRh and TRi can be controlled to be simultaneously set in the ON state or the OFF state by the signals S2 and S2b having a complementary relationship.

[0171] The nodes NDe and NDf function as output terminals of the preamplifier 141.

[0172] The node NDe is connected to the gate of the transistor TR13 (one input terminal of the sense amplifier 142) of the sense amplifier 142 (described above). The node NDe includes a capacitance component Cl. For example, the capacitance component Cl is an interconnection capacitance (parasitic capacitance of interconnection lines and terminals) of the node NDe. The size of the capacitance component Cl (and the charging time of the capacitance component Cl) is set so that the transistors TRe and TR13 can be driven by a voltage held in the capacitance component Cl (for example, a charging voltage of the node NDe).

[0173] The node NDf is connected to the gate of the transistor TR14 (another input terminal of the sense amplifier) of the sense amplifier 142 described above. The node NDf includes a capacitance component C2. For example, the capacitance component C2 is an interconnection capacitance (parasitic capacitance of interconnection lines and terminals) of the node NDf. The size of the capacitance component C2 (and the charging time of the capacitance component C2) is set so that the transistor TR14 can be driven by a voltage held in the capacitance component C2 (for example, a charging voltage of the node NDf).

[0174] Note that each of the capacitance components Cl and C2 is not limited to an interconnection capacitance of a node, and can be an element (for example, a capacitor) connected to the node NDe or NDf.

[0175] Each of the nodes NDe and NDf can hold a signal sensed by the capacitance component Cl or C2.

[0176] The node NDe can hold a result of sensing the cell current Icell at the first processing time with the capacitance component Cl. For example, the node NDe is charged with a current supplied to the node NDe. This causes the node NDe to hold a voltage VSMPL in the capacitance component Cl as a result of sensing.

[0177] The node NDf can hold a sensing result of the cell current Icell at the time of the second processing performed after the first processing, with the capacitance component C2. For example, the node NDf is charged with the current supplied to the node NDf. This causes the node NDf to hold the voltage VEVAL in the capacitance component C2 as the sensing result.

[0178] In the MRAM 1 according to this embodiment, the preamplifier 141 includes the offset circuit 71a. In the embodiment, the preamplifier 141 can control the current driving force of the diode-connected transistor TRe by using the offset circuit 71a.

[0179] The offset circuit 71a is connected to the node NDd, the node NDe, and the ground terminal VSS.

[0180] The offset circuit 71a includes transistors TRp and TRq.

[0181] One terminal of the transistor TRp is connected to the node NDd. The other terminal of the transistor TRp is connected to one terminal of the transistor TRq. The other terminal of the transistor TRq is connected to the ground terminal VSS. The gate of the transistor TRp is connected to the node NDe (and the gate of the transistor TRe). The signal OFST1 is supplied to the gate of the transistor TRq.

[0182] The offset circuit 71a is activated or not activated according to the signal level of the signal OFST1. The transistor TRq is on / off controlled according to the signal level of the signal OFST1.

[0183] The offset circuit 71a adds an offset value of a given size to the mirror current Imr based on the cell current Icell in the selected cell MC-s to offset the sensing result obtained by the preamplifier 141. The offset circuit 71a causes the offset current Iofst1 to flow from the node NDd to the ground terminal VSS to add the offset value to the current Imr.

[0184] In the offset circuit 71a in the activated state, the offset current Iofst1 flows from the node NDd to the ground terminal VSS via the current paths (channels) of the transistors TRp and TRq.

[0185] When the offset circuit 71 is set in the activated state, the signal level of the signal OFST1 is set at the "H (high)" level. The transistor TRq is set in the ON state by the "H" level signal OFST1. The transistor TRq in the ON state electrically connects the transistor TRp to the ground terminal VSS. In this case, the offset current Iofst1 flows in the current paths of the transistors TRp and TRq.

[0186] The offset circuit 71a draws the current Iofst1 from the node NDd to the ground terminal VSS.

[0187] When the offset circuit 71a is set in the inactive state, the signal level of the signal OFST1 is set at the "L (low)" level. The "L" level signal OFST1 sets the transistor TRq in the OFF state. The transistor TRq in the OFF state electrically disconnects the transistor TRp from the ground terminal. In this case, the offset current Iofst1 does not flow in the current path of the transistors TRp and TRq.

[0188] For example, the current value of the offset current Iofst1 is smaller than the current value of the mirror current (the current output from the transistor TRd) Imr. The magnitude of the current value of the offset current Iofst1 is set in accordance with the current driving force of the transistor TRp.

[0189] The current driving force of the transistor TRp can be set in accordance with the gate size (gate width) of the transistor TRp. The gate width of the transistor TRp is smaller than the gate width of the transistor TRe. For example, the gate width of the transistor TRp is set to be about 0.1 to 0.2 times the gate width of the transistor TRe. In this case, the current value of the offset current Iofst1 is about 0.1 to 0.2 times the current value of the current Imr output from the transistor TRd.

[0190] In this way, the upper limit of the current value of the offset current Iofst1 is set based on the gate size of the transistor TRp.

[0191] The current value of the offset current Iofst1 changes in accordance with the potential of the node NDe applied to the gate of the transistor TRp, in which the current value based on the gate size of the transistor TRp is the upper limit.

[0192] In this way, in this embodiment, the offset circuit 71a can increase the driving force of the transistor (diode-connected transistor) TRe.

[0193] The above configuration allows the preamplifier 141 to hold a plurality of signals (voltages) corresponding to a plurality of cell currents in the given memory cell MC, respectively, in the node NDe and the node NDf, respectively, at the time of a read operation based on a self-reference scheme (to be described later).

[0194] The potential of the node NDe corresponds to the cell current Icell in the memory cell MC and the mirror current Imr in the preamplifier 141. Therefore, the potential of the node NDe includes the influence of the characteristic variation among the elements (e.g., the transistor TR) in the memory cell MC and the preamplifier 141. Therefore, the influence of the characteristic variation among the memory cell MC and the transistor TR can be reflected in the current value of the offset current Iofst1.

[0195] For this reason, the MRAM 1 according to this embodiment can reduce the influence of the PVT (process-voltage-temperature) variation among the memory cell MC and the transistor TR on the sensing result by using the offset circuit 71a.

[0196] Therefore, the MRAM 1 according to this embodiment can automatically reduce the adverse influence of the characteristic variation among the memory cell MC and the transistor TR on the sensing result. This allows the MRAM 1 according to this embodiment to shorten the charging time (rise time and fall time of the signal voltage) of the nodes NDe and NDf.

[0197] The MRAM 1 according to this embodiment can increase the potential difference between the voltage VSMPL and the voltage VEVAL by providing the offset current Iofst1 in the preamplifier 141. This allows the MRAM 1 according to this embodiment to improve the read margin. This allows the MRAM 1 according to this embodiment to improve the reliability of data reading.

[0198] The MRAM 1 according to this embodiment can improve the read operation characteristics by using the preamplifier 141 including the offset circuit 71.

[0199] (1b) Operation

[0200] An example of the operation of the storage device (e.g., MRAM) according to this embodiment will be described with reference to Figure 9 , Figure 10 , Figure 11 and Figure 12 An example of the operation of the storage device (e.g., MRAM) according to this embodiment will be described with reference to

[0201] Note that in the MRAM according to this embodiment, data is written to the memory cell MC by a known data write technique. Therefore, the description of the data write operation will be omitted.

[0202] (1b-1) Read operation based on self-reference scheme

[0203] Figure 9 is a flowchart for explaining the read operation based on the self-reference scheme in the MRAM according to this embodiment. Figure 9 Various types of processing performed when reading data from a given memory cell MC are shown.

[0204] <st10>

[0205] As Figure 9 shown in FIG. 10, in the read operation based on the self-reference scheme, in step ST10, the MRAM 1 reads first data from the memory cell (selected cell) MC-s as a data read target (hereinafter, also referred to as a first cell access process). The control circuit 17 controls the read circuit 14 (e.g., the preamplifier 141) to perform the first cell access process.

[0206] The first cell access process includes a process of charging the node NDe of the preamplifier 141 to a voltage VSMPL based on data (herein referred to as user data) stored in the selected cell MC-s by accessing the selected cell MC-s.

[0207] In this way, in the first cell access process, the control circuit 17 charges the node NDe to the voltage VSMPL based on the data stored in the selected cell MC-s in step ST10. As a result, in the first cell access process, the preamplifier 141 senses the voltage VSMPL as a signal from the selected cell MC-s.

[0208] <st20>

[0209] In the read operation based on the self-reference scheme, in step ST20, the MRAM 1 performs a predetermined data write (hereinafter referred to as reset write processing) for the selected cell MC-s.

[0210] The control circuit 17 controls the write circuit 13 for the reset write processing.

[0211] The reset write processing includes a process of resetting the data stored in the selected cell MC-s by writing predetermined data (hereinafter referred to as reference data or reset data) to the selected cell MC-s.

[0212] In this embodiment, by the reset write processing, "0" data is written to the selected cell MC-s. However, note that by the reset write processing, "1" data can also be written to the selected cell MC-s.

[0213] <st30>

[0214] In the read operation based on the self-reference scheme, after the reset write processing, in step ST30, the MRAM 1 performs second data reading with respect to the selected cell MC-s (hereinafter also referred to as second cell access processing). The control circuit 17 controls the read circuit 14 (e.g., the preamplifier 141) for the second cell access processing.

[0215] The second cell access processing includes processing of accessing the selected cell MC-s and charging the node NDf of the preamplifier 141 to the voltage VEVAL based on the data in the selected cell MC-s.

[0216] In this way, in the second cell access processing, the control circuit 17 charges the node NDf to the voltage VEVAL based on the reference data written in the selected cell MC-s in step ST20. As a result, in the second cell access processing, the preamplifier 141 senses the voltage VEVAL as a signal from the selected cell MC-s.

[0217] In this embodiment, the control circuit 17 controls the operation of the offset circuit 71a of the preamplifier 141 in the second cell access processing. The offset circuit 71a adds an offset value of a given size to the sensing result (e.g., a mirror current based on a cell current) at the time of the second cell access processing.

[0218] <st40>

[0219] In the read operation based on the self-reference scheme, in step ST40, the MRAM 1 performs sensing processing. The control circuit 17 controls the read circuit 14 (e.g., the sense amplifier 142) for the sensing processing.

[0220] The sensing processing includes processing of comparing the voltage VSMPL charged to the node NDe in step ST10 with the voltage VEVAL charged to the node NDf in step ST30. With this processing, the sense amplifier 142 determines whether the data (user data) stored in the selected cell MC-s is identical to the reference data.

[0221] As described above, the MRAM 1 according to this embodiment can read data from the selected cell MC-s by the read operation based on the self-reference scheme.

[0222] (1b-2) Operation Example

[0223] Figure 10 is a timing chart for explaining the read operation of the MRAM according to this embodiment. Figure 10 is shown in Figure 9 The various types of signals supplied to the preamplifier 141 and the sense amplifier 142 and the voltages charged to the nodes NDe and NDf in the various types of processing in the read operation based on the self-reference scheme shown in Figure 10 In the case of

[0224] Upon issuance of a request for an operation of the MRAM 1 according to this embodiment, the external device 9 transmits a command CMD, an address ADR, and a control signal CNT to the MRAM 1 according to the embodiment. The MRAM 1 receives the command CMD, the address ADR, and the control signal CNT. The control circuit 17 performs an operation with respect to a storage cell (selected cell) based on the address ADR according to the command CMD.

[0225] When the command CMD indicates a read operation, in the MRAM 1 according to this embodiment, the control circuit 17 performs various types of control for performing the read operation based on the self-reference scheme.

[0226] <Time t0 to time t3: S10>

[0227] As Figure 10 shown, in the read operation based on the self-reference scheme, the control circuit 17 performs the first cell access processing (first data read) in a period including an interval from time t0 to time t2 based on the processing sequence for the read operation based on the self-reference scheme.

[0228] Control circuit 17 activates preamplifier 141 of read circuit 14. Preamplifier 141 controls the signal level of various types of signals under the control of control circuit 17.

[0229] At time t0, preamplifier 141 changes the signal level of signal REN from "L" to "H". In preamplifier 141, transistor TR1 is set to the ON state. Preamplifier 141 applies a predetermined voltage VCLMP to the gate of transistor TR2. Transistor TR2 controls the potential of the bit line BL connected to the selected cell MC-s (the selected bit line).

[0230] For example, the read circuit 14 (e.g., preamplifier 141) applies a ground voltage VSS to the word line (selected word line) WL connected to the selected cell MC-s. With this operation, a predetermined voltage (also referred to hereinafter as the read voltage) is applied to the cell MC-s selected for the read target.

[0231] The application of the read voltage (or the current generated by the read voltage) sets the switching element 20 in the selected cell MC-s to the ON state. This allows the selected cell MC-s to access the preamplifier 141.

[0232] Figure 11 The internal state of the preamplifier in the MRAM according to this embodiment is schematically shown during the first cell access process in a read operation based on a self-reference scheme.

[0233] like Figure 11 As shown, the selected unit MC-s is electrically connected to the transistor TRc of the current mirror circuit 70 in the preamplifier 141 via transistors TRa and TRb, which are in the ON state.

[0234] After time t0, the cell current Icell1 flows in the selected cell MC-s (between bit line BL and word line WL). The current value of cell current Icell1 corresponds to the user data (resistance state of MTJ element) in the selected cell MC-s. The potential (voltage value) of node NDc varies according to the amplitude of cell current Icell1.

[0235] The current mirror circuit 70, including transistors TRc and TRd, causes a mirror current Imr1 (the potential of node NDc) based on the cell current Icell1 to flow into node NDd. When the gate size (e.g., gate width) of transistor TRd is substantially the same as the gate size (e.g., gate width) of transistor TRc, the current value of the mirror current Imr1 output from transistor TRd is substantially equal to the current value of the cell current Icell1.

[0236] The preamplifier 141 sets the signal level of the signal S2 at the "L" level and sets the signal level of the signal S2b at the "H" level. This sets the transistors TRh and TRi of the MOS switch SW2 in the OFF state. The node NDd is electrically disconnected from the node NDf through the MOS switch SW2 in the OFF state.

[0237] At the time t1, the preamplifier 141 changes the signal level of the signal S1 from the "L" level to the "H" level and changes the signal level of the signal S1b from the "H" level to the "L" level. This sets the transistors TRf and TRg of the MOS switch SW1 in the ON state. The node NDd is electrically connected to the node NDe through the MOS switch SW1 in the ON state.

[0238] In this embodiment, the preamplifier 141 maintains the signal level of the signal OFST1 at the "L" level at the time of the first cell access processing. This sets the offset circuit 71a in the inactive state. No current flows in the transistor TRp.

[0239] Therefore, the offset circuit 71a does not apply the offset current Iofst1 to the mirror current Imr1 at the time of the first access processing.

[0240] The mirror current Imr1 flows from the node NDd to the node NDe through the MOS switch SW1 in the ON state as the current Ismpl1. The capacitor component Cl of the node NDe is charged with the supplied current Ismpl1. The current value of the current Ismpl1 flowing into the node NDe is substantially equal to the current value of the mirror current Imr1 output from the current mirror circuit 70.

[0241] With this operation, the capacitor component Cl of the node NDe is charged to a voltage (hereinafter also referred to as a charging voltage) VSMPL having a given voltage value. For example, the voltage value of the voltage VSMPL (the potential of the node NDe) rises from the ground voltage VSS to a given voltage value.

[0242] The voltage value of the charging voltage VSMPL can have a magnitude corresponding to the current value of the current Ismpl1. The voltage value of the voltage VSMPL of the node NDe is slightly different between when the user data in the selected cell MC-s is "0" data and when the user data in the selected cell MC-s is "1" data.

[0243] For example, the voltage value of the voltage VSMPL when the "0" data is stored in the selected cell MC-s is "V1". The voltage VSMPL when the "1" data is stored in the selected cell MC-s has a voltage value (V1- δa) lower than the voltage value V1 by a value δa (> 0).

[0244] For example, the voltage value of the voltage VSMPL of the node NDe stabilizes at the time ta.

[0245] Subsequently, at the time 2, the preamplifier 141 changes the signal level of the signal S1 from the "H" level to the "L" level, and changes the signal level of the signal S1b from the "L" level to the "H" level.

[0246] This sets the transistors TRg and TRf of the MOS switch SW1 in the OFF state. The node NDe is electrically disconnected from the node NDd through the MOS switch SW1 in the OFF state. As a result, the charging of the node NDe stops.

[0247] At the time t3, the preamplifier 141 changes the signal level of the signal REN from the "H" level to the "L" level. This sets the transistor TRa in the OFF state. The preamplifier 141 is electrically disconnected from the selected cell MC-s through the transistor TRa in the OFF state.

[0248] As a result, the supply of the current (and voltage) from the preamplifier 141 to the selected cell MC-s stops.

[0249] In this way, the first cell access processing in the self-reference scheme-based read operation terminates.

[0250] <Time t4 to time t5: S20>

[0251] In the self-reference scheme-based read operation in the MRAM 1 according to this embodiment, the control circuit 17 performs the reset write processing in the interval from the time t4 to the time t5.

[0252] At the time t4, the control circuit 17 changes the signal level of the control signal CNT-WR for the write circuit 13 from the "L" level to the "H" level. This sets the write circuit 13 in the active state. The write circuit 13 writes the reference data (for example, "0" data) to the selected cell MC-s while the write current is supplied. This sets the selected cell MC-s in the reset state (reference data holding state).

[0253] Note that, in the reset write processing, the node NDf of the preamplifier 141 is set in the floating state. For this reason, the potential of the node NDf can be lowered to, for example, close to the ground voltage VSS.

[0254] At the time t5, the control circuit 17 changes the signal level of the signal CNT-WR from the "H" level to the "L" level. The "L" level signal CNT-WR sets the write circuit 13 in the inactive state. The write circuit 13 stops supplying the write current to the selected cell MC-s.

[0255] In this way, the reset write processing in the self-reference scheme-based read operation is terminated.

[0256] <Time t6 to time t9: S30>

[0257] In the self-reference scheme-based read operation in the MRAM 1, the control circuit 17 performs the second cell access processing in the interval from time t6 to time t9.

[0258] The control circuit 17 activates the preamplifier 141. The preamplifier 141 controls the signal level of various types of signals under the control of the control circuit 17.

[0259] At time t6, the preamplifier 141 changes the signal REN from the "L" level to the "H" level. The transistor TRa is set in the ON state. The predetermined voltage is applied to the selected cell MC-s. The switching element 20 in the selected cell MC-s is set in the ON state by the applied voltage (or current). This causes the preamplifier 141 to access the selected cell MC-s.

[0260] Figure 12 The internal state of the preamplifier in the MRAM according to the embodiment at the time of the second cell access processing in the self-reference scheme-based read operation is schematically shown.

[0261] As shown in Figure 12 At the time of the second access processing, the cell current Icell2 based on the reference data (in this case, "0" data) flows in the selected cell MC-s. The current mirror circuit 70 causes the mirror current Imr2 based on the cell current Icell2 (reference current Iref) to flow into the node NDd.

[0262] The transistor TRe causes the current Ix to flow from the node NDd to the ground terminal VSS in accordance with the voltage VSMPL applied to the gate.

[0263] The preamplifier 141 sets the signal level of the signal S1 at the "L" level and sets the signal level of the signal S1b at the "H" level. This sets the transistors TRf and TRg of the MOS switch SW1 in the OFF state. The node NDe is electrically disconnected from the node NDd through the MOS switch SW1 in the OFF state. The node NDe maintains the charged state (the hold state of the voltage VSMPL).

[0264] At time t7, the preamplifier 141 changes the signal level of the signal S2 from the "L" level to the "H" level, and changes the signal level of the signal S2b from the "H" level to the "L" level. This sets the transistors TRr and TRi of the MOS switch SW2 in the ON state. The node NDd is electrically connected to the node NDf via the MOS switch SW2 in the ON state.

[0265] This causes the current Ieval1 to flow into the node NDf.

[0266] In this embodiment, during the second cell access processing, the control circuit 17 causes the preamplifier 141 to offset (shift) the cell current Icell2.

[0267] The preamplifier 141 changes the signal level of the signal OFST1 from the "L" level to the "H" level. The "H" level signal OFST1 activates the offset circuit 71a. The "H" level signal OFST1 is supplied to the gate of the transistor TRq of the offset circuit 71a. This sets the transistor TRq in the ON state.

[0268] The transistor TRp of the offset circuit 71a is connected to the ground terminal VSS via the transistor TRq in the ON state. This causes the transistor TRp to output the offset current Iofst1.

[0269] As described above, the offset current Iofst1 has a current value corresponding to the current driving force (for example, the gate width of the transistor TRp) and the gate voltage of the transistor TRp. For example, the gate width of the transistor TRp is set to about 0.1 to 0.2 times the gate width of the transistor TRd. In this case, the current value of the offset current Iofst1 is about 0.1 to 0.2 times the current value of the mirror current Imr2 output from the transistor TRd.

[0270] The current value of the offset current Iofst1 varies according to the voltage VSMPL applied to the gate of the transistor TRe.

[0271] The offset circuit 71a applies the offset current Iofst1 to the node NDd. With this operation, the offset current Iofst1 is added to the mirror current Imr2 based on the cell current Icell. The offset current Iofst1 flows from the node NDd to the ground terminal VSS via the transistors TRp and TRq in the ON state. In this way, in the offset circuit 71a, the transistors TRp and TRq in the ON state pull a portion (the offset current Iofst1) of the mirror current Imr2 flowing into the node NDd to the ground terminal VSS.

[0272] As a result, the mirror current Imr2 at the time of the second cell access processing is offset in accordance with the current Ix corresponding to the driving force of the transistor TRe and the offset current Iofstl corresponding to the driving force of the transistor TRp.

[0273] In this way, in this embodiment, the transistor TRp can increase the driving force (output current) of the transistor TRe.

[0274] At the time of the second cell access processing, the transistor TRp is driven by the charge voltage VSMPL obtained at the time of the first cell access processing. The charge voltage VSMPL can include the influence of variations (e.g., PVT variations) among elements in the selected cell and the preamplifier. Therefore, the influence of the characteristic variations can be reflected in the current value of the offset current Iofstl.

[0275] The capacitance component C2 of the node NDf is charged with the current Ievall to which the offset current Iofstl is applied. The charge voltage VEVAL of the node NDf saturates at the time tb.

[0276] At the time of the second cell access processing, the current Ix from the transistor TRe driven by the charge voltage VSMPL is applied to the current flowing into the node NDf. Applying the charge voltage VSMPL to the gate will cause the transistor TRe to flow the current Ix. The current value of the current Ix corresponds to the voltage value VI or the voltage value VI - δa of the charge voltage VSMPL.

[0277] In addition, in the offset circuit 71a, the charge voltage VSMPL is applied to the gate of the transistor TRp. Therefore, the current value of the offset current Iofstl corresponds to the voltage value VI or the voltage value VI - δa of the charge voltage VSMPL.

[0278] As described above, the charge voltage VSMPL of the node NDe at the time of the first cell access processing includes a slight difference δa between the voltage value of the voltage VSMPL set when the user data is "1" data and the voltage value of the voltage VSMPL set when the user data is "0" data, in accordance with the user data in the selected cell MC-s. This difference δa causes a change in the amplitude of the current flowing in the transistors TRe and TRp at the time of the second cell access processing. Therefore, the amplitude of the current (the current provided to the capacitance component C2) Ievall flowing into the node NDf changes in accordance with the user data in the selected cell MC-s.

[0279] In this way, the voltage value of the voltage VEVAL of the node NDf after the charge changes in accordance with the sensing result (VSMPL) obtained by the first cell access processing.

[0280] For example, the current value of the current Ix when the voltage value of the charge voltage VSMPL is "V1" (when the user data is "0" data) is greater than the current value of the current Ix when the voltage value of the charge voltage VSMPL is "V1 - δa" (when the user data is "1" data).

[0281] In addition, the current value of the offset current Iofstl when the voltage value of the charge voltage VSMPL is "V1" is greater than the current value of the offset current Iofstl when the voltage value of the charge voltage VSMPL is "V1 - δa".

[0282] When the data in the selected cell MC-s at the second cell access process (after the reset write process) is the same as the data in the selected cell MC-s at the first cell access process (before the reset write process), the voltage value of the charge voltage VEVAL of the node NDf is the voltage value V2.

[0283] When the data in the selected cell MC-s at the second cell access process is different from the data in the selected cell MC-c at the first cell access process, the voltage value of the charge voltage VEVAL of the node NDf becomes the voltage value V2 - δb.

[0284] The voltage value V2 is greater than the voltage value V2 - δb. The potential difference δb of the charge voltage VEVAL in the second cell access process is sufficiently large with respect to the potential difference δa of the charge voltage VEVAL in the first cell access process.

[0285] As described above, in this embodiment, the mirror current Imr2 based on the cell current Icell2 is offset by the offset current Iofstl at the second cell access process.

[0286] With this operation, the voltage value V2 becomes greater than the voltage value V1 and the voltage value V1 - δa, and the voltage value V2 - δb becomes smaller than the voltage value V1 and the voltage value V1 - δa.

[0287] After the voltage value of the charge voltage VEVAL of the node NDf is stabilized, at time t8, the preamplifier 141 changes the signal level of the signal S2 from the "H" level to the "L" level, and changes the signal level of the signal S2b from the "L" level to the "H" level. The transistors TRh and TRi of the MOS switch S2 are set in the OFF state. The MOS switch S2 in the OFF state electrically disconnects the node NDf from the node NDd.

[0288] As a result, the charge of the node NDf is stopped.

[0289] The preamplifier 141 changes the signal level of the signal OFST1 from the "L" level to the "H" level. The "H" level signal OFST1 sets the transistor TRq in the OFF state. This sets the offset circuit 71a in the inactive state.

[0290] As a result, the supply of the offset current Iofst1 to the node NDd stops.

[0291] At time t9, the preamplifier 141 changes the signal level of the signal REN from the "H" level to the "L" level. This sets the transistor TRa in the OFF state. The transistor TRa in the OFF state electrically disconnects the preamplifier 141 from the selected cell MC-s.

[0292] As a result, the supply of the current (and voltage) from the preamplifier 141 to the selected cell MC-s stops.

[0293] In this way, the second cell access processing in the self-reference scheme-based read operation terminates.

[0294] <Time t10 to time t15: S40>

[0295] In the self-reference read operation of the MRAM 1 according to this embodiment, the control circuit 17 performs the sensing processing in the interval from time t10 to time t15.

[0296] In the interval before time t10 (the interval from time t0 to time t9), in the sense amplifier 142 in Figure 7 The "L" level signal SEN sets the transistors TR4, TR5, and TR6 in the ON state. The node ND2 is electrically connected to the node ND3 via the transistor TR4 in the ON state.

[0297] The transistors TR5 and TR6 in the ON state precharge the nodes ND2 and ND3 to approximately the power supply voltage VDD.

[0298] At time t10, the sense amplifier 142 changes the signal level of the signal SEN2 from the "L" level to the "H" level. The "H" level signal SEN2 sets the transistors TR9 and TR10 in the ON state.

[0299] The nodes ND2 and ND4 are electrically connected to the node ND6 via the transistor TR9 in the ON state.

[0300] The nodes ND3 and ND5 are electrically connected to the node ND7 via the transistor TR10 in the ON state.

[0301] At time tl l, the sense amplifier 142 changes the signal level of the signal SEN from the "L" level to the "H" level. The "H" level signal SEN sets the transistors TR4, TR5, and TR6 in the OFF state. With this operation, the transistors TR5 and TR6 in the OFF state stop supplying the power supply voltage VDD to the nodes ND2 and ND3. The node ND2 is electrically disconnected from the node ND3 through the transistor TR4 in the OFF state.

[0302] Note that in the interval from time tlO to time tl l, the signal level of the signal LATN is set at the "L" level, and the signal level of the signal LATNB is set at the "H" level. This sets the transistors TRl, TRl l, and TRl 2 in the OFF state in the interval from time tlO to time tl l.

[0303] The nodes ND2 and ND4 are electrically connected to the node ND6 via the transistor TR9 in the ON state. The nodes ND3 and ND5 are electrically connected to the node ND7 via the transistor TRlO in the ON state.

[0304] The voltage VSMPL of the node NDe is applied to the gate of the transistor TRl 3. The transistor TRl 3 causes the current II corresponding to the voltage value of the voltage VSMPL to flow into the node ND2.

[0305] The voltage VEVAL of the node NDf is applied to the gate of the transistor TRl 4. The transistor TRl 4 causes the current I2 corresponding to the voltage value of the voltage VEVAL to flow into the node ND3.

[0306] In this embodiment, the offset circuits 72a and 72b operate based on the signals SHFTDO and SHFTDOB at the time of the sensing processing by the sense amplifier 142. To offset the currents II and I2, one of the two offset circuits 72a and 72b is activated.

[0307] For example, at the time of the second cell access processing, when the set amplifier 141 has offset the cell current Icell2 (the mirror current Imr2) by using the offset current lofstl, the signal level of the signal SHFTDO is set at the "H" level, and the signal level of the signal SHFTDOB is set at the "L" level. This activates the offset circuit 72b on the side of the transistor TRl 4 and does not activate the offset circuit 72a on the side of the transistor TRl 3.

[0308] In the offset circuit 72a, the "L" level signal SHFTDOB sets the transistor TRl 5 in the OFF state. The transistor TRl 6 is electrically disconnected from the node ND6 through the transistor TRl 7 in the OFF state. Therefore, the offset circuit 72a does not cause any offset current to flow.

[0309] In the offset circuit 72b, the "H" level signal SHFTDO sets the transistor TR17 in the ON state. The transistor TR18 is electrically connected to the node ND7. The transistor TR18 causes a current Ishftb corresponding to the voltage VSHFT applied to the gate to flow. The offset current Ishftb flows from the node ND7 to the ground terminal VSS connected to the offset circuit 72b.

[0310] As a result, a current I2+Ishftb that is the sum of the current I2 and the current Ishftb flows into the node ND3.

[0311] In this way, the MRAM 1 according to the embodiment can offset one of the currents I1 and I2 in the sense amplifier 142 by using the offset circuits 72a and 72b. This allows the sense amplifier 142 to reliably make the amplitude of the voltage VSMPL (the current Ismpl1 and the current I1) different from the amplitude of the voltage VEVAL (the current Ieval1 and the current I2).

[0312] This allows the MRAM 1 according to the embodiment to further increase the read margin based on the voltage VSMPL and the voltage VEVAL.

[0313] Note that the current value of the offset current Ishft (Ishfta, Ishftb) is set according to the amplitude of the voltage VSHFT (VSHFTa, VSHFTb). The amplitude of the voltage VSHFT can be appropriately set based on a test process for the MRAM, a specification of the MRAM, adjustment of the MRAM after use, and the like. Note, however, that the current value of the offset current Ishft is set to about 0.1 to 0.2 times the current value of the currents I1 and I2.

[0314] The potential of the node ND2 changes according to the amplitude of the current I1. The potential of the node ND3 changes according to the amplitude of the current I2+Ishftb.

[0315] The amplitude relationship between the current I1 and the current I2+Ishftb changes according to the voltage value of the voltage VSMPL and the voltage value of the voltage VEVAL.

[0316] When the voltage value of the voltage VSMPL is greater than the voltage value of the voltage VEVAL, the current value of the current I1 is greater than the current value of the current I2+Ishftb. In this case, the amount of change in the potential of the node ND2 (in this case, the amount of discharge) is greater than the amount of change in the potential of the node ND3 (in this case, the amount of discharge). Therefore, the potential of the node ND2 is lower than the potential of the node ND3.

[0317] When the voltage value of the voltage VSMPL is smaller than the voltage value of the voltage VEVAL, the current value of the current I1 is smaller than the current value of the current I2+Ishftb. In this case, the discharge amount of the node ND2 is smaller than the discharge amount of the node ND3. Therefore, the potential of the node ND2 is higher than the potential of the node ND3.

[0318] In this way, based on the amplitude relationship between the voltage VSMPL and the voltage VEVAL sensed by the preamplifier 141, a potential difference appears between the node ND2 and the node ND3. The potential difference between the node DN2 and the node ND3 increases due to the positive feedback of the transistors TR2, TR3, TR7, and TR8.

[0319] At the time t12, the sense amplifier 142 changes the signal level of the signal LATN from the "H" level to the "L" level, and changes the signal level of the signal LATNB from the "L" level to the "H" level. The transistors TR1, TR11, and TR12 are set in the ON state. Through the transistors in the ON state, the transistors TR1, TR11, and TR12 electrically connect the nodes ND2 and ND3 to the power supply terminal VDD or the ground terminal VSS.

[0320] According to the amplitude relationship between the node ND2 and the node ND3, this amplifies the potentials of the node ND2 and the node ND3 to the power supply voltage VDD or the ground voltage VSS.

[0321] For example, when the potential of the node ND2 is lower than the potential of the node ND3 (the voltage value of the voltage VSMPL is larger than the voltage value of the voltage VEVAL), the potential of the node ND2 drops to approximately the ground voltage VSS, and the potential of the node ND3 rises to approximately the power supply voltage VDD.

[0322] In this case, the node ND2 is set in the hold state of the "L" level signal (data), and the node ND3 is set in the hold state of the "H" level signal (data).

[0323] For example, when the potential of the node ND2 is lower than the potential of the node ND3 (the voltage value of the voltage VSMPL is larger than the voltage value of the voltage VEVAL), the potential of the node ND2 drops to approximately the ground voltage VSS, and the potential of the node ND3 rises to approximately the power supply voltage VDD.

[0324] In this case, the node ND2 is set in the hold state of the "L" level signal (data), and the node ND3 is set in the hold state of the "H" level signal (data).

[0325] As a result of the sensing processing, when the potential of the node ND2 is lower than the potential of the node ND3, the signal level of the signal DO is an "L" level, and the signal level of the signal DOB is an "H" level. Therefore, "0" data is outputted as the signal DO from the output terminal OT1 of the sense amplifier 142, and "1" data is outputted as the signal DOB from the output terminal OT2 of the sense amplifier 142.

[0326] In contrast to this, when the potential of the node ND2 is higher than the potential of the node ND3, the signal level of the signal DO is an "H" level, and the signal level of the signal DOB is an "L" level. With this operation, "1" data is outputted as the signal DO from the output terminal OT1 of the sense amplifier 142, and "0" data is outputted as the signal DOB from the output terminal OT2 of the sense amplifier 142.

[0327] In this way, the signals based on the potentials of the nodes ND2 and ND3 are distinguished as user data (read data) in the selected cell MC-s.

[0328] At time t13, the sense amplifier 142 changes the signal level of the signal LATN from an "H" level to an "L" level, and changes the signal level of the signal LATNB from an "L" level to an "H" level. The transistors TR1, TR11, and TR12, which are in the OFF state, electrically disconnect the nodes ND2 and ND3 from the power supply terminal VDD and the ground terminal VSS.

[0329] At time t14, the sense amplifier 142 changes the signal level of the signal SEN from an "H" level to an "L" level. The transistors TR2, TR3, and TR4, which are in the ON state, electrically connect the nodes ND2 and ND3 to the power supply terminal VDD.

[0330] At time t15, the sense amplifier 142 changes the signal level of the signal SEN2 from an "H" level to an "L" level. The transistors TR9 and TR10, which are in the OFF state, electrically disconnect the node ND2 from the node ND6, and electrically disconnect the node ND3 from the node ND7.

[0331] This deactivates the sense amplifier 142. The nodes ND2 and ND3 are set in the pre-charge state.

[0332] In this way, the sensing processing in the read operation based on the self-reference scheme is terminated.

[0333] The data DO and DOB obtained by the read operation are transferred from the read circuit 14 to the external device 9 via the input / output circuit 16.

[0334] In this embodiment, the read data (signal DO) can be written in the selected cell MC-s by the write-back processing at a given timing (for example, before the operation corresponding to the next command). This changes the selected cell MC-s from the reset state to the holding state of the user data.

[0335] In the above-described manner, the read operation based on the self-reference scheme in the MRAM according to this embodiment is terminated.

[0336] (1c) Characteristics

[0337] The characteristics of the read circuit (pre-amplifier and sense amplifier) of the MRAM according to this embodiment will be described with reference to Figure 13 , Figure 14 and Figure 15 .

[0338] Figure 13 Each of (a) and (b) of FIG. 12 is a graph showing the operating point characteristics of the pre-amplifier in the MRAM according to this embodiment.

[0339] Figure 13 (a) of FIG. 13 is a graph showing the operating characteristics of the pre-amplifier according to the comparative example. Figure 13 (b) of FIG. 13 is a graph showing the operating point analysis of the pre-amplifier in the MRAM according to this embodiment.

[0340] Referring to each of (a) and (b) of FIG. 14, the abscissa of the graph corresponds to the voltage, and the ordinate of the graph corresponds to the current. Figure 13

[0341] Each of (a) and (b) of FIG. 14 indicates the voltage-current characteristics of the transistor TRd of the current mirror circuit in the pre-amplifier in relation to the data holding state of the storage cell (selected cell). Figure 13

[0342] Each of (a) and (b) of FIG. 14 indicates a plurality of lines M1-0, M1-1, M2-0, M2-1, M2a-0, and M2a-1 corresponding to the voltage-current characteristics. Figure 13 The line M1-0 indicates the voltage-current characteristics of the transistor TRd when the selected cell holds "0" data (the MTJ element is in the P state) at the time of the first cell access processing. The line M1-1 indicates the voltage-current characteristics of the transistor TRd when the selected cell holds "0" data (the MTJ element is in the P state) at the time of the first cell access processing.

[0343]

[0344] ​The line M2-0 and M2a-0 indicate the voltage-current characteristics of the transistor TRd (for example, a constituent element including the transistors TRd, TRe, and TRp) at the time of the second cell access processing when the selected cell holds "0" data as the user data at the time of the first cell access processing. The line M2-1 and M2a-1 indicate the voltage-current characteristics of the transistor TRd (for example, a constituent element including the transistors TRd, TRe, and TRp) at the time of the second cell access processing when the selected cell holds "1" data as the user data at the time of the first cell access processing.

[0345] The line D1 indicates the voltage-current characteristics of the transistor (diode-connected transistor) TRe of the preamplifier.

[0346] Figure 13 (a) of FIG. 10 shows the characteristics of the preamplifier according to the comparative example. The preamplifier according to the comparative example does not include the offset circuit.

[0347] Figure 13 (b) of FIG. 10 shows the characteristics of the preamplifier in the MRAM according to the embodiment. As described above, in this embodiment, the preamplifier 141 includes the offset circuit 71a. The offset circuit 71a applies an offset current to the current corresponding to the cell current at the time of the second cell access processing in the read operation based on the self-reference scheme.

[0348] As shown in (a) of FIG. 11, based on the voltage-current characteristics of each element, the voltage VEVAL-0x obtained by the second cell access processing is substantially the same as the voltages VSMPL-0 and VSMPL-1 obtained by the first cell access processing when the user data is "0" data. Figure 13

[0349] The voltage VEVAL-1x obtained by the second cell access processing is higher than the voltages VSMPL-0 and VSMPL-1 obtained by the first cell access processing when the user data is "1" data.

[0350] As shown in (a) of FIG. 11, based on the voltage-current characteristics of each element, the voltage VEVAL-0x obtained by the second cell access processing is substantially the same as the voltages VSMPL-0 and VSMPL-1 obtained by the first cell access processing when the user data is "0" data. Figure 14 This makes the voltage VEVAL-0 lower than the voltage VSMPL. The voltage VEVAL-1 is higher than the voltage VSMPL.

[0351] In this way, in this embodiment, a relatively large margin between the voltage VEVAL-0 and the voltage VSMPL is ensured.

[0352]

[0353] ​​ Figure 14 is a graph for illustrating a relationship between a voltage obtained by the first cell access processing and a voltage obtained by the second cell access processing in the MRAM according to this embodiment.

[0354] Referring to Figure 14 , the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to a voltage value. Referring to Figure 14 , since there is a slight difference between the voltage value set when the user data is "0" data and the voltage value set when the user data is "1" data, the voltage VSMPL is represented by a line.

[0355] As Figure 14 indicated, the voltage value of the voltage VEVAL-0 is shifted to a lower potential side with respect to the voltage VEVAL-0x in the comparative example by the offset operation of the offset circuit 71a in the preamplifier 141.

[0356] Therefore, the difference between the voltage VSMPL sensed at the time of the first cell access processing and the voltage VEVAL-0 sensed at the time of the second cell access processing in this embodiment is larger than the difference between the voltage VSMPL and the voltage VEVAL-0x in the comparative example.

[0357] In this way, in the MRAM according to this embodiment, for the voltage value corresponding to the sensing result obtained by the second cell access processing, it is possible to secure a larger read margin for the voltage value corresponding to the sensing result obtained by the first cell access processing.

[0358] As a result, the MRAM according to this embodiment can improve data read reliability.

[0359] As Figure 15 indicated, in the MRAM according to this embodiment, the preamplifier 141 including the offset circuit 71a can shorten the time period T1 taken for the voltage VEVAL to reach a predetermined voltage value (for example, 80% of the maximum voltage value or 80% of the minimum voltage value) compared to the time period T1x taken for the voltage VEVAL to reach the predetermined voltage value in the preamplifier according to the comparative example, for reasons described later.

[0360] Figure 15 is a graph showing a time change of a voltage in a preamplifier in the MRAM according to this embodiment.

[0361] Figure 15 (a) of FIG. 10 is a graph showing a time change of an internal voltage of a preamplifier according to a first comparative example. The circuit configuration of the preamplifier according to the first comparative example does not include an offset circuit. Figure 15 (b) is a graph showing the time variation of the internal voltage of the preamplifier according to the second comparative example. The circuit configuration of the preamplifier according to the second comparative example includes an offset circuit that outputs an offset current with a fixed voltage value. Figure 15 (c) is a graph showing the time variation of the internal voltage of the preamplifier in the MRAM according to this embodiment.

[0362] refer to Figure 15 For each of (a), (b), and (c), the horizontal axis of the graph corresponds to time, and the vertical axis corresponds to voltage.

[0363] refer to Figure 15 For each of (a), (b), and (c), the multiple lines belonging to group G1 correspond to the charging voltage VSMPL-0 of node NDe when the user data is "0". The multiple lines belonging to group G2 correspond to the charging voltage VSMPL-1 of node NDe when the user data is "1". The multiple lines belonging to group G3 correspond to the charging voltage VEVAL-0 of node NDf when the user data is "0". The multiple lines belonging to group G4 correspond to the charging voltage VEVAL-1 of node NDf when the user data is "1".

[0364] refer to Figure 15 In each of (a), (b) and (c), the threshold voltage of the transistors TRd and TRe connected to node NDd in the preamplifier 141 is set as a parameter in the experiment.

[0365] refer to Figure 15 In (a), the voltage difference between voltage VEVAL-0 and voltages VSMPL-0 and VSMPL-1 is relatively small. Therefore, as in the first comparative example, when the preamplifier does not include the offset circuit, the read margin in the read circuit is small.

[0366] like Figure 15 As shown in (b), when an offset current is generated with a voltage of a fixed value, the voltage value varies greatly under the angular conditions (the leading and trailing edges of the voltage pulse) for the corresponding voltages VSMPL and VEVAL, depending on the changes in the characteristics of the storage cell and the changes in the threshold voltages of the transistors TRd and TRe.

[0367] exist Figure 15 In the preamplifier shown in (b), due to the influence of the characteristic variations between components, the time period (hereinafter referred to as SDT (signal development time) for each signal voltage to reach a given voltage value from the leading edge (tail edge) of the voltage is relatively long.

[0368] like Figure 16 As shown in (c) of FIG. 10, in the MRAM according to this embodiment, the preamplifier 141 including the offset circuit 71a allows a relatively large voltage difference between the voltage VEVAL-0 and the voltage VSMPL and between the voltage VEVAL-1 and the voltage VSMPL. Thus, the MRAM according to this embodiment can obtain a large read margin.

[0369] In this embodiment, in the offset circuit 71a in the preamplifier 141, a voltage corresponding to the cell current Icell is applied to the gate of the transistor TRp that outputs an offset current.

[0370] As a result, in this embodiment, a result of monitoring the cell current from the memory cell, which can include a characteristic variation, is reflected in the magnitude of the offset current. The preamplifier 141 can apply a more appropriate offset value (offset current) to the sensing result (cell current).

[0371] Thus, the MRAM 1 according to this embodiment can reduce the adverse effects of PVT (process-voltage-time) variations on the sensing results (voltages VSMPL and VEVAL) by using the offset circuit 71a of the preamplifier 141.

[0372] The MRAM 1 according to this embodiment can shorten the SDT (e.g., the time period T1) of the voltage sensed by the preamplifier with the reduction of the effects of PVT variations. This allows the MRAM 1 according to this embodiment to shorten the read operation period.

[0373] As a result, the MRAM according to this embodiment can speed up the read operation.

[0374] Figure 16 is a graph for illustrating the characteristics of the read circuit in the MRAM according to this embodiment.

[0375] Figure 16 is a graph for evaluating the characteristics of the preamplifier and the sense amplifier in the read circuit in the MRAM according to this embodiment.

[0376] Figure 16 (a) of FIG. 10 shows the characteristics of the read circuit when only the sense amplifier according to this embodiment applies an offset to the sensing result obtained by the preamplifier. Figure 16 (b) of FIG. 10 shows the characteristics of the read circuit in the MRAM according to this embodiment when only the preamplifier applies an offset to the sensing result obtained by the preamplifier. Figure 16 (c) of FIG. 10 shows the characteristics of the read circuit in the MRAM according to this embodiment when both the preamplifier and the sense amplifier apply an offset to the sensing result obtained by the preamplifier.

[0377] Reference Signs List Figure 16 of each of (a), (b), and (c) of FIG. 8, the abscissa of the graph corresponds to the offset voltage (VSHFT) used in the offset circuit of the sense amplifier, and the ordinate of the graph corresponds to the standard deviation (σ). Figure 16 Each of (a), (b), and (c) of FIG. 8 shows a σ graph of the offset voltage of the sense amplifier.

[0378] Referring to Figure 16 Each of (a), (b), and (c) of FIG. 8, the region in which the offset voltage is positive corresponds to a case in which the signal level of the signal SHFTDO is set at the "H" level and the signal level of the signal SHFTDOB is set at the "L" level. Referring to Figure 15 Each of (a), (b), and (c) of FIG. 8, the region in which the offset voltage is negative corresponds to a case in which the signal level of the signal SHFTDO is set at the "L" level and the signal level of the signal SHFTDOB is set at the "H" level.

[0379] Referring to Figure 16 In (a), (b), and (c) of FIG. 8, when the read circuit (the preamplifier and the sense amplifier) has an ideal characteristic, a σ graph showing the relationship between the offset voltage VSHFT of the sense amplifier 142 and the deviation σ is represented by a straight line.

[0380] As shown in (a) of FIG. 8, when only the sense amplifier 142 applies an offset value to the sensing result, in a voltage range equal to or lower than the threshold voltage of the N-type transistor of the offset circuit 72 of the sense amplifier 142 (for example, the region RX in each of (a), (b), and (c) of FIG. 8), the graph is not represented by a straight line. Figure 16 Figure 16 As shown in (b) of FIG. 8, in this embodiment, when only the preamplifier 141 applies an offset value to the sensing result, the σ graph is represented by a straight line.

[0381] As shown in (c) of FIG. 8, in this embodiment, when both the preamplifier 141 and the sense amplifier 142 apply offset values to the sensing result, a straight line σ graph is obtained in a voltage region higher than the threshold voltage of the N-type transistor. Figure 16 In this way, the MRAM according to this embodiment can improve the read margin by using the offset circuit of the preamplifier and the offset circuit of the sense amplifier.

[0382] Figure 13 As shown in (a) of FIG. 8, when only the sense amplifier 142 applies an offset value to the sensing result, in a voltage range equal to or lower than the threshold voltage of the N-type transistor of the offset circuit 72 of the sense amplifier 142 (for example, the region RX in each of (a), (b), and (c) of FIG. 8), the graph is not represented by a straight line.

[0383] As shown in (b) of FIG. 8, in this embodiment, when only the preamplifier 141 applies an offset value to the sensing result, the σ graph is represented by a straight line.

[0384] As shown in (c) of FIG. 8, in this embodiment, when both the preamplifier 141 and the sense amplifier 142 apply offset values to the sensing result, a straight line σ graph is obtained in a voltage region higher than the threshold voltage of the N-type transistor. Figure 14 Figure 15 Figure 16 and Figure 17 As shown in (a) of FIG. 8, when only the sense amplifier 142 applies an offset value to the sensing result, in a voltage range equal to or lower than the threshold voltage of the N-type transistor of the offset circuit 72 of the sense amplifier 142 (for example, the region RX in each of (a), (b), and (c) of FIG. 8), the graph is not represented by a straight line.​​​​

[0385] Accordingly, the characteristics of the storage device according to this embodiment can be improved.

[0386] (2) Second Embodiment

[0387] A storage device according to a second embodiment will be described with reference to Figure 18 , Figure 19 , Figure 20 and Figure 17 .

[0388] In the storage device (e.g., MRAM) according to this embodiment, the configuration of the preamplifier of the read circuit is different from that of the preamplifier described in the first embodiment.

[0389] (2a) Configuration Example

[0390] Figure 17 is an equivalent circuit diagram showing an example of the configuration of the preamplifier of the read circuit in the MRAM according to this embodiment.

[0391] As shown in Figure 18 , in this embodiment, the connection position of the offset circuit 71b in the preamplifier 141 is different from that of the offset circuit in the preamplifier according to the first embodiment.

[0392] In this embodiment, the preamplifier 141 can control the driving force of the current mirror circuit 70 by using the offset circuit 71b.

[0393] The offset circuit 71b is connected to the node NDc, the node NDd, and the power supply terminal VDD in the preamplifier 141.

[0394] The offset circuit 71b includes transistors TRr and TRs. Each of the transistors TRr, TRs is a p-type electric field effect transistor. Each of the transistors TRr, TRs has two terminals and a gate.

[0395] One terminal of the transistor TRr is connected to the node NDd. The other terminal of the transistor TRr is connected to one terminal of the transistor TRs. The other terminal of the transistor TRs is connected to the power supply terminal VDD.

[0396] The gates of the transistors TRr, TRs are commonly connected to the node NDc with the gates of the transistors TRc, TRd.

[0397] The signal OFST2 is supplied to the gate of the transistor TRs. The transistor TRs is on / off controlled in accordance with the signal level of the signal OFST2.

[0398] When the offset circuit 71b is set in the inactive state, the signal level of the signal OFST2 is set at the "H" level. The "H" level signal OFST2 sets the transistor TRs in the OFF state. In this case, the offset circuit 71b does not cause the offset current Iofst2 to flow.

[0399] When the offset circuit 71b is set in the active state, the signal level of the signal OFST2 is set at the "L" level. The "L" level signal OFST2 sets the transistor TRs in the ON state. In this case, the transistor TRr is electrically connected to the power supply terminal VDD via the transistor TRs in the ON state. This causes the offset circuit 71b to cause the offset current Iofst2 to flow.

[0400] In the offset circuit 71b in the active state, the offset current Iofst2 flows from the power supply terminal VDD to the node NDd via the current paths (channels) of the transistors TRr and TRs.

[0401] The offset circuit 71b supplies the offset current Iofst2 from the power supply terminal VDD to the node NDd. With this operation, the offset circuit 71b increases the current value of the current flowing into the node NDd by the current value of the offset current Iofst2.

[0402] The offset circuit 71b offsets the amplitude of the mirror current Imr on the basis of the cell current Icell of the selected cell MC-s. The offset circuit 71b applies the offset current Iofst2 having a given current value to the mirror current Imr.

[0403] The amplitude of the offset current Iofst2 corresponds to the current driving force of the transistor TRr.

[0404] The current driving force of the transistor TRr can be set in accordance with the gate size (e.g., the gate width of the transistor TRr) of the transistor TRr.

[0405] The gate width of the transistor TRr is smaller than the gate width of the transistor TRe. The current value of the offset current Iofst2 is smaller than the current value of the mirror current Imr output from the transistor TRd.

[0406] For example, the gate width of the transistor TRr is set to about 0.1 to 0.2 times the gate width of the transistor TRd. In this case, the current value of the offset current Iofst2 is about 0.1 to 0.2 times the current value of the mirror current Imr.

[0407] The amplitude of the offset current Iofst2 changes in accordance with the potential of the node NDc (e.g., the cell current Icell in the first cell access processing).

[0408] In this embodiment, the offset circuit 71b applies the offset current Iofst2 to the mirror current Imr flowing from the node NDd to the node NDe at the first cell access processing in the self-reference scheme-based read operation.

[0409] In this way, in this embodiment, the offset circuit 71b can increase the driving force of the transistor TRd of the current mirror circuit 40.

[0410] (2b) Examples of operation

[0411] Examples of operation of the MRAM according to this embodiment will be described with reference to Figure 19 、 Figure 20 and Figure 18

[0412] Figure 9 is a timing chart for explaining an example of operation of the MRAM according to this embodiment.

[0413] The MRAM 1 according to this embodiment performs a self-reference scheme-based read operation in the same manner as in the first embodiment. Figure 18

[0414] <time t0 to time t3: S10>

[0415] As shown in Figure 19 , in the MRAM 1 according to this embodiment, the control circuit 17 performs the first cell access processing in the self-reference scheme-based read operation in the interval from the time t0 to the time t3.

[0416] The control circuit 17 activates the preamplifier 141 of the read circuit 14. The preamplifier 141 controls the signal level of various types of signals under the control of the control circuit 17.

[0417] At the time t0, the preamplifier 141 changes the signal level of the signal REN from the "L" level to the "H" level. The preamplifier 141 supplies the predetermined voltage VCLMP to the gate of the transistor TRb.

[0418] This causes the cell current Icell1 to flow in the selected cell MC-s. The cell current Icell1 has a current value corresponding to the user data in the selected cell MC-s.

[0419] Figure 20 The internal state of the preamplifier at the first cell access processing in the self-reference scheme-based read operation in the MRAM according to this embodiment is schematically shown.

[0420] In the preamplifier 141, the current mirror circuit 70 causes the mirror current Imr1 based on the cell current Icell1 to flow into the node NDd.​​

[0421] At time tl, the preamplifier 141 sets the signal level of the signal Sl at the "H" level and sets the signal level of the signal Sib at the "L" level. This sets the transistors TRg and TRh of the MOS switch SWl at the ON state. The MOS switch SWl in the ON state electrically connects the node NDe to the node NDd.

[0422] Note that the MOS switch SW2 in the OFF state electrically disconnects the node NDf from the node NDd.

[0423] In this embodiment, the offset circuit 71b is activated at the time of the first cell access processing.

[0424] The preamplifier 141 changes the signal level of the signal OFST2 from the "H" level to the "L" level at the time of the first cell access processing. The "L" level signal OFST2 sets the offset circuit 71b at the activated state. With this operation, the offset circuit 71b causes the offset current Iofst2 to flow at the time of the first cell access processing.

[0425] When the offset circuit 71b is set at the activated state, the potential of the node NDc is applied to the gate of the transistor TRr. The offset circuit 71b causes the offset current Iofst2 to flow at the time of the first cell access processing.

[0426] The offset current Iofst2 flows from the power supply terminal VDD via the current paths of the transistors TRr and TRs to the node NDd.

[0427] The current value of the offset current Iofst2 corresponds to the current value of the current output from the transistor TRr. Therefore, the current value of the offset current Iofst2 changes in a range corresponding to the current driving force of the transistor TRr in accordance with the potential of the node NDc (the amplitude of the cell current Icelll).

[0428] In this way, in this embodiment, the transistor TRr can increase the driving force (output current) of the transistor TRd.

[0429] The current including the mirror current Imrl and the offset current Iofst2 flows as the current Ismpl2 from the node NDd via the MOS switch SWl in the ON state to the node NDe. The node NDe is charged with the current Ismpl2. In this embodiment, the current value of the current Ismpl2 flowing into the node NDe is substantially equal to the sum of the current value of the mirror current Imrl and the current value of the offset current Iofst2.

[0430] Charging the node NDe with the current Ismpl2 (the mirror current Imr2 + Iofst2) will raise the charging voltage VSMPL of the node NDe from the ground voltage VSS to a given voltage value.

[0431] As described above, when the selected cell MC-s holds "0" data, the charging voltage VSMPL has a voltage value V3. When the selected cell MC-s holds "1" data, the charging voltage VSMPL has a voltage value V3 - δc lower than the voltage value V3.

[0432] For example, at time ta, the potential of the node NDe is saturated.

[0433] At time t2, the preamplifier 141 changes the signal level of the signal S1 from the "H" level to the "L" level, and changes the signal level of the signal S1b from the "L" level to the "H" level. This sets the MOS switch SW1 in the OFF state. The MOS switch SW1 in the OFF state electrically disconnects the node NDe from the node NDd.

[0434] At time t3, the preamplifier 141 changes the signal level of the signal REN from the "H" level to the "L" level. This electrically disconnects the preamplifier 141 from the selected cell MC-s.

[0435] In this way, the first cell access processing in the read operation based on the self-reference scheme is terminated.

[0436] <Time t4 to time t5: S20>

[0437] In the MRAM 1 according to this embodiment, the control circuit 17 performs the reset write processing as in the first embodiment in the interval from time t3 to time t4 in the read operation based on the self-reference scheme.

[0438] After the first cell access processing, at time t4, the write circuit 13 is activated by the "H" level control signal CNT-WR. The write circuit 13 writes the reference data (in this case, "0" data) into the selected cell MC. This sets the selected cell MC-s in the reset state (the holding state of the reference data).

[0439] At time t5, the write circuit 13 is not activated by the "L" level control signal CNT-WR.

[0440] In this way, the reset write processing in the read operation based on the self-reference scheme is terminated.

[0441] <Time t6 to time t9: S30>

[0442] In the interval from time t6 to time t9, the control circuit 17 executes the second cell access processing.

[0443] The control circuit 17 activates the preamplifier 141. The preamplifier 141 controls the signal level of various types of signals under the control of the control circuit 17.

[0444] At time t6, the preamplifier 141 changes the signal REN from the "L" level to the "H" level. With this operation, as in the first embodiment, the preamplifier 141 accesses the selected cell MC-s via the transistor TRa in the ON state.

[0445] Figure 20 is a schematic diagram showing the internal state of the preamplifier in the MRAM according to this embodiment at the time of the second cell access processing in the read operation.

[0446] As shown in Figure 13 , the cell current Icell2 corresponding to the reference data (in this case, "0" data) flows in the selected cell MC-s.

[0447] The current mirror circuit 70 causes a mirror current Imr2 based on the cell current Icell2 to flow into the node NDd.

[0448] At time t7, the preamplifier 141 sets the signal level of the signal S1 at the "L" level and sets the signal level of the signal S1b at the "H" level. This sets the MOS switch SW1 in the OFF state. The MOS switch SW1 in the OFF state electrically disconnects the node NDe from the node NDd. The node NDe maintains the charged state (the hold state of the voltage VSMPL).

[0449] The preamplifier 141 changes the signal level of the signal S2 from the "L" level to the "H" level and changes the signal level of the signal S2b from the "H" level to the "L" level. This sets the MOS switch SW2 in the ON state. This electrically connects the node NDd to the node NDf via the MOS switch SW2 in the ON state.

[0450] At the time of the second cell access processing, the voltage VSMPL of the node NDe sets the transistor TRe in the ON state.

[0451] Therefore, the transistor TRe causes the current Ix having a current value corresponding to the voltage value (V3 or V3-δc) of the charged voltage VSMPL to flow from the node NDd to the ground terminal VSS.

[0452] In this embodiment, the preamplifier 141 does not activate the offset circuit 71b at the time of the second cell access processing. The preamplifier 141 sets the signal level of the signal OFST2 at the "H" level. This sets the offset circuit 71b at the inactivation state. As a result, no offset current is supplied to the node NDd.

[0453] The mirror current Imr2 flows into the node NDd. In addition, the current Ix flows from the node NDd to the ground terminal VSS.

[0454] Therefore, in this embodiment, the current Ieval2 flowing into the node NDf corresponds to "Imr2 - Ix".

[0455] The supply of the current Ieval2 charges the capacitive component C2 of the node NDf. The charging voltage of the node NDf saturates at the time tb.

[0456] For example, when the user data in the selected cell MC-s is "0" data, the voltage value of the charging voltage VEVAL is "V4". When the user data in the selected cell MC-s is "1" data, the voltage value of the charging voltage VEVAL becomes a value (V4 - δd) which is smaller than the voltage value V4 by a given value δd.

[0457] In this way, in this embodiment, as in the first embodiment, a difference δd which is sufficiently larger than the difference δc is ensured between the voltage value of the charging voltage VEVAL when the selected cell MC-s holds "0" data and the voltage value of the charging voltage VEVAL when the selected cell MC-s holds "1" data.

[0458] In addition, in this embodiment, as in the first embodiment, a relatively large margin (potential difference) is ensured between the voltage VEVAL when the user data is "0" data and the voltage VSMPL.

[0459] After the voltage VEVAL of the node NDf stabilizes, at the time t8, the preamplifier 141 changes the signal level of the signal S2 from the "H" level to the "L" level and changes the signal level of the signal S2b from the "L" level to the "H" level. The MOS switch SW2 in the OFF state electrically disconnects the node NDf from the node NDd. This stops the charging of the node NDf.

[0460] The preamplifier 141 changes the signal level of the signal REN from the "H" level to the "L" level. The "L" level signal REN sets the transistor TRa in the OFF state. The transistor TRa in the OFF state stops supplying the current from the preamplifier 141 to the selected cell MC-s.

[0461] In this way, the second cell access processing in the read operation based on the self-reference scheme is terminated.

[0462] <Time t10 to time t15: S40>

[0463] After the second cell access processing in the read operation based on the self-reference scheme, the control circuit 17 performs the sensing processing in the same manner as in the first embodiment.

[0464] As in the first embodiment, the signal levels of the signals SEN2, SEN, and LATN are controlled by the sense amplifier 142.

[0465] The node ND2 is electrically connected to the node ND6, and the node ND3 is electrically connected to the node ND7.

[0466] The transistor TR13 causes the current II to flow into the node ND6. The transistor TR14 causes the current I2 to flow into the node ND7.

[0467] In this embodiment, the sensing result (voltage VSMPL) obtained by the first cell access processing is offset.

[0468] Accordingly, the offset circuit 72a is activated, and the offset circuit 72b is not activated. The "H" level signal SHFTDOB sets the transistor TR15 in the offset circuit 72a in the ON state. The transistor TR16 causes the current Ishfta to flow from the node ND6 to the ground terminal VSS. The current value of the current Ishfta corresponds to the voltage VSHFTa.

[0469] With this operation, the offset current Ishfta is applied to the current II flowing into the node ND6 in accordance with the voltage VSMPL. The current II + Ishfta flows into the node ND2.

[0470] The potential of the node ND2 and the potential of the node ND3 vary in accordance with the current II + Ishfta and the current I2. The potentials of the nodes ND2 and ND3 are amplified by the provision of the voltages VDD and VSS from the transistors TR1, TR11, and TR12 and the positive feedback of the transistors TR2, TR3, TR7, and TR8.

[0471] This determines the potential of the node ND2 and the potential of the node ND3 (the signal levels of the signals DO and DOB).

[0472] In this way, the sensing processing in the read operation based on the self-reference scheme is terminated.

[0473] The data DO and DOB obtained by the read operation are transferred from the read circuit 14 to the external device 9 via the input / output circuit 16.

[0474] In the above-described manner, the read operation based on the self-reference scheme in the MRAM according to the embodiment ends.

[0475] The MRAM 1 according to the embodiment can obtain substantially the same effects as those described with reference to Figure 14 、 Figure 15 、 Figure 16 and Figure 21 .

[0476] Therefore, the storage device according to the second embodiment can improve the characteristics of the storage device.

[0477] (3) Third Embodiment

[0478] The storage device according to the third embodiment will be described with reference to Figure 22 and Figure 21 .

[0479] Figure 22 is a schematic diagram for illustrating an example of the operation of the storage device according to the embodiment. Figure 21 is a timing chart for illustrating an example of the operation of the storage device according to the embodiment.

[0480] As shown in Figure 22 , in the read circuit of the MRAM 1 according to the first embodiment described above, the offset circuit 71a of the preamplifier 141 can not flow any offset current at the time of the second cell access processing, and can flow the offset current Iofst1z at the time of the first cell access processing.

[0481] With this operation, the MRAM according to the embodiment applies the offset current Iofst1z to the mirror current Imr1 of the cell current Icell1 in the selected cell MC-s based on the holding state of the user data at the time of the first cell access processing.

[0482] For example, as shown in Figure 21 , at the time t1 during the first cell access processing, the preamplifier 141 changes the signal level of the signal OFST1 from the "L" level to the "H" level. This sets the offset circuit 71a in the active state.

[0483] As shown in Figure 8 , in this embodiment, the offset circuit 71a flows the offset current Iofst1z from the node NDd to the ground terminal VSS during the first cell access processing. This applies the offset current Iofst1z to the mirror current Imr1 based on the cell current Icell1.

[0484] The node NDe is charged with the mirror current Imr1 to which the offset current Iofst1z is applied.

[0485] In the second cell access processing, the preamplifier 141 maintains the signal level of the signal OFST1 at the "L" level. This sets the offset circuit 71a in the inactive state in the second cell access processing. Therefore, in this embodiment, the offset circuit 71a does not flow any offset current during the second cell access processing.

[0486] The node NDf is charged with the mirror current Imr2 to which no offset current is applied.

[0487] Subsequently, the sense amplifier 142 performs the sensing processing as in the first embodiment. Note, however, that in the sense amplifier 142 in the second embodiment, the offset circuit 72a is activated, and the offset circuit 72b is not activated. The offset current Ishfta in the offset circuit 72a is applied to the current I1.

[0488] With this operation, in this embodiment, the data in the selected cell MC-s is distinguished.

[0489] For example, in this embodiment, the offset direction with respect to the sensing result obtained by the offset circuit 71a is different from the offset direction with respect to the sensing result obtained in the first embodiment. In this case, the voltage VEVAL-0 is shifted to a voltage value higher than the voltage VSMPL (VSMPL-0 or VSMPL-1).

[0490] In this way, the preamplifier 141 including Figure 13 the offset circuit 71a can control the offset direction with respect to the sensing result by controlling the timing of activating the offset circuit 71a.

[0491] The MRAM according to this embodiment can obtain substantially the same effects as those described with reference to Figure 14 , Figure 15 , Figure 16 and Figure 23 .

[0492] Therefore, the storage device according to the third embodiment can obtain the same effects as those described above.

[0493] (4) Fourth Embodiment

[0494] A storage device according to the fourth embodiment will be described with reference to Figure 24 and Figure 23 .

[0495] Figure 24 is a schematic diagram for illustrating an example of the operation of the storage device (e.g., MRAM) according to this embodiment. Figure 23 is a timing chart for illustrating an example of the operation of the storage device according to the embodiment.

[0496] like Figure 24 As shown, in the read circuit of MRAM 1 according to the second embodiment, the offset circuit 71b of the preamplifier 141 can prevent any offset current from flowing during the first cell access process, and can allow the offset current Iofst2z to flow during the second cell access process.

[0497] Using this operation, according to this embodiment, the MRAM applies an offset current Iofst2z to the mirror current Imr2 of the cell current Icell2 in the selected cell MC-s, which is in a holding state of reference data, during the second access process.

[0498] For example, such as Figure 23 As shown, during the first unit access process, the preamplifier 141 maintains the signal level of the signal OFST1 at the "H" level. This sets the offset circuit 71b in an inactive state during the first unit access process. Therefore, in this embodiment, the offset circuit 71a does not allow any offset current to flow during the first unit access process.

[0499] Node NDe is charged with a mirror current Imr1 that is not subject to an applied offset current.

[0500] During time t6 of the second unit access processing, preamplifier 141 changes the signal level of signal OFST1 from "H" level to "L" level. This activates offset circuit 71b.

[0501] like Figure 17 As shown, in this embodiment, during the second cell access process, the offset circuit 71b causes an offset current Iofst2z to flow from the power supply terminal VDD to the node NDd. This applies the offset current Iofst2z to the mirror current Imr2 based on the cell current Icell2.

[0502] Node NDf is charged using the mirror current Imr2, which is applied with offset current Iofst2z.

[0503] Subsequently, the sensing amplifier 142 performs the sensing process as described in the second embodiment above. However, note that in this embodiment, the offset circuit 72a is not activated in the sensing amplifier 142, and the offset circuit 72b is activated. The offset circuit 72b applies an offset current Ishftb to the current I2.

[0504] Using this operation, in this embodiment, the data in the selected cell MC-s is distinguished.

[0505] For example, in this embodiment, the direction of offset with respect to the sensing result obtained by the offset circuit 71b is different from the direction of offset with respect to the sensing result obtained in the second embodiment. In this case, the voltage VEVAL-0 is shifted to a voltage value higher than the voltage VSMPL (VSMPL-0 or VSMPL-1).

[0506] In this way, the preamplifier 141 of the offset circuit 71b in Figure 13 may control the direction of offset with respect to the sensing result by controlling the timing of activation of the offset circuit 71b.

[0507] The MRAM 1 according to this embodiment can obtain substantially the same effects as those described with reference to Figure 14 , Figure 15 , Figure 16 and Figure 25 .

[0508] Therefore, the storage device according to the fourth embodiment can obtain the same effects as those described above.

[0509] (5) Fifth Embodiment

[0510] A storage device according to the fifth embodiment will be described with reference to Figure 25 .

[0511] Figure 25 is a circuit diagram showing an example of the configuration of a storage device (e.g., an MRAM) according to this embodiment.

[0512] As shown in Figure 26 , the offset circuit 71a includes a plurality of field effect transistors TRp<0> to TRp <j-1>wherein j is an integer equal to or greater than 1. The transistors TRp flowing the offset current include a plurality of field effect transistors.

[0513] The plurality of transistors TRp<0> to TRp <j-1>have the same gate size (e.g., gate width) or different gate sizes.

[0514] a plurality of transistors TRp<1> to TRp <j-1>Current path and transistor TRp <0> The current paths are connected in parallel. Transistor TRp <1> To TRp <j-1>The gate of the transistor TRp<0> is connected to the gate of the transistor TRp<1>.

[0515] The plurality of transistors TRp<0> to TRp <j-1>a transistor (hereinafter referred to as an offset transistor) TRp which is effectively used as an output offset current Iofst.

[0516] According to the current value set by the offset current Iofst, the transistors TRp<0> to TRp <j-1>Trimming is performed.

[0517] For example, the plurality of transistors TRp<1> to TRp <j-1>The gates of a given number (k) of transistors are electrically separated from the gate of the transistor TRq<0> by fuses, switch circuits, etc. In this case, k is an integer equal to or greater than 0 and equal to or less than j-1.

[0518] Therefore, (j-k) transistors TR<0> to TRp <j-k-1>the effective gate width of the offset transistor TRp is smaller than the effective gate width of the j transistors TRp<0> to TRp <j-1>the effective gate width of the offset transistor TRp.

[0519] As a result, the (j-k) transistors TRp<0> to TRp <j-k-1>The current value of the offset current Iofst flowing through the offset transistor TRp is smaller than the current value of the current Iin flowing through the j transistors TRp<0> to TRp <j-1>The offset transistor TRp causes a current value of the offset current Iofst to flow.

[0520] In this way, according to the transistors TRp<0> to TRp <j-1>the number of the transistor TRp causes the current value of the offset current Iofst flowing to be adjusted.

[0521] Note that the transistor TRp<0> to TRp <j-1>The number (k) of the offset current is appropriately determined through a test process of the MRAM 1.

[0522] When the current value of the offset current flowing is made to have a desired amplitude by the offset circuit 71a, the plurality of transistors TRp<0> to TRp <j-1>Sometimes the trimming is not performed.

[0523] Note that the transistor TRd of the current mirror circuit 70 can include a plurality of field effect transistors TRd<0> to TRd <h-1>, like the transistor TRp (TRp < 0) to TRp <j-1>In this case, h is an integer equal to or greater than 1.

[0524] This allows for adjustment of the magnitude of the mirror current Imr relative to the cell current Icell. For example, the gate size of transistor TRd (the current ratio between transistor TRc and transistor TRd) is appropriately set based on the magnetoresistive value (or MR ratio) of the MTJ element used in the storage element.

[0525] The storage device according to this embodiment can achieve the same effects as the embodiment described above.

[0526] (6) Sixth Embodiment

[0527] Reference Figure 26 A storage device according to a sixth embodiment is described.

[0528] Figure 26 This is a circuit diagram illustrating an example configuration of a storage device (e.g., MRAM) according to this embodiment.

[0529] like Figure 25 As shown, the offset circuit 71b may include multiple transistors TRr having current paths connected in parallel. <0> To TRr <j-1>.

[0530] a plurality of transistors TRr<0> to TRr <j-1>A transistor (hereinafter referred to as an offset transistor) TRr effective as an output offset current Iofst.

[0531] In this case, as in Figure 27 In the case shown, the current value of the offset current Iofstmay be adjusted by trimming the plurality of transistors TRr<0> to TRr <j-1>The predetermined number of transistors is adjusted.

[0532] Note that the transistors TRp<0> to TRp <j-1>The number (k) of the offset current flowing through the MRAM 1 is appropriately determined through a test process of the MRAM 1. When the current value of the offset current flowing through the MRAM 1 caused by the offset circuit 71b has a desired amplitude, the plurality of transistors TRp<0> to TRp <j-1>Sometimes not trimmed.

[0533] The storage device according to this embodiment can obtain substantially the same effects as those of the above-described embodiments.

[0534] (7) Seventh Embodiment

[0535] A storage device according to the seventh embodiment will be described with reference to Figure 27

[0536] Figure 27 is a circuit diagram showing an example of a configuration of a storage device (e.g., MRAM) according to this embodiment.

[0537] As shown in ​ One preamplifier 141 can include a plurality of offset circuits 71a and 71b.

[0538] In this embodiment, one of the two offset circuits 71a and 71b is activated at one read operation. With this operation, an offset current (offset value) is provided to the sensing result in one of the first cell access processing and the second cell access processing.

[0539] The storage device according to this embodiment can obtain substantially the same effects as those of the above-described embodiments.

[0540] (8) Other Embodiments

[0541] The storage device according to the embodiments is not limited to the above embodiments, and various modifications can be made.

[0542] For example, the storage unit MC according to each of the above-described embodiments includes a magnetoresistive element and a two-terminal switching element. Note, however, that the storage unit MC can also include a magnetoresistive element and a three-terminal switching element (e.g., field effect transistor).

[0543] Note that the storage device according to the above embodiments is exemplified as a storage device (e.g., MRAM) using a magnetoresistive element as a storage element.

[0544] Note, however, that the storage device according to this embodiment can use a variable resistance element other than a magnetoresistive element as a storage element.

[0545] For example, the storage device can be a resistive random access memory (e.g., ReRAM) or a phase change memory (e.g., PCRAM), as long as it is a device using an element that stores data by using a change in resistance of the element.

[0546] The storage device according to this embodiment can be a volatile memory or a nonvolatile memory.

[0547] ​While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

[0548] Legend

[0549] 1: memory device, 10: memory cell array, 11: row control circuit, 12: column control circuit, 13: write circuit, 14: read circuit, 15: voltage generating circuit, 16: input / output circuit, 17: control circuit, 141: preamplifier, 142: sense amplifier. < / j>

Claims

1. A memory device comprising: a memory cell; and a read circuit configured to sense a first signal based on first data in the memory cell, write second data into the memory cell, sense a second signal based on the second data in the memory cell, and read data in the memory cell based on a comparison result between the first signal and the second signal, wherein the read circuit includes a pre-stage sense amplifier circuit configured to sense the first signal and the second signal, the pre-stage sense amplifier circuit includes: a current mirror circuit configured to cause a first current to flow into a first node connected to the memory cell, and based on a potential of the first node, cause a second current to flow into a second node; a first switching element including a first terminal connected to the second node and a second terminal connected to a third node; a first transistor including a third terminal connected to the second node and a first gate connected to the third node; a second switching element including a fourth terminal connected to the second node and a fifth terminal connected to a fourth node; and a first circuit connected to the second node and the third node, and configured to cause a third current to flow into the second node based on a potential of the third node.

2. The storage device of claim 1, wherein, the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the second signal.

3. The storage device of claim 1, wherein, the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the second signal.

4. The storage device of claim 1, wherein, the first circuit includes: a second transistor including a sixth terminal, a seventh terminal connected to the second node, and a second gate connected to the third node, and a third transistor including an eighth terminal connected to the sixth terminal, a ninth terminal connected to a ground terminal, and a third gate to which a first control signal is supplied.

5. The storage device of claim 4, wherein, the second transistor causes the third current to flow from the second node to the ground terminal when the third transistor is activated based on the first control signal at a first level, and the second transistor does not cause the third current to flow when the third transistor is not activated based on the first control signal at a second level.

6. The storage device of claim 5, wherein, a size of the second gate is smaller than a size of the first gate.

7. The storage device of claim 1, wherein, a current value of the third current is based on the potential of the third node.

8. The storage device of claim 1, wherein, the read circuit further includes a post-stage sense amplifier circuit configured to compare the first signal and the second signal, and the post-stage sense amplifier circuit includes a second circuit configured to apply an offset value to one of the first signal of the third node and the second signal of the fourth node.

9. The storage device of claim 1, wherein, the memory cell includes a magnetoresistive element.

10. A memory device comprising: a memory cell; and a read circuit configured to sense a first signal based on first data in the memory cell, write second data into the memory cell, sense a second signal based on the second data in the memory cell, and read data in the memory cell based on a comparison between the first signal and the second signal, wherein the read circuit includes a pre-stage sense amplifier circuit configured to sense the first signal and the second signal, the pre-stage sense amplifier circuit includes: a current mirror circuit configured to cause a first current to flow into a first node connected to the memory cell, and based on a potential of the first node, cause a second current to flow into a second node; a first switching element including a first terminal connected to the second node and a second terminal connected to a third node; a first transistor including a third terminal connected to the second node and a first gate connected to the third node; a second switching element including a fourth terminal connected to the second node and a fifth terminal connected to a fourth node; and a first circuit connected to the first node and the second node, and configured to cause a third current to flow into the second node based on the potential of the first node.

11. The storage device of claim 10, wherein, the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the second signal.

12. The storage device of claim 10, wherein, the first circuit does not cause the third current to flow when the pre-stage sense amplifier circuit senses the first signal, and the first circuit causes the third current to flow when the pre-stage sense amplifier circuit senses the second signal.

13. The storage device of claim 10, wherein, the first circuit includes: a second transistor including a sixth terminal, a seventh terminal connected to the second node, and a second gate connected to the first node, and a third transistor including an eighth terminal connected to the sixth terminal, a ninth terminal connected to a power supply terminal, and a third gate to which a first control signal is supplied.

14. The storage device of claim 13, wherein, the second transistor causes the third current to flow from the power supply terminal to the second node when the third transistor is activated based on the first control signal at a first level, and the second transistor does not cause the third current to flow when the third transistor is not activated based on the first control signal at a second level.

15. The storage device of claim 13, wherein, the current mirror circuit includes: a fourth transistor including a tenth terminal connected to the first node and a fourth gate connected to the first node, a fifth transistor including a fifth gate connected to the first node and a first terminal connected to the second node, and a size of the second gate is smaller than a size of the fifth gate.

16. The storage device of claim 10, wherein, a current value of the third current is based on the potential of the first node.

17. The storage device of claim 10, wherein, the read circuit further includes a post-stage sense amplifier circuit configured to compare the first signal and the second signal, and The post-stage sense amplifier circuit includes a second circuit configured to apply an offset value to one of the first signal of the third node and the second signal of the fourth node.

18. The storage device of claim 10, wherein, The storage unit includes a magnetoresistance effect element.

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