Storage system and method for determining a capacitance value

Abstract

Embodiments provide a storage system and a method of measuring a capacitance value of a capacitor with high precision. The storage system of the embodiments includes a capacitor that supplies electric charges to a nonvolatile semiconductor memory and a controller at the time of power loss, a constant current circuit that draws electric charges from the capacitor at a certain current, a measurement circuit that measures a terminal voltage across the capacitor, and a timer circuit that measures a time during which the measurement circuit measures the terminal voltage. The controller calculates the capacitance value of the capacitor using an algorithm in which a resistance value of a leakage resistance of a leakage current flowing through the capacitor is included in a variable, based on a change in the terminal voltage of the capacitor over time in each of a first period during which the capacitor naturally discharges and a second period during which the constant current circuit draws electric charges from the capacitor.

Description

[0001] This application claims priority to Japanese Patent Application No. 2020-155223 (Filing date: September 16, 2020). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a storage system and a method of measuring a capacitance value of a capacitor provided in the storage system. BACKGROUND

[0003] As a storage system including a nonvolatile semiconductor memory, a solid state drive (SSD) or the like is used. Various capacitors for various purposes are installed in such a storage system. A method of measuring a capacitance value of a capacitor for a specific purpose with high precision among various capacitors is studied. SUMMARY

[0004] Embodiments of the present application provide a storage system and a method of measuring a capacitance value capable of measuring a capacitance value of a used capacitor with high precision.

[0005] The storage system according to the embodiment is a storage system that operates with power supplied from an external device, and includes a capacitor that supplies electric charges to a nonvolatile semiconductor memory and a controller at the time of loss of power, a constant current circuit that draws electric charges from the capacitor at a certain current, a measurement circuit that measures a voltage of both terminals of the capacitor, and a timer circuit that measures a time of a period in which the measurement circuit measures the voltage of the terminals. The controller calculates a capacitance value of the capacitor using an algorithm in which a resistance value of a leakage resistance of a leakage current flowing through the capacitor is included in a variable, based on a change in the voltage of the terminals of the capacitor over time in each of a first period in which the capacitor naturally discharges and a second period in which the constant current circuit draws electric charges from the capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic view showing a configuration of the storage system according to the first embodiment.

[0007] Figure 2 is a schematic circuit diagram showing an example of a method of measuring a capacitance value of a capacitor.

[0008] Figure 3 is a circuit block diagram for explaining natural discharge measurement of the storage system according to the first embodiment.

[0009] Figure 4 is a graph showing a change in the voltage of the terminals of the capacitor over time in the natural discharge measurement.

[0010] Figure 5 is a circuit block diagram for explaining the constant current measurement of the storage system relating to the 1st embodiment.

[0011] Figure 6 is a graph showing the change in the terminal voltage of the capacitor over time in the constant current measurement.

[0012] Figure 7 is a flowchart for explaining the measurement method of the storage system relating to the 1st embodiment.

[0013] Figure 8 is a graph showing another example of the setting of the 1st period and the 2nd period.

[0014] Figure 9 is a graph showing the change in the terminal voltage of the capacitor over time in the measurement method of the comparative example.

[0015] Figure 10 is a graph showing another example of the setting of the 1st period and the 2nd period.

[0016] Figure 11 is a schematic diagram showing the configuration of the storage system relating to the 2nd embodiment.

[0017] Figure 12 is a circuit block diagram for explaining the natural discharge measurement of the storage system relating to the 2nd embodiment.

[0018] Figure 13 is a circuit block diagram for explaining the constant current measurement of the storage system relating to the 2nd embodiment.

[0019] Figure 14 is a schematic diagram showing an example of the configuration of the switch.

[0020] Explanation of Reference Numerals

[0021] 1, 1a storage system

[0022] 10 constant current circuit

[0023] 20 measurement circuit

[0024] 30 timer circuit

[0025] 40 calculation circuit

[0026] 100 substrate

[0027] 110, 110a controller

[0028] 111 analog-digital converter

[0029] 120 nonvolatile semiconductor memory

[0030] 130, 130a power management circuit

[0031] 131 step-up / down circuit

[0032] 140 capacitor DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described with reference to the drawings. In the description of the drawings, the same portions will be denoted by the same reference numerals, and the description will be omitted.

[0034] (1st Embodiment)

[0035] As shown in FIG. 1, a storage system 1 according to the 1st embodiment of the present application includes a substrate 100. A controller 110, a nonvolatile semiconductor memory 120, a power management circuit 130, a capacitor 140, an interface connector 150, and a dynamic random access memory (DRAM) 170 are mounted on the substrate 100. The storage system 1 is, for example, a solid state drive (SSD) or a universal flash storage (UFS). Figure 1 The controller 110 can be constituted by a circuit such as a system-on-a-chip (SoC). The controller 110 comprehensively controls the operation of the storage system 1. Each function of the controller 110 can also be implemented by the controller 110 executing firmware. Each function of the controller 110 can also be implemented by dedicated hardware within the controller 110. The nonvolatile semiconductor memory 120 is, for example, a NAND-type flash memory.

[0036] The storage system 1 is connected to a host device (omitted from the drawing) via the interface connector 150. The interface connector 150 and the controller 110 are connected via a bus 160. That is, data transmitted between the host device and the controller 110 of the storage system 1 is transmitted via the interface connector 150 and the bus 160.

[0037]

[0038] ​The controller 110 controls communication between the host device and the storage system 1. For example, the controller 110 receives a command from the host device, and controls the nonvolatile semiconductor memory 120 while using the DRAM 170 so that a write operation, a read operation is performed. Alternatively, the controller 110 controls the nonvolatile semiconductor memory 120 while using the DRAM 170 so that an erase operation of erasing stored data is performed. In the following, the write operation, the read operation, and the erase operation performed by the nonvolatile semiconductor memory 120 are also collectively referred to as "operation of the nonvolatile semiconductor memory 120". Each function of the controller 110 can also be realized by the controller 110 executing firmware.

[0039] Each function of the controller 110 can also be realized by dedicated hardware within the controller 110.

[0040] The power management circuit 130 controls power supply to the nonvolatile semiconductor memory 120 and the controller 110. In addition, the power management circuit 130 controls charge and discharge of the capacitor 140. The capacitor 140 is a capacitor for supplying power to the storage system 1 in a power loss protection (PLP) process for protecting the storage system 1 in a case where power supplied from an external device to the storage system 1 has been lost. During the PLP process, power corresponding to the amount of charge accumulated in the capacitor 140 is supplied to electronic components mounted on the substrate 100, such as the controller 110, the nonvolatile semiconductor memory 120, and the like, by control of the power management circuit 130. The capacitor is an electrolytic capacitor, a laminated capacitor, a tantalum capacitor, an electric double layer capacitor, a polymer capacitor, or a battery, and the like.

[0041] The power management circuit 130 includes a constant current circuit 10, a measurement circuit 20, a timer circuit 30, and a step-up / down circuit 131. The controller 110 includes a calculation circuit 40. The function of the calculation circuit 40 can also be realized by the controller 110 executing a program.

[0042] The constant current circuit 10 draws electric charges from the capacitor 140 with a certain current. In other words, drawing electric charges with a certain current means drawing electrons with a current of a certain magnitude or a certain amount of electric charges per unit time, or reducing the amount of stored electric charges. The measurement circuit 20 measures the voltage between the terminals of the capacitor 140 (hereinafter also referred to as "terminal voltage"). The timer circuit 30 measures various times during which the measurement circuit 20 measures the terminal voltage of the capacitor 140. The calculation circuit 40 calculates the capacitance value of the capacitor 140 using an expression that includes, as a variable, the resistance value of the resistance (hereinafter also referred to as "leakage resistance") that includes the leakage current of the capacitor 140. Details of the operations of the constant current circuit 10, the measurement circuit 20, the timer circuit 30, and the calculation circuit 40 will be described later.

[0043] The DRAM 170 is used for management of management information used in the operation control of the nonvolatile semiconductor memory 120, and cache of data transmitted with the host device. For example, the controller 110 uses the DRAM 170 in order to temporarily hold data transmitted from the host device and to be stored in the nonvolatile semiconductor memory 120. In addition, the controller 110 uses the DRAM 170 in order to temporarily hold data read out from the nonvolatile semiconductor memory 120 and to be transmitted to the host device.

[0044] In addition, a part or all of the management information stored in the nonvolatile semiconductor memory 120 is loaded (cached) to the DRAM 170 at the time of startup of the storage system 1 or in the case where the controller 110 receives a read command or a write command from the host device, and the like. The controller 110 updates the management information loaded to the DRAM 170 and backs up to the nonvolatile semiconductor memory 120 at a predetermined timing. The management information includes, for example, a Look Up Table (LUT) that is a correspondence table for referring to the data holding position of the nonvolatile semiconductor memory 120.

[0045] Power is supplied from the outside of the storage system 1 to the power management circuit 130 via the interface connector 150 (hereinafter also referred to as "external power P0"). The power management circuit 130 controls the on / off of the supply of power PW to the controller 110, the nonvolatile semiconductor memory 120, and the DRAM 170 in accordance with the operation of the storage system 1. The power management circuit 130 is configured as an integrated IC and is also referred to as a Power Management IC (PMIC). The external power P0 and the power PW are supplied as voltages that can flow a limited current.

[0046] Further, the power management circuit 130 controls charging and discharging of the capacitor 140. The power management circuit 130 charges the capacitor 140 by the electric power PC. In order to increase energy corresponding to the amount of the electric charge accumulated in the capacitor 140, the power management circuit 130 can also step up the voltage of the supplied external electric power PO, and charge the capacitor 140 with the stepped-up voltage. The power management circuit 130 steps up the voltage of the external electric power PO by the step-up / down circuit 131, and charges the capacitor 140.

[0047] The power management circuit 130 supplies the electric charge accumulated in the capacitor 140 to the controller 110, the nonvolatile semiconductor memory 120, and the DRAM 170 at the time of power loss of the storage system 1. The "time of power loss" is a state in which the external electric power PO becomes insufficient for the power management circuit 130 to supply the electric power PW required for the normal operation of the storage system 1 to the controller 110, the nonvolatile semiconductor memory 120, and the like.

[0048] The power management circuit 130 monitors the external electric power PO during the operation of the storage system 1, and discharges the capacitor 140 at the time of power loss. Thereby, the electric charge accumulated in the capacitor 140 is supplied to the nonvolatile semiconductor memory 120 and the controller 110 via the power management circuit 130. At this time, in the case where the capacitor 140 is charged by stepping up the voltage of the external electric power PO, the power management circuit 130 reduces the voltage corresponding to the electric power PD supplied to the capacitor 140 to a predetermined voltage by the step-up / down circuit 131. Further, the power management circuit 130 supplies the electric power PW corresponding to the voltage after the step-down to the controller 110 and the nonvolatile semiconductor memory 120.

[0049] During the operation of the storage system 1 using the electric charge supplied by the capacitor 140, the storage system 1 performs the operation of power-off similar to that at the time of normal shutdown. For example, by the control of the controller 110, the operation of writing the content of the cache buffer stored in the DRAM 170 to the nonvolatile semiconductor memory 120, and / or the update of the LUT are performed. In this way, in the storage system 1 having the capacitor 140, even at the time of unintended shutdown due to power loss, the predetermined operation for power-off is performed. Thereby, the data that should be stored in the nonvolatile semiconductor memory 120 is protected.

[0050] To ensure high data reliability, in the storage system 1, a large-capacity capacitor 140 is mounted as a capacitor for PLP processing to enable protection of data at the time of power loss. As already described, the capacitor 140 functions to, at the time of sudden loss of power supply to the storage system 1 due to a power outage or the like, or at the time of instantaneous disconnection of the power supply due to disconnection and / or poor contact or the like, implement a backup operation of performing transfer saving (retreat) of all data without losing data that should be stored. Therefore, power for performing the backup operation is accumulated in the capacitor 140. The write operation in the nonvolatile semiconductor memory 120 requires a very large amount of energy, and therefore, the larger the amount of energy corresponding to the amount of charge accumulated in the capacitor 140, the better.

[0051] However, a capacitor having a large capacitance value decreases in capacitance value due to aging. When the capacitance value of the capacitor 140 decreases greatly due to aging, the energy required for the backup operation is insufficient, and the backup operation cannot be guaranteed.

[0052] Therefore, the storage system 1 periodically measures the capacitance value of the capacitor 140 in order to monitor the capacitance value of the capacitor 140. Also, if the capacitance value of the capacitor 140 falls below a prescribed value, the storage system 1 shifts to a mode in which new write operations are stopped. Therefore, the period until the capacitance value of the capacitor 140 decreases to the prescribed value can be regarded as the actual product life of the storage system 1. The prescribed value of the capacitance value of the capacitor 140 is set in accordance with the power with which the backup operation of the storage system 1 can be implemented.

[0053] As described above, the time during which the storage system 1 can be used is determined in accordance with the measured capacitance value of the capacitor 140. Therefore, the higher the accuracy of the measurement of the capacitance value of the capacitor 140, the better.

[0054] The capacitance value of the capacitor 140 can be measured by constant current measurement of drawing charge from the capacitor 140 at a certain current. At this time, to accurately measure the capacitance value of the capacitor 140, the leakage current of the capacitor 140 needs to be taken into account. The resistance of the path through which the leakage current of the capacitor 140 flows is also referred to as "leakage resistance". The leakage resistance also includes the resistance of a circuit connected to the terminals of the capacitor 140, and the like. Here, a circuit 200 shown in FIG. 2 is used as the leakage resistance of the capacitor 140. Figure 2 A method of measuring the capacitance value of the capacitor 140 will be described. Figure 2 is a schematic circuit diagram showing an example of a method of measuring the capacitance value of the capacitor 140. As shown in FIG. 2, the circuit 200 includes a resistor 210, a switch 220, and a voltmeter 230. The resistor 210 is connected to the terminals of the capacitor 140. The switch 220 is connected to the resistor 210 and the voltmeter 230. The voltmeter 230 is connected to the switch 220. Figure 2As shown, a constant current source is connected between the connection point of the parallel connection of the leakage resistance and the capacitor 140 on one side and the connection point on the other side. The constant current source draws electric charges from the capacitor 140 by a certain current Iconst. Based on such a circuit structure, the capacitance value of the capacitor 140 can be accurately measured. The capacitance value Ctotal of the capacitor 140 is calculated using the following equation (1):

[0055] Ctotal = - dt / {Rleak x ln(l - dV / (V0 + Rleak x Iconst))} (1)

[0056] In equation (1), Rleak is the resistance value of the leakage resistance, and Iconst is the value of the certain current by which electric charges are drawn from the capacitor 140. In addition, V0 is the terminal voltage of the capacitor 140 at the start of measurement, dt is the measurement time of the terminal voltage, and dV is the amount of change in the terminal voltage corresponding to the measurement time dt.

[0057] In the case where Rleak x Iconst » V0, dV, equation (1) is Taylor expanded to obtain equation (2):

[0058] Ctotal = (Iconst + V0 / Rleak) x (dt / dV) (2)

[0059] Here, the capacitance value Ctotal of the capacitor 140 is calculated using the following equation (3) without considering the influence by the leakage current:

[0060] Ctotal = Iconst x (dt / dV) (3)

[0061] However, as described later, the product life of the storage system 1 is estimated to be short based on the capacitance value Ctotal calculated without considering the influence by the leakage current.

[0062] In this regard, according to the storage system 1, the capacitance value of the capacitor 140 can be accurately measured by considering the leakage current, as described below.

[0063] The measurement method of the capacitance value of the capacitor 140 of the storage system 1 combines measurement in a first period within a period in which the capacitor 140 naturally discharges and measurement in a second period within a period in which electric charges are drawn from the capacitor 140 by a certain current. The measurement methods in the first and second periods are described separately.

[0064] Hereinafter, the measurement in the first period is also referred to as "natural discharge measurement". First, the natural discharge measurement is described with reference to Figure 3 and Figure 4 . Figure 3is a circuit block diagram for explaining the natural discharge measurement of the storage system 1. Figure 4 is a graph showing the temporal change in the terminal voltage of the capacitor 140 in the natural discharge measurement. In the 1st period, the temporal change in the terminal voltage of the capacitor 140 is measured while the capacitor 140 is discharged naturally.

[0065] The natural discharge measurement is started by the controller 110 sending a control signal Sc1 instructing the natural discharge measurement to the power management circuit 130. The power management circuit 130 receiving the control signal Sc1 starts the natural discharge measurement in a state where the charging of the capacitor 140 is stopped. During the natural discharge measurement, the operation of the constant current circuit 10 is off.

[0066] In the natural discharge measurement, as shown in Figure 4 , the terminal voltage Vcap of the capacitor 140 gradually decreases with the passage of time. At this time, the temporal change in the terminal voltage Vcap is not linear due to the influence of the leakage current flowing in the leakage resistor. Specifically, the voltage decrease per unit time is large immediately after the natural discharge starts.

[0067] The measurement circuit 20 measures the terminal voltage Vcap until the voltage V01 from the start time t01 of the natural discharge measurement decreases by a 1st differential voltage dV1 set in advance. The timer circuit 30 measures a 1st elapsed time dt1 from the start time t01 to the time when the terminal voltage Vcap decreases by the 1st differential voltage dV1. The power management circuit 130 outputs a data signal Sd1 including the 1st differential voltage dV1 and the 1st elapsed time dt1 to the calculation circuit 40.

[0068] In the following, the measurement in the 2nd period is also referred to as "constant current measurement". Next, the constant current measurement is explained with reference to Figure 5 and Figure 6 . Figure 5 is a circuit block diagram for explaining the constant current measurement of the storage system 1. Figure 6 is a graph showing the temporal change in the terminal voltage of the capacitor 140 in the constant current measurement. In the 2nd period, the temporal change in the terminal voltage of the capacitor 140 is measured while the charge is drawn from the capacitor 140 at a certain current.

[0069] The constant current measurement is started by the controller 110 sending a control signal Sc2 instructing the constant current measurement to the power management circuit 130. The power management circuit 130 receiving the control signal Sc2 starts the constant current measurement in a state where the charging of the capacitor 140 is stopped. Specifically, while the constant current circuit 10 draws the electric charge from the capacitor 140 at a certain current, the measurement circuit 20 measures the terminal voltage Vcap of the capacitor 140.

[0070] In Figure 6 represents the change in the terminal voltage Vcap over time in the constant current measurement. The measurement circuit 20 measures the terminal voltage Vcap until the voltage V02 from the start time t02 decreases by a pre-set 2nd differential voltage dV2. The timer circuit 30 measures a 2nd elapsed time dt2 from the start time t02 until the terminal voltage Vcap decreases by the 2nd differential voltage dV2. The power management circuit 130 outputs a data signal Sd2 including the 2nd differential voltage dV2 and the 2nd elapsed time dt2 to the calculation circuit 40.

[0071] The calculation circuit 40 calculates the resistance value of the leakage resistance and the capacitance value of the capacitor 140 using the 1st differential voltage dV1, the 1st elapsed time dt1, the 2nd differential voltage dV2, and the 2nd elapsed time dt2. Details of the method of calculating the resistance value of the leakage resistance and the capacitance value of the capacitor 140 will be described later.

[0072] Next, the method of measuring the capacitance value of the capacitor 140 in the storage system 1 will be described with reference to the flowchart of Figure 7 .

[0073] In S10, the controller 110 sets the 1st differential voltage dV1 in a 1st period in which the capacitor 140 is naturally discharged, and the 2nd differential voltage dV2 in a 2nd period in which the electric charge is drawn from the capacitor 140 at a certain current. For example, the controller 110 sets the 1st period and the 2nd period consecutively.

[0074] In S20, the controller 110 sends a control signal Sc1 to the power management circuit 130. Thus, the storage system 1 performs the natural discharge measurement. In the natural discharge measurement, as described with reference to Figure 3 and Figure 4 , the 1st elapsed time dt1 corresponding to the 1st differential voltage dV1 is measured. The 1st differential voltage dV1 and the 1st elapsed time dt1 are output to the calculation circuit 40.

[0075] In S30, the controller 110 sends a control signal Sc2 to the power management circuit 130. Thus, the storage system 1 performs the constant current measurement. In the constant current measurement, as described with reference to Figure 5 and Figure 6As explained above, the second elapsed time dt2 corresponding to the second differential voltage dV2 is measured. The second differential voltage dV2 and the second elapsed time dt2 are output to the calculation circuit 40.

[0076] In S40, the calculation circuit 40 calculates the capacitance value of the capacitor 140 and the resistance value of the leakage resistance connected to the capacitor 140 using the first differential voltage dV1, the second differential voltage dV2, the first elapsed time dt1, and the second elapsed time dt2. Specifically, the calculation circuit 40 calculates the resistance value Rleak of the leakage resistance and the capacitance value Ctotal of the capacitor 140 using the following relational expressions of Equations (4) and (5):

[0077] Rleak = -dt1 x dV2 / {Iconst x dt2 x ln(l - dV1 / V0)} - (V0 - dV1) / Iconst... (4)

[0078] Ctotal = -dt1 / {Rleak x ln(l - dV1 / V0)}... (5)

[0079] In Equations (4) and (5), V0 is the terminal voltage of the capacitor 140 at the start of measurement.

[0080] Further, since the controller 110 continuously sets the first period and the second period, as shown in FIG. 6, the constant current measurement is started from the state where the natural discharge measurement ends. Figure 8 Figure 8 is an example in which the first period and the second period are continuously set. That is, the initial voltage of the constant current measurement is the voltage (V0 - dV1) in which the initial voltage V0 at the start time to of the natural discharge measurement is decreased by the first differential voltage dV1.

[0081] As explained above, the calculation circuit 40 calculates the capacitance value of the capacitor 140 based on the temporal change in the terminal voltage Vcap of the capacitor 140 in each of the first period and the second period. In the measurement method of the capacitance value Ctotal of the capacitor 140 of the storage system 1, the resistance value Rleak of the leakage resistance is taken into account. Therefore, according to the storage system 1, it is possible to accurately measure the capacitance value Ctotal of the capacitor 140.

[0082] Further, Equations (4) and (5) are obtained by solving simultaneous equations of Equation (6) obtained in the constant current measurement and Equation (7) obtained in the natural discharge measurement, and deforming them:

[0083] Ctotal = (Iconst + (V0 - dV1) / Rleak) x dt2 / dV2... (6)

[0084] ​Rleak = -dtl / {Ctotal x ln(l - dVl / V0)} (7)

[0085] In the formula (6) and the formula (7), V0 is the terminal voltage of the capacitor 140 at the start of the measurement, dtl is the 1st elapsed time, dt2 is the 2nd elapsed time, dVl and dV2 are the amounts of change in the terminal voltage corresponding to the 1st elapsed time dtl and the 2nd elapsed time dt2, respectively.

[0086] Further, by solving the following simultaneous equations, the resistance value Rleak of the leakage resistance and the capacitance value Ctotal of the capacitor 140 can be calculated more strictly:

[0087] Ctotal = -dt2 / (Rleak x ln{1 - dV2 / (V0 - dVl + Rleak x Iconst)})

[0088] Ctotal = -dtl / (Rleak x ln{1 - dVl / V0})

[0089] When the above simultaneous equations are solved, the following formula is obtained:

[0090] Rleak = dV2 / (Iconst x {1 - (1 - dVl / V0) dt2 / dt1}) - (V0 - dVl)

[0091] / Iconst

[0092] Ctotal = -dtl / (Rleak x ln{1 - dVl / V0})

[0093] The capacitor 140 can also be configured by connecting a plurality of capacitors in parallel. In this case, the capacitance value Ctotal is the sum of the capacitance values of the capacitor 140 configured by the plurality of capacitors.

[0094] The capacitor 140 can be, for example, a multilayer ceramic capacitor or an aluminum capacitor. Alternatively, in order to miniaturize the storage system 1, the capacitor 140 can be a tantalum capacitor.

[0095] The resistance value Rleak calculated in the storage system 1 is a combination of the resistance values of all the leakage resistances connected to the capacitor 140. For example, the leakage resistance is not only the leakage resistance related to the leakage current flowing in the capacitor 140 itself, but also includes the leakage resistance related to the leakage current flowing in the circuit elements connected in series or in parallel to the capacitor 140.

[0096] The lengths of the first and second periods used for each measurement can be arbitrarily set. For example, the longer the first and second periods are, the higher the measurement accuracy. On the other hand, during the period of measuring the capacitance value of capacitor 140, the operation of non-volatile semiconductor memory 120 stops. Therefore, in order to shorten the stop time of non-volatile semiconductor memory 120, the shorter the first and second periods are, the better.

[0097] In other words, the measurement accuracy and the stopping time of the non-volatile semiconductor memory 120 are a trade-off. Therefore, if it is desirable to measure the capacitance value accurately, the first and second periods are increased. On the other hand, if it is desirable to shorten the stopping time of the non-volatile semiconductor memory 120 even if the measurement accuracy is reduced to some extent, the first and second periods are set to be shorter.

[0098] Alternatively, the order of the first and second periods can be reversed. That is, the second period can be set first, and the first period can be set last.

[0099] Here, as a comparative example, a method for determining the capacitance value of capacitor 140 by ignoring the influence of the leakage current of capacitor 140 is investigated. In the comparative example method, the capacitance value of capacitor 140 is determined by constant current measurement.

[0100] exist Figure 9 The value in the figure represents the change in terminal voltage Vcap over time during the constant current measurement of the comparative example. In the case where no leakage current occurs during the measurement of the capacitance value of capacitor 140, such as... Figure 9 As shown by the dashed line in characteristic S1, the change of terminal voltage Vcap over time is linear. In the constant current measurement of the comparative example, the capacitance value Ctotal is calculated by neglecting the influence of leakage current using equation (2). That is, using the change in terminal voltage Vcap dVa during the measurement time dta, the capacitance value Ctotal is calculated using the following equation (8):

[0101] Ctotal=Iconst×dta / dVa…(8)

[0102] However, in reality, leakage current will be generated in capacitor 140, therefore, as Figure 9 As shown by the solid line in characteristic S2, the change in terminal voltage Vcap over time is not linear. Therefore, when the leakage current is large, the capacitance value of capacitor 140 is measured to be smaller than the actual value. Therefore, when using the measurement results for the period during which the change in terminal voltage Vcap over time corresponds to characteristic S2, the product life of the storage system will be predicted to be shorter than it actually is.

[0103] As described above, in the comparative example in which the capacitance value Ctotal is calculated without taking the leakage current of the capacitor 140 into consideration, the capacitance value Ctotal is calculated to be smaller than the actual value. Therefore, in a case where the capacitance value of the capacitor 140 is calculated by the measurement method of the comparative example, the predicted product life of the storage system 1 is shorter than in a case where the capacitance value of the capacitor 140 is calculated by the measurement method described above. Figure 7 and Figure 8 As described above, in the comparative example in which the capacitance value Ctotal is calculated without taking the leakage current of the capacitor 140 into consideration, the capacitance value Ctotal is calculated to be smaller than the actual value. Therefore, in a case where the capacitance value of the capacitor 140 is calculated by the measurement method of the comparative example, the predicted product life of the storage system 1 is shorter than in a case where the capacitance value of the capacitor 140 is calculated by the measurement method described above.

[0104] As described above, in the comparative example in which the capacitance value Ctotal is calculated without taking the leakage current of the capacitor 140 into consideration, the capacitance value Ctotal is calculated to be smaller than the actual value. Therefore, in a case where the capacitance value of the capacitor 140 is calculated by the measurement method of the comparative example, the predicted product life of the storage system 1 is shorter than in a case where the capacitance value of the capacitor 140 is calculated by the measurement method described above.

[0105] In addition, it is important to predict the occurrence of a short-circuit defect between the terminals of the capacitor 140 by detecting a decrease in the leakage resistance of the capacitor 140 or the like. This is because, when a short-circuit defect between the terminals of the capacitor 140 occurs, charging of the capacitor 140 can not be performed. Also, when a short-circuit defect of the capacitor 140 occurs during the operation period of the storage system 1, the charge stored in the capacitor 140 can be discharged all at once, and thus the storage system 1 can catch fire due to heat generation. For example, in a case where a tantalum capacitor is used for the capacitor 140, a short-circuit defect is a common defect mode of the tantalum capacitor.

[0106] In addition, when the leakage resistance of the capacitor 140 decreases, the capacitor 140 can not be sufficiently charged due to the occurrence of the leakage current. In a case where the capacitor 140 is not sufficiently charged, the backup operation of the storage system 1 at the time of power supply loss can not be ensured. Therefore, the data stored in the nonvolatile semiconductor memory 120 can be lost, and the storage system 1 can malfunction.

[0107] According to the storage system 1 related to the first embodiment, the resistance value of the leakage resistance connected to the capacitor 140 can be calculated with high precision. Therefore, the decrease in the leakage resistance can be detected at an early stage, and the failure of the storage system 1 due to the increase in the leakage current or short-circuit failure can be prevented.

[0108]

[0109] In Figure 8 , the case where the first period and the second period are continuously set is shown. However, as shown in Figure 10 , an interval can be provided between the first period and the second period. In the case where an intermediate period is set between the first period and the second period as shown in Figure 10 , the measurement in the first period and the second period is the same as the measurement method described with reference to Figure 7 .

[0110] That is, in the natural discharge measurement, the first elapsed time dtl corresponding to the first differential voltage dVl is measured. In the constant current measurement, the second elapsed time dt2 corresponding to the second differential voltage dV2 is measured. The first differential voltage dVl, the first elapsed time dtl, the second differential voltage dV2, and the second elapsed time dt2 are output to the calculation circuit 40. The calculation circuit 40 calculates the capacitance value Ctotal of the capacitor 140 and the resistance value Rleak of the leakage resistance using the following relational expressions of equations (9) and (10):

[0111] Rleak = -dtl x dV2 / {Iconst x dt2 x ln(l - dVl / V0)} - V0 / Iconst... (9)

[0112] Ctotal = -dtl / {Rleak x ln(l - dVl / V0)}... (10)

[0113] As shown in Figure 10 , between the first period and the second period, the power management circuit 130 charges the capacitor 140, and the terminal voltage Vcap returns to the initial voltage V0. That is, the initial voltage before the start of the constant current measurement is the same as the initial voltage before the start of the natural discharge measurement. Therefore, the second term on the right side of equation (9) is different from equation (4). Equation (10) is the same as equation (5).

[0114] Further, by solving the following simultaneous equations, the resistance value Rleak of the leakage resistance and the capacitance value Ctotal of the capacitor 140 in the case where an interval is provided between the first period and the second period can be more strictly calculated:

[0115] ​Ctotal=-dt2 / (Rleak×ln{1-dV2 / (V0+Rleak×Iconst)})

[0116] Ctotal=-dt1 / (Rleak×ln{1-dV1 / V0})

[0117] When solving the above simultaneous equations, the following equation is obtained:

[0118] Rleak=dV2 / (Iconst×{1-(1―dV1 / V0) dt2 / dt1})-V0 / Iconst

[0119] Ctotal=-dt1 / (Rleak×ln{1-dV1 / V0})

[0120] According to the measurement method of the modified example, compared with the case where the first and second periods are set continuously, the initial voltage of the constant current measurement can be increased. Therefore, the first and second periods can be set to be longer. As a result, the measurement accuracy can be improved.

[0121] On the other hand, when the first and second periods are set continuously, the measurement time is shorter compared to the measurement method of the modified example. Therefore, the stop time of the non-volatile semiconductor memory 120 can be shortened.

[0122] (Second Implementation)

[0123] exist Figure 1 In the storage system 1 shown, the terminal voltage of capacitor 140 is measured by power management circuit 130. Alternatively, the terminal voltage of capacitor 140 can be measured without using power management circuit 130. For example, the analog-to-digital converter built into controller 110 can be used in the measurement circuit 20.

[0124] exist Figure 11 The image shows a storage system 1a according to the second embodiment. The storage system 1a has a controller 110a, which is built into... Figure 1 The analog-to-digital converter 111 functions as the measurement circuit 20 in the storage system 1 shown. The controller 110a also incorporates a timer circuit 30. Furthermore, the storage system 1a includes a constant current circuit 10 that is not integrated into the power management circuit 130a. Additionally, with... Figure 1 Similarly, in the storage system 1a shown, the power management circuit 130a also charges the capacitor 140 by boosting the voltage of the external power P0 through the buck-boost circuit 131.

[0125] In storage system 1a, similarly to storage system 1 according to the first embodiment, the capacitance value of capacitor 140 is measured by combining natural discharge measurement and constant current measurement. Hereinafter, reference will be made to the diagram illustrating natural discharge measurement. Figure 12 And represent constant current measurement Figure 13 The method for measuring the capacitance value of capacitor 140 using storage system 1a is explained. Figure 12 This is a circuit block diagram used to illustrate the measurement of spontaneous discharge of storage system 1a. Figure 13 This is a circuit block diagram used to illustrate the constant current measurement of storage system 1a.

[0126] like Figure 12 and Figure 13 As shown, the first voltage divider resistor 181 and the second voltage divider resistor 182, connected in series, are connected in parallel with the capacitor 140. Thus, in the storage system 1a, the voltage charged to the capacitor 140 is divided by the first voltage divider resistor 181 connected to one terminal of the capacitor 140 and the second voltage divider resistor 182 connected to a wiring that becomes the GND potential. The analog-to-digital converter 111 measures the voltage at the connection point of the first voltage divider resistor 181 and the second voltage divider resistor 182. The voltage division of the capacitor 140 terminal voltage is necessary because the capacitor 140 is charged by boosting the voltage of the external power supply P0, thus preventing the capacitor 140 terminal voltage from being input to the controller 110a. That is, when the voltage charged to the capacitor 140 is greater than the withstand voltage of the analog-to-digital converter 111, the capacitor 140 terminal voltage needs to be divided to prevent damage to the analog-to-digital converter 111.

[0127] First, refer to Figure 12 The spontaneous discharge measurement of storage system 1a will be described. In the spontaneous discharge measurement, switch SW1 is turned off to stop the charging of capacitor 140 via power management circuit 130a. Additionally, switch SW2 is turned off to stop the charge extraction from capacitor 140 via constant current circuit 10. For example, the on and off states of switches SW1 and SW2 are controlled by controller 110a.

[0128] In this state, the analog-to-digital converter 111 measures the terminal voltage Vcap until the initial voltage from the start of the natural discharge measurement decreases by the first differential voltage dV1. The timer circuit 30 measures the first elapsed time dt1 from the start of the measurement until the terminal voltage Vcap decreases by the first differential voltage dV1.

[0129] Next, refer to Figure 13The constant current measurement of the storage system la will be described. In the constant current measurement, the switch SW1 is turned off to stop the charging of the capacitor 140 by the power management circuit 130a. In addition, the switch SW2 is turned off and the extraction of the charge from the capacitor 140 by the constant current circuit 10 is started. Further, in a state where the constant current circuit 10 extracts the charge from the capacitor 140 at a certain current, the analog-digital converter 111 measures the terminal voltage of the capacitor 140.

[0130] That is, the analog-digital converter 111 measures the terminal voltage Vcap until the initial voltage from the start of the constant current measurement is reduced by the second differential voltage dV2. The timer circuit 30 measures the second elapsed time dt2 from the start of the measurement to the reduction of the terminal voltage Vcap by the second differential voltage dV2.

[0131] Then, the calculating circuit 40 calculates the capacitance value of the capacitor 140 and the resistance value of the leakage resistance connected to the capacitor 140 using the first differential voltage dVl, the second differential voltage dV2, the first elapsed time dtl, and the second elapsed time dt2.

[0132] In the storage system la related to the second embodiment, the analog-digital converter 111 built in the controller 110a is used for the measurement of the terminal voltage of the capacitor 140. Therefore, the configuration of the power management circuit 130a can be simply realized. In addition, the same as the storage system 1 related to the first embodiment, the overlapping description is omitted.

[0133] Further, a field effect transistor (FET) can be used as the switch for the switches SW1 and SW2. A relay can be used for the switch, but in the case where a relay is used for the switch, the response speed of the switch is slower than in the case where an FET is used for the switch.

[0134] Generally, in a controller of an SSD or the like, a general purpose input / output (GPIO) pin is mounted as a general input / output pin. The GPIO pin can output a signal of a high level, a low level, and a high impedance level. Therefore, the GPIO pin can be used to control the on and off of the switch. For example, as shown in FIG. 10, in the case where an n-channel MOS transistor NMOS connected to the GPIO pin is used for the switch, a level shift circuit 190 is needed between the GPIO pin and the n-channel MOS transistor NMOS in order to transmit the signal. Alternatively, as shown in FIG. 11, in the case where a p-channel MOS transistor PMOS connected to the GPIO pin is used for the switch, the switch can be realized by the combination of the p-channel MOS transistor PMOS and a resistance Rp. Figure 14 Figure 14 ​​

[0135] (Other Embodiments)

[0136] The above describes several embodiments of the present application, but these embodiments are presented as examples and are not intended to limit the scope of the application. These embodiments can be implemented in other various ways, and various omissions, substitutions, and modifications can be made without departing from the scope of the application. These embodiments and modifications thereof are included in the scope and spirit of the application, and are also included in the scope of the application and equivalents thereof recited in the claims.

[0137] For example, the storage system 1 is not limited to an SSD, a UFS. In addition, in the above, the case where the capacitor 140 is a capacitor for PLP processing is described, but the measurement of the capacitance value of the capacitor 140 other than the capacitor for PLP processing can also apply the measurement method related to the embodiments. For example, the capacitance value of a bypass capacitor installed in the storage system 1 to cope with power supply noise can be measured by the measurement method related to the embodiments.

Claims

1. A storage system that operates with power supplied from an external device, comprising: a nonvolatile semiconductor memory; a controller that controls the nonvolatile semiconductor memory; a capacitor that supplies electric charge to the nonvolatile semiconductor memory and the controller when the power supply is lost; a constant current circuit that draws electric charge from the capacitor at a certain current; a measurement circuit that measures a terminal voltage across the capacitor; and a timer circuit that measures a time during which the measurement circuit measures the terminal voltage, the measurement circuit measuring the terminal voltage during a period in which the capacitor naturally discharges from the start of measurement until a first differential voltage decreases, and measuring the terminal voltage during a period in which the constant current circuit draws electric charge from the capacitor from the start of measurement until a second differential voltage decreases, the timer circuit measuring a first elapsed time during the first period from the start of measurement until the terminal voltage decreases by the first differential voltage, and measuring a second elapsed time during the second period from the start of measurement until the terminal voltage decreases by the second differential voltage, the controller calculating a resistance value of a leakage resistance of a leakage current flowing in the capacitor using values of the terminal voltage at the start of measurement, the certain current, the first differential voltage, the second differential voltage, the first elapsed time, and the second elapsed time for each of the first period and the second period, and calculating a capacitance value of the capacitor using the resistance value of the leakage resistance, the first differential voltage, and the first elapsed time.

2. The storage system according to claim 1, the controller setting the terminal voltage at the start of measurement for each of the first period and the second period as V0, setting the certain current as Iconst, setting the first differential voltage as dVl, setting the second differential voltage as dV2, setting the first elapsed time as dtl, setting the second elapsed time as dt2, and calculating a capacitance value Ctotal of the capacitor and a resistance value Rleak of the leakage resistance using the following relational expression: Rleak = -dtl x dV2 / {Iconst x dt2 x ln(l - dVl / V0)} - V0 / Iconst Ctotal = -dtl / {Rleak x ln(l - dVl / V0)}.

3. The storage system according to claim 1, the controller setting the first period and the second period consecutively.

4. The storage system according to claim 3, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The controller sets the terminal voltage at the start of the measurement in the first period as V0, sets the certain current as Iconst, sets the first differential voltage as dV1, sets the second differential voltage as dV2, sets the first elapsed time as dt1, sets the second elapsed time as dt2, and calculates the capacitance value Ctotal of the capacitor and the resistance value Rleak of the leakage resistance using the following relational expressions: Rleak = -dt1 x dV2 / {Iconst x dt2 x ln (1 - dV1 / V0)} - (V0 - dV1) / Iconst Ctotal = -dt1 / {Rleak x ln (1 - dV1 / V0)}.

5. The storage system according to any one of claims 1 to 4, Further comprising a power management circuit that controls power supply to the nonvolatile semiconductor memory and the controller and charging and discharging of the capacitor, The power management circuit supplies the nonvolatile semiconductor memory and the controller with the charge accumulated in the capacitor at the time of loss of the power supply.

6. The storage system according to claim 5, The power management circuit has the constant current circuit, the measurement circuit, and the timer circuit built therein.

7. The storage system according to any one of claims 1 to 4, The controller has the measurement circuit and the timer circuit built therein.

8. The storage system according to any one of claims 1 to 4, The nonvolatile semiconductor memory is a NAND-type flash memory.

9. A method of measuring a capacitance value, which is a method of measuring a capacitance value of a capacitor in a storage system that includes a nonvolatile semiconductor memory, a controller that controls the nonvolatile semiconductor memory, and the capacitor that supplies the nonvolatile semiconductor memory and the controller with a charge at the time of loss of a power supply, the method comprising: measuring a terminal voltage of the capacitor at a period from the start of measurement to a period in which a first differential voltage is reduced in a first period in which the capacitor is naturally discharged, measuring the terminal voltage at a period from the start of measurement to a period in which a second differential voltage is reduced in a second period in which the capacitor is discharged at a certain current, measuring a first elapsed time from the start of measurement to a period in which the terminal voltage is reduced by the first differential voltage in the first period and a second elapsed time from the start of measurement to a period in which the terminal voltage is reduced by the second differential voltage in the second period, calculating a resistance value of a leakage resistance of a leakage current flowing through the capacitor using values of the terminal voltage at the start of measurement, the certain current, the first differential voltage, the second differential voltage, the first elapsed time, and the second elapsed time in the first period and the second period, respectively, calculating a capacitance value of the capacitor using the resistance value of the leakage resistance, the first differential voltage, and the first elapsed time.

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