Image sensor structure, manufacturing method and working sequence thereof

Abstract

The present invention discloses an image sensor structure, a manufacturing method and a working sequence thereof. From the center of the pixel to the surrounding, there are a reset transistor source, a reset transistor gate, a floating diffusion node, a second transfer transistor gate, an oxide layer isolation, a first transfer transistor gate, and a deep P well. The floating diffusion node and the reset transistor source are arranged in the N+ injection layer of silicon on both sides of the reset transistor gate. Below the first transfer transistor gate, from shallow to deep, there are: a shallow P well, a secondary P well, and a photodiode. Below the second transfer transistor gate and the reset transistor gate, there is a deep P well that isolates the floating diffusion node and the reset transistor source from the photodiode, the shallow P well, and the secondary P well. The first transfer transistor is a junction field effect transistor, and the second transfer transistor is a CMOS transistor. The two gates of the junction field effect transistor JEFT and CMOS are simultaneously applied to the transfer gate. The gate structure of the JEFT can prevent the transferred electrons from flowing back into the PD to cause noise such as image tailing, which not only increases the pixel area, but also each pixel has a separate readout circuit to avoid signal crosstalk.

Description

Technical Field

[0001] The present invention relates to a CIS chip design, and in particular to an image sensor structure, a manufacturing method thereof and a working sequence. Background Art

[0002] At present, CMOS image sensors have been applied to various scenes in daily life, such as mobile phones, surveillance, vehicles, medical endoscopes, artificial intelligence, etc. Different application fields have different requirements for various indicators of sensors. For example, in low-light scenes, for image sensors with the same resolution, the larger the pixel area, the larger the photosensitive area, and the better the image quality; so in recent years, there have been many studies and inventions to improve the pixel ratio, such as the common three-transistor active pixel (3T-APS), four-transistor active pixel with clamped diode (4TAPS), and five-transistor active pixel with clamped diode (5TAPS), among which 4TAPS is more widely used.

[0003] In the actual application of the existing technology, image lag and tailing occur, which seriously affects the user experience. The main reason for this phenomenon is that the electrons flow back during the transfer from pixels to floating diffusion points, which leads to the above phenomenon.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide an image sensor structure and a manufacturing method and working sequence thereof to solve the above-mentioned technical problems existing in the prior art.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] The image sensor structure of the present invention has a reset transistor source 131, a reset transistor gate 130, a floating diffusion node 122, a second transfer transistor gate 120, an oxide layer isolation 121, and a first transfer transistor gate 110 in order from the center of the pixel to the periphery. The periphery of the pixel is a deep P well 113 that serves as an isolation function.

[0008] The floating diffusion node 122 and the reset transistor source 131 are disposed in the N+ implantation layer of silicon on both sides of the reset transistor gate 130;

[0009] Below the first transfer transistor gate 110 are, from shallow to deep, a shallow P-well 111, a secondary P-well 112, and a photodiode 115;

[0010] A deep P-well 113 is provided below the second transfer transistor gate 120 and the reset transistor gate 130 to isolate the floating diffusion node 122 and the reset transistor source 131 from the photodiode 115 , the shallow P-well 111 , and the sub-P-well 112 .

[0011] The method for manufacturing the above-mentioned image sensor structure comprises the steps of:

[0012] 1) Pixel unit formation:

[0013] Through mask 1, n-type high-energy implantation is performed in the pixel area to form a PD, and through mask 2, high-energy P+-type implantation is performed outside the pixel to form an isolation layer between pixels; p+-type implantation is performed inside the pixel defined by mask 3 to form isolation between the subsequent transistor structure and the PD;

[0014] 2) Junction field effect transistor formation:

[0015] Through mask 4, p-doping is performed from deep to shallow between the high-energy p+ type doping region and the internal p+ doping region to form a secondary P well (PB), and p-doping is performed at a shallower position to form a shallow P well (PW);

[0016] 3) Gate isolation oxide layer formation:

[0017] An oxide layer with a thickness of 60A is deposited in the pixel area as a gate oxide layer, and then polysilicon with a thickness of 1450A is deposited. Through mask 5, a trench with a width of 0.15um is formed between TG1 and TG2 through photolithography and etching processes to connect to the bottom gate oxide layer but not to the gate oxide layer. Subsequently, HDP chemical vapor deposition is performed to fill the trench with silicon dioxide, and finally the excess oxide on the surface is removed through the CMP process;

[0018] 4) Gate formation:

[0019] Through the photolithography and etching process of mask six, a transfer gate and a reset gate are formed; N+ type implantation is performed in the area defined by mask seven to finally form a floating diffusion area FD and a reset transistor source vdd.

[0020] The working sequence of the above-mentioned image sensor structure includes:

[0021] After being reset by the reset transistor, there are no electrons in the FD;

[0022] At time T1, after exposure, PD generates photoelectrons. At this time, TG1 and TG2 are both in the off state. Due to the type and concentration of doped ions, the electrostatic potential of PD is the largest, followed by PW, and PB has the smallest potential.

[0023] At time T2, TG1 is turned on, and TG2 is still in the off state. At this time, due to the high voltage of TG1, PB and PW are inverted, and electrons are transferred to the PW area under the action of the electric field from top to bottom. At this time, the PW potential is larger, followed by PB, and the PD potential is the smallest;

[0024] At T3, TG1 is turned off, PW, PB and PD return to their initial state. Due to the existence of the potential barrier, electrons will not flow back into PD. FD and PW on both sides of TG2 are equivalent to the source and drain of the MOS tube. When TG2 is turned on, electrons are transmitted to the floating diffusion node FD through the communication under TG2. The external circuit reads the FD signal again at this time to complete a complete pixel working sequence.

[0025] Compared with the prior art, the image sensor structure, manufacturing method and working timing provided by the present invention apply two types of gates, junction field effect transistor JEFT and CMOS, on the transfer gate at the same time. The gate structure of JEFT can prevent the transferred electrons from flowing back into the PD to cause image tailing and other noise, which not only increases the pixel area but also each pixel has a separate readout circuit to avoid signal crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a top view of an image sensor structure provided by an embodiment of the present invention;

[0027] Figure 2 Figure 1 A schematic cross-sectional view along the A-A' direction;

[0028] Figure 3 A flowchart of a process for forming a pixel structure according to an embodiment of the present invention;

[0029] Figure 4 This is a timing diagram of pixel operation according to an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of potential distribution of electron transfer path at different time sequences according to an embodiment of the present invention.

[0031] In the figure:

[0032] 110. First transfer transistor gate (TG1), 111. Shallow P-well (PW(p-)), 112. Sub-P-well (PB(p)), 113. Deep P-well (Pwell(p+)), 115. Photodiode (PD), 116. Polysilicon, 114. Substrate (sub), 121. Oxide isolation (oxide), 120. Second transfer transistor gate (TG2), 122. Floating diffusion node (FD), 130. Reset transistor gate (RST), 131. Reset transistor source (vdd). DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0034] First, the terms that may be used in this article are explained as follows:

[0035] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y means both “X” or “Y” and “X and Y”.

[0036] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0037] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0038] Unless otherwise specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0039] The orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or position relationship shown in the drawings and are only for the convenience and simplification of description, and do not explicitly or implicitly indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation of this document.

[0040] The contents not described in detail in the examples of the present invention belong to the prior art known to professionals in the field. If no specific conditions are specified in the examples of the present invention, the conditions are carried out according to the conventional conditions in the field or the conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used in the examples of the present invention, they are all conventional products that can be purchased commercially.

[0041] The image sensor structure of the present invention has a reset transistor source 131, a reset transistor gate 130, a floating diffusion node 122, a second transfer transistor gate 120, an oxide layer isolation 121, and a first transfer transistor gate 110 in order from the center of the pixel to the periphery. The periphery of the pixel is a deep P well 113 that serves as an isolation function.

[0042] The floating diffusion node 122 and the reset transistor source 131 are disposed in the N+ implantation layer of silicon on both sides of the reset transistor gate 130;

[0043] Below the first transfer transistor gate 110 are, from shallow to deep, a shallow P-well 111, a secondary P-well 112, and a photodiode 115;

[0044] A deep P-well 113 is provided below the second transfer transistor gate 120 and the reset transistor gate 130 to isolate the floating diffusion node 122 and the reset transistor source 131 from the photodiode 115 , the shallow P-well 111 , and the sub-P-well 112 .

[0045] The first transfer transistor is a junction field effect transistor, and the second transfer transistor is a CMOS transistor.

[0046] The method for manufacturing the above-mentioned image sensor structure comprises the steps of:

[0047] 1) Pixel unit formation:

[0048] Through mask 1, n-type high-energy implantation is performed in the pixel area to form a PD, and through mask 2, high-energy P+-type implantation is performed outside the pixel to form an isolation layer between pixels; p+-type implantation is performed inside the pixel defined by mask 3 to form isolation between the subsequent transistor structure and the PD;

[0049] 2) Junction field effect transistor formation:

[0050] Through mask 4, p-doping is performed from deep to shallow between the high-energy p+ type doping region and the internal p+ doping region to form a secondary P well (PB), and p-doping is performed at a shallower position to form a shallow P well (PW);

[0051] 3) Gate isolation oxide layer formation:

[0052] An oxide layer with a thickness of 60A is deposited in the pixel area as a gate oxide layer, and then polysilicon with a thickness of 1450A is deposited. Through mask 5, a trench with a width of 0.15um is formed between TG1 and TG2 through photolithography and etching processes to connect to the bottom gate oxide layer but not to the gate oxide layer. Subsequently, HDP chemical vapor deposition is performed to fill the trench with silicon dioxide, and finally the excess oxide on the surface is removed through the CMP process;

[0053] 4) Gate formation:

[0054] Through the photolithography and etching process of mask six, a transfer gate and a reset gate are formed; N+ type implantation is performed in the area defined by mask seven to finally form a floating diffusion area FD and a reset transistor source vdd.

[0055] The working sequence of the above-mentioned image sensor structure includes:

[0056] After being reset by the reset transistor, there are no electrons in the FD;

[0057] At time T1, after exposure, PD generates photoelectrons. At this time, TG1 and TG2 are both in the off state. Due to the type and concentration of doped ions, the electrostatic potential of PD is the largest, followed by PW, and PB has the smallest potential.

[0058] At time T2, TG1 is turned on, and TG2 is still in the off state. At this time, due to the high voltage of TG1, PB and PW are inverted, and electrons are transferred to the PW area under the action of the electric field from top to bottom. At this time, the PW potential is larger, followed by PB, and the PD potential is the smallest;

[0059] At T3, TG1 is turned off, PW, PB and PD return to their initial state. Due to the existence of the potential barrier, electrons will not flow back into PD. FD and PW on both sides of TG2 are equivalent to the source and drain of the MOS tube. When TG2 is turned on, electrons are transmitted to the floating diffusion node FD through the communication under TG2. The external circuit reads the FD signal again at this time to complete a complete pixel working sequence.

[0060] In summary, it can be seen that the image sensor structure, its manufacturing method and working timing of the embodiment of the present invention apply two types of gates of the junction field effect transistor JEFT and CMOS on the transfer gate at the same time. The gate structure of JEFT can prevent the transferred electrons from flowing back into the PD to cause noise such as image tailing, which not only increases the pixel area but also each pixel has a separate readout circuit to avoid signal crosstalk.

[0061] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the embodiments of the present invention are described in detail with specific embodiments below.

[0062] Example 1

[0063] like Figure 1 , Figure 2 As shown, the two gates of the junction field effect transistor JEFT and CMOS are simultaneously applied on the transfer gate. Figure 1 As shown in the top view, 110 is the gate TG1 of the junction field effect transistor, 121 is the silicon dioxide isolation layer, 120 is the gate TG2 of the CMOS, 130 is the reset transistor gate, the N+ injection layers of silicon on both sides of the reset transistor gate are the floating diffusion node 122 and the reset transistor source 131, and the periphery of the pixel is the deep P well 113 (PWell (p+)) for isolation; Figure 2 is along Figure 1 The cross-sectional view along the AA' direction below TG1 shows, from shallow to deep, a shallow P-well 111 (PW(p-)), a secondary P-well 112 (PB(p)), and a photodiode 115. A deep P-well 113 is provided below 120 and 130 to isolate 122, 131 from 115, 111, and 112.

[0064] The new image sensor of the present invention is different from the traditional transfer gate TG (transfer gate) in that the two gates of the junction field effect transistor JEFT and CMOS are made on TG at the same time, separated by oxide in the middle, but the gate oxide layer above the channel is connected together. P-type ions are injected between PD and the first transfer gate TG1 to form PB and p- to form PW. Figure 2 As shown, at this time, the electrostatic potential of the PB region with a deeper doping concentration is small, forming a potential barrier to clamp the electrons in the PD. At this time, the electrostatic potential of PW is slightly greater than that of PB but less than that of PD. The side close to FD is the gate of the CMOS tube. Its working principle is that under the JEFT gate, PB and PW are inverted under the action of the forward voltage, and the electrons in the PD are transferred to the PW region under the action of the electric field; then turn on TG2. At this time, PW is equivalent to the drain of the CMOS tube, and TG2 is pressurized to transfer the electrons to FD, thereby completing the reading of the entire pixel signal.

[0065] Compared with traditional image sensors, this structure has the following two advantages: 1. The gate structure of JEFT can prevent the transferred electrons from flowing back into the PD and causing noise such as image tailing; 2. Due to this special readout method, the entire pixel can be made under the TG, and the readout circuit can also be integrated on the pixel, which not only increases the pixel area but also each pixel has a separate readout circuit to avoid signal crosstalk.

[0066] The manufacturing process of the entire pixel structure, as well as the subsequent working sequence and potential changes of the electron transmission path during the process are as follows:

[0067] 1. Pixel unit formation: n-type high-energy implantation is performed in the pixel area through mask 1 to form PD, and high-energy P+-type implantation is performed around the pixel through mask 2 to form an isolation layer between pixels; p+-type implantation is performed inside the pixel defined by mask 3 to form isolation between the subsequent transistor structure and PD;

[0068] 2. Formation of junction field effect transistors: Through mask 4, p-doping is performed from deep to shallow between the high-energy p+ doping area and the internal p+ doping area to form a secondary P well (PB), and p-doping is performed at a shallower position to form a shallow P well (PW);

[0069] 3. The gate isolation oxide layer is formed. A 60A thick oxide layer is deposited in the pixel area as the gate oxide layer, and then a 1450A thick polysilicon is deposited. Through mask 5, a 0.15um wide groove is formed between TG1 and TG2 through photolithography and etching processes to connect to the bottom gate oxide layer but not etch the gate oxide layer. Then HDP chemical vapor deposition is performed to fill the groove with silicon dioxide, and finally the excess oxide on the surface is removed through the CMP process;

[0070] 4. Gate formation: Through mask 6, photolithography and etching processes are performed to form transfer gate and reset gate; N+ type implantation is performed in the area defined by mask 7 to finally form floating diffusion area FD and reset transistor source vdd;

[0071] like Figure 3 The cross-sectional structure of the pixel corresponding to the above four manufacturing steps is shown.

[0072] The electron transmission path is the horizontal axis, and the corresponding electric potential is the vertical axis. Figure 4 It is the gate voltage timing diagram when the pixel unit is working, where sample1 and sample2 are correlated double sampling signals of the peripheral circuit; RST, TG1, TG2 represent the timing changes of the gate voltage of the reset gate, transfer gate 1 and transfer gate 2 respectively.

[0073] Figure 5 As in Figure 4Schematic diagram of the instantaneous potential state on the electron transfer path at three different time points T1, T2, and T3. Figure 5 -a shows that after the reset transistor is reset, there are no electrons in FD. After exposure at time T1, PD generates photoelectrons. At this time, TG1 and TG2 are both in the off state. Due to the type and concentration of doped ions, the electrostatic potential of PD is the largest, followed by PW, and PB is the smallest. Figure 5 -b When TG1 is turned on and TG2 is still turned off, the high voltage of TG1 causes PB and PW to be inverted, and electrons are transferred to the PW region under the action of the electric field from top to bottom. At this time, the PW potential is larger, followed by PB, and the PD potential is the smallest; Figure 5 At -c, TG1 turns off PW, PB and PD to return to the initial state. Due to the existence of the potential barrier, electrons will not flow back into PD. FD and PW on both sides of TG2 are equivalent to the source and drain of the MOS tube. When TG2 is turned on, electrons are transmitted to the floating diffusion node FD through the communication under TG2. At this time, the external circuit reads the signal of FD again to complete a complete pixel working sequence.

[0074] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. An image sensor structure, characterized in that: From the center of the pixel to the periphery, there are a reset transistor source (131), a reset transistor gate (130), a floating diffusion node (122), a second transfer transistor gate (120), an oxide layer isolation (121), and a first transfer transistor gate (110), and the periphery of the pixel is a deep P well (113) that plays an isolation role; The floating diffusion node (122) and the reset transistor source (131) are arranged in the N+ injection layer of silicon on both sides of the reset transistor gate (130); Below the first transfer transistor gate (110), from shallow to deep, are: a shallow P well (111), a secondary P well (112), and a photodiode (115); A deep P well (113) is provided below the second transfer transistor gate (120) and the reset transistor gate (130) to isolate the floating diffusion node (122) and the reset transistor source (131) from the photodiode (115), the shallow P well (111) and the secondary P well (112).

2. The image sensor structure according to claim 1, characterized in that: The first transfer transistor is a junction field effect transistor, and the second transfer transistor is a CMOS transistor.

3. A method for manufacturing an image sensor structure according to claim 1 or 2, characterized in that: Includes steps: 1) Pixel unit formation: Through mask 1, n-type high-energy implantation is performed in the pixel area to form a PD, and through mask 2, high-energy P+-type implantation is performed outside the pixel to form an isolation layer between pixels; p+-type implantation is performed inside the pixel defined by mask 3 to form isolation between the subsequent transistor structure and the PD; 2) Junction field effect transistor formation: Through mask 4, p-doping is performed from deep to shallow between the high-energy p+ type doping region and the internal p+ doping region to form a secondary P well, and p-doping is performed at a shallower position to form a shallow P well; 3) Gate isolation oxide layer formation: An oxide layer with a thickness of 60A is deposited in the pixel area as a gate oxide layer, and then polysilicon with a thickness of 1450A is deposited. Through mask 5, a trench with a width of 0.15um is formed between TG1 and TG2 through photolithography and etching processes to connect to the bottom gate oxide layer but not to the gate oxide layer. Subsequently, HDP chemical vapor deposition is performed to fill the trench with silicon dioxide, and finally the excess oxide on the surface is removed through the CMP process; 4) Gate formation: Through the photolithography and etching process of mask six, a transfer gate and a reset gate are formed; N+ type implantation is performed in the area defined by mask seven to finally form a floating diffusion area FD and a reset transistor source vdd.

4. A working timing of the image sensor structure according to claim 1 or 2, characterized in that: include: After being reset by the reset transistor, there are no electrons in the FD; At time T1, after exposure, PD generates photoelectrons. At this time, TG1 and TG2 are both in the off state. Due to the type and concentration of doped ions, the electrostatic potential of PD is the largest, followed by PW, and PB has the smallest potential. At time T2, TG1 is turned on, and TG2 is still in the off state. At this time, due to the high voltage of TG1, PB and PW are inverted, and electrons are transferred to the PW area under the action of the electric field from top to bottom. At this time, the PW potential is larger, followed by PB, and the PD potential is the smallest; At T3, TG1 is turned off, PW, PB and PD return to their initial state. Due to the existence of the potential barrier, electrons will not flow back into PD. FD and PW on both sides of TG2 are equivalent to the source and drain of the MOS tube. When TG2 is turned on, electrons are transmitted to the floating diffusion node FD through the communication under TG2. The external circuit reads the FD signal again at this time to complete a complete pixel working sequence.

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