Semiconductor device and semiconductor circuit

Abstract

An embodiment provides a semiconductor device and a semiconductor circuit that can suppress damage caused by current concentration. The semiconductor device according to the embodiment includes: a semiconductor layer having a first surface and a second surface opposed to the first surface, the semiconductor layer including a first trench, a second trench, and a third trench provided on the first surface side; a first gate electrode among the first trenches; a second gate electrode among the second trenches; a third gate electrode among the third trenches; a fourth gate electrode and a fifth gate electrode provided on the second surface side; a first electrode in contact with the first surface; a second electrode in contact with the second surface; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-155895 (filing date: September 16, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a semiconductor circuit. Background Art

[0004] As an example of a semiconductor device for power use, there is an Insulated Gate Bipolar Transistor (IGBT) having a trench gate structure. In the IGBT having a trench gate structure, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on a collector electrode. Then, a gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film interposed therebetween. Further, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0005] In the above IGBT, by applying a positive voltage higher than a threshold voltage to the gate electrode, a channel is formed in the p-type base region. Then, electrons are injected from the n-type emitter region into the n-type drift region, and holes are injected from the p-type collector region into the n-type drift region. Thereby, a conduction current with electrons and holes as carriers flows between the collector electrode and the emitter electrode.

[0006] An end region is provided around a cell region having a trench gate structure. The end region includes, for example, an electric field relaxation structure such as a guard ring. By providing the end region, the electric field intensity at the end of the cell region is reduced, and a reduction in breakdown voltage when the IGBT is in an off state is suppressed.

[0007] At the end of the cell region, carriers spread to the end region where there is no cell when the IGBT is in an on state. During a turn-off operation in which the IGBT transfers from an on state to an off state, the carriers that have spread to the end region are concentrated and discharged to the end of the cell region. Therefore, current concentration occurs at the end of the cell region. As a result, there is a risk of breakdown of the IGBT caused by current concentration. Summary of the Invention

[0008] Embodiments of the present invention provide a semiconductor device and a semiconductor circuit that reduce turn-off loss and suppress breakdown caused by current concentration.

[0009] The semiconductor device of the embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface, the semiconductor layer including: a first trench provided on the first surface side; a second trench provided on the first surface side; and a third trench provided on the first surface side; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a third gate electrode provided in the third trench; a fourth gate electrode provided on the second surface side; a fifth gate electrode provided on the second surface side; a first electrode connected to the first surface; a second electrode connected to the second surface; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a semiconductor circuit according to the first embodiment.

[0011] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment.

[0012] Figure 3 (a) and (b) of are schematic top views of the semiconductor device according to the first embodiment.

[0013] Figure 4 is a timing diagram of the semiconductor device according to the first embodiment.

[0014] Figure 5 (a) and (b) of are schematic top views of the semiconductor device according to the second embodiment.

[0015] Figure 6 is a schematic cross-sectional view of a part of the semiconductor device according to the third embodiment.

[0016] Figure 7 is a timing diagram of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the following description, the same or similar components may be denoted by the same reference numerals, and the description of the components that have been described once will be appropriately omitted.

[0018] In this specification, the distribution and absolute value of the impurity concentration in a semiconductor region can be measured, for example, using Secondary Ion Mass Spectrometry (SIMS). In addition, the relative magnitude relationship of the impurity concentrations in two semiconductor regions can be determined, for example, using Scanning Capacitance Microscopy (SCM). Further, the distribution and absolute value of the impurity concentration can be measured, for example, using Spreading Resistance Analysis (SRA). In SCM and SRA, the relative magnitude relationship and absolute value of the carrier concentration in the semiconductor region are obtained. By assuming the activation rate of the impurities, the relative magnitude relationship between the impurity concentrations in the two semiconductor regions, the distribution of the impurity concentration, and the absolute value of the impurity concentration can be obtained based on the measurement results of SCM and SRA.

[0019] (First Embodiment)

[0020] The semiconductor device of the first embodiment includes: a semiconductor layer having a first surface and a second surface opposed to the first surface, the semiconductor layer including a first trench provided on the first surface side, a second trench provided on the first surface side, and a third trench provided on the first surface side; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a third gate electrode provided in the third trench; a fourth gate electrode provided on the second surface side; a fifth gate electrode provided on the second surface side; a first electrode in contact with the first surface; a second electrode in contact with the second surface; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.

[0021] In addition, the semiconductor circuit of the first embodiment includes: the above semiconductor device; and a control circuit that controls the voltages applied to the first electrode pad, the second electrode pad, the third electrode pad, the fourth electrode pad, and the fifth electrode pad.

[0022] The semiconductor device of the first embodiment is an IGBT 100 having a double-gate structure with gate electrodes on both the front and back sides of the semiconductor layer. In addition, the IGBT 100 has three independently controllable gate electrodes on the front side of the semiconductor layer. Further, the IGBT 100 has two independently controllable gate electrodes on the back side of the semiconductor layer. The gate electrodes on the front side of the semiconductor layer have a trench gate structure provided in the trench. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

[0023] Figure 1 It is a schematic diagram of the semiconductor circuit of the first embodiment. The semiconductor circuit of the first embodiment is the semiconductor module 1000.

[0024] The semiconductor module 1000 includes an IGBT 100 and a control circuit 150.

[0025] Figure 1 The layout of the IGBT 100 is shown. The IGBT 100 has a cell region 100a, an end region 100b, a first surface gate electrode pad 101 (first electrode pad), a second surface gate electrode pad 102 (second electrode pad), a third surface gate electrode pad 103 (third electrode pad), a first back gate electrode pad 104 (fourth electrode pad), and a second back gate electrode pad 105 (fifth electrode pad).

[0026] The end region 100b surrounds the cell region 100a. The first surface gate electrode pad 101, the second surface gate electrode pad 102, and the third surface gate electrode pad 103 are located on the surface side of the IGBT 100. The first back gate electrode pad 104 and the second back gate electrode pad 105 are located on the back side of the IGBT 100.

[0027] Figure 2 It is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 It is Figure 1 the AA' cross-section of

[0028] The IGBT 100 of the first embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first surface gate insulating film 21, a second surface gate insulating film 22, a third surface gate insulating film 23, a first back gate insulating film 24, a second back gate insulating film 25, a main gate electrode 31 (first gate electrode), a control gate electrode 32 (second gate electrode), a pre-gate electrode 33 (third gate electrode), a back cell gate electrode 34 (fourth gate electrode), a back end gate electrode 35 (fifth gate electrode), a surface interlayer insulating layer 40, and a back interlayer insulating layer 42.

[0029] In the semiconductor layer 10, a main gate trench 51 (first trench), a control gate trench 52 (second trench), a pre-gate trench 53 (third trench), an n-type unit drain region 60 (sixth semiconductor region), an n-type end drain region 62 (seventh semiconductor region), a p-type unit collector region 64 (fourth semiconductor region), a p-type end collector region 65 (fifth semiconductor region), an n-type buffer region 66, an n-type drift region 68 (first semiconductor region), a p-type base region 70 (second semiconductor region), an n-type emitter region 72 (third semiconductor region), a p-type contact region 74, a p-type boundary region 76 (eighth semiconductor region), and a p-type guard ring region 78 are provided.

[0030] The semiconductor layer 10 has a first surface P1 and a second surface P2 opposed to the first surface P1. The first surface P1 is the surface of the semiconductor layer 10, and the second surface P2 is the back surface of the semiconductor layer 10.

[0031] In this specification, a direction parallel to the first surface P1 is referred to as a first direction. Further, a direction parallel to the first surface P1 and orthogonal to the first direction is referred to as a second direction.

[0032] The semiconductor layer 10 includes a unit portion 10a and an end portion 10b. The unit portion 10a is included in a unit region 100a of the semiconductor layer 10. The end portion 10b is included in an end region 100b of the semiconductor layer 10. The end portion 10b surrounds the unit portion 10a.

[0033] The semiconductor layer 10 is, for example, single crystal silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0034] The emitter electrode 12 is provided on the first surface P1 side of the semiconductor layer 10. At least a part of the emitter electrode 12 is in contact with the first surface P1 of the semiconductor layer 10. The emitter electrode 12 is, for example, metal. An emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V.

[0035] The collector electrode 14 is provided on the second surface P2 side of the semiconductor layer 10. At least a part of the collector electrode 14 is in contact with the second surface P2 of the semiconductor layer 10. The collector electrode 14 is, for example, metal.

[0036] A collector voltage (Vc) is applied to the collector electrode 14. The collector voltage is, for example, 200 V or more and 6500 V or less.

[0037] The main gate trench 51 is provided in the cell region 100a. The main gate trench 51 is provided on the first surface P1 side of the cell portion 10a. The main gate trench 51 is a trench provided in the cell portion 10a. The main gate trench 51 extends in the first direction. The main gate trench 51 is repeatedly provided in the second direction.

[0038] The control gate trench 52 is provided in the cell region 100a. The control gate trench 52 is provided on the first surface P1 side of the cell portion 10a. The control gate trench 52 is a trench provided in the cell portion 10a. The control gate trench 52 extends in the first direction. The control gate trench 52 is repeatedly provided in the second direction.

[0039] The pre-gate trench 53 is provided in the cell region 100a. The pre-gate trench 53 is provided on the first surface P1 side of the cell portion 10a. The pre-gate trench 53 is a trench provided in the cell portion 10a. The pre-gate trench 53 extends in the first direction. The pre-gate trench 53 is repeatedly provided in the second direction.

[0040] The main gate electrode 31 is provided in the cell region 100a. The main gate electrode 31 is provided on the first surface P1 side of the cell portion 10a. At least a part of the main gate electrode 31 is provided in the main gate trench 51. The first surface gate electrode pad 101 is electrically connected to the main gate electrode 31 using wiring (not shown).

[0041] The main gate electrode 31 is, for example, polysilicon containing n-type impurities or p-type impurities. A first gate voltage (Vg1) is applied to the main gate electrode 31. The first gate voltage (Vg1) is a voltage based on the emitter voltage (Ve).

[0042] Hereinafter, the transistor controlled by the first gate voltage (Vg1) applied to the main gate electrode 31 is referred to as the main gate transistor.

[0043] The first surface gate insulating film 21 is provided between the main gate electrode 31 and the cell portion 10a. At least a part of the first surface gate insulating film 21 is provided in the main gate trench 51. The first surface gate insulating film 21 is, for example, a silicon oxide film.

[0044] The control gate electrode 32 is provided in the cell region 100a. The control gate electrode 32 is provided on the first surface P1 side of the cell portion 10a. At least a part of the control gate electrode 32 is provided in the control gate trench 52. The second surface gate electrode pad 102 is electrically connected to the control gate electrode 32 using wiring (not shown).

[0045] The control gate electrode 32 is, for example, polysilicon containing n-type impurities or p-type impurities. A second gate voltage (Vg2) is applied to the control gate electrode 32. The second gate voltage (Vg2) is a voltage based on the emitter voltage (Ve).

[0046] Hereinafter, the transistor controlled by the second gate voltage (Vg2) applied to the control gate electrode 32 is referred to as the control gate transistor.

[0047] The second surface gate insulating film 22 is provided between the control gate electrode 32 and the cell portion 10a. At least a part of the second surface gate insulating film 22 is provided in the control gate trench 52. The second surface gate insulating film 22 is, for example, a silicon oxide film.

[0048] The pre-gate electrode 33 is provided in the cell region 100a. The pre-gate electrode 33 is provided on the first surface P1 side of the cell portion 10a. At least a part of the pre-gate electrode 33 is provided in the pre-gate trench 53. The third surface gate electrode pad 103 is electrically connected to the pre-gate electrode 33 using a wiring (not shown).

[0049] The pre-gate electrode 33 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. A third gate voltage (Vg3) is applied to the pre-gate electrode 33. The third gate voltage (Vg3) is a voltage based on the emitter voltage (Ve).

[0050] Hereinafter, the transistor controlled by the third gate voltage (Vg3) applied to the pre-gate electrode 33 is referred to as the pre-gate transistor.

[0051] The third surface gate insulating film 23 is provided between the pre-gate electrode 33 and the cell portion 10a. At least a part of the third surface gate insulating film 23 is provided in the pre-gate trench 53. The third surface gate insulating film 23 is, for example, a silicon oxide film.

[0052] The back cell gate electrode 34 is provided in the cell region 100a. The back cell gate electrode 34 is provided on the second surface P2 side of the cell portion 10a. The first back gate electrode pad 104 is electrically connected to the back cell gate electrode 34 using a wiring (not shown).

[0053] The back cell gate electrode 34 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. A fourth gate voltage (Vg4) is applied to the back cell gate electrode 34. The fourth gate voltage (Vg4) is a voltage based on the collector voltage (Vc).

[0054] Hereinafter, the transistor controlled by the fourth gate voltage (Vg4) applied to the back cell gate electrode 34 is referred to as the back cell transistor.

[0055] The first back gate insulating film 24 is provided between the back cell gate electrode 34 and the cell portion 10a. The first back gate insulating film 24 is, for example, a silicon oxide film.

[0056] The back-end gate electrode 35 is provided in the end region 100b. The back-end gate electrode 35 is provided on the second surface P2 side of the end portion 10b. The second back gate electrode pad 105 is electrically connected to the back-end gate electrode 35 using wiring (not shown).

[0057] The back-end gate electrode 35 is, for example, polysilicon containing n-type impurities or p-type impurities. A fifth gate voltage (Vg5) is applied to the back-end gate electrode 35. The fifth gate voltage (Vg5) is a voltage based on the collector voltage (Vc).

[0058] Hereinafter, the transistor controlled by the fifth gate voltage (Vg5) applied to the back-end gate electrode 35 is referred to as the back-end transistor.

[0059] The second back gate insulating film 25 is provided between the back-end gate electrode 35 and the end portion 10b. The second back gate insulating film 25 is, for example, a silicon oxide film.

[0060] Figure 3 It is a schematic top view of the semiconductor device of the first embodiment. Figure 3 (a) of is a top view observed from the surface side of the IGBT 100, that is, the first surface P1 side of the semiconductor layer 10. Figure 3 (b) of is a top view observed from the back side of the IGBT 100, that is, the second surface P2 side of the semiconductor layer 10.

[0061] Figure 3 (a) of is a diagram schematically showing the arrangement of the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33. Figure 3 (b) of is a diagram schematically showing the arrangement of the back cell gate electrode 34 and the back-end gate electrode 35.

[0062] As Figure 3 As shown in (a) of, the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 are provided in the cell region 100a. The main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 extend in the first direction.

[0063] As Figure 3 As shown in (b) of, the back cell gate electrode 34 is provided in the cell region 100a. In addition, the back-end gate electrode 35 is provided in the end region 100b. The back cell gate electrode 34 and the back-end gate electrode 35 extend in the first direction.

[0064] The surface interlayer insulating layer 40 is provided on the first surface P1 side of the semiconductor layer 10. The surface interlayer insulating layer 40 is provided between a part of the semiconductor layer 10 and the emitter electrode 12. The surface interlayer insulating layer 40 electrically separates a part of the semiconductor layer 10 from the emitter electrode 12. The surface interlayer insulating layer 40 electrically separates the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 from the emitter electrode 12.

[0065] The surface interlayer insulating layer 40 is, for example, silicon oxide.

[0066] The back surface interlayer insulating layer 42 is provided on the second surface P2 side of the semiconductor layer 10. The back surface interlayer insulating layer 42 is provided between a part of the semiconductor layer 10 and the collector electrode 14. The back surface interlayer insulating layer 42 electrically separates a part of the semiconductor layer 10 from the collector electrode 14. The back surface interlayer insulating layer 42 electrically separates the back surface unit gate electrode 34 and the back surface end gate electrode 35 from the collector electrode 14.

[0067] The back surface interlayer insulating layer 42 is, for example, silicon oxide.

[0068] The p-type unit collector region 64 is provided in the unit portion 10a. The unit collector region 64 is provided in a part between the drift region 68 and the second surface P2. A part of the unit collector region 64 is in contact with the second surface P2.

[0069] A part of the unit collector region 64 faces the back surface unit gate electrode 34 with the first back surface gate insulating film 24 interposed therebetween. The unit collector region 64 extends in the first direction on the second surface P2. In the unit collector region 64 facing the back surface unit gate electrode 34, a channel of the back surface unit transistor controlled by the back surface unit gate electrode 34 is formed.

[0070] The unit collector region 64 is electrically connected to the collector electrode 14. A part of the unit collector region 64 is in contact with the collector electrode 14.

[0071] The p-type end collector region 65 is provided in the end portion 10b. The end collector region 65 is provided in a part between the drift region 68 and the second surface P2. A part of the end collector region 65 is in contact with the second surface P2.

[0072] A part of the end collector region 65 faces the back surface end gate electrode 35 with the second back surface gate insulating film 25 interposed therebetween. The end collector region 65 extends in the first direction on the second surface P2. In the end collector region 65 facing the back surface end gate electrode 35, a channel of the back surface end transistor controlled by the back surface end gate electrode 35 is formed.

[0073] The terminal collector region 65 is electrically connected to the collector electrode 14. A part of the terminal collector region 65 is in contact with the collector electrode 14.

[0074] The n-type unit drain region 60 is provided in the unit portion 10a. The unit drain region 60 is provided in a part between the unit collector region 64 and the second surface P2. A part of the unit collector region 64 faces the back unit gate electrode 34 with the first back gate insulating film 24 interposed therebetween.

[0075] A part of the unit drain region 60 is in contact with the collector electrode 14. The unit drain region 60 extends in the first direction. The unit drain region 60 functions as the drain of the back unit transistor.

[0076] The n-type impurity concentration of the unit drain region 60 is higher than the n-type impurity concentration of the drift region 68.

[0077] The n-type terminal drain region 62 is provided in the terminal portion 10b. The terminal drain region 62 is provided in a part between the terminal collector region 65 and the second surface P2. A part of the terminal drain region 62 faces the back terminal gate electrode 35 with the second back gate insulating film 25 interposed therebetween.

[0078] A part of the terminal drain region 62 is in contact with the collector electrode 14. The terminal drain region 62 extends in the first direction. The terminal drain region 62 functions as the drain of the back terminal transistor.

[0079] The n-type impurity concentration of the terminal drain region 62 is higher than the n-type impurity concentration of the drift region 68.

[0080] The n-type drift region 68 is provided between the unit collector region 64 and the first surface P1. The drift region 68 is provided between the terminal collector region 65 and the first surface P1. The drift region 68 is provided between the unit collector region 64 and the base region 70.

[0081] The drift region 68 becomes the path of the on-current when the IGBT 100 is in the on state. The drift region 68 has the function of depleting when the IGBT 100 is in the off state and maintaining the breakdown voltage of the IGBT 100.

[0082] The n-type buffer region 66 is provided between the drift region 68 and the unit collector region 64. The buffer region 66 is provided between the drift region 68 and the terminal collector region 65.

[0083] A part of the buffer region 66 is in contact with the second surface P2. A part of the buffer region 66 faces the back unit gate electrode 34 with the first back gate insulating film 24 interposed therebetween. A part of the buffer region 66 faces the back terminal gate electrode 35 with the second back gate insulating film 25 interposed therebetween.

[0084] The n-type impurity concentration in the buffer region 66 is higher than the n-type impurity concentration in the drift region 68.

[0085] The resistance of the buffer region 66 is lower than the resistance of the drift region 68. By providing the buffer region 66, when the back unit transistor is in the on state, the discharge of electrons from the drift region 68 to the collector electrode 14 via the back unit transistor is promoted. By providing the buffer region 66, when the back end transistor is in the on state, the discharge of electrons from the drift region 68 to the collector electrode 14 via the back end transistor is promoted.

[0086] In addition, the buffer region 66 also has a function of suppressing the extension of the depletion layer when the IGBT 100 is in the off state. In addition, a configuration in which the buffer region 66 is not provided can also be adopted.

[0087] The p-type base region 70 is provided in the cell region 100a. The base region 70 is provided in the cell portion 10a. The base region 70 is provided between the drift region 68 and the first surface P1.

[0088] A part of the base region 70 faces the main gate electrode 31 with the first surface gate insulating film 21 interposed therebetween. In the base region 70 facing the main gate electrode 31, a channel of the main gate transistor controlled by the main gate electrode 31 is formed.

[0089] A part of the base region 70 faces the control gate electrode 32 with the second surface gate insulating film 22 interposed therebetween. In the base region 70 facing the control gate electrode 32, a channel of the control gate transistor controlled by the control gate electrode 32 is formed.

[0090] A part of the base region 70 faces the pre-gate electrode 33 with the third surface gate insulating film 23 interposed therebetween. In the base region 70 facing the pre-gate electrode 33, a channel of the pre-gate transistor controlled by the pre-gate electrode 33 is formed.

[0091] The n-type emitter region 72 is provided in the cell region 100a. The emitter region 72 is provided in the cell portion 10a. The emitter region 72 is provided between the base region 70 and the first surface P1. The emitter region 72 extends along the first direction on the first surface P1.

[0092] A part of the emitter region 72 faces the main gate electrode 31 with the first surface gate insulating film 21 interposed therebetween. A part of the emitter region 72 is in contact with the main gate trench 51. A part of the emitter region 72 is in contact with the first surface gate insulating film 21.

[0093] A part of the emitter region 72 is opposed to the control gate electrode 32 with the second surface gate insulating film 22 interposed therebetween. A part of the emitter region 72 is in contact with the control gate trench 52. A part of the emitter region 72 is in contact with the second surface gate insulating film 22.

[0094] A part of the emitter region 72 is opposed to the pre-gate electrode 33 with the third surface gate insulating film 23 interposed therebetween. A part of the emitter region 72 is in contact with the pre-gate trench 53. A part of the emitter region 72 is in contact with the third surface gate insulating film 23.

[0095] The emitter region 72 is electrically connected to the emitter electrode 12. A part of the emitter region 72 is in contact with the emitter electrode 12.

[0096] The n-type impurity concentration of the emitter region 72 is higher than the n-type impurity concentration of the drift region 68. The emitter region 72 becomes a supply source of electrons when the IGBT 100 is in the on state.

[0097] The p-type contact region 74 is provided in the cell region 100a. The contact region 74 is provided in the cell part 10a. The contact region 74 is provided between the base region 70 and the first surface P1. The contact region 74 extends along the first direction on the first surface P1.

[0098] The contact region 74 is electrically connected to the emitter electrode 12. The contact region 74 is in contact with the emitter electrode 12.

[0099] The p-type impurity concentration of the contact region 74 is higher than the p-type impurity concentration of the base region 70.

[0100] The p-type boundary region 76 is provided in the terminal region 100b. The boundary region 76 is provided in the terminal part 10b. The boundary region 76 is provided between the drift region 68 and the first surface P1. The boundary region 76 surrounds the cell part 10a.

[0101] The p-type guard ring region 78 is provided in the terminal region 100b. The guard ring region 78 is provided in the terminal part 10b. The guard ring region 78 is provided between the drift region 68 and the first surface P1. The guard ring region 78 surrounds the cell part 10a. The guard ring region 78 is provided in plural, for example.

[0102] By providing the boundary region 76 and the guard ring region 78, the electric field strength at the end of the cell region 100a is reduced, and a decrease in the breakdown voltage when the IGBT 100 is in the off state is suppressed.

[0103] The control circuit 150 controls the IGBT 100. The control circuit 150 is, for example, a gate drive circuit. The gate drive circuit independently controls the magnitude and timing of the voltages applied to the first surface gate electrode pad 101, the second surface gate electrode pad 102, the third surface gate electrode pad 103, the first back gate electrode pad 104, and the second back gate electrode pad 105.

[0104] The control circuit 150 independently controls the first gate voltage (Vg1) applied to the main gate electrode 31, the second gate voltage (Vg2) applied to the control gate electrode 32, the third gate voltage (Vg3) applied to the pre-gate electrode 33, the fourth gate voltage (Vg4) applied to the back cell gate electrode 34, and the fifth gate voltage (Vg5) applied to the back end gate electrode 35.

[0105] Next, the operation of the IGBT 100 will be described.

[0106] Figure 4 is a timing diagram of the semiconductor device of the first embodiment. Figure 4 Shows the change timing of the first gate voltage (Vg1), the second gate voltage (Vg2), the third gate voltage (Vg3), the fourth gate voltage (Vg4), and the fifth gate voltage (Vg5).

[0107] The first gate voltage (Vg1) is the gate voltage applied to the main gate transistor controlled by the main gate electrode 31. The second gate voltage (Vg2) is the gate voltage applied to the control gate transistor controlled by the control gate electrode 32. The third gate voltage (Vg3) is the gate voltage applied to the pre-gate transistor controlled by the pre-gate electrode 33. The fourth gate voltage (Vg4) is the gate voltage applied to the back cell transistor controlled by the back cell gate electrode 34. The fifth gate voltage (Vg5) is the gate voltage applied to the back end transistor controlled by the back end gate electrode 35.

[0108] In the off state of the IGBT 100, an emitter voltage (Ve) is applied to the emitter electrode 12. For example, at time t0, an emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage (Ve) is, for example, 0V.

[0109] In the off state of the IGBT 100, a collector voltage (Vc) is applied to the collector electrode 14. The collector voltage (Vc) is, for example, 200V or more and 6500V or less. The collector-emitter voltage (Vce) applied between the collector electrode 14 and the emitter electrode 12 is, for example, 200V or more and 6500V or less.

[0110] In addition, the first gate voltage (Vg1), the second gate voltage (Vg2), and the third gate voltage (Vg3) are voltages referenced to the emitter voltage (Ve). In addition, the fourth gate voltage (Vg4) and the fifth gate voltage (Vg5) are voltages referenced to the collector voltage (Vc).

[0111] First, the change timing of the first gate voltage (Vg1) applied to the main gate transistor will be described.

[0112] For example, at time t0, a first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). The first turn-off voltage (Voff1) is a voltage below the threshold voltage at which the main gate transistor does not become in the on state.

[0113] The first turn-off voltage (Voff1) is, for example, 0V or a negative voltage. In Figure 4 an example, the case where the first turn-off voltage (Voff1) is -15V is illustrated.

[0114] At time t1, a first turn-on voltage (Von1) is applied as the first gate voltage (Vg1). The first turn-on voltage (Von1) is a positive voltage exceeding the threshold voltage of the main gate transistor. In Figure 4 an example, the case where the first turn-on voltage (Von1) is 15V is illustrated.

[0115] By applying the first turn-on voltage (Von1) to the main gate transistor, IGBT100 becomes in the on state. At time t1, IGBT100 performs a turn-on operation.

[0116] By applying the first turn-on voltage (Von1) to the main gate transistor, an n-type inversion layer is formed near the interface of the p-type base region 70 and the first surface gate insulating film 21. By forming the n-type inversion layer, electrons are injected from the n-type emitter region 72 through the n-type inversion layer into the n-type drift region 68. The electrons injected into the n-type drift region 68 forward bias the pn junctions formed between the n-type buffer region 66 and the p-type cell collector region 64 and between the n-type buffer region 66 and the p-type end collector region 65. The electrons reach the collector electrode 14 and cause the injection of holes from the p-type cell collector region 64 and the p-type end collector region 65. Thus, IGBT100 becomes in the on state.

[0117] At time t4, the first turn-off voltage (Voff1) is applied as the first gate voltage (Vg1). By applying the first turn-off voltage (Voff1) to the main gate transistor, IGBT100 becomes in the off state. Between time t1 and time t4, IGBT100 becomes in the on state.

[0118] Next, the change timing of the second gate voltage (Vg2) applied to the control gate transistor will be described.

[0119] For example, at time t0, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) refers to a voltage below the threshold voltage at which the control gate transistor does not become in an on state.

[0120] The second turn-off voltage (Voff2) is, for example, a negative voltage. In Figure 4 an example is shown where the second turn-off voltage (Voff2) is -15V.

[0121] At time t1, a second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) is a positive voltage exceeding the threshold voltage of the control gate transistor. In Figure 4 an example is shown where the second turn-on voltage (Von2) is 15V.

[0122] By applying the second turn-on voltage (Von2) to the control gate transistor, an n-type inversion layer is formed near the interface of the p-type base region 70 and the second surface gate insulating film 22. By forming the n-type inversion layer, electrons are injected from the n-type emitter region 72 into the n-type drift region 68 through the n-type inversion layer.

[0123] At time t3 before time t4, a second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). By applying the second turn-off voltage (Voff2) to the control gate transistor, the injection of electrons into the drift region 68 via the control gate transistor is blocked. In addition, by making the second gate voltage (Vg2) a negative voltage, a p-type accumulation layer is formed in the p-type base region 70 near the control gate trench 52. By forming the p-type accumulation layer, the discharge of holes to the emitter electrode 12 is promoted. As a result, the carriers in the drift region 68 are reduced.

[0124] Next, the change timing of the third gate voltage (Vg3) applied to the pre-gate transistor will be described.

[0125] For example, at time t0, a third turn-off voltage (Voff3) is applied as the third gate voltage (Vg3). The third turn-off voltage (Voff3) refers to a voltage below the threshold voltage at which the pre-gate transistor does not become in an on state.

[0126] The third turn-off voltage (Voff3) is, for example, 0V or a negative voltage. In Figure 4 an example is shown where the third turn-off voltage (Voff3) is 0V.

[0127] At time t1, a third turn-on voltage (Von3) is applied as the third gate voltage (Vg3). The third turn-on voltage (Von3) is a positive voltage that exceeds the threshold voltage of the pre-gate transistor. In Figure 4 an example is shown where the third turn-on voltage (Von3) is 15V.

[0128] By applying the third turn-on voltage (Von3) to the pre-gate transistor, the pre-gate transistor becomes in an on state. By applying the third turn-on voltage (Von3) to the pre-gate transistor, an n-type inversion layer is formed near the interface of the p-type base region 70 and the third surface gate insulating film 23. By forming the n-type inversion layer, electrons are injected from the n-type emitter region 72 into the n-type drift region 68 through the n-type inversion layer.

[0129] At time t2 before time t3, a third turn-off voltage (Voff3) is applied as the third gate voltage (Vg3). By applying the third turn-off voltage (Voff3) to the pre-gate transistor, the pre-gate transistor becomes in an off state. By the pre-gate transistor becoming in an off state, the injection of electrons into the drift region 68 via the pre-gate transistor is blocked. As a result, the electrons injected into the drift region 68 are reduced.

[0130] In addition, for example, a negative voltage can also be applied as the third gate voltage (Vg3) at time t3. By applying a negative voltage as the third gate voltage (Vg3), a p-type accumulation layer is formed in the p-type base region 70 near the pre-gate trench 53. By forming the p-type accumulation layer, the discharge of holes to the emitter electrode 12 is promoted. Thus, the carriers in the drift region 68 are reduced.

[0131] Next, the change timing of the fourth gate voltage (Vg4) applied to the back unit transistor will be described.

[0132] For example, at time t0, a fourth turn-off voltage (Voff4) is applied as the fourth gate voltage (Vg4). The fourth turn-off voltage (Voff4) is a voltage below the threshold voltage at which the back unit transistor does not become in an on state.

[0133] The fourth turn-off voltage (Voff4) is, for example, 0V or a negative voltage. In Figure 4 an example is shown where the fourth turn-off voltage (Voff4) is 0V.

[0134] At time ty, a fourth turn-on voltage (Von4) is applied as the fourth gate voltage (Vg4). The fourth turn-on voltage (Von4) is a positive voltage that exceeds the threshold voltage of the back unit transistor. In Figure 4 an example is shown where the fourth turn-on voltage (Von4) is 15V.

[0135] By applying a fourth conduction voltage (Von4) to the back cell transistor, an n-type inversion layer is formed near the interface of the p-type cell collector region 64 and the first back gate insulating film 24.

[0136] By forming an n-type inversion layer near the interface of the p-type cell collector region 64 and the first back gate insulating film 24, a path for electrons to be discharged from the n-type buffer region 66 of the cell portion 10a through the n-type inversion layer and the n-type cell drain region 60 to the collector electrode 14 is formed. That is, a state where the n-type buffer region 66 of the cell portion 10a is short-circuited with the collector electrode 14, namely, so-called anode short-circuit, is generated.

[0137] Due to the generation of anode short-circuit, the passage of electrons from the n-type buffer region 66 of the cell portion 10a through the p-type cell collector region 64 to the collector electrode 14 is hindered. Therefore, the injection of holes from the p-type cell collector region 64 into the drift region 68 of the cell portion 10a is suppressed.

[0138] After that, at time t5, a fourth turn-off voltage (Voff4) is applied as the fourth gate voltage (Vg4), and the back cell transistor is turned off.

[0139] Next, the change timing of the fifth gate voltage (Vg5) applied to the back end transistor will be described.

[0140] For example, at time t0, a fifth turn-off voltage (Voff5) is applied as the fifth gate voltage (Vg5). The fifth turn-off voltage (Voff5) is a voltage below the threshold voltage at which the back end transistor does not turn on.

[0141] The fifth turn-off voltage (Voff5) is, for example, 0V or a negative voltage. In Figure 4 , the case where the fifth turn-off voltage (Voff5) is 0V is illustrated.

[0142] At time tx before time ty, a fifth conduction voltage (Von5) is applied as the fifth gate voltage (Vg5). The fifth conduction voltage (Von5) is a positive voltage exceeding the threshold voltage of the back end transistor. In Figure 4 , the case where the fifth conduction voltage (Von5) is 15V is illustrated.

[0143] By applying the fifth conduction voltage (Von5) to the back end transistor, an n-type inversion layer is formed near the interface of the p-type end collector region 65 and the second back gate insulating film 25.

[0144] By forming an n-type inversion layer near the interface between the p-type end collector region 65 and the second back gate insulating film 25, a path is formed for electrons to be discharged from the n-type buffer region 66 at the end portion 10b through the n-type inversion layer and the n-type end drain region 62 to the collector electrode 14. That is, a state where the buffer region 66 at the n-type end portion 10b is short-circuited with the collector electrode 14 is generated, namely, so-called anode short-circuit.

[0145] Due to the generation of anode short-circuit, it hinders electrons from reaching the collector electrode 14 from the n-type buffer region 66 at the end portion 10b through the p-type end collector region 65. Therefore, the injection of holes from the p-type end collector region 65 into the drift region 68 at the end portion 10b is suppressed.

[0146] In addition, the time tx can be either before the time t3 or after the time t3. In addition, the time tx can be either before the time t4 or after the time t4.

[0147] After that, at the time t5, a fifth turn-off voltage (Voff5) is applied as the fifth gate voltage (Vg5) to turn the back-end transistor into an off state.

[0148] The control circuit 150 controls the magnitudes and timings of the first gate voltage (Vg1) applied to the first surface gate electrode pad 101, the second gate voltage (Vg2) applied to the second surface gate electrode pad 102, the third gate voltage (Vg3) applied to the third surface gate electrode pad 103, the fourth gate voltage (Vg4) applied to the first back gate electrode pad 104, and the fifth gate voltage (Vg5) applied to the second back gate electrode pad 105 to achieve the operation of the above IGBT100.

[0149] For example, the control circuit 150 applies a first turn-on voltage (Von1) to the first surface gate electrode pad 101 at the time t1, applies a second turn-on voltage (Von2) to the second surface gate electrode pad 102 at the time t1, and applies a third turn-on voltage (Von3) to the third surface gate electrode pad 103 at the time t1. After that, at the time t2, which is after a predetermined time from the time t1, a third turn-off voltage (Voff3) is applied to the third surface gate electrode pad 103. Then, at the time tx, which is after a predetermined time from the time t2, a fifth turn-on voltage (Von5) is applied to the second back gate electrode pad 105. Then, at the time ty, which is after a predetermined time from the time tx, a fourth turn-on voltage (Von4) is applied to the first back gate electrode pad 104.

[0150] For example, after the control circuit 150 applies the third conduction voltage (Von3) to the third surface gate electrode pad 103 at time t1, at time t4 after a predetermined time has elapsed, the first turn-off voltage (Voff1) is applied to the first surface gate electrode pad 101. Then, at time tx before time t4, the fifth conduction voltage (Von5) is applied to the second back gate electrode pad 105.

[0151] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0152] The IGBT 100 of the first embodiment includes a control gate transistor on the surface side of the semiconductor layer 10 that can be controlled independently of the main gate transistor. At time t3 before time t4 when the IGBT 100 performs a turn-off operation, a negative voltage is applied to the gate electrode of the control gate transistor to make it in an off state, thereby promoting the discharge of holes to the emitter electrode 12. Therefore, compared with the case where the control gate transistor is not provided, the amount of carriers to be discharged during the turn-off operation of the IGBT 100 can be reduced. Thereby, the turn-off loss of the IGBT 100 can be reduced.

[0153] For example, at time t3, by applying a negative voltage to the gate electrode of the pre-gate transistor, the amount of carriers to be discharged during the turn-off operation can be further reduced. Thereby, the turn-off loss of the IGBT 100 can be further reduced.

[0154] In addition, the IGBT 100 of the first embodiment includes a pre-transistor on the surface side of the semiconductor layer 10 that can be controlled independently of the main gate transistor and the control gate transistor. By making the pre-transistor in an on state at time t1 when the IGBT 100 performs a conduction operation, the amount of electrons injected into the drift region 68 increases compared with the case where the pre-transistor is not provided. Therefore, compared with the case where the pre-transistor is not provided, the conduction time of the IGBT 100 is shortened. Thereby, the conduction loss of the IGBT 100 can be reduced.

[0155] Moreover, at time t2 before time t4 when the IGBT 100 performs a turn-off operation, the pre-transistor is made in an off state. By making the pre-transistor in an off state, the saturation current of the IGBT 100 is reduced. Therefore, it is possible to suppress, for example, the breakdown of the IGBT 100 when a large current flows through the IGBT 100 due to a load short circuit.

[0156] In addition, the IGBT 100 of the first embodiment includes a back unit transistor on the back side of the semiconductor layer 10. During the turn-off operation of the IGBT 100, by turning on the back unit transistor, the injection of holes into the drift region 68 of the cell portion 10a is suppressed. By suppressing the injection of holes into the drift region 68, the turn-off loss is reduced compared to the case where the back unit transistor is not provided. As a result, the power consumption of the IGBT 100 can be reduced.

[0157] In addition, the IGBT 100 of the first embodiment has a terminal region 100b provided around the cell region 100a. A boundary region 76 and a guard ring region 78 are provided in the terminal region 100b. By providing the boundary region 76 and the guard ring region 78, the electric field strength at the end of the cell region 100a is reduced, and a decrease in the breakdown voltage when the IGBT 100 is in the off state is suppressed.

[0158] In the on state of the IGBT 100, a conduction current also flows between the emitter electrode 12 and the collector electrode 14 of the terminal region 100b. Therefore, in the on state of the IGBT 100, carriers are also accumulated in the drift region 68 of the terminal portion 10b. In other words, in the on state of the IGBT 100, it becomes a state where carriers expand to the terminal region 100b where no transistor exists on the surface.

[0159] During the turn-off operation of the IGBT 100, it is necessary to discharge the carriers accumulated in the drift region 68 of the terminal portion 10b. However, there is no carrier discharge path on the surface side of the terminal region 100b. Therefore, the carriers are concentrated and discharged to the end of the cell region 100a. As a result, current concentration occurs at the end of the cell region 100a. Thus, there is a risk of breakdown of the IGBT 100 caused by current concentration.

[0160] The IGBT 100 of the first embodiment includes a back terminal transistor on the back side of the semiconductor layer 10 of the terminal region 100b, which can be controlled independently of the back unit transistor. At a time tx before a time ty when the back unit transistor is turned on, the back terminal transistor is turned on. By turning on the back terminal transistor, the injection of holes into the n-type drift region 68 of the terminal portion 10b is suppressed.

[0161] By turning on the back terminal transistor before the back unit transistor, the carriers accumulated in the drift region 68 of the terminal portion 10b can be selectively reduced. Therefore, during the turn-off operation of the IGBT 100, current concentration at the end of the cell region 100a can be suppressed. Thus, breakdown of the IGBT 100 caused by current concentration can be suppressed.

[0162] From the viewpoint of suppressing the breakdown of the IGBT 100 caused by current concentration, it is preferable to turn on the back-end transistor before the turn-off operation of the IGBT 100. In other words, it is preferable to turn on the back-end transistor before the time t4 when the IGBT 100 performs the turn-off operation. In other words, the time tx is preferably before the time t4. In other words, it is preferable to apply the fifth conduction voltage (Von5) to the second back gate electrode pad 105 before applying the first turn-off voltage (Voff1) to the first surface gate electrode pad 101.

[0163] As described above, according to the first embodiment, it is possible to realize a semiconductor device and a semiconductor circuit that reduce turn-off loss and suppress breakdown caused by current concentration.

[0164] (Second Embodiment)

[0165] The semiconductor device and the semiconductor circuit of the second embodiment are different from the semiconductor device and the semiconductor circuit of the first embodiment in that the first gate electrode extends in a first direction parallel to the first surface, the fourth gate electrode extends in a second direction parallel to the first surface and orthogonal to the first direction, and the fifth gate electrode extends in a direction orthogonal to the fourth gate electrode. Hereinafter, for the content that overlaps with the first embodiment, some descriptions may be omitted.

[0166] The semiconductor device of the second embodiment is the same as the first embodiment, and is an IGBT 200 having a two-sided gate structure with gate electrodes on the surface side and the back side of the semiconductor layer. In addition, the IGBT 200 has three types of independently controllable gate electrodes on the surface side of the semiconductor layer. In addition, the IGBT 200 has two types of independently controllable gate electrodes on the back side of the semiconductor layer.

[0167] Figure 5 is a schematic plan view of the semiconductor device of the second embodiment. Figure 5 The (a) of is a plan view observed from the surface side of the IGBT 200, that is, the first surface P1 side of the semiconductor layer 10. Figure 5 The (b) of is a plan view observed from the back side of the IGBT 200, that is, the second surface P2 side of the semiconductor layer 10.

[0168] Figure 5 The (a) of is a diagram schematically showing the arrangement of the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33. Figure 5 The (b) of is a diagram schematically showing the arrangement of the back unit gate electrode 34 and the back-end gate electrode 35.

[0169] The IGBT 200 has a cell region 100a, an end region 100b, a first surface gate electrode pad 101 (first electrode pad), a second surface gate electrode pad 102 (second electrode pad), a third surface gate electrode pad 103 (third electrode pad), a first back gate electrode pad 104 (fourth electrode pad), and a second back gate electrode pad 105 (fifth electrode pad).

[0170] The end region 100b surrounds the cell region 100a. The first surface gate electrode pad 101, the second surface gate electrode pad 102, and the third surface gate electrode pad 103 are located on the surface side of the IGBT 200. In addition, the first back gate electrode pad 104 and the second back gate electrode pad 105 are located on the back side of the IGBT 200.

[0171] As Figure 5 shown in (a) of [], the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 are provided in the cell region 100a. The main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33 extend in a first direction in the cell region 100a.

[0172] As Figure 5 shown in (b) of [], the back cell gate electrode 34 is provided in the cell region 100a. The back cell gate electrode 34 extends in a second direction orthogonal to the first direction.

[0173] In addition, the back end gate electrode 35 is provided in the end region 100b. The back end gate electrode 35 extends in the first direction orthogonal to the second direction. The back end gate electrode 35 extends in a direction orthogonal to the back cell gate electrode 34.

[0174] The back cell gate electrode 34 extends in a direction orthogonal to the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33, thereby equalizing the flow of the on-current of the IGBT 200. Therefore, it is difficult to generate local on-current concentration. Therefore, breakdown caused by current concentration in the IGBT 200 can be suppressed.

[0175] As described above, according to the second embodiment, a semiconductor device and a semiconductor circuit capable of reducing the turn-off loss and suppressing breakdown caused by current concentration can be realized.

[0176] (Third Embodiment)

[0177] The semiconductor device and the semiconductor circuit of the third embodiment are different from the semiconductor device and the semiconductor circuit of the first embodiment in that the third semiconductor region is separated from the second trench. Hereinafter, for the content repeated with the first embodiment, a part of the description may be omitted.

[0178] The semiconductor device of the third embodiment is the same as that of the first embodiment, and is an IGBT 300 with a double-gate structure having gate electrodes on both the front and back sides of the semiconductor layer. In addition, the IGBT 300 has three independently controllable gate electrodes on the front side of the semiconductor layer. In addition, the IGBT 300 has two independently controllable gate electrodes on the back side of the semiconductor layer.

[0179] Figure 6 It is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 6 It is the same as that of the first embodiment Figure 2 corresponding figure.

[0180] The IGBT 300 of the third embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first surface gate insulating film 21, a second surface gate insulating film 22, a third surface gate insulating film 23, a first back gate insulating film 24, a second back gate insulating film 25, a main gate electrode 31 (first gate electrode), a control gate electrode 32 (second gate electrode), a pre-gate electrode 33 (third gate electrode), a back unit gate electrode 34 (fourth gate electrode), a back end gate electrode 35 (fifth gate electrode), a surface interlayer insulating layer 40, and a back interlayer insulating layer 42.

[0181] In the semiconductor layer 10, a main gate trench 51 (first trench), a control gate trench 52 (second trench), a pre-gate trench 53 (third trench), an n-type unit drain region 60 (sixth semiconductor region), an n-type end drain region 62 (seventh semiconductor region), a p-type unit collector region 64 (fourth semiconductor region), a p-type end collector region 65 (fifth semiconductor region), an n-type buffer region 66, an n-type drift region 68 (first semiconductor region), a p-type base region 70 (second semiconductor region), an n-type emitter region 72 (third semiconductor region), a p-type contact region 74, a p-type boundary region 76, and a p-type guard ring region 78 are provided.

[0182] The emitter region 72 is separated from the control gate trench 52. The emitter region 72 does not contact the control gate trench 52.

[0183] The emitter region 72 is separated from the second surface gate insulating film 22. The emitter region 72 does not contact the second surface gate insulating film 22.

[0184] Figure 7 It is a timing diagram of the semiconductor device of the third embodiment. Figure 7Shows the change timing of the first gate voltage (Vg1), the second gate voltage (Vg2), the third gate voltage (Vg3), the fourth gate voltage (Vg4), and the fifth gate voltage (Vg5).

[0185] Figure 7 Compared with that in the first embodiment Figure 4 The timing diagram shown only differs in the change timing of the second gate voltage (Vg2) applied to the control gate electrode 32. Therefore, only the timing of the second gate voltage (Vg2) will be described.

[0186] In addition, even if the second gate voltage (Vg2) applied to the control gate electrode 32 changes, since the emitter region 72 does not contact the control gate trench 52, no transistor action occurs. However, hereinafter, for the sake of consistency with the description of the first embodiment, for convenience, terms such as the second turn-on voltage (Von2) and the second turn-off voltage (Voff2) are used.

[0187] For example, at time t0, the second turn-on voltage (Von2) is applied as the second gate voltage (Vg2). The second turn-on voltage (Von2) refers to a voltage higher than the voltage at which a p-type accumulation layer is formed in the p-type base region 70 near the control gate trench 52.

[0188] The second turn-on voltage (Von2) is, for example, 0V or a positive voltage. In Figure 7 an example of the second turn-on voltage (Von2) being 0V is illustrated.

[0189] At time t3 before time t4, the second turn-off voltage (Voff2) is applied as the second gate voltage (Vg2). The second turn-off voltage (Voff2) is a voltage below the voltage at which a p-type accumulation layer is formed in the p-type base region 70 near the control gate trench 52. The second turn-off voltage (Voff2) is a negative voltage. In Figure 7 an example of the second turn-off voltage (Voff2) being -15V is illustrated.

[0190] By applying the second turn-off voltage (Voff2) to the control gate transistor, a p-type accumulation layer is formed in the p-type base region 70 near the control gate trench 52. By forming the p-type accumulation layer, the discharge of holes to the emitter electrode 12 is promoted. As a result, the carriers in the drift region 68 are reduced.

[0191] After that, at time t5, the second turn-on voltage (Von2) is applied as the second gate voltage (Vg2) to make the p-type accumulation layer disappear.

[0192] Even if the second gate voltage (Vg2) applied to the control gate electrode 32 of the IGBT 300 according to the third embodiment changes, transistor operation is not generated. Therefore, compared with the IGBT 100, the operation of the IGBT 300 is stable.

[0193] In addition, since there is no emitter region 72 in contact with the control gate trench 52, the discharge of holes to the emitter electrode 12 is promoted compared with the case where the emitter region 72 is present. Therefore, compared with the IGBT 100, the turn-off loss is further reduced.

[0194] As described above, according to the third embodiment, a semiconductor device and a semiconductor circuit capable of reducing the turn-off loss and suppressing breakdown due to current concentration can be realized.

[0195] In the first to third embodiments, the case where the semiconductor layer is single-crystalline silicon has been described as an example, but the semiconductor layer is not limited to single-crystalline silicon. For example, it may also be other single-crystalline semiconductors such as single-crystalline silicon carbide.

[0196] In the first to third embodiments, the case where the main gate electrode 31, the control gate electrode 32, the pre-gate electrode 33, the back unit gate electrode 34, and the back end gate electrode 35 are all in a stripe shape has been described as an example. However, the shapes of the main gate electrode 31, the control gate electrode 32, the pre-gate electrode 33, the back unit gate electrode 34, and the back end gate electrode 35 are not limited to the stripe shape. For example, one or all of the main gate electrode 31, the control gate electrode 32, the pre-gate electrode 33, the back unit gate electrode 34, and the back end gate electrode 35 may also be in a shape other than the stripe shape, such as a polygonal shape.

[0197] In the first to third embodiments, the case where the semiconductor layer 10 has three types of gate electrodes, namely, the main gate electrode 31, the control gate electrode 32, and the pre-gate electrode 33, on the surface side has been described as an example. However, in addition to the above three types of gate electrodes, a dummy gate electrode may also be provided. The dummy gate electrode is, for example, a gate electrode whose potential in the trench is fixed to the potential of the emitter electrode 12.

[0198] In the first to third embodiments, the case where the back unit transistor and the back end transistor are planar gate type transistors has been described as an example. However, one or both of the back unit transistor and the back end transistor may also be trench gate type transistors.

[0199] In the first to third embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0200] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. For example, the constituent elements of one embodiment can be replaced or changed with those of other embodiments. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Claims

1. A semiconductor device, comprising: A semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including: A first trench provided on the first surface side; A second trench provided on the first surface side; And A third trench provided on the first surface side; A first gate electrode provided in the first trench; A second gate electrode provided in the second trench; A third gate electrode provided in the third trench; A fourth gate electrode provided on the second surface side; A fifth gate electrode provided on the second surface side; A first electrode connected to the first surface; A second electrode connected to the second surface; A first electrode pad electrically connected to the first gate electrode; A second electrode pad electrically connected to the second gate electrode; A third electrode pad electrically connected to the third gate electrode; A fourth electrode pad electrically connected to the fourth gate electrode; And A fifth electrode pad electrically connected to the fifth gate electrode, At a first time earlier than the time when the semiconductor device performs a turn-off operation, a transistor controlled by a second gate voltage applied to the second gate electrode is made into an off state, at the time when the semiconductor device performs a turn-on operation, a transistor controlled by a third gate voltage applied to the third gate electrode is made into an on state, at a second time earlier than the time when the semiconductor device performs a turn-off operation, a transistor controlled by the third gate voltage applied to the third gate electrode is made into an off state, at a time earlier than the time when the semiconductor device performs a turn-off operation, a transistor controlled by a fourth gate voltage applied to the fourth gate electrode is made into an on state, and the second time is before the first time.

2. The semiconductor device according to claim 1, wherein The semiconductor layer includes: A first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, opposite to the first gate electrode, opposite to the second gate electrode, and opposite to the third gate electrode; A third semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface and connected to the first electrode; A fourth semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface, opposite to the fourth gate electrode, and connected to the second electrode; A fifth semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface, opposite to the fifth gate electrode, and connected to the second electrode; A sixth semiconductor region of a first conductivity type provided between the fourth semiconductor region and the second surface and connected to the second electrode; and A seventh semiconductor region of a first conductivity type provided between the fifth semiconductor region and the second surface and connected to the second electrode.

3. The semiconductor device according to claim 1 or 2, wherein The semiconductor layer has a unit portion and an end portion, the end portion surrounding the unit portion, The first trench, the second trench, and the third trench are provided on the first surface side of the unit portion, The fourth gate electrode is provided on the second surface side of the unit portion. The fifth gate electrode is provided on the second surface side of the end portion.

4. The semiconductor device according to claim 1 or 2, wherein the first gate electrode extends in a first direction, and the first direction is parallel to the first surface. the fourth gate electrode extends in a second direction, the second direction is parallel to the first surface, and is orthogonal to the first direction.

5. The semiconductor device according to claim 1 or 2, wherein the fifth gate electrode extends in a direction orthogonal to the fourth gate electrode.

6. The semiconductor device according to claim 1 or 2, wherein the first electrode pad, the second electrode pad, and the third electrode pad are provided on the first surface side of the semiconductor layer. the fourth electrode pad and the fifth electrode pad are provided on the second surface side of the semiconductor layer.

7. A semiconductor circuit, comprising: the semiconductor device according to any one of claims 1 to 6; and a control circuit that controls voltages applied to the first electrode pad, the second electrode pad, the third electrode pad, the fourth electrode pad, and the fifth electrode pad.

8. The semiconductor circuit according to claim 7, wherein the control circuit after applying a conduction voltage equal to or higher than a threshold voltage to the first electrode pad, the second electrode pad, and the third electrode pad, after a predetermined time, applies a cutoff voltage lower than the threshold voltage to the third electrode pad, the threshold voltage causing an inversion layer to be formed in portions of the semiconductor layer facing the first gate electrode, the second gate electrode, and the third gate electrode. after applying the cutoff voltage to the third electrode pad, after a predetermined time, applies a conduction voltage to the fifth electrode pad. after applying the conduction voltage to the fifth electrode pad, after a predetermined time, applies a conduction voltage to the fourth electrode pad.

9. The semiconductor circuit according to claim 8, wherein the control circuit after applying a conduction voltage to the first electrode pad, the second electrode pad, and the third electrode pad, after a predetermined time, applies a cutoff voltage to the first electrode pad. before applying the cutoff voltage to the first electrode pad, applies a conduction voltage to the fifth electrode pad.

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