Data processing methods, equipment and storage media

Abstract

A data processing method, apparatus, and storage medium are disclosed. The method includes: responding to a read request for target data, when a first child node is not verified in the processor, the processor obtains a compressed first child node from memory (S101). This first child node is a child node related to the target data in an integrity tree, the integrity tree including multiple root nodes and multiple child nodes, the child nodes being stored in compressed form in memory, and the root nodes being stored in decompressed form in the processor; the processor decompresses the compressed first child node and caches the decompressed first child node in the processor (S102) for integrity verification of the target data. By storing the child nodes of the integrity tree in compressed form in memory, memory storage space is saved, the size of the child nodes is reduced, and the processor can quickly read the compressed child nodes from memory for data integrity verification, thus improving the speed of integrity verification.

Description

Technical Field

[0001] This application relates to the field of computer security technology, and in particular to a data processing method, device and storage medium. Background Technology

[0002] Data integrity is one of the three fundamental elements of information security. It refers to ensuring that information or data is not tampered with without authorization or that any tampering can be detected quickly during the transmission, storage, and processing of information or data.

[0003] To prevent data tampering, Intel's Software Guard Extensions (SGX) architecture introduces the concept of an Integrity Tree. The Integrity Tree protects the integrity of in-memory data, safeguarding it from replay attacks. The Integrity Tree is stored in main memory and loaded into the cache when the processor needs to access it. For example, when the processor reads data from memory, it reads encrypted data and decrypts it. To verify the integrity of the read data, the processor reads the Integrity Tree from memory and uses it to verify the data's integrity.

[0004] Currently, the data integrity verification process suffers from high time overhead, slow verification speed, and excessive consumption of storage resources. Summary of the Invention

[0005] This application provides a data processing method, device, and storage medium to solve the problems of high time consumption, slow verification, and excessive storage resource consumption in the current data integrity verification process.

[0006] In a first aspect, embodiments of this application provide a data processing method applied to a data processing device, which includes a processor and a memory. The processor includes a cache and registers. An integrity tree for data integrity verification includes multiple root nodes and multiple child nodes, wherein the multiple root nodes are stored in the processor's registers in a decompressed state, and the multiple child nodes are stored in the memory in a compressed state. Furthermore, the processor's cache caches child nodes previously read from the memory, and these read child nodes are stored in the processor's cache in a decompressed state.

[0007] Based on the aforementioned data processing equipment, the data processing procedure of this application embodiment specifically includes:

[0008] In response to a read request for target data, if the first child node is not detected in the processor, for example, if the first child node is not detected in the processor's cache, the compressed first child node is obtained from memory. This first child node is a child node in the integrity tree that is related to the target data. The compressed first child node is decompressed and the decompressed first child node is cached in the processor. The first child node is used for target data integrity verification.

[0009] In this embodiment, since the processor is trusted and the data within it is not easily tampered with, the root node of the integrity tree and its cached child nodes are stored in the processor in a decompressed state. This facilitates the processor's use of the decompressed integrity tree node for data integrity verification. Storing the child nodes of the integrity tree in a compressed state in memory saves memory space, reduces memory overhead, and effectively reduces the size of the child nodes. During data reading, in response to a read request for the target data, if the processor has not verified the first child node, it retrieves the compressed first child node from memory, decompresses it, and caches the decompressed first child node in the processor so that the processor can use it to verify the integrity of the target data. Because the compressed first child node has a small data volume, the processor can quickly read it from memory for integrity verification of the target data, thereby reducing the time overhead of data integrity verification and improving the speed of integrity verification.

[0010] In some embodiments, due to limited processor storage space, when the number of cached child nodes in the processor reaches a preset value, the cached child nodes need to be removed. The process of removing cached child nodes includes: when it is detected that the number of child nodes in the processor has reached the preset value, obtaining a second child node to be removed from the processor; when it is detected that the second child node to be removed has been changed, compressing the second child node to be removed, and replacing the second child node in memory with the compressed second child node.

[0011] In one implementation, the compression of the second child node to be removed includes the following two cases:

[0012] Case 1: The second child node to be removed is pre-compressed. If the size of the pre-compressed second child node is smaller than the size of the smallest storage unit in the memory, the pre-compressed second child node is used as the final compression result and stored in the memory.

[0013] Case 2: The second child node to be removed is pre-compressed. If the size of the pre-compressed second child node is larger than the smallest storage unit in the memory, the overflow counter of the second child node is incremented by a first value, and the value of each sub-counter of the second child node is set to a second value. The reset second child node is then recompressed. Here, the first value is a positive number greater than 0, and the second value is a positive number; for example, if the first value is 1, the second value is 0.

[0014] Since the MAC of the second child node is related to the value of the counter of the second child node, in the above case 2, when the value of the counter of the second child node to be removed changes, the MAC of the second child node also changes. Therefore, it is necessary to redetermine the MAC of the second child node according to the value of the reset counter in the second child node, and write the redetermined MAC into the memory.

[0015] In some embodiments, the branching factor of the integrity tree in this application is a preset parameter, which is a positive integer greater than 8 among multiples of 2. Currently, the common branching factor for integrity trees is 8, while the branching factor of the integrity tree in this application is greater than 8, for example, 16 or 32. This reduces the number of levels in the integrity tree, reduces the number of times the processor accesses the integrity tree, and thus improves the speed of data integrity verification. For example, taking the integrity tree maintaining 16GB of storage space as an example, the current integrity tree has a numerator factor of 8, and the number of levels of the generated integrity tree is: log8(16,000,000,000) = 12 levels. During integrity verification, 12 accesses to the memory are required, resulting in high time overhead and slow verification speed. In the embodiments of this application, the numerator factor of the integrity tree is greater than 8, for example, 32. When the integrity tree with a numerator factor of 32 maintains 16GB of storage space, the number of levels of its integrity tree is log8(16,000,000,000) = 12. 32 (16,000,000,000) = 7. During integrity verification, only 7 memory accesses are required, which effectively reduces the number of times the processor accesses the integrity tree, thereby reducing the time overhead of integrity verification and improving the speed of integrity verification.

[0016] In some embodiments, to further improve the speed of data integrity verification, when decompressing the first child node in compressed state, at least two threads can be used to decompress the first child node in parallel; and / or, when compressing the second child node, at least two threads can be used to compress the second child node in parallel.

[0017] Secondly, embodiments of this application provide a data processing device, including: a memory and a processor, wherein the memory is configured to store data; and the processor is configured to read and write access to the data stored in the memory;

[0018] The processor is specifically configured to: in response to a read request for target data, if the first child node is not detected in the processor, obtain the compressed first child node from memory. The first child node is a child node in the integrity tree that is related to the target data. The integrity tree includes multiple root nodes and multiple child nodes. The multiple child nodes are stored in memory in a compressed state, and the multiple root nodes are stored in the processor in a decompressed state. The compressed first child node is decompressed, and the decompressed first child node is cached in the processor. The first child node is used for target data integrity verification.

[0019] In this embodiment, since the processor is trusted and the data within it is not easily tampered with, the root node of the integrity tree and its cached child nodes are stored in the processor in a decompressed state. This facilitates the processor's use of the decompressed integrity tree node for data integrity verification. Storing the child nodes of the integrity tree in a compressed state in memory saves memory space, reduces memory overhead, and effectively reduces the size of the child nodes. During data reading, in response to a read request for the target data, if the processor has not verified the first child node, it retrieves the compressed first child node from memory, decompresses it, and caches the decompressed first child node in the processor so that the processor can use it to verify the integrity of the target data. Because the compressed first child node has a small data volume, the processor can quickly read it from memory for integrity verification of the target data, thereby reducing the time overhead of data integrity verification and improving the speed of integrity verification.

[0020] In some embodiments, the processor is specifically configured to: when the number of child nodes in the processor reaches a preset value, obtain a second child node to be removed from the processor; and when the second child node to be removed is detected to have been changed, compress the second child node to be removed and replace the second child node in the memory with the compressed second child node.

[0021] In some embodiments, the processor is specifically configured to: pre-compress the second child node to be removed, and if the size of the pre-compressed second child node is greater than the size of the smallest storage unit in the memory, increment the overflow counter of the second child node by a first value, set the value of each sub-counter of the second child node to a second value, and re-compress the reset second child node, wherein the first value is a positive number greater than 0 and the second value is a positive number. For example, the first value is 1 and / or the second value is 0.

[0022] In some embodiments, the processor is specifically configured to: redetermine the message authentication code (MAC) of the second child node while setting the value of each child counter of the second child node to a second value; and write the redetermined MAC into memory.

[0023] In some embodiments, the branching factor of the integrity tree is a preset parameter, which is a positive integer greater than 8 that is a power of 2. For example, the preset parameter is 16 or 32.

[0024] In some embodiments, the processor is specifically configured to: use at least two threads to decompress the first child node in parallel; and / or use at least two threads to compress the second child node to be removed in parallel.

[0025] The beneficial effects of the data processing apparatus provided by the second aspect and the various possible implementations of the second aspect can be seen from the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here.

[0026] Thirdly, embodiments of this application provide a computer storage medium including computer instructions, which, when executed by a computer, cause the computer to implement the data processing method as described in any of the first aspects.

[0027] Fourthly, embodiments of this application provide a computer program product, the program product including a computer program stored in a readable storage medium, at least one processor of a communication device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the communication device to implement any of the data processing methods described in the first aspect.

[0028] The data processing method, apparatus, and storage medium provided in this application, in response to a read request for target data, when the first child node is not verified in the processor, the processor obtains a compressed first child node from memory. This first child node is a child node related to the target data in an integrity tree. The integrity tree includes multiple root nodes and multiple child nodes, wherein the multiple child nodes are stored in memory in a compressed state, and the multiple root nodes are stored in the processor in a decompressed state. Then, the processor decompresses the compressed first child node and caches the decompressed first child node in the processor for integrity verification of the target data. In this application embodiment, by storing the root node of the integrity tree in the processor in a decompressed state, the processor can conveniently use the decompressed root node for data integrity verification. Storing the child nodes of the integrity tree in memory in a compressed state saves memory storage space, reduces memory storage overhead, and effectively reduces the size of the child nodes. This facilitates the processor's rapid reading of compressed child nodes from memory for data integrity verification, thereby reducing the time overhead of integrity verification and improving the speed of integrity verification. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of an integrity tree according to an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the data structure of a counter integrity tree according to an embodiment of this application;

[0031] Figure 3 A schematic diagram of a data structure for a node in an integrity tree;

[0032] Figure 4 This is a schematic diagram illustrating an application scenario according to an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of a system architecture according to an embodiment of this application;

[0034] Figure 6 This is a schematic flowchart of the data processing method provided in the embodiments of this application;

[0035] Figure 7 This is a schematic diagram of the node decompression process involved in the embodiments of this application;

[0036] Figure 8 Another schematic diagram of the data processing method provided in the embodiments of this application;

[0037] Figure 9 This is a schematic diagram of the node compression process involved in an embodiment of this application;

[0038] Figure 10This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0040] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A. In one implementation, B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information. The term "multiple" in this document refers to two or more. The term "and / or" in this document is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In addition, the character " / " in this document generally indicates that the related objects before and after are in an "or" relationship; in formulas, the character " / " indicates that the related objects before and after are in a "division" relationship.

[0041] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention distinguish between identical or similar items that have substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or order of execution, and that "first," "second," etc., do not necessarily imply differences.

[0042] To facilitate understanding of the embodiments of this application, the relevant concepts involved in the embodiments of this application will be briefly introduced as follows:

[0043] Data integrity is one of the three fundamental elements of information security. It refers to ensuring that information or data is not tampered with without authorization or that any tampering can be detected quickly during the transmission, storage, and processing of information or data.

[0044] A replay attack refers to an attacker recording data and MAC values ​​at time point T1, and then replaying the data and MAC values ​​recorded at time point T1 at time point T2, attempting to tamper with the data at time point T2 and change it to the data at time point T1.

[0045] An integrity tree is a data structure used to protect the integrity of storage. It is a tree-like structure composed of multiple integrity tree nodes. Its key feature is its ability to quickly verify the integrity of local data, and it is widely used in scenarios including Bitcoin and Android phone system partitioning.

[0046] The branching factor is the number of child nodes included in each node of an integrity tree. For example, if each node in an integrity tree includes 8 child nodes, then the branching factor of the integrity tree is 8.

[0047] Integrity trees have many variations; below is an introduction to a common type, such as... Figure 1 As shown.

[0048] Figure 1 This is a schematic diagram of a completeness tree structure according to an embodiment of this application. Figure 1 As shown, this integrity tree consists of 4 levels, with each level connected by specific dependencies. The branching factor is 8, meaning each node has 8 child nodes. Figure 1 As shown, n37, n36, ..., n30 are the root nodes, and n20, n21, ..., n27 are the eight child nodes of the root node n33, located in layer 3. n10, n11, ..., n17 are the child nodes of node n20, located in layer 2. n00, n01, ..., n07 are the child nodes of node n10, located in layer 1. v0, v1, ..., v7 are the leaf nodes of child node n01, located in layer 0. The memory's storage area is divided into multiple data blocks, with one leaf node corresponding to one data block, used to maintain the integrity of the data in that block.

[0049] Assumption Figure 1 Each node in the system includes 8 counters and one tag (T for short). Figure 1 The data structure of the integrity tree shown is as follows: Figure 2 As shown. Figure 2 This is a schematic diagram of the data structure of a counter integrity tree according to an embodiment of this application, as shown below. Figure 2As shown, assuming each node's label is a Message Authentication Code (MAC), taking root node n33 as an example, the root counter corresponding to root node n33 is counter 11. Root node n33 includes 8 counters and MAC10. The 8 counters are C0 to C7, and MAC10 is calculated using the MAC function based on root counter 11 and the 8 counters C0 to C7 of root node n33. The 8 counters of root node n33 correspond one-to-one with the 8 child nodes n20 to n27 of root node n33. For example, node n20 corresponds to counter C0 of root node n33, node n21 corresponds to counter C1 of root node n33, and so on, with node n27 corresponding to counter C7 of root node n33. Each child node from n20 to n27 includes eight counters and one MAC. For example, child node n20 includes eight counters C00 to C07 and MAC20, where MAC20 is calculated using the MAC function based on the counter C0 of root node n33 and the eight counters C00 to C07 of child node n20. Similarly, the MAC27 of child node n27 is calculated using the MAC function based on the counter C7 of root node n33 and the eight counters C70 to C77 of child node n27. Similarly, the MAC30 of child node n10 is calculated using the MAC function based on the counter C00 of node n20 and the eight counters C000 to C007 of node n10; the MAC37 of child node n17 is calculated using the MAC function based on the counter C07 of node n20 and the eight counters C070 to C077 of node n17; the MAC40 of child node n00 is calculated using the MAC function based on the counter C000 of node n10 and the eight counters C0000 to C0007 of node n00; and the MAC47 of child node n07 is calculated using the MAC function based on the counter C007 of node n10 and the eight counters C0070 to C0077 of node n07.

[0050] Similarly, for the eight leaf nodes v0 to v7 of child node n00, each leaf node includes eight counters and one MAC. Taking leaf node v0 as an example, leaf node v0 includes eight counters C00000 to C00007 and MAC50. MAC50 is calculated using the MAC function based on the counter C0000 of child node n00 and the eight counters C00000 to C00007 of leaf node v0. The eight counters of leaf node v0 correspond to eight data blocks in memory, and each data block corresponds to one MAC. For example, MAC60 of data block 70 is calculated using the MAC function based on counter C00000 and the data 000 in data block 70, and MAC67 of data block 77 is calculated using the MAC function based on counter C00007 and the data 007 in data block 77.

[0051] Depend on Figure 2 It can be seen that the MAC used to verify the integrity of data in a data block is maintained by its corresponding leaf node, while the MAC used to verify the integrity of a leaf node is maintained by its parent node, and the integrity of the parent node itself can be maintained by other parent nodes in the tree, and so on, until the root node.

[0052] During the data reading process, such as Figure 2As shown, for example, when reading data 000 from data block 70, in order to verify the integrity of data 000 in data block 70, the MAC60 of data block 70 is verified. Specifically, the counter C00000 in leaf node v0 is read, and MAC1 is calculated using the MAC function based on counter C000000 and data 000. The calculated MAC1 is then matched with the MAC60 stored in data block 70. If the stored MAC60 does not match the calculated MAC1, it indicates that data 000 has been tampered with. If the stored MAC60 matches the calculated MAC1, the integrity of leaf node v0 is verified. Specifically, the parent node of leaf node v0 (i.e., node n00) is read. Based on the counter corresponding to leaf node v0 in node n00 (i.e., counter C0000) and the eight counters of leaf node v0, the calculated MAC of leaf node v0 is calculated using the MAC function. The calculated MAC of leaf node v0 is then matched with its stored MAC. If the stored MAC of leaf node v0 does not match its calculated MAC, it indicates that leaf node v0 has been tampered with, and the integrity verification of data 000 fails. If the stored MAC of leaf node v0 matches its calculated MAC, the integrity of the parent node of leaf node v0 (i.e., node n00) is verified. This process continues until the root node n33 is verified. If the stored MAC of root node n33 matches its calculated MAC, it indicates that data 000 has not been tampered with.

[0053] During the data writing process, such as Figure 2 As shown, each time data is written to a data block, the corresponding counter in the integrity tree is incremented or updated. For example, when data is written to data block 70 and the data in data block 70 is updated, the counter C00000 in the leaf node v0 corresponding to data block 70 is incremented, for example, by 1. The increment of the counter C00000 in leaf node v0 will trigger the recalculation of the MAC of leaf node v0. The recalculation of the MAC of leaf node v0 will trigger the increment of the counter (i.e., counter C0000) in the parent node n00 of leaf node v0, and so on, until the MAC of the root node is updated again.

[0054] It should be noted that the above Figure 2 The diagram shows that the MAC address of a data block and its corresponding data are stored in the same cache line. Optionally, the MAC address of a data block and its corresponding data can be stored separately.

[0055] Each node in the integrity tree stores its MAC address and multiple counters in the same cache line to ensure the integrity of that node. Figure 2The diagram shows that the MAC addresses of a node are stored together. Optionally, the MAC addresses of a node can be stored separately, for example... Figure 3 As shown, Figure 3 This is a data structure diagram of a node in an integrity tree. The node's MAC address can be divided into multiple parts for separate storage. For example, the node's MAC address can be divided into 8 equal parts, each corresponding to one of the node's 8 counters, with each counter occupying 56 bits. It should be noted that... Figure 3 The diagram shows a MAC size of 56 bits, divided into 8 equal parts, each 8 bits long. Of these 8 bits, 7 bits are used and 1 bit is unused. Optionally, the MAC size may include, but is not limited to, 56 bits, and the MAC may not be divided into equal parts during partitioning.

[0056] Optional, Figure 2 The MAC function can be a one-way cryptographic function such as AES-GCM or SHA-256.

[0057] Figure 4 This is a schematic diagram of an application scenario involved in an embodiment of this application, such as... Figure 4 As shown, the system includes a processor and memory, where the processor is trusted, and the memory is untrusted. This means that data in the processor cannot be attacked or tampered with by an attacker, while data in the memory can be arbitrarily attacked or tampered with by an attacker. Therefore, to prevent attackers from reading data in the memory, the processor needs to encrypt the data in the memory, making it impossible for attackers to read it. Furthermore, to prevent attackers from performing replay attacks on the data in the memory to tamper with it, the processor needs to perform data integrity verification every time it reads data from the memory.

[0058] like Figure 4 As shown, the processor includes a first cache, an encryption engine, and a second cache. The first cache can be a multi-level cache, such as including L1, L2, and L3 caches. The first cache is used to cache data, for example, data read from memory. The encryption engine is used to encrypt data written to memory and to decrypt data read from memory. The second cache is used to cache the integrity tree nodes last read from memory. The memory includes ciphertext data and the integrity tree.

[0059] During the data reading process, the processor first checks if the target data to be read is cached in the first cache. If the target data is cached in the first cache, it is read directly from the first cache. If the target data is not found in the first cache, it is read from memory. Specifically, the encrypted data of the target data is read from memory, decrypted, and then placed into the first cache.

[0060] To verify the integrity of the target data, the processor queries the second cache for a corresponding integrity tree node. If it exists, the processor uses that integrity tree node to verify the integrity of the target data. If the processor does not find a corresponding integrity tree node in the second cache, it reads the corresponding integrity tree node (e.g., node 1) from memory and uses node 1 to calculate the MAC of the target data. If the calculated MAC matches the stored MAC of the target data, the processor continues to verify the integrity of node 1, and so on, until the corresponding root node is verified.

[0061] As mentioned above, due to the large number of levels in the integrity tree, data integrity verification requires reading integrity tree nodes from registers multiple times. For example, Figure 1 and Figure 2 As shown, verifying the integrity of target data requires verifying the integrity of the corresponding leaf nodes. Verifying the integrity of a leaf node requires verifying the integrity of the nodes in layer 1 corresponding to that leaf node. Verifying the integrity of nodes in layer 1 requires verifying the integrity of the corresponding nodes in layer 2, and so on, with the number of verifications equal to the number of layers in the integrity tree. Each verification requires accessing memory once, resulting in high memory access time overhead and slow verification speed. Furthermore, the integrity tree is stored in memory in a decompressed state, occupying excessive storage space and causing high storage space overhead.

[0062] To address the aforementioned technical problems, this application embodiment stores the integrity tree in a compressed form in memory, effectively saving memory space and reducing memory overhead. During integrity verification, the processor reads the compressed integrity tree from memory. Because the compressed integrity tree has a smaller data volume, the processor's speed in reading the integrity tree from memory is increased, thereby reducing the time overhead of data integrity verification and improving the speed of integrity verification.

[0063] The technical solutions of the embodiments of this application will be described in detail below through some examples. The following embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0064] First, combine Figure 5 The system architecture involved in the embodiments of this application will be described in detail.

[0065] Figure 5 This is a schematic diagram of a system architecture involved in an embodiment of this application, such as... Figure 5As shown, the system architecture includes a processor and memory. The processor is trusted, while the memory is untrusted. This means that data on the processor is difficult for attackers to tamper with; therefore, the edge of the processor can be considered a trust boundary. Any data crossing this trust boundary can be tampered with. For example, data on memory or data via the physical channel between memory and processor can be intercepted or modified. The processor and memory are connected via a bus communication connection, such as a bus communication connection.

[0066] The processor stores the root node of the integrity tree. Optionally, the processor may include one or more registers, and the root node of the integrity tree can be stored in any one of these registers. The root node of the integrity tree exists in the processor in a decompressed state, allowing the processor to quickly read the root node for integrity verification, for example... Figure 1 The integrity tree shown has its root nodes n30 to n37 stored in the processor in a decompressed state, and these nodes are not lost even when power is off. The root node can be used to verify the integrity of its child nodes. For example, root node n33 is used to verify the integrity of its child nodes n20 to n27. Taking the integrity verification of child node n20 as an example, the processor reads the counter and MAC of node n20 from memory. Node n20 corresponds to one of the counters in node n33, for example, counter 1. Based on counter 1 and the counters of node n20, the MAC function is used to calculate the MAC of node n20. This calculated MAC is then matched with the MAC read from memory. If they match, the integrity verification of node n20 is successful; otherwise, the integrity verification of node n20 fails.

[0067] Since the number of root nodes in the integrity tree is relatively small, this embodiment stores the root nodes in the processor in a decompressed state, facilitating rapid reading of the root nodes by the processor for data integrity verification. Furthermore, the processor is trustworthy; storing the root nodes in the processor prevents attackers from reading or tampering with them, thereby ensuring the reliability and accuracy of data integrity verification.

[0068] The processor also includes a first cache, which may include multiple levels of cache, such as L1, L2, and L3. This first cache is used to cache data, for example, data read from memory, where the data in the first cache is data that has passed integrity verification. Thus, during the reading of target data, the processor first queries the first cache. Specifically, the processor queries the L1 cache; if the target data is not found in the L1 cache, it queries the L2 cache; if the target data is not found in the L2 cache, it queries the L3 cache. If the processor finds the target data in the first cache, it directly returns the retrieved target data. If the processor does not find the target data in the first cache, it reads the target data from memory and performs integrity verification on the target data.

[0069] The processor also includes a second cache, which caches child nodes of the integrity tree read from memory. Specifically, the processor reads compressed child nodes of the integrity tree from memory, decompresses them, and caches them in the second cache for data integrity verification. In other words, the second cache contains one or more child nodes of the integrity tree read during the last integrity verification. Therefore, during the current integrity verification, to improve speed, the processor first queries the second cache for the required child node, such as node 1. If node 1 is found in the second cache, it is used directly for integrity verification without needing to read it from memory, thus improving speed. Furthermore, because the processor is trusted, the integrity tree nodes stored in the second cache are secure and cannot be tampered with by attackers. Therefore, there is no need to perform integrity verification on the nodes cached in the second cache again, further improving the speed of integrity verification. Figure 1 and Figure 2As shown, for example, the second cache stores leaf node v00, node n16, and node n22. The processor reads data 000 and its corresponding MAC 60 from data block 70 in memory, and then performs integrity verification on data 000. Based on the correspondence between data blocks and leaf nodes, the processor determines that data block 70 corresponds to leaf node v00. Next, the processor checks if leaf node v00 is cached in the second cache. If leaf node v00 is found in the second cache, it uses the counters C00000 to C00007 of leaf node v00 and the read data 000 to calculate the MAC corresponding to data 000 using the MAC function, denoted as MAC6. The processor matches the calculated MAC6 with the MAC60 read from memory. If MAC6 matches MAC60, it means that data 000 has not been tampered with, the integrity verification is successful, and there is no need to perform integrity verification on leaf node v00 again. If the processor does not find the leaf node v00 in the second cache, the processor reads the leaf node v00 from memory. According to the above method, it checks whether the calculated MAC6 matches the MAC60 read from memory. If they match, it reads the parent node of the leaf node v00 from memory to verify the integrity of the leaf node v00. This process continues until the root node is reached.

[0070] The processor also includes a memory encryption engine (MEE), which encrypts plaintext based on a counter and decrypts ciphertext read from memory. This prevents malicious observers from reading data from memory. The encryption keys used for encryption and decryption can be stored in the processor, for example, in a register within the processor. This application does not limit the encryption or decryption methods used by the encryption engine.

[0071] The processor also includes a compression algorithm, which is used to compress the integrity tree nodes and store the compressed integrity tree nodes in memory. Correspondingly, after reading the compressed integrity tree nodes from memory, the processor uses the same compression algorithm to decompress them and caches the decompressed integrity tree nodes in a second cache.

[0072] The memory includes ciphertext data, where the ciphertext data is data that has been encrypted by an encryption engine. For example, the processor controls the encryption engine to encrypt plaintext data to obtain ciphertext data, which is then stored in the memory. An attacker cannot decrypt this ciphertext data, thus preventing malicious observers from reading the data in the memory.

[0073] The memory also includes plaintext data, which is data that has not been encrypted and can be read arbitrarily by an attacker.

[0074] The memory also includes all nodes in the integrity tree except the root node. For ease of understanding, these nodes are collectively referred to as child nodes. In memory, child nodes in the integrity tree are stored in a compressed state. This reduces the size of the integrity tree, saves memory space, and allows the processor to quickly read the compressed child nodes for integrity verification, thereby saving time overhead and improving the speed of integrity verification.

[0075] The processor in this application embodiment can be a single processor element or a collective term for multiple processor elements. For example, the processor can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0076] The memory in this application embodiment can be RAM, any available medium accessible to a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks (SSDs)).

[0077] In the above Figure 5 Based on the system structure shown, combined with Figure 6 The data processing method provided in the embodiments of this application will be described in detail.

[0078] Figure 6 This is a schematic diagram of the data processing method provided in the embodiments of this application, such as... Figure 6 As shown, the method in this application embodiment includes:

[0079] S101. In response to a read request for target data, if the first child node is not detected in the processor, obtain the compressed first child node from the memory.

[0080] Here, the first child node is the child node in the integrity tree that is related to the target data. Optionally, the first child node can be the leaf node corresponding to the target data, for example... Figure 2 As shown, assuming the target data is data 000, which is stored in data block 70, and data block 70 corresponds to the leaf node v0 in the integrity tree, the first child node corresponding to data 000 can be the leaf node v0. Optionally, the first child node can also be the parent node of the leaf node corresponding to the target data. (Continue referring to...) Figure 2 As shown, assuming the target data is data 000, the leaf node corresponding to data 000 is node v0, and the parent node corresponding to leaf node v0 is node n00. Therefore, the first child node corresponding to data 000 can also be node n00. Optionally, the first child node corresponding to the target data can also be the parent node of the parent node of the leaf node corresponding to the target data. (Continue referring to...) Figure 2 Assuming the target data is data 000, the parent node of the leaf node corresponding to data 000 is node n00, and the parent node corresponding to node n00 is n10. Therefore, the first child node corresponding to the target data can also be node n10, and so on. That is to say, the first child node described in this application embodiment is any child node in the integrity tree involved in the target data integrity verification process, wherein the child nodes of the integrity tree are nodes other than the root node in the integrity tree.

[0081] A complete tree consists of multiple root nodes and multiple child nodes, such as Figure 1 The integrity tree shown includes eight root nodes (n30 to n37) and four levels of child nodes. Each root node has eight child nodes; therefore, level 3 has 64 child nodes, level 2 has 512 child nodes, level 1 has 4096 child nodes, and level 0 has 32768 leaf nodes. It should be noted that the integrity tree in this embodiment includes, but is not limited to, […]. Figure 1 As shown, the branching factor of the integrity tree involved in the embodiments of this application includes, but is not limited to, 8, the number of layers of the integrity tree includes, but is not limited to, 5, and the number of bits occupied by each node can be the same or different.

[0082] In some embodiments, the branching factor of the integrity tree in this application is a preset parameter, which is a positive integer greater than 8 among powers of 2. Assume the preset parameter is b, and preset parameter b satisfies the following formula (1).

[0083] b>2 n n = 4, 5, 6, 7...... (1)

[0084] Where n is a positive integer greater than or equal to 4, that is, the branching factor of the integrity tree in this application embodiment is a positive integer greater than 8 among the exponents of 2, such as 16, 32, 64, etc.

[0085] Currently, the common branching factor for integrity trees is 8. However, this embodiment uses a branching factor greater than 8, such as 16 or 32. This reduces the number of levels in the integrity tree, decreasing the number of times the processor accesses the integrity tree and thus improving the speed of data integrity verification. For example, considering an integrity tree maintaining 16GB of storage space, a current integrity tree with a numerator factor of 8 generates a tree with 12 levels (log8(16,000,000,000)). During integrity verification, this requires 12 accesses to the memory, resulting in high time overhead and slow verification speed. In this embodiment, the integrity tree has a numerator factor greater than 8, such as 32. When this integrity tree with a numerator factor of 32 maintains 16GB of storage space, its number of levels is log32(16,000,000,000) = 7. During integrity verification, only 7 accesses to the memory are needed, effectively reducing the number of times the processor accesses the integrity tree, thereby reducing the high time overhead of integrity verification and improving its speed.

[0086] In some embodiments, the processor may determine the branching factor of the integrity tree based on the size of the memory and / or the processor's access patterns to the memory. For example, if the memory space is small or the processor's access to the memory space is uneven, the processor may choose a smaller branching factor for the integrity tree, such as 16. Conversely, if the memory space is large and the processor's access to the memory space is relatively even, the processor may choose a larger branching factor for the integrity tree, such as 32 or 54.

[0087] In this embodiment, the root node of the integrity tree is stored in the processor in a decompressed state to ensure its security and prevent attackers from tampering with it. If the root node is tampered with, the integrity tree cannot perform data integrity verification. Simultaneously, storing the root node in a decompressed state in the processor facilitates rapid reading of the root node by the MEE for integrity verification, thereby improving the speed of integrity verification. Since the processor's storage space is limited and cannot store the entire integrity tree, the child nodes of the integrity tree, excluding the root node, are stored in memory.

[0088] To conserve memory space and improve the speed of integrity verification, this embodiment stores multiple child nodes of the integrity tree in a compressed form in memory. Specifically, as the above analysis shows, during data integrity verification, the processor reads child nodes of the integrity tree multiple times from memory. This embodiment stores the child nodes of the integrity tree in a compressed form, effectively reducing the size of the child nodes. This allows the processor to quickly read the compressed child nodes for integrity verification, thereby reducing the time overhead of integrity verification and improving its speed.

[0089] The compression process of child nodes of the integrity tree involved in the embodiments of this application will be described below through specific examples.

[0090] Assuming the branching factor of the integrity tree is 16, meaning each node includes 16 child nodes, each node includes one overflow counter, 16 sub-counters, and a MAC (Macro-Controlled Array). Each sub-counter occupies 40 bits, and both the MAC and overflow counter occupy 56 bits. The size of each node is 56 bits × 2 + 40 bits × 16 = 752 bits. Since each node has the same size, its compression method is the same. For ease of explanation, this application uses one node as an example, such as node 1, to describe the node compression process; other nodes can be referred to accordingly.

[0091] The data structure of node 1 is shown in Table 1:

[0092] Table 1

[0093]

[0094] As shown in Table 1, a node contains one overflow counter and 16 sub-counters. The overflow counter occupies 56 bits, indicating that the overflow counter can represent a value from 0 to 2. 56 For integers -1, a sub-counter occupies 40 bits, meaning a sub-counter can represent a value from 0 to 2. 40 The integer -1. Using 40 bits to represent 0, its actual storage value is: 0000000000000000000 0000000000 0000000000. Using 40 bits to represent 1, its actual storage value is: 00000000000000000000 00000000000 0000000001. However, since most sub-counter values ​​are relatively small, there are a large number of 0s, wasting storage space. Furthermore, because the 40-bit node length is relatively long, it takes time for the processor to read the node from memory, affecting the efficiency of data integrity verification.

[0095] To address the aforementioned technical problems, embodiments of this application compress node 1 shown in Table 1. The methods for compressing node 1 include, but are not limited to, the following:

[0096] Method 1: Use equal-length compression to compress node 1 shown in Table 1, that is, compress the length of each sub-counter in node 1 from 40 bits to a first preset value, which is any even number less than 40 bits and greater than 0.

[0097] For example, assuming the first preset value is 16 bits, the decimal value of sub-counter 1, A1, is 1, corresponding to a 40-bit binary value of: 0000000000 0000000000 0000000000 0000000001. Compressing the value of sub-counter 1, A1, from 40 bits to 16 bits gives A1 a 16-bit binary value of: 000000 0000000001. Similarly, assuming the decimal value of sub-counter 2, A2, is 555, corresponding to a 40-bit binary value of: 00000000000 0000000000000000000 0000110111. Compressing the value of sub-counter 2, A2, from 40 bits to 16 bits gives A2 a 16-bit binary value of: 000000 0000110111. Similarly, the sub-counters of node 1 in Table 1 can be compressed from 40 bits to 16 bits, as shown in Table 2:

[0098] Table 2

[0099]

[0100] As shown in Table 2, the size of node 1 after compression is 56 bits × 2 + 16 bits × 16 = 368 bits. Compared with the original 752 bits, the data volume of node 1 is effectively reduced. When the smaller data volume of node 1 is stored in memory, the storage space of memory can be saved, and the processor can quickly read the compressed node 1, thereby improving the speed of data integrity verification and saving the time overhead of integrity verification.

[0101] As shown in Table 2, when compressing node 1, the sub-counters of node 1 are compressed, but the MAC and overflow counter of node 1 are not compressed. This can prevent the MAC or overflow counter of node 1 from overflowing.

[0102] In some examples, to further compress node 1, the MAC and / or overflow counter of node 1 are compressed, that is, the value of the MAC and / or overflow counter of node 1 is compressed from 56 bits to 16 bits, as shown in Table 3:

[0103] Table 3

[0104]

[0105] As shown in Table 3, compressing the MAC and overflow counter of node 1 from 56 bits to 16 bits further reduces the amount of data in node 1. This improves the processor's read speed when reading the compressed node 1 from memory, thereby further improving the speed of data integrity verification.

[0106] Because processors read data from memory in units of the smallest storage unit, the size of a child node in a complete tree stored in memory cannot exceed this unit. For example, when the memory is RAM, the smallest storage unit is a cache line, typically 512 bits or 64 bytes. Therefore, when storing a compressed second child node in RAM, its size cannot exceed 512 bits or 64 bytes. Similarly, when the memory is a hard disk, the smallest storage unit is a sector or block, typically 4096 bytes. This means that when storing a compressed second child node on the hard disk, its size cannot exceed 4096 bytes.

[0107] In some embodiments, if node 1 cannot be compressed to the smallest storage unit of the memory, the overflow counter value B1 of node 1 can be increased by a first preset value to become B2. For example, if the first preset value is 1, then B2 = B1 + 1. Simultaneously, the values ​​of each sub-counter of node 1 are set to a second value, for example, 0. In this case, the data structure of the compressed node 1 is shown in Table 4:

[0108] Table 4

[0109]

[0110] In Table 4, C is the second value, and D2 is the recalculated MAC value of node 1. Specifically, based on the value of the counter of the parent node corresponding to node 1, and the value of the overflow counter B2 and the values ​​of child counters 1 to 16 C in Table 4, the MAC function is used to recalculate the MAC value D2 of node 1.

[0111] It should be noted that the aforementioned first preset value can be specified by the user or determined by the processor. The processor can determine the first preset value in ways including but not limited to the following examples:

[0112] Example 1: The processor determines the size of the first preset value based on the size of the smallest storage unit in the memory and the data structure of the decompressed child nodes. For example, taking main memory as an example, the smallest storage unit in main memory is a cache line, and the size of a cache line is 512 bits or 64 bytes. The size of a child node stored in the memory cannot exceed the size of one cache line. Taking node 1 as an example from Table 1 above, node 1 includes one overflow counter, 16 sub-counters, and a MAC. Both the MAC and the overflow counter occupy 56 bits. If the MAC and overflow counter of node 1 are not compressed, they each still occupy 56 bits in one cache line. Thus, the remaining 400 bits in one cache line are distributed among the 16 sub-counters, thereby determining that the first preset value cannot exceed 25 bits. If the MAC and overflow counter of node 1 are also compressed, the 512 bits are divided into 18 equal parts, each occupying 28 bits. Therefore, the first preset value cannot exceed 28 bits.

[0113] Example 2: The processor determines the size of the first preset value based on the values ​​of a preset number of sub-counters in the child node. For example, assuming the preset number is 80%, taking node 1 as shown in Table 1, if 80% of the 16 sub-counters in node 1 have values ​​less than the decimal number 100, which can be represented using 7 bits, then the first preset value can be determined to be greater than or equal to 7 bits and less than 28 bits.

[0114] It should be noted that the first preset value can also be determined in other ways according to the embodiments of this application, and the specific method of determining the first preset value is not limited in the embodiments of this application.

[0115] As shown in the first method, the child nodes of the integrity tree are compressed to a first preset value using an equal-length compression method. The data volume of the compressed child nodes is significantly reduced. Then, the compressed child nodes are stored in the memory.

[0116] After the processor reads the compressed child nodes from memory, it decompresses them. Specifically, the length of the compressed child nodes is decompressed back to its original length. Taking node 1 as an example, the processor decompresses the compressed node 1 shown in Tables 2 to 4 into the decompressed state shown in Table 1. Specifically, the length of each counter in the compressed node 1 shown in Tables 2 to 4 is decompressed from 16 bits to 40 bits.

[0117] In Method 1 above, equal-length compression is used to compress each child node of the integrity tree. This method is simple, fast, and easy to operate.

[0118] Method 2 uses variable-length compression to compress node 1 shown in Table 1. Specifically, based on the value of each sub-counter in node 1, each sub-counter in node 1 is compressed from 40 bits to different lengths.

[0119] It should be noted that the process of compressing node 1 by the processor using variable length compression combined with preamble algorithm is described in this application embodiment. In addition to using preamble compression algorithm, Huffman coding, LZ algorithm, arithmetic coding and other compression algorithms can also be used in this application embodiment.

[0120] Assuming that the embodiments of this application can compress the counter to four different compression lengths, namely 16 bits, 24 bits, 32 bits, and 40 bits, and use 2 bits to identify these four different compression lengths, the correspondence between these four compression lengths and their respective identifiers is shown in Table 5. Here, 16 bits can represent a number from 0 to 2. 16 -1 is an integer when the counter value is between 0 and 2. 16 When the value is -1, the counter can be compressed from 40 bits to 16 bits. 24 bits can represent a number from 0 to 2. 24 -1 is an integer when the counter value is between 0 and 2. 24 When the value is -1, the counter can be compressed from 40 bits to 24 bits. 32 bits can represent a number from 0 to 2. 32 -1 is an integer when the counter value is between 0 and 2. 32 When the value is -1, the counter can be compressed from 40 bits to 32 bits. 32 bits can represent a number from 0 to 2. 32 -1 is an integer when the counter value is between 0 and 2. 32 When the value is -1, the counter can be compressed from 40 bits to 32 bits. Therefore, when the counter value is less than or equal to 2... 16 When the value is an integer less than or equal to -1, the counter can be compressed from 40 bits to 16 bits, 24 bits, or 32 bits, depending on the actual needs. For example, to achieve the maximum compression effect, the counter can be compressed from 40 bits to 16 bits; to minimize the overflow probability of the counter, it can be compressed from 40 bits to 32 bits. This application does not impose any limitations on this. Similarly, when the value of the counter is greater than 2... 16 -1 and less than or equal to 2 24 When the value is an integer less than or equal to -1, the counter can be compressed from 40 bits to 24 bits or 32 bits. When the value of the counter is greater than 2... 24 -1 and less than or equal to 2 32 When the integer is -1, the counter can be compressed from 40 bits to 32 bits.

[0121] Table 5

[0122]

[0123] It should be noted that Table 5 is an example showing four compression lengths involved in the embodiments of this application. The compression lengths involved in the embodiments of this application include, but are not limited to, those shown in Table 5.

[0124] Thus, using the compression lengths shown in Table 5, each sub-counter in node 1 is compressed from 40 bits to different lengths. For example, the decimal value of sub-counter 1, A1, is 1, and its corresponding 40-bit binary value is: 00000000000000000000 0000000000 000000001. Compressing the value of sub-counter 1, A1, from 40 bits to 16 bits, the corresponding binary value of A1 is: 00 000000 0000000001, where the highest bit 00 is used to indicate that the length of the compressed sub-counter 1 is 16 bits. Assuming the decimal value of sub-counter 2, A2, is 555, its corresponding 40-bit binary value is: 00000000000 0000000000 0000000000 0000110111. Compressing the value of sub-counter 2, A2, from 40 bits to 16 bits, the corresponding binary value of A2 is: 00 000000 0000110111, where the highest bit 00 is used to indicate that the length of the compressed sub-counter 2 is 16 bits. Assuming the decimal value A3 of sub-counter 3 is 333,333, its corresponding 40-bit binary value is: 0000000000 0000000000 0101000101 1000010101. Compressing the value A3 from 40 bits to 32 bits gives A3 the binary value: 10 0000000000 0101000101 1000010101, where the highest bit 10 indicates that the compressed sub-counter 3 has a length of 32 bits. Similarly, the sub-counters of node 1 shown in Table 1 can be compressed from 40 bits to different lengths, as shown in Table 6.

[0125] Table 6

[0126]

[0127] The compressed node 1 is less than 752 bits in size, which effectively reduces the amount of data in node 1. When storing the smaller node 1 in memory, it can save memory space and facilitate the processor to quickly read the compressed node 1, thereby improving the speed of data integrity verification and saving the time overhead of integrity verification.

[0128] As shown in Table 6, when compressing node 1, the sub-counters of node 1 are compressed, but the MAC and overflow counter of node 1 are not compressed. This can prevent the MAC or overflow counter of node 1 from overflowing.

[0129] In some examples, to further compress node 1, the MAC and / or overflow counter of node 1 are compressed, that is, the MAC and / or overflow counter of node 1 are compressed from 56 bits to a certain length shown in Table 5, for example, the MAC and overflow counter of node 1 are compressed from 56 bits to 32 bits, as shown in Table 7:

[0130] Table 7

[0131]

[0132] As shown in Table 7, the MAC and overflow counter of node 1 are compressed from 56 bits to 32 bits, further reducing the amount of data in node 1. This further improves the processor's read speed when reading the compressed node 1 from memory, thereby further improving the speed of data integrity verification.

[0133] In some embodiments, if node 1 cannot be compressed to the smallest storage unit of the memory, the overflow counter value of node 1 is incremented by a first value, and the values ​​of all other sub-counters are set to a second value. For example, the overflow counter value B1 of node 1 is incremented by a first preset value, becoming B2. For example, if the first preset value is 1, then B2 = B1 + 1. Simultaneously, the values ​​of all sub-counters of node 1 are set to the second value, for example, 0. In this case, the data structure of the compressed node 1 is shown in Table 8:

[0134] Table 8

[0135]

[0136] In Table 8, C is the second value, and D3 is the recalculated MAC value of node 1. Specifically, based on the value of the counter of the parent node corresponding to node 1, and the value of the overflow counter B2 and the values ​​of child counters 1 to 16 C in Table 8, the MAC function is used to recalculate the MAC value D3 of node 1.

[0137] Method 2 shows that variable-length compression is used to compress each child node of the integrity tree. The data size of the compressed child nodes is significantly reduced. Then, the compressed child nodes are stored in memory.

[0138] After the processor reads the compressed child nodes from the memory, it decompresses the compressed child nodes. Specifically, it decompresses the length of the compressed nodes to the length before compression. For example, it decompresses the length of each counter in node 1 shown in Tables 6 to 8 to the length shown in Table 1.

[0139] In the second method described above, a variable-length compression method is used, which selects an appropriate compression length based on the value of the counter in the node, resulting in high compression flexibility.

[0140] It should be noted that, in addition to the above-mentioned methods one and two, other existing compression methods may also be used when compressing the child nodes of the integrity tree in this embodiment of the application. This embodiment of the application does not limit this.

[0141] In this embodiment of the application, the child nodes of the integrity tree are compressed and stored in the memory, which not only saves the storage space of the memory, but also increases the speed at which the processor reads the compressed child nodes, thereby improving the efficiency of integrity verification.

[0142] During the data reading process, combined with Figure 5 In response to a read request for target data, the processor first queries the first cache, which may include multiple levels of cache: L1, L2, and L3. The processor queries the L1 cache; if the target data is not found in L1, it queries the L2 cache; if not found in L2, it queries the L3 cache. If the target data is still not found in L3, the processor reads the target data from memory.

[0143] From the above Figure 5 As can be seen, to improve the speed of integrity verification, the processor caches the child nodes previously used for integrity verification in the second cache, which can be reused. Therefore, after reading the target data from memory, the processor can query the first child node corresponding to the target data from the second cache to verify the integrity of the target data. Specifically, the processor queries the second cache for the first child node corresponding to the target data. If the first child node is found in the second cache, it is used to verify the integrity of the target data, and the integrity verification process ends. If the first child node is not found in the processor, the processor reads the compressed first child node from memory.

[0144] S102. Decompress the first child node in the compressed state and cache the decompressed first child node in the processor.

[0145] This first child node is used for integrity verification of the target data.

[0146] Specifically, after the processor reads the compressed first child node from memory, it decompresses the compressed first child node. For example, the processor uses... Figure 5 The compression algorithm shown decompresses the first child node and caches the decompressed first child node in the processor, for example, caching the decompressed first child node in the second cache for integrity verification of the target data.

[0147] The integrity verification process involved in the embodiments of this application will be further described below with specific examples:

[0148] Assuming the integrity tree involved in the embodiments of this application is as follows: Figure 1 As shown, the data structure of each node is as follows: Figure 2 As shown, assuming the target data is data 000, the second cache contains leaf node v1, node n00, and node n20. In response to a read request for the target data, the processor first... Figure 5 The processor checks if the target data (i.e., data 000) is cached in the first cache. If data 000 is not found in the first cache, the processor reads the encrypted data of data 000 from memory. The encrypted data of data 000 is encrypted. The encryption engine decrypts the encrypted data of data 000 to obtain the decrypted data 000 and its corresponding MAC address, which is recorded as the stored MAC address of data 000. Since the memory is untrusted, an attacker may tamper with the encrypted data of data 000 in memory; therefore, the integrity of the read data 000 also needs to be verified.

[0149] It should be noted that the processor stores the correspondence between nodes in the integrity tree, as well as the correspondence between leaf nodes of the integrity tree and data blocks in memory. Alternatively, the processor obtains the correspondence between nodes in the integrity tree and the correspondence between leaf nodes of the integrity tree and data blocks in memory from memory. Therefore, when performing integrity verification on data 000, the processor determines the leaf node v0 corresponding to data 000 based on the correspondence between leaf nodes of the integrity tree and data blocks in memory. Next, the processor checks whether leaf node v0 is cached in the second cache. If leaf node v0 is not cached in the second cache, the processor reads the compressed leaf node v0 from memory and decompresses it using a compression algorithm. For example, the data structure of the compressed leaf node v0 is shown in Table 2. The decompressed leaf node v0 shown in Table 2 is decompressed, and the data structure of the decompressed leaf node v0 is shown in Table 1. The decompressed leaf node v0 is then cached in the second cache. Assuming data 000 corresponds to sub-counter 1 in leaf node v0, the processor calculates the MAC corresponding to data 000 using the MAC function based on the value of sub-counter 1 and data 000, and records this MAC as the calculated MAC of data 000. This calculated MAC is then matched with the stored MAC of data 000. If the calculated MAC and the stored MAC of data 000 do not match, it indicates that data 000 has been tampered with, and the integrity verification fails.

[0150] If the calculated MAC of data 000 matches the stored MAC of data 000, the integrity of leaf node v0 still needs to be verified since it is stored in untrusted memory. The processor determines that the parent node of leaf node v0 is node n00 based on the correspondence between nodes in the integrity tree. The processor retrieves node n00 from the second cache and uses node n00 to verify the integrity of leaf node v0. Specifically, leaf node v0 corresponds to child counter 1 in node n00. Based on the value of child counter 1 in node n00 and the values ​​of each counter in leaf node v0, the processor uses the MAC function to calculate the MAC corresponding to leaf node v0 and records this MAC as the calculated MAC of leaf node v0. This calculated MAC of leaf node v0 is then matched with the stored MAC of leaf node v0, where the stored MAC is the MAC read by the processor from memory. If the calculated MAC of leaf node v0 does not match the stored MAC of leaf node v0, it indicates that leaf node v0 has been tampered with, and the integrity verification of data 000 fails. If the calculated MAC of leaf node v0 matches the stored MAC of leaf node v0, it means that leaf node v0 has not been tampered with, and the integrity verification of data 000 is successful.

[0151] Optionally, to improve the decompression speed of the first child node in the compressed state, embodiments of this application may employ at least two threads to decompress the first child node in parallel. For example, assuming the first child node is as shown in Table 7, it includes 16 sub-counters, each with a size of 512 bits, as shown in Table 7. Figure 7 As shown, the processor uses two threads to decompress the first child node from both ends, which can improve the decompression speed, reduce the time overhead of the processor decompressing the first child node, and ensure the speed of integrity verification.

[0152] The data processing method provided in this application, in response to a read request for target data, when the first child node is not verified in the processor, obtains the compressed first child node from memory. This first child node is a child node related to the target data in an integrity tree. The integrity tree includes multiple root nodes and multiple child nodes, wherein the child nodes are stored in memory in a compressed state, and the root nodes are stored in the processor in a decompressed state. Then, the processor decompresses the compressed first child node and caches the decompressed first child node in the processor for target data integrity verification. In this application embodiment, by storing the root node of the integrity tree in the processor in a decompressed state, the processor can conveniently use the decompressed root node for data integrity verification. Storing the child nodes of the integrity tree in memory in a compressed state saves memory storage space, reduces memory storage overhead, and effectively reduces the size of the child nodes. This facilitates the processor's rapid reading of the compressed child nodes from memory for data integrity verification, thereby reducing the time overhead of integrity verification and improving the speed of integrity verification.

[0153] As described in the above embodiments, to improve the speed of integrity verification, the processor can cache the child nodes of the integrity tree previously read from memory in the processor, for example, in the processor's second cache. During integrity verification, the processor can directly read the corresponding child nodes from the second cache, thereby improving the integrity verification speed. However, the processor's storage space is limited. When the number of cached child nodes in the processor reaches a preset value, the cached child nodes need to be removed. Specifically, as... Figure 8 As shown, the method in this application embodiment further includes:

[0154] S201. When the number of child nodes in the processor reaches a preset value, obtain the second child node to be removed from the processor.

[0155] The above preset value is a positive integer greater than or equal to 1. This application embodiment does not limit the specific range of the above preset value, but determines it according to the actual situation, such as 3, 4, 5, etc., which are positive integers greater than or equal to 1.

[0156] Optionally, the above preset values ​​can be configured by the user through a configuration file.

[0157] Optionally, the above preset values ​​can also be determined by the processor based on the size of the cache space, such as the size of the second cache space, and the size of each child node of the integrity tree in the decompressed state. For example, assuming the size of the second cache space is 2500 bits, and the data structure of the child nodes of the integrity tree in the decompressed state is shown in Table 1, with a size of 752 bits, then the second cache can cache a maximum of 3 child nodes, i.e., the preset value does not exceed 3.

[0158] When the processor detects that the number of child nodes cached in the second cache has reached a preset value, it obtains the second child nodes to be evicted from the second cache. The processor obtains the second child nodes to be evicted in the following ways, including but not limited to:

[0159] Method 1: The processor randomly selects one or more child nodes from the multiple child nodes cached in the second cache as the second child node to be removed.

[0160] Method 2: The processor uses all child nodes cached in the second cache as the second child nodes to be removed.

[0161] Method 3: The processor selects the child node with the longest cache time among the multiple child nodes cached in the second cache as the second child node to be removed.

[0162] Method 4: When the processor reads a child node from the second cache for integrity verification, it records the number of reads for each child node. In this way, the processor can determine the child node with the fewest reads among all the child nodes cached in the second cache as the second child node to be removed.

[0163] S202. When it is verified that the second child node to be removed has been changed, the second child node to be removed is compressed, and the compressed second child node is used to replace the second child node in the memory.

[0164] In some cases, child nodes cached in the second cache may be modified, for example, the value of one or more counters of a child node may change, making the child node inconsistent with the child node stored in memory. In this case, if the modified child node is directly removed from the processor and the original, unchanged child node in memory is used for integrity verification, it will cause inaccurate integrity verification.

[0165] To address this technical problem, in this embodiment, the processor needs to verify whether the second child node to be removed has been altered before removing it. If the second child node to be removed has been altered, the processor compresses the second child node and replaces the original second child node in the memory with the compressed second child node, ensuring the timeliness of the child nodes of the integrity tree stored in the memory, thereby ensuring the reliability of data integrity verification.

[0166] In one example, the processor detects a change to the second child node by storing the original value of each sub-counter in the second child node in memory. Therefore, the processor can compare the current value of each sub-counter in the second child node with its original value, and when a change is detected in one or more sub-counters, it indicates that the second child node has been changed.

[0167] In another example, the processor can detect a change to the second child node by storing the original MAC value of the second child node in memory. Since the MAC value of the second child node needs to be re-determined when one or more counters in the second child node change, the processor can compare the current MAC value of the second child node with the original MAC value. If the current MAC value of the second child node is inconsistent with the original MAC value, it indicates that the second child node has been changed.

[0168] In this embodiment of the application, the processor can compress the second child node to be removed in the manner described in S101 above, that is, by using the equal-length compression method. The compression process can be referred to the description of the first method above, and will not be repeated here.

[0169] Optionally, the processor can also compress the second child node to be removed using method two in S101 above, i.e., variable-length compression. The following description, using a preamble algorithm, illustrates the process of the processor compressing the second child node using variable-length compression. It should be noted that, in addition to preamble compression, this embodiment can also employ compression algorithms such as Huffman coding, LZ algorithm, and arithmetic coding.

[0170] Assuming the branching factor of the integrity tree is 32, the data structure of the second child node is shown in Table 9. The second child node includes: 1 overflow counter and 32 sub-counters, as well as a MAC. Each sub-counter occupies 24 bits, and the MAC and overflow counter each occupy 56 bits. The size of the second child node is 56 bits × 2 + 24 bits × 32 = 880 bits.

[0171] Table 9

[0172]

[0173] As shown in Table 9, the overflow counter of the second child node occupies 56 bits, indicating that the overflow counter can represent a value from 0 to 2. 56 For integers -1, a sub-counter occupies 24 bits, meaning a sub-counter can represent a value from 0 to 2. 24 An integer of -1.

[0174] Example 1: Suppose that the variable-length compression method used in this application uses compression lengths of 8 bits, 16 bits, and 24 bits, respectively. Two bits are used to identify these different compression lengths. The correspondence between the three different compression lengths and their respective identifiers is shown in Table 10.

[0175] Table 10

[0176]

[0177] Using the three compression lengths shown in Table 10, the 24-bit sub-counters in the second child node shown in Table 9 are compressed. The lengths of the sub-counter values ​​before and after compression in Table 9 are shown in Table 11.

[0178] Table 11

[0179]

[0180]

[0181] In Table 11, the highest 2 bits of the variable-length binary are used to identify the length of the compressed sub-counter. For example, 00 indicates that the length of the compressed sub-counter is 8 bits, and 11 indicates that the length of the compressed sub-counter is 24 bits.

[0182] Using the three compression lengths shown in Table 10, the second child node shown in Table 9 is compressed, and the resulting compressed data structure of the second child node is shown in Table 12.

[0183] Table 12

[0184]

[0185] In the second child node shown in Table 12, the maximum length of the sub-counter is 24 bits. Therefore, the length of the compressed second child node shown in Table 12 is smaller than the length of the decompressed second child node shown in Table 9. Storing the compressed second child node shown in Table 12 in memory can save memory storage space.

[0186] As can be seen from the description of the above embodiments, when the processor reads data from the memory, it uses the smallest storage unit of the memory as the reading unit. Therefore, the size of the child nodes of the integrity tree stored in the memory cannot be greater than the smallest storage unit of the memory.

[0187] However, in some embodiments, when the second child node cannot be compressed to the smallest storage unit of the memory, the process of compressing the second child node to be removed in S202 above further includes steps A1 and A2:

[0188] Step A1: Pre-compress the second child node to be removed;

[0189] In step A2, if the size of the pre-compressed second child node is greater than the size of the smallest storage unit of the memory, the processor adds a first value to the overflow counter of the second child node, sets the value of each sub-counter of the second child node to a second value, and recompresses the reset second child node.

[0190] The first value is a positive number greater than 0, and the second value is a positive number.

[0191] Specifically, as shown in Table 10 above, the value of sub-counter 2 is 12345678. Before pre-compression, it is 24 bits, and after pre-compression, it is 26 bits. That is, the pre-compressed data is longer because of the addition of 2 flag bits. Thus, when there are multiple sub-counter 2 values ​​greater than or equal to 12345678 in the second child node, the compressed second child node will be larger than the smallest storage unit of the memory, for example, greater than 512 bits.

[0192] To address this technical problem, in this embodiment, when the processor detects that the size of the pre-compressed second child node is greater than the size of the smallest storage unit of the memory, the processor increments the overflow counter value of the second child node by a first value and sets the value of each sub-counter of the second child node to a second value. Assuming the first value is 1 and the second value is 0, the data structure of the reset second child node shown in Table 9 is as shown in Table 13.

[0193] Table 13

[0194]

[0195] The values ​​of all sub-counters of the second sub-node shown in Table 13 are 0, indicating that the compression speed of this second sub-node is fast.

[0196] Next, using the different compression lengths shown in Table 10, the second child node shown in Table 13 is compressed, and the compressed second child node is shown in Table 14:

[0197] Table 14

[0198]

[0199] As shown in Table 14 above, when the value of each sub-counter of the second child node is set to the second value, such as 0, the MAC value corresponding to the second child node changes. At this time, the processor re-determines the MAC value of the second child node based on the values ​​of each counter shown in Table 14. Specifically, based on the counter value of the parent node corresponding to the second child node, and the overflow counter value 5001 and the values ​​of sub-counters 1 to 32 of the second child node in Table 14 (which are 0), the MAC function is used to recalculate the MAC value of the second child node, for example, D. The re-determined MAC value of the second child node is then written into memory along with the compressed state of the second child node shown in Table 14.

[0200] In some embodiments, to improve the compression speed of the second child node, at least two threads can be used to compress the second child node. For example... Figure 9 As shown, assuming the size of the decompressed second child node is 880 bits, including 32 word counters, two threads can be used to compress the second child node from both ends, thereby improving the compression speed of the second child node.

[0201] S203, Remove the second child node from the processor.

[0202] According to the method in S202 described above, when the processor determines that the second child node has been changed, it compresses the changed second child node and writes it into memory, replacing the original second child node stored in memory. Then, the processor removes the changed second child node from the processor to free up processor storage space for storing the child node that has been read from memory again.

[0203] In this embodiment, when the number of child nodes in the integrity tree cached in the processor reaches a preset value, a second child node to be removed is determined from these cached child nodes. It is then checked whether the second child node to be removed has been changed. If the second child node to be removed has not been changed, it is removed from the processor. If a change is detected, the second child node is compressed, and the compressed second child node replaces the second child node in memory. Finally, the second child node is removed from the processor. This process releases the processor's storage space while ensuring the timeliness of the child nodes of the integrity tree stored in memory, thereby guaranteeing the reliability of data integrity detection.

[0204] Figure 10 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. See also... Figure 10 The data processing device 100 includes a processor 120 and a memory 110. The memory 110 is configured to store data; the processor 120 is configured to read and write access to the data stored in the memory 110.

[0205] The processor 120 is specifically configured to: in response to a read request for target data, when no first child node is detected in the processor 120, obtain a compressed first child node from the memory 110. The first child node is a child node related to the target data in the integrity tree. The integrity tree includes multiple root nodes and multiple child nodes. The multiple child nodes are stored in the memory 110 in a compressed state, and the multiple root nodes are stored in the processor 120 in a decompressed state. The compressed first child node is decompressed, and the decompressed first child node is cached in the processor 120. The first child node is used for target data integrity verification.

[0206] In some embodiments, the processor 120 is specifically configured to: when the number of child nodes in the processor 120 reaches a preset value, obtain a second child node to be removed from the processor 120; and when the second child node to be removed is detected to have been changed, compress the second child node to be removed and replace the second child node in the memory 110 with the compressed second child node.

[0207] In some embodiments, the processor 120 is specifically configured to: pre-compress the second child node to be removed, and if the size of the pre-compressed second child node is greater than the size of the smallest storage unit of the memory 110, add a first value to the overflow counter of the second child node, set the value of each sub-counter of the second child node to a second value, and re-compress the reset second child node, wherein the first value is a positive number greater than 0 and the second value is a positive number.

[0208] Optionally, the first value is 1 and / or the second value is 0.

[0209] In some embodiments, the processor 120 is specifically configured to: redetermine the message authentication code (MAC) of the second child node while setting the value of each sub-counter of the second child node to a second value; and write the redetermined MAC into the memory 110.

[0210] Optionally, the branching factor of the integrity tree is a preset parameter, which is a positive integer greater than 8 that is a power of 2. For example, the preset parameter is 16 or 32.

[0211] In some embodiments, the processor 120 is specifically configured to: use at least two threads to decompress the first child node in parallel; and / or use at least two threads to compress the second child node to be removed in parallel.

[0212] The data processing device in this application embodiment can be used to execute the technical solutions of the above methods. Its implementation principle and technical effect are similar, and will not be described again here.

[0213] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0214] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Furthermore, reference can be made between the various method embodiments and between the various device embodiments; identical or corresponding content in different embodiments can be mutually referenced, without further elaboration.

Claims

1. A data processing method, characterized in that, include: In response to a read request for the target data, check if the first child node exists in the processor's cache; If the first child node is not detected in the cache, the compressed first child node is obtained from the memory. The first child node is a child node in the integrity tree that is related to the target data. The integrity tree includes multiple root nodes and multiple child nodes. The multiple child nodes are stored in the memory in a compressed state, and the multiple root nodes are stored in the processor in a decompressed state. The first child node in the compressed state is decompressed, and the decompressed first child node is cached in the processor; The message authentication code (MAC) of the target data is calculated using the first child node. If the calculated MAC matches the stored MAC of the target data, the parent node of the first child node is obtained. The parent node is used to verify the integrity of the first child node. If the first child node is detected in the cache, the integrity of the target data is verified only using the first child node in the cache.

2. The method according to claim 1, characterized in that, The method further includes: When the number of child nodes in the processor reaches a preset value, a second child node to be removed from the processor is obtained. When a change is detected in the second child node to be removed, the second child node to be removed is compressed, and the compressed second child node replaces the second child node in the memory.

3. The method according to claim 2, characterized in that, The second child node to be removed is compressed, including: Pre-compress the second child node to be removed; If the size of the pre-compressed second child node is greater than the size of the smallest storage unit of the memory, the overflow counter of the second child node is incremented by a first value, the value of each sub-counter of the second child node is set to a second value, and the reset second child node is recompressed. The first value is a positive number greater than 0, and the second value is a positive number.

4. The method according to claim 3, characterized in that, The method further includes: With each child counter of the second child node set to the second value, the message authentication code (MAC) of the second child node is re-determined. The redefined MACs are written into the memory.

5. The method according to any one of claims 1-4, characterized in that, The branching factor of the integrity tree is a preset parameter, which is a positive integer greater than 8 among the exponents of 2.

6. The method according to claim 5, characterized in that, The preset parameter is 16 or 32.

7. The method according to any one of claims 2-4, characterized in that, The decompression of the first child node in the compressed state includes: using at least two threads to decompress the first child node in parallel; and / or, The compression of the second child node includes: using at least two threads to compress the second child node in parallel.

8. The method according to claim 3 or 4, characterized in that, The first value is 1, and the second value is 0.

9. A data processing device, characterized in that, include: The memory is configured to store data; The processor is configured to read and write access to data stored in the memory; The processor is specifically configured as follows: In response to a read request for the target data, check if the first child node exists in the processor's cache; If the first child node is not detected in the cache, the compressed first child node is obtained from the memory. The first child node is a child node in the integrity tree that is related to the target data. The integrity tree includes multiple root nodes and multiple child nodes. The multiple child nodes are stored in the memory in a compressed state, and the multiple root nodes are stored in the processor in a decompressed state. The first child node in the compressed state is decompressed, and the decompressed first child node is cached in the processor; The message authentication code (MAC) of the target data is calculated using the first child node. If the calculated MAC matches the stored MAC of the target data, the parent node of the first child node is obtained. The parent node is used to verify the integrity of the first child node. If the first child node is detected in the cache, the integrity of the target data is verified only using the first child node in the cache.

10. The device according to claim 9, characterized in that, The processor is specifically configured to: when the number of child nodes in the processor reaches a preset value, obtain a second child node to be removed from the processor; and when the second child node to be removed is detected to have been changed, compress the second child node to be removed, and replace the second child node in the memory with the compressed second child node.

11. The device according to claim 10, characterized in that, The processor is specifically configured to: pre-compress the second child node to be removed, and if the size of the pre-compressed second child node is greater than the size of the smallest storage unit of the memory, add a first value to the overflow counter of the second child node, set the value of each sub-counter of the second child node to a second value, and re-compress the reset second child node, wherein the first value is a positive number greater than 0 and the second value is a positive number.

12. The device according to claim 11, characterized in that, The processor is specifically configured to: redetermine the message authentication code (MAC) of the second child node while setting the value of each child counter of the second child node to the second value; The redefined MAC is then written into the memory.

13. The device according to any one of claims 9-12, characterized in that, The branching factor of the integrity tree is a preset parameter, which is a positive integer greater than 8 among the exponents of 2.

14. The device according to claim 13, characterized in that, The preset parameter is 16 or 32.

15. The device according to any one of claims 10-12, characterized in that, The processor is specifically configured to: use at least two threads to decompress the first child node in parallel; and / or use at least two threads to compress the second child node to be removed in parallel.

16. The device according to claim 11 or 12, characterized in that, The first value is 1, and / or the second value is 0.

17. A computer storage medium, characterized in that, The device stores a computer-readable program that, when read and executed, causes the data processor device to perform the method as described in any one of claims 1 to 8.

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