A method for forming a quantum computing device and a quantum computing device

Abstract

Methods related to processing quantum computing devices to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method also includes selectively removing a portion of the superconducting metal layer to allow for subsequent formation of a gate dielectric associated with the device, where the selective removal causes a decrease in channel mobility associated with the quantum computing device. The method also includes subjecting the wafer to a plasma treatment prior to forming the gate dielectric, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

Description

BACKGROUND

[0001] Various physical systems have been proposed for building quantum computers, including trapped ions, nuclear spins, electron spins in semiconductors, photons, and other types of systems. Each of these systems aims to implement a quantum bit (the quantum equivalent of a bit), which is not a value 0 or a value 1, but is represented by a two-dimensional vector that evolves according to the rules of quantum physics. Topological quantum computing can provide better performance than traditional quantum computing approaches. SUMMARY

[0002] In one example, the disclosure relates to a method for forming a quantum computing device. The method can include forming a superconducting metal layer on a surface of a wafer. The method can also include selectively removing a portion of the superconducting metal layer to allow for subsequent formation of a gate dielectric associated with the device, where the selective removal causes a reduction in a channel mobility associated with the quantum computing device. The method can further include subjecting the wafer to a plasma treatment prior to forming the gate dielectric, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

[0003] In another aspect, the disclosure relates to a quantum computing device including a quantum well formed in a substrate. The quantum computing device can also include a superconducting metal layer formed on a surface of the substrate. The quantum computing device can further include a gate dielectric associated with the quantum computing device, the gate dielectric formed after a selective removal of a portion of the superconducting metal layer, where the selective removal causes a reduction in a channel mobility adjacent to the quantum well formed in the substrate, and where the gate dielectric is formed after subjecting the substrate to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well.

[0004] In yet another aspect, the disclosure relates to a method for processing a wafer including a quantum well to form a quantum computing device. The method can include forming a superconducting metal layer on a surface of the wafer. The method can also include selectively removing a portion of the superconducting metal layer to allow for subsequent formation of a gate dielectric associated with the quantum computing device, where the selective removal causes a reduction in a channel mobility adjacent to the quantum well. The method can further include subjecting the wafer to an in-situ plasma treatment prior to forming the gate dielectric, utilizing at least hydrogen as a precursor associated with the plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well such that the channel mobility adjacent to the quantum well and an intrinsic channel mobility are substantially the same.

[0005] This summary is provided to introduce some concepts in a simplified form, which will be further described in the detailed embodiments below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0006] This disclosure is illustrative by way of example and is not limited to the accompanying drawings, wherein the same reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 A cross-sectional view of an example topological quantum computing device is shown during at least one step in the process of forming the device;

[0008] Figure 2 A cross-sectional view of an example topological quantum computing device is shown during at least one step in the process of forming the device;

[0009] Figure 3 A cross-sectional view of an example topological quantum computing device is shown during at least one step in the process of forming the device;

[0010] Figure 4 An illustration of damage to a semiconductor adjacent to a quantum well, based on an example, is shown.

[0011] Figure 5 A graph showing mobility versus density for the test sample is shown.

[0012] Figure 6 The peak mobility of various processing implementations is shown;

[0013] Figure 7 The peak mobility versus density for various processes at zero gate voltage is shown;

[0014] Figure 8 An illustration shows the changes in semiconductors caused by plasma treatment.

[0015] Figure 9 A cross-sectional view of an example topological quantum computing device is shown during at least one step in the process of forming the device;

[0016] Figure 10 A cross-sectional view of an example topological quantum computing device is shown during at least one step in the process of forming the device;

[0017] Figure 11 A top view of an example topological quantum computing device is shown during at least one step in the process of forming the device; and

[0018] Figure 12A top view of an example topological quantum computing device is shown during at least one step in the process of forming the device. Detailed Implementation

[0019] The examples described in this disclosure relate to quantum computing devices and methods for fabricating them, including processes during the formation of the quantum computing device. Some examples also relate to topological qubits that can be realized using a two-dimensional electron gas (2-DEG) structure. Such a 2-DEG structure can be formed using materials from Group III and Group V of the periodic table. Furthermore, such a 2-DEG structure can also be formed using materials from Group II, Group IV, or Group VI of the periodic table. These materials can also be used to form gas-liquid-solid (VLS) nanowires. VLS nanowires can be formed using chemical beam epitaxy or molecular beam epitaxy and then transferred to a substrate to form the source, drain, and gate aspects of the device. Furthermore, these materials can be used to form topological qubits using selective region growth (SAG) techniques. During the formation of topological qubits using any of these techniques, in the examples described herein, a superconductor formed on the surface is coupled to a quantum well.

[0020] Example devices can be formed using superconducting metals such as aluminum or niobium grown in situ on a wafer. Example wafers include those formed using indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), or any suitable combination of materials selected from Groups II, III, IV, V, and VI of the periodic table, or any ternary compound of three different atoms selected from Groups II, III, IV, V, and VI of the periodic table. As an example, a wafer can be formed by epitaxially growing any of these material combinations on a substrate. Topological quantum computing devices can be created by forming a superconducting metal layer on a wafer. In some examples, the metal layer can be formed by growing or depositing the metal in situ on the wafer.

[0021] Direct in-situ deposition of superconductors, such as epitaxially grown aluminum, after semiconductor growth leads to significant improvements in the quality of superconducting gaps. However, this technique introduces additional fabrication challenges. For example, aluminum must be removed to define the topological regions of the device. Selective wet etching solutions for aluminum are highly exothermic and cause damage to the semiconductor. This results in increased roughness and induced impurities, reduced mobility of the two-dimensional electron gas (2DEG), and impaired fragile induced p-wave superconducting pairing. Since the lengthscale of maintaining hard gap superconductivity through interface cleaning is set by the height and thickness of the barrier, burying the 2DEG within the heterostructure may be infeasible. Therefore, fabrication techniques to repair defects are needed.

[0022] Figure 1A cross-sectional view is shown of at least one step used in forming a topological quantum computing device 100 according to an example. In this example, as part of this step, a buffer layer 104 can be formed starting from a substrate 102. Next, a quantum well layer 106 can be formed on the buffer layer 104. Next, another buffer layer 108 can be formed on the quantum well layer 106 to complete the formation of a heterostructure corresponding to one or more superconducting quantum wells. The buffer layer 108 may not be necessary for completing the formation of certain types of quantum wells. In this example, the substrate 102 may be an indium phosphide (InP) substrate. The buffer layer 104 may be an indium gallium arsenide (InGaAs) layer. The quantum well layer 106 may be an indium arsenide (InAs) layer. The buffer layer 108 may be an indium aluminum arsenide (InAlAs) layer. Each of these layers can be formed using molecular beam epitaxy (MBE). As an example, MBE-related processes can be performed in an MBE system, which allows the deposition of appropriate materials in a vacuum. Although Figure 1 A certain number of layers of a topological quantum computing device 100 arranged in a certain way are shown, but there may be more or fewer layers arranged differently.

[0023] Figure 2 A cross-sectional view is shown of at least one step used in forming a topological quantum computing device 100 according to an example. As part of this step, a metal layer 110 may be formed on a buffer layer 108. In this example, an MBE (Metal-Based Electrode) may be used to deposit the metal layer 110. The metal layer 110 may comprise aluminum, niobium, or any other metal that may be superconducting at certain temperatures. Although Figure 2 A certain number of layers of a topological quantum computing device 100 arranged in a certain way are shown, but there may be more or fewer layers arranged differently.

[0024] Figure 3A cross-sectional view is shown of at least one step used in forming a topological quantum computing device 100 according to an example. As part of this step, a portion 318 of the metal layer 110 may be selectively removed. This step may be performed using wet etching or dry etching. A mask may be used to define the topological active region of the topological quantum computing device. The topological active region may include quantum wells, such as InAs quantum wells or GaAs quantum wells. For the purposes of topological quantum computing, the interface between the topological active region (including the metal layer (e.g., aluminum layer)) and the topological non-active region (excluding the metal layer (e.g., aluminum layer)) is important. The etching step damages a portion of the semiconductor exposed due to the etching step (e.g., portion 320), including the interface between the topological active region and the topological non-active region. Some of this damage corresponds to charged surface states, which may interfere with the operation of the topological quantum computing device 100. This is because the quantum well is formed at a shallow depth (e.g., within approximately 10 nm of the surface). Charged surface states may interfere with the quality of the 2DEG. Similarly, other structures (such as nanowires grown using the VLS method) are damaged due to the lack of a buffer layer.

[0025] Figure 4 A diagram illustrating damage to a semiconductor surface 422 adjacent to a quantum well, according to one example, is shown. Damage to the semiconductor surface 422 causes increased roughness and induced impurities, which increases carrier scattering and reduces the mobility of the 2DEG. As shown in the undamaged portion 424, in this example, the quantum well comprises atoms corresponding to indium 430, gallium 432, and arsenic 434. If a dielectric layer (e.g., an oxide layer) is formed before repairing this damage, the oxide layer is likely to contain a high charge density caused by unpaired arsenic atoms and other unbonded positive and negative charges. Furthermore, damage to the semiconductor includes other charged surface states, including electrons 442. Damage to the semiconductor also includes the formation of native oxides (including oxygen atoms 440). Additionally, the breaking of bonds between the elements constituting the wafer increases roughness. All of these contribute to scattering effects, which reduce channel mobility.

[0026] To address the damage, two methods for reducing impurity density were tested. The first method involved using a trimethylaluminum (TMA) precursor to remove native oxides, thus allowing for the growth of abrupt semiconductor / dielectric interfaces and reduced defect density. The second method involved removing oxides and passivating charged impurities via hydrogen plasma. As part of the first method, a 1-second TMA pulse was applied to the wafer (e.g., a wafer in an atomic layer deposition (ALD) chamber). This was followed by a 30-second purging with nitrogen at a process temperature of 200°C. This pulse cycle was repeated several times (e.g., 18 times) prior to dielectric growth to maximize the reaction. As part of testing the second method, a remotely generated argon-hydrogen (ArH) plasma was applied to the wafer for a total of 120 seconds prior to dielectric layer growth. Table 1 below shows a list of the samples tested. During the testing of these samples, two treatments (TMA reduction and hydrogen passivation) and two oxidants (H2O and O3) were evaluated to determine their effects on the channel mobility of the samples.

[0027] Sample Treatment Oxidation growth A Untreated [CAT] / H20 B TMA reduction [CAT] / H20 C TMA reduction [CAT] / O3 D Hydrogen passivation [CAT] / H20 E Hydrogen passivation [CAT] / O3

[0028] Table 1

[0029] For each sample, the gate voltage was scanned, and the mobility and density values ​​were extracted. Figure 5 Representative mobility-density traces for each treatment of five samples (A, B, C, D, and E) are shown. The results of this test indicate that using ozone (O3) as a precursor is ineffective for creating a clean semiconductor-dielectric interface. This is because the two ozone-treated samples exhibited reduced mobility compared to the untreated samples. As part of the performed tests, it was found that using argon and hydrogen (ArH) plasma combined with oxide growth using TMA and H2O as oxidants was the only treatment that increased the measured mobility relative to the untreated samples. Figure 5 A graph showing mobility versus density for the test sample is shown. Density is related to the electron density within the quantum well. For topological quantum computing devices including 2DEGs, for the example test sample, density is related to the electron density within the 2DEG. For the example test sample, mobility is related to the distance electrons travel before they are scattered or reflected.

[0030] Figure 6 The peak mobility of various processing implementations is shown. Figure 7 This shows the effect at zero gate voltage (V) TGThe peak mobility versus density was measured. As these results show, there is an improvement in channel mobility adjacent to the heterostructure including quantum wells compared to the channel mobility of the untreated sample. Although the tests show results related to hydrogen plasma, other plasma precursors can also be used. As an example, helium plasma or nitrogen plasma can be used instead of hydrogen plasma. Furthermore, although the tests show results related to trimethylaluminum (TMA) precursor, other atomic layer deposition precursors can also be used, such as tetramethylaminohafnium.

[0031] Therefore, in an example consistent with this disclosure, the wafer undergoes plasma treatment, wherein parameters associated with the plasma treatment are selected to increase the channel mobility adjacent to the quantum well. In this example, the plasma treatment is provided using a remote plasma source; therefore, the wafer is not subjected to direct plasma. Parameters associated with the plasma treatment include any precursors associated with the plasma treatment, the density of any ions or electrons associated with the plasma treatment, and the type of power supply associated with the plasma treatment. In one example, the precursors include argon and hydrogen. The power supply can be a direct current (DC) power supply, a pulsed DC power supply, or a radio frequency (RF) power supply.

[0032] Figure 8 An illustration shows the changes to semiconductor 810 resulting from plasma treatment. Atomic hydrogen 820 bonds to arsenic (As) atoms (e.g., 430) to partially saturate dangling bonds, thus passivating the wafer. The hydrogen plasma also selectively removes oxides via dry etching, again resulting in abrupt semiconductor-dielectric interfaces. These techniques significantly increase mobility, a critical requirement for topological materials, and reduce mobility differences between multiple samples compared to alternative treatments or no treatment. Furthermore, as previously stated, these techniques are applicable not only to InAs2DEG but also to VLS lines, SAG materials, or any other devices made from semiconductor materials selected from Groups III-V of the periodic table.

[0033] Figure 9 A cross-sectional view is shown of at least one step used in forming a topological quantum computing device 100 according to an example. As part of this step, a dielectric layer 116 is formed. In this example, the dielectric layer 116 is formed using atomic layer deposition. The dielectric layer 116 may comprise aluminum oxide (e.g., Al₂O₃). Although Figure 9 A certain number of layers of a topological quantum computing device 100 arranged in a certain way are shown, but there may be more or fewer layers arranged differently.

[0034] Figure 10A cross-sectional view is shown of at least one step used in forming a topological quantum computing device 100 according to an example. This step includes forming a gate 118 (e.g., a metal gate) for controlling a channel between the source and drain, associated with a switching component of the topological quantum computing device 100. In one example, the gate 118 may be a titanium (Ti-Au) gate. Although... Figure 10 A certain number of layers of a topological quantum computing device 100 arranged in a certain way are shown, but there may be more or fewer layers arranged differently.

[0035] Figure 11 A top view of an example topological quantum computing device 100 is shown during at least one step in forming the device. In this example, the topological quantum computing device 100 includes a source 1110, a drain 1120, and a gate 1106. The gate 1106 may correspond to... Figure 10 The gate 118. The top view also shows a dielectric layer 1102, which may correspond to... Figure 9 Layer 116 is shown. The topological quantum computing device 100 may also include a channel 1112 between the source 1110 and the gate 1106, and another channel between the drain 1120 and the gate 1106. The process steps described above, including processing, contribute to increasing the mobility of each of the channels 1112 and 1122. Although Figure 11 The planar arrangement of the source, drain, and gate is shown, but these can be arranged non-planarly. As an example, gate 1106 can be a vertical fin gate. Furthermore, although... Figure 11 Only one gate, one source, and one drain are shown, but topological quantum computing devices can include multiple gates, sources, or drains.

[0036] Figure 12 A top view of an example topological quantum computing device 100 is shown during at least one step in forming the device. In this example, the topological quantum computing device 100 includes a source 1208, a drain 1218, a gate 1206, another gate 1210, and yet another gate 1220. Gate 1206 may correspond to... Figure 10 Gate 118. Gates 1210 and 1220 can allow for additional control of the topological quantum computing device 100. The top view also shows dielectric layer 1202, which can correspond to Figure 9 Layer 116 is shown. The topological quantum computing device 100 may also include a channel 1212 between the source 1208 and the gate 1206, and another channel 1222 between the drain 1218 and the gate 1206. The process steps described above, including processing, contribute to increasing the mobility of each of the channels 1212 and 1222. Although Figure 12The planar arrangement of the source, drain, and various gates is shown, which can be arranged in a non-planar manner. As an example, gate 1206 can be a vertical fin gate.

[0037] In summary, this disclosure relates to a method for forming a quantum computing device. The method may include forming a superconducting metal layer on the surface of a wafer. The method may further include selectively removing a portion of the superconducting metal layer to allow subsequent formation of a gate dielectric associated with the device, wherein the selective removal causes a reduction in channel mobility associated with the quantum computing device. The method may also include subjecting the wafer to a plasma treatment prior to forming the gate dielectric, wherein a set of parameters associated with the plasma treatment is selected to increase channel mobility.

[0038] The parameter set may include parameters of any precursors associated with the plasma process, the density of any ions or electrons associated with the plasma process, and the type of power source associated with the plasma process. Precursors associated with the plasma process may include argon and hydrogen.

[0039] A quantum well can correspond to a topological active region associated with a quantum computing device. Plasma processing can include remote plasma processing. Remote plasma processing can be provided using a power source selected from the group consisting of direct current (DC) power sources, pulsed DC power sources, or radio frequency (RF) power sources.

[0040] The method may also include applying trimethylaluminum to the surface of the wafer in an atomic layer deposition chamber prior to subjecting the wafer to plasma treatment. Precursors associated with plasma treatment may also include helium. Topological quantum computing devices may include at least one of two-dimensional electron gas (2DEG), gas-liquid-solid (VLS) nanowires, or structures formed using selective region growth.

[0041] In another aspect, this disclosure relates to a quantum computing device including a quantum well formed in a substrate. The quantum computing device may further include a superconducting metal layer formed on the surface of the substrate. The quantum computing device may also include a gate dielectric associated with the quantum computing device, formed after selectively removing a portion of the superconducting metal layer, wherein the selective removal causes a decrease in the channel mobility adjacent to the quantum well formed in the substrate, and wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well. The parameter set may include parameters of any precursors associated with the plasma treatment, the density of any ions or electrons associated with the plasma treatment, and the power source type associated with the plasma treatment. Precursors associated with the plasma treatment may include argon and hydrogen.

[0042] Plasma processing can include remote plasma processing. Remote plasma processing can be powered by a power source selected from the group consisting of direct current (DC) power sources, pulsed DC power sources, or radio frequency (RF) power sources.

[0043] In another aspect, this disclosure relates to a method for processing a wafer including a quantum well to form a quantum computing device. The method may include forming a superconducting metal layer on the surface of the wafer. The method may further include selectively removing a portion of the superconducting metal layer to allow subsequent formation of a gate dielectric associated with the quantum computing device, wherein the selective removal causes a reduction in the channel mobility adjacent to the quantum well. The method may further include subjecting the wafer to an in-situ plasma treatment prior to forming the gate dielectric, utilizing at least hydrogen as a precursor associated with the plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well such that the channel mobility adjacent to the quantum well is substantially the same as the intrinsic channel mobility.

[0044] The parameter set may include the density of any ions or electrons associated with the plasma processing, as well as the type of power source associated with the plasma processing. Additional precursors associated with the plasma processing may also include argon.

[0045] Plasma processing can include remote plasma processing. Remote plasma processing can be provided using a power source selected from the group consisting of direct current (DC) power sources, pulsed DC power sources, or radio frequency (RF) power sources. The method can also include applying trimethylaluminum to the surface of a wafer in an atomic layer deposition chamber prior to subjecting the wafer to in-situ plasma processing.

[0046] It should be understood that the methods, modules, and components described herein are merely exemplary. For example, but not limited to, illustrative devices may include quantum computing devices, semiconductor devices, topological quantum computing devices, etc.

[0047] Furthermore, in an abstract yet still explicit sense, any arrangement of components that perform the same function is effectively “associated” in order to achieve the desired function. Therefore, any two components combined in this paper to achieve a specific function can be considered “associated” with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “coupled” with each other to achieve the desired function.

[0048] Furthermore, those skilled in the art will recognize that the boundaries between the functions of the above operations are merely illustrative. The functions of multiple operations can be combined into a single operation, and / or the functions of a single operation can be distributed across additional operations. Additionally, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments.

[0049] While specific examples are provided in this disclosure, various modifications and variations may be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as key, essential, or necessary features or elements of any or all claims.

[0050] Furthermore, the terms “a” or “an” as used herein are defined as one or more. Moreover, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that another claim element introduced by the indefinite article “a” or “an” limits any particular claim containing such an introductory claim element to an invention containing only that element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same applies to the use of definite articles.

[0051] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of these elements.

Claims

1. A method for forming a quantum computing device, comprising: A superconducting metal layer is formed on the surface of the wafer; A portion of the superconducting metal layer is selectively removed to allow subsequent formation of the gate dielectric associated with the quantum computing device, wherein the selective removal causes a reduction in channel mobility with respect to the quantum well associated with the quantum computing device; as well as Before forming the gate dielectric, the wafer is subjected to a plasma treatment, wherein a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well associated with the quantum computing device and to increase the electron density within the quantum well.

2. The method according to claim 1, wherein the parameter set comprises: Parameters of any precursors associated with the plasma treatment, the density of any ions or electrons associated with the plasma treatment, and the type of power source associated with the plasma treatment.

3. The method of claim 2, wherein the precursor associated with the plasma treatment comprises argon and hydrogen.

4. The method of claim 1, wherein the quantum well corresponds to a topological active region associated with the quantum computing device.

5. The method of claim 1, wherein the plasma processing includes remote plasma processing.

6. The method of claim 5, wherein the remote plasma processing is provided using a power source selected from the group consisting of a DC power source, a pulsed DC power source, or a radio frequency (RF) power source.

7. The method according to claim 1, further comprising: Before subjecting the wafer to the plasma treatment, trimethylaluminum is applied to the surface of the wafer in an atomic layer deposition chamber.

8. The method of claim 2, wherein the precursor associated with the plasma treatment comprises helium.

9. The method of claim 1, wherein the quantum computing device comprises at least one of the following: a two-dimensional electron gas (2DEG), a gas-liquid-solid VLS nanowire, or a structure formed using selective region growth.

10. A quantum computing device, comprising: A quantum well is formed in a substrate; A superconducting metal layer is formed on the surface of the substrate; as well as A gate dielectric, associated with the quantum computing device, is formed after selectively removing a portion of the superconducting metal layer, wherein the selective removal causes a decrease in the channel mobility adjacent to the quantum well formed in the substrate, wherein the gate dielectric is formed after subjecting the substrate to a plasma treatment, and wherein a set of parameters associated with the plasma treatment is selected to increase the channel mobility adjacent to the quantum well and to increase the electron density within the quantum well.

11. The quantum computing device of claim 10, wherein the parameter set comprises: Parameters of any precursors associated with the plasma treatment, the density of any ions or electrons associated with the plasma treatment, and the type of power source associated with the plasma treatment.

12. The quantum computing device of claim 11, wherein the precursor associated with the plasma processing comprises argon and hydrogen.

13. The quantum computing device of claim 10, wherein the plasma processing includes remote plasma processing.

14. The quantum computing device of claim 13, wherein the remote plasma processing is provided using a power source selected from the group consisting of a DC power source, a pulsed DC power source, or a radio frequency (RF) power source.

15. A method for processing a wafer including a quantum well to form a quantum computing device, the method comprising: A superconducting metal layer is formed on the surface of the wafer; A portion of the superconducting metal layer is selectively removed to allow subsequent formation of the gate dielectric associated with the quantum computing device, wherein the selective removal causes a reduction in the channel mobility adjacent to the quantum well; as well as Prior to forming the gate dielectric, the wafer is subjected to plasma treatment using at least hydrogen as a precursor associated with in-situ plasma treatment, wherein the set of parameters associated with the plasma treatment is selected to: (1) increase the channel mobility adjacent to the quantum well such that the channel mobility adjacent to the quantum well and the intrinsic channel mobility adjacent to the quantum well are substantially the same, and (2) increase the electron density within the quantum well.

16. The method of claim 15, wherein the parameter set comprises: The density of any ions or electrons associated with the plasma treatment and the type of power source associated with the plasma treatment.

17. The method of claim 15, wherein the additional precursor associated with the plasma treatment further comprises argon.

18. The method of claim 15, wherein the plasma processing includes remote plasma processing.

19. The method of claim 18, wherein the remote plasma processing is provided using a power source selected from the group consisting of a DC power source, a pulsed DC power source, or a radio frequency (RF) power source.

20. The method of claim 15, further comprising: Before subjecting the wafer to the in-situ plasma treatment, trimethylaluminum is applied to the surface of the wafer in an atomic layer deposition chamber.

21. A method for processing a wafer to form a topological quantum computing device, the method comprising: A superconducting metal layer is formed on the surface of the wafer; Selectively removing a portion of the superconducting metal layer to allow subsequent formation of the gate dielectric associated with the topological quantum computing device, wherein the selective removal causes a decrease in channel mobility adjacent to the quantum well associated with the topological quantum computing device, wherein the topological quantum computing device comprises at least one of: a two-dimensional electron gas (2DEG), a gas-liquid-solid VLS nanowire, or a structure formed using selective region growth; and Prior to forming the gate dielectric, the wafer is subjected to plasma treatment using at least hydrogen as a precursor associated with in-situ plasma treatment, wherein the set of parameters associated with the plasma treatment is selected to: (1) increase the channel mobility adjacent to the quantum well associated with the topological quantum computing device such that the channel mobility adjacent to the quantum well and the intrinsic channel mobility adjacent to the quantum well are substantially the same, and (2) increase the electron density within the quantum well associated with the topological quantum computing device.

22. The method of claim 21, wherein the parameter set comprises: The density of any ions or electrons associated with the plasma treatment and the type of power source associated with the plasma treatment.

23. The method of claim 21, wherein the additional precursor associated with the plasma treatment further comprises argon.

24. The method of claim 21, wherein the plasma processing includes remote plasma processing, and wherein the remote plasma processing is provided using a power source selected from the group consisting of a DC power source, a pulsed DC power source, or a radio frequency (RF) power source.

25. The method of claim 21, further comprising: Before subjecting the wafer to the in-situ plasma treatment, trimethylaluminum is applied to the surface of the wafer in an atomic layer deposition chamber.

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