Integrated circuit load adjustment method and related device

Abstract

This application provides an integrated circuit load adjustment method and related apparatus. The integrated circuit load adjustment method includes: obtaining the current maximum allowable load of the integrated circuit; generating a load state adjustment signal for the integrated circuit based on the current maximum allowable load; and adjusting the load state of the integrated circuit based on the load state adjustment signal. The integrated circuit load adjustment method and related apparatus provided in this application can improve the performance of the integrated circuit under corresponding DIDT voltage drop conditions based on the individual integrated circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular to an integrated circuit load adjustment method and related devices. Background Art

[0002] The power supply system of the integrated circuit includes: external power supply, power connection and internal power network. The internal devices are connected to the internal power network, and the internal power network is connected to the external power supply through the power connection. During the operation of the integrated circuit, the power connection between the internal power network and the external power supply will generate current, which will cause voltage drop. When the integrated circuit has a small load or no load, since the resistance of the internal power network is small and the resistance of the internal device is large, it can be considered that the external voltage acts completely on the internal device.

[0003] When the load of an integrated circuit suddenly increases, that is, when more internal devices are in operation at the same time, the rate of change of the integrated circuit current over time (DIDT) suddenly increases. That is, when the current suddenly increases, the power supply voltage on the internal devices of the integrated circuit will drop sharply if the power remains unchanged for a short period of time. The reduction in power supply voltage will cause an increase in the delay of the internal devices, resulting in the inability to meet the setup time of the registers on the critical path, thereby causing the entire integrated circuit to fail.

[0004] However, existing solutions to the problem of chip functional failure caused by DIDT cannot be adjusted based on the specific conditions of each integrated circuit to improve the performance of the integrated circuit.

[0005] Therefore, how to improve the performance of integrated circuits under corresponding DIDT voltage drops based on individual integrated circuits has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0006] In view of this, the integrated circuit load adjustment method provided in the embodiment of the present application can improve the performance of the integrated circuit under the corresponding DIDT voltage drop based on the individual integrated circuit.

[0007] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0008] In a first aspect, an embodiment of the present application provides an integrated circuit load adjustment method, comprising:

[0009] Get the current maximum allowable load of the integrated circuit;

[0010] generating a load state adjustment signal for the integrated circuit according to the current maximum allowable load;

[0011] The load state of the integrated circuit is adjusted according to the load state adjustment signal.

[0012] In a second aspect, an embodiment of the present application provides an integrated circuit load adjustment device, comprising:

[0013] A current maximum allowable load acquisition module, adapted to acquire the current maximum allowable load of the integrated circuit;

[0014] A load state adjustment signal generating module, adapted to generate a load state adjustment signal of the integrated circuit according to the current maximum allowable load;

[0015] The state adjustment module is adapted to adjust the load state of the integrated circuit according to the load state adjustment signal.

[0016] In a third aspect, an embodiment of the present application provides an integrated circuit, including:

[0017] An upstream data processing module, suitable for transmitting data downstream;

[0018] A downstream data processing module, adapted to receive the data transmitted by the upstream data processing module;

[0019] The integrated circuit load adjustment device as described in the second aspect is connected between the upstream data processing module and the downstream data processing module, and is suitable for adjusting the data transmission status between the upstream data processing module and the downstream data processing module according to the current maximum allowable load of the integrated circuit.

[0020] The integrated circuit load adjustment method provided in the embodiment of the present application first obtains the current maximum allowable load of the integrated circuit; then generates a load state adjustment signal of the integrated circuit based on the current maximum allowable load; and finally adjusts the load state of the integrated circuit based on the load state adjustment signal.

[0021] In this way, the integrated circuit load adjustment method provided in the embodiment of the present application first obtains the current maximum allowable load of the integrated circuit, which is the current maximum allowable load corresponding to the real-time voltage of the integrated circuit load, that is, according to the different integrated circuits, the current maximum allowable load corresponding to different integrated circuits is obtained, and then, according to the current maximum allowable load, a load state adjustment signal of the integrated circuit is generated to adjust the load state, so that part of the load is not in the working state at the same time, so that the integrated circuit can always work in the state of the current maximum allowable load. It can be seen that the integrated circuit load adjustment method provided in the embodiment of the present application, through the real-time acquisition of the current maximum allowable load of a specific integrated circuit and the generation of the load state adjustment signal, adjusts the load state, and can realize the integrated circuit based on the individual integrated circuit, so that the integrated circuit can adjust the load of the integrated circuit according to the real-time voltage drop of the integrated circuit, so that it always works in the maximum load allowed by the current voltage drop, thereby improving the performance of each integrated circuit under the corresponding DIDT voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] Figure 1 This is a schematic diagram of a chip power supply structure.

[0024] Figure 2 A schematic diagram of the structure of an integrated circuit load adjustment device provided in an embodiment of the present application.

[0025] Figure 3 A schematic diagram of the power supply structure of an integrated circuit provided in an embodiment of the present application.

[0026] Figure 4 A schematic diagram of an optional flow chart of an integrated circuit load adjustment method provided in an embodiment of the present application.

[0027] Figure 5 A flowchart for obtaining corresponding test loads and test equivalent loads provided in an embodiment of the present application.

[0028] Figure 6 A flowchart of obtaining the most average control signal of the integrated circuit load adjustment method provided in an embodiment of the present application.

[0029] Figure 7A schematic diagram of a load gating structure of an integrated circuit load adjustment method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The following takes a common chip as an example to explain the basic working performance of the integrated circuit under voltage drop conditions.

[0032] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip power supply structure.

[0033] As shown in the figure, a typical chip power supply structure includes a power supply 10, an internal wiring 12, a power connection 14, a power wiring 16, an internal power network 17, a connection 18 and an integrated circuit internal device 19.

[0034] The power supply process is:

[0035] The power output by the power supply 10 enters the substrate 13 of the chip through the internal wiring 12 of the integrated circuit board 11, and then enters the inside of the chip 15 through the power connection 14 between the substrate 13 and the chip pins. The power is connected to the internal power network 17 of the integrated circuit through the power wiring 16 inside the chip. The internal power network 17 of the integrated circuit can be connected to the internal device 19 of the integrated circuit through the connection 18 of the power pin to supply power to the internal device 19 of the integrated circuit.

[0036] When the chip load is small or no load, the power supply 10 can provide a stable voltage output and act on the internal device 19 of the integrated circuit in the working state to ensure the normal operation of the internal device 19 of the integrated circuit. However, when the chip load suddenly increases, resulting in a sudden increase in the rate of change of current over time (DIDT), the power supply 10 cannot provide enough energy in a short time. When the power supply power remains unchanged for a short time, the current increases. When the power supply output voltage cannot be adjusted for a short time, the voltage divided on the connection line before the internal device 19 of the integrated circuit increases, resulting in a sharp drop in the voltage on the internal device 19 of the integrated circuit. Due to the sharp drop in the voltage on the internal device 19 of the integrated circuit, the delay of the internal device 19 of the integrated circuit increases, resulting in the inability to meet the establishment time of the register on the critical path, thereby causing the entire integrated circuit to fail.

[0037] In the prior art, the following technical solutions are usually adopted to solve the problem of chip function failure caused by DIDT:

[0038] 1. Estimate the voltage drop during severe DIDT so that the output voltage of the power supply provided on the integrated circuit board can ensure that in severe DIDT conditions, the power supply to the internal device 19 of the integrated circuit still meets the power supply requirements.

[0039] However, this solution has the following disadvantages: since the power supply of the integrated circuit board is increased, the power consumption of the integrated circuit board will increase. When the load decreases sharply, the voltage of the internal components of the chip will rise, and there is a risk of voltage overshoot and burning out the internal components of the chip.

[0040] 2. Voltage drop detection (voltage droop detect) and clock stretch (clock stretch) are introduced inside the chip. The amplitude of clock stretch (clock stretch) is set according to the amplitude of voltage drop detection (voltage droop detect) to reduce the clock frequency, so as to reduce the load of the integrated circuit and alleviate the voltage drop situation.

[0041] However, this solution has the following disadvantages: the relationship between the amplitude of voltage drop detection (voltage droop detect) and the amplitude of clock stretch (clock stretch) is difficult to determine. Being too rough will cause the amplitude of clock stretch to be too large, resulting in performance loss. At the same time, it also does not take into account the individual differences between chips, which will cause clock stretch to fail in some specific cases.

[0042] 3. Add a module to the internal devices of the chip to automatically estimate the current load. When the load increases sharply, the data processing unit of the internal devices of the chip is controlled by gating to reduce task dispatch and thus reduce the chip load.

[0043] However, this solution has the following disadvantages: it only reduces task allocation based on changes in the number of loads, without considering changes in actual voltage. Different external power supplies can support different loads in different situations, and it also does not take into account individual differences between chips. As a result, the performance loss of the integrated circuit will be higher than ideal.

[0044] It can be seen that the various existing methods are difficult to improve the working performance of the integrated circuit under the corresponding DIDT voltage drop based on a specific integrated circuit.

[0045] In order to overcome the shortcomings of the prior art, the present application embodiment provides an integrated circuit load adjustment device, please refer to Figure 2 , Figure 2A schematic diagram of the structure of an integrated circuit load adjustment device provided in an embodiment of the present application.

[0046] Depend on Figure 2 It can be seen that the integrated circuit load adjustment device provided in the embodiment of the present application includes a current maximum allowable load acquisition module 21, a load state adjustment signal generating module 22 and a state adjustment module 23. Of course, the integrated circuit also includes an operation core module 1, which includes each integrated circuit internal device 19.

[0047] Among them, the current maximum allowable load acquisition module 21 is used to obtain the current maximum allowable load. The maximum allowable load acquisition module 21 can include a device that can directly obtain the maximum allowable load to directly obtain the current maximum allowable load. In order to increase the selectable range of devices and reduce costs, the current maximum allowable load acquisition module 21 can also include a device that can indirectly reflect the maximum allowable load (such as: a current maximum equivalent load acquisition unit), that is, a device with a mutual mapping relationship between the acquired value and the maximum allowable load, and a device that further obtains the maximum allowable load based on the mapping relationship (such as: a current maximum allowable load acquisition unit). In this case, it is necessary to pre-construct the corresponding relationship between the reading value of the current maximum allowable load acquisition module (that is, the current maximum equivalent load) and the current maximum allowable load, so that when the reading value of the current maximum equivalent load is specifically obtained, the corresponding current maximum allowable load can be obtained.

[0048] For easier understanding, please continue to refer to Figure 2 The current maximum allowable load acquisition module 21 includes a current maximum equivalent load acquisition unit 211 and a current maximum allowable load acquisition unit 212 .

[0049] The current maximum equivalent load acquisition unit 211 acquires the current maximum equivalent load, and the current maximum allowable load acquisition unit 212 obtains the current maximum allowable load based on the current maximum equivalent load.

[0050] Specifically, the current maximum equivalent load acquisition unit 211 may include a power supply monitor (PSM, Power Supply Monitor) 2110 .

[0051] In a specific implementation, to facilitate understanding of the configuration of the power monitor 2110, please refer to Figure 3 , Figure 3 A schematic diagram of the power supply structure of an integrated circuit provided in an embodiment of the present application.

[0052] Depend on Figure 3It can be seen that in the integrated circuit provided in the embodiment of the present application, the power supply monitor (PSM) 2110 is connected to the internal power supply network 17 of the integrated circuit through the connection 18 of the power supply pin.

[0053] The power supply monitor (PSM) 2110 includes a ring oscillator and a counter composed of an inverter. The ring oscillator will generate different frequency clocks according to the different PVT (process, voltage, temperature) of the current integrated circuit. The counter can count the generated frequency clocks, and the size of the count value (PSM value) per unit time can reflect the voltage condition of the integrated circuit under the temperature and process, that is, the voltage value of the load can be understood by obtaining the PSM value. When the unit time is small enough, the size of the PSM value can reflect the instantaneous value of the voltage.

[0054] The reasons why the PSM value of the power supply monitor (PSM) 2110 can reflect the voltage status of the integrated circuit are as follows:

[0055] The charging and discharging of the capacitor in the inverter of the ring oscillator will be affected by the voltage. The larger the voltage, the faster the capacitor charges and discharges. The faster the capacitor charges and discharges, the shorter the time it takes for the inverter to reverse. Therefore, the oscillation frequency of the ring oscillator is higher and the cycle is shorter. By recording the number of cycles per unit time through the counter in the PSM, the count value of the counter, that is, the PSM value, can be obtained, and the PSM value can reflect the voltage.

[0056] The voltage condition of the internal device 19 of the integrated circuit directly determines the load that the integrated circuit can bear, and the internal voltage condition corresponds to the PSM value. Therefore, the PSM value corresponds to the load condition that the integrated circuit can bear.

[0057] Of course, in order to obtain the current maximum allowable load based on the PSM value, it is also necessary to establish a mapping relationship between the PSM value and the current maximum allowable load of the integrated circuit in advance. Then, the current maximum allowable load acquisition unit 212 can obtain the current maximum allowable load based on the PSM value (i.e., the current maximum equivalent load) and the mapping relationship.

[0058] To this end, the chip can be tested before the integrated circuit actually works to obtain a mapping relationship between the PSM value and the current maximum allowable load of the integrated circuit. For ease of description, in a specific implementation, the current maximum allowable load can be represented by the M / N value.

[0059] Wherein, M represents the number of cycles, N represents the amount of effective control signals, and the M / N value represents the number of effective control signals generated in the number of cycles. The load state of the integrated circuit can be adjusted according to the effective control signals generated. For example, 255 / 1 represents that in 255 cycles, 1 effective control load stop signal is generated, so the current maximum allowable load can be represented by the M / N value. Of course, in other embodiments, the current maximum allowable load can also be represented by other parameter values. It is easy to understand that during the test process, it is the test load.

[0060] When starting the test, set the test load, that is, the M / N value (the M / N value can be determined according to the required load control accuracy of the integrated circuit). For example, the M value can be set to 255 and the N value can be set to any value from 0 to 255. For example, it can be set to 0 first. In this case, the power supply voltage value is continuously reduced, and the power supply voltage value and the PSM value are recorded until the test result of the integrated circuit is abnormal. The PSM value when the last state is normal is obtained, thereby obtaining a set of corresponding PSM values ​​and M / N values, until each set of corresponding PSM values ​​and M / N values ​​is obtained, and a mapping relationship between the two is obtained. Therefore, when the integrated circuit is actually working, the corresponding M / N value, that is, the current maximum allowable load, can be obtained based on the obtained PSM value.

[0061] Of course, the above mapping relationship needs to be stored in the corresponding device in advance, which can be a one-time programmable circuit 213 (shown in FIG. Figure 2 middle).

[0062] The one-time programmable circuit 213 can well save and protect the obtained mapping relationship, which can specifically be load equivalent model parameters or other types of data, thereby improving data security.

[0063] In a specific embodiment, the current maximum allowable load acquisition unit 212 can be a microcontroller unit, which is suitable for processing internal information of the integrated circuit chip. When the integrated circuit chip is initialized, the microcontroller unit will read the pre-stored load equivalent model parameters and other data representing the mapping relationship between the equivalent load and the load from the one-time programmable circuit 213, and then construct a load equivalent model based on the load equivalent model parameters and other data. The load equivalent model can be in the form of a table or a fitting curve.

[0064] Of course, the data representing the mapping relationship between the equivalent load amount and the load amount, such as the load equivalent model parameters, may be data obtained with or without considering the test temperature information.

[0065] Thus, in one embodiment, when the integrated circuit is powered on, the microcontroller unit reads the data representing the mapping relationship stored in the one-time programmable circuit 213 and establishes a load equivalent model. In the actual operation of the integrated circuit, the power supply monitor (PSM) 2110 monitors the integrated circuit in real time to obtain the PSM value and sends it to the microcontroller unit for processing. The microcontroller unit processes the real-time monitored PSM value according to the pre-established load equivalent model. The processing may include looking up a table or obtaining relevant parameter values ​​through a fitting curve to obtain the M / N value corresponding to the real-time monitored PSM value. After obtaining the corresponding M / N value, the microcontroller unit sends the M / N value to the load state adjustment signal generating module 22.

[0066] After acquiring the M / N value, the load state adjustment signal generating module 22 generates a load state adjustment signal according to the M / N value.

[0067] In a specific embodiment, the load state adjustment signal generating module 22 may include a most average M / N gating signal generating module 221, which is suitable for generating the most average load state adjustment signal according to the M / N value, and sending the generated load state adjustment signal to the state adjustment module 23.

[0068] After receiving the load state adjustment signal, the state adjustment module 23 can control the computing core module 1 to adjust the state of the internal device 19 of the integrated circuit according to the load state adjustment signal, thereby adjusting the size of the integrated circuit load.

[0069] Specifically, the state of the device 19 inside the integrated circuit can be adjusted by controlling the data flow.

[0070] In a specific embodiment, the state adjustment module 23 may be a main channel gating module, that is, the data flow of the computing core module 1 is controlled through the main channel gating module to adjust the state of the integrated circuit load.

[0071] The operation core module 1 is suitable for transmitting various data in the integrated circuit according to the timing to realize the operation on the data.

[0072] Based on the above structure, the integrated circuit load adjustment method provided in the embodiment of the present application is described in detail below:

[0073] Please combine Figure 2 , Figure 3 refer to Figure 4 , Figure 4 A schematic diagram of an optional flow chart of an integrated circuit load adjustment method provided in an embodiment of the present application.

[0074] like Figure 4As shown, the integrated circuit load adjustment method provided in the embodiment of the present application may include the following steps:

[0075] Step S40: Obtain the current maximum allowable load of the integrated circuit.

[0076] In order to adjust the load of an integrated circuit, the current maximum allowable load of the integrated circuit must first be obtained. After obtaining the current maximum allowable load of the integrated circuit, the load state of the integrated circuit can be adjusted according to the current maximum allowable load.

[0077] Specifically, the current maximum allowable load can be obtained through a device that can directly obtain the maximum allowable load, or can be obtained through a device that can indirectly reflect the maximum allowable load.

[0078] In a specific implementation, in order to improve the convenience of obtaining the current maximum allowable load, the maximum allowable load is obtained through a device that can indirectly reflect the maximum allowable load. Specifically, the step of obtaining the current maximum allowable load of the integrated circuit may include:

[0079] Obtaining the current maximum equivalent load of the integrated circuit;

[0080] The current maximum allowable load is obtained according to the current maximum equivalent load and a pre-built load equivalent model.

[0081] It is easy to understand that the load equivalent model refers to a model of the equivalent relationship between the current maximum equivalent load and the current maximum allowable load; the pre-built load equivalent model described in this article refers to a model that is built before the current maximum allowable load is obtained based on the current maximum equivalent load. Specifically, it can be built before the current maximum equivalent load, such as when the integrated circuit is powered on; it can also be built at the same time as the current maximum equivalent load; or it can be built after obtaining the current maximum equivalent load and before obtaining the current maximum allowable load.

[0082] After obtaining the current maximum equivalent load and the load equivalent model, the current maximum allowable load can be obtained based on the corresponding relationship.

[0083] Specifically, the PSM may be used to obtain the current maximum equivalent load, that is, the PSM value. When the integrated circuit is working, the PSM value may be obtained by using the PSM to obtain the aforementioned current maximum equivalent load.

[0084] The current maximum allowable load can be expressed in a variety of ways. In a specific embodiment, as described above, the current maximum allowable load can be expressed by an M / N value, wherein M represents the number of cycles and N represents the number of valid control signals. The M / N value represents the number of valid control signals generated in the number of cycles, and the load state of the integrated circuit can be adjusted based on the generated valid control signals.

[0085] Using the M / N value to represent the current maximum allowable load can not only represent the current maximum allowable load, but also directly generate a load state adjustment signal based on the M / N value, thereby reducing the difficulty of generating the load state adjustment signal and further adjusting the size of the integrated circuit load.

[0086] In this way, the constructed load equivalent model may be a model of the corresponding relationship between the PSM value and the M / N value, and the obtained current maximum allowable load is the M / N value.

[0087] It can be seen that by utilizing the current maximum equivalent load and the load equivalent model, the current maximum allowable load can be conveniently obtained based on the current maximum equivalent load, and the restrictions on the devices for obtaining the current maximum allowable load can be relaxed. Any device that can obtain the mapping relationship between the current maximum equivalent load and the current maximum allowable load can be used, thereby increasing the range of choices. At the same time, it also provides the possibility of selecting devices with higher accuracy and lower cost, which can improve the accuracy of obtaining the current maximum allowable load and reduce the cost of integrated circuits.

[0088] Step S41: generating a load state adjustment signal of the integrated circuit according to the current maximum allowable load.

[0089] After the current maximum allowable load is obtained, a load state adjustment signal is generated based on the current maximum allowable load.

[0090] It is easy to understand that when the current maximum allowable load is represented by the M / N value, the M / N value can be used to generate a load state adjustment signal. In a specific implementation, the load state adjustment signal can be a most average M / N gating signal.

[0091] The most average M / N gating signal may be generated in many ways. In a specific implementation, the most average M / N gating signal may be generated by changing a value stored in a register.

[0092] Step S42: adjusting the load state of the integrated circuit according to the load state adjustment signal.

[0093] By obtaining the load state adjustment signal, the load state of the integrated circuit can be adjusted. Specifically, the data transmission of one clock cycle in the data transmission stream can be suspended so that the processing of the relevant operation unit of the integrated circuit can be suspended for one clock cycle, thereby realizing the change of the state of the integrated circuit load, thereby realizing the control of the number of internal devices of the integrated circuit in the working state at the same time.

[0094] Since the load state adjustment signal is generated based on the current maximum allowable load, and the current maximum allowable load is acquired in real time for a specific integrated circuit, the state of the adjusted integrated circuit can be placed in the state of the current maximum allowable load.

[0095] It can be seen that the integrated circuit load adjustment method provided in the embodiment of the present application adjusts the load state by acquiring the current maximum allowable load of the specific integrated circuit in real time and generating a load state adjustment signal. It can be implemented based on the individual integrated circuit, so that the integrated circuit can adjust the load of the integrated circuit according to the real-time voltage drop of the integrated circuit, so that the integrated circuit always operates at the maximum load allowed by the current voltage drop, thereby improving the performance of each integrated circuit under the corresponding DIDT voltage drop.

[0096] From the steps of obtaining the current maximum allowable load of the integrated circuit mentioned above, it can be seen that in order to obtain the current maximum allowable load of the integrated circuit, it is necessary to first construct a load equivalent model. In a specific implementation, the load equivalent model can be constructed by pre-stored corresponding test loads and test equivalent loads.

[0097] Specifically, the steps of constructing a load equivalent model may include:

[0098] Acquire the pre-stored test equivalent load of the integrated circuit under each test load condition, at the minimum voltage at which the integrated circuit can work normally, and obtain the test equivalent load corresponding to each test load;

[0099] The load equivalent model is constructed according to the test load amounts and the test equivalent load amounts that correspond to each other.

[0100] The corresponding test load and test equivalent load are obtained in advance and stored. When it is necessary to build a load equivalent model, they can be read out and used.

[0101] In some embodiments, the corresponding test load and test equivalent load can be stored in the one-time programmable circuit 213. The one-time programmable circuit 213 can well save and protect the obtained load equivalent model parameters, and will not damage the parameter data due to improper operation, thereby improving data security.

[0102] In a specific embodiment, the test load can be represented by an M / N value, wherein M represents the number of cycles and N represents the effective control signal amount.

[0103] In a specific embodiment, the test equivalent load amount can be represented by a PSM value monitored by a power supply monitor PSM.

[0104] The corresponding test load and test equivalent load can be obtained by presetting the test load, i.e., the M / N value, and adjusting the voltage to obtain the critical test equivalent load. This application takes the M value as 255 and the N value as 0 to 255 as an example. For details, please refer to Figure 5 , Figure 5 A flowchart for obtaining corresponding test loads and test equivalent loads provided in an embodiment of the present application.

[0105] As shown in the figure, the steps of obtaining the corresponding test load and test equivalent load may include:

[0106] Step S50: Obtain the current test load.

[0107] In order to ensure the comprehensiveness of the test, the current test load can be set in descending order, so the current test load obtained is also adjusted in descending order. For this reason, the current test load obtained for the first time is M=255, N=0, which means that the number of valid control signals generated every 255 cycles is 0, that is, all devices inside the integrated circuit are in working condition.

[0108] Step S51: Obtain the current voltage.

[0109] During the first test, the current voltage may be randomly determined; during subsequent cycles, in order to improve efficiency, the voltage at the last successful test during the previous test may be selected.

[0110] Step S52: Determine whether the state of the integrated circuit under the current test load and current voltage state is normal, and read the corresponding test equivalent load. If normal, execute step S53; if abnormal, execute step S54.

[0111] After obtaining the current test load and the current voltage, the integrated circuit is operated under the current test load and the current voltage state, the state of the integrated circuit is judged, and different steps are executed according to the state, namely step S53 and step S54, and the test equivalent load is read at the same time, so as to obtain the required test equivalent load later.

[0112] Step S53: lower the voltage value of the current voltage and go to step S52.

[0113] When the test result is normal, the voltage value of the current voltage is further reduced to prepare for obtaining a critical voltage value and testing an equivalent load.

[0114] Specifically, the voltage may be reduced at a fixed value or in proportion. After the voltage is reduced, step S52 is continued to determine the state of the integrated circuit until the state of the integrated circuit becomes abnormal, and step S54 is executed.

[0115] Step S54: Acquire the test equivalent load of the integrated circuit when the last state is normal, and obtain the current test equivalent load corresponding to the current test load.

[0116] When the test result is abnormal, the test equivalent load of the integrated circuit when the last state is normal is obtained. When the test equivalent load is a PSM value, that is, the PSM value monitored by the integrated circuit using the power supply monitor PSM when the last state is normal is obtained, and the current test equivalent load corresponding to the current test load is obtained, that is, the PSM value corresponding to M=255, N=0 is obtained, which can be recorded as PSM 0 .

[0117] Step S55: After executing step S54, determine whether the test is completed. If completed, execute step S57; otherwise, execute step S56.

[0118] The test process is to construct a load equivalent model. Therefore, in one embodiment, it is necessary to determine whether all load conditions have been traversed, that is, to determine whether N is equal to 255. When N is equal to 255, execute step S57 to end the test. When N is not equal to 255, execute step S56.

[0119] Step S56: adjusting the current test load and the current voltage, and using them as new current test load and new current voltage.

[0120] Adjusting the current test load may be adjusting the load by continuously decreasing it from the full load of the integrated circuit.

[0121] In a specific embodiment, adjusting the current test load is adjusting the value of M / N, fixing the value of M to 255, adding 1 to the value of N, and using the adjusted value of M / N as the new current test load in step S50.

[0122] The current voltage may be adjusted to the voltage value recorded in the previous cycle when the state was normal for the last time, and this voltage value is used as the current voltage in step S51 to shorten the test time.

[0123] Then continue to execute step S52 and subsequent steps.

[0124] Step S57: The test ends.

[0125] When the test is completed, the PSM corresponding to M=255 and N=0 is obtained by executing the test equivalent load acquisition process corresponding to the test load. 0 (255 / 0--PSM 0 ); PSM corresponding to M = 255 and N = 1 1 (255 / 1--PSM 1 ); PSM corresponding to M = 255 and N = 2 2 (255 / 2--PSM 2 ); and so on, until the final PSM corresponding to M = 255, N = 255 255 (255 / 255--PSM 255 ).

[0126] It can be seen that by executing the test equivalent load acquisition process corresponding to the test load, the PSM values ​​corresponding to N from 0 to 255 when M is fixed to 255 can be obtained, and the PSM value can reflect the voltage value, that is, the M / N value corresponding to different voltage values ​​can be indirectly obtained through the correspondence between the M / N value and the PSM value.

[0127] After each test equivalent load corresponding to each test load is obtained, a mapping relationship between the test load and each test equivalent load is established according to each test load and the corresponding test equivalent load.

[0128] Of course, in other embodiments, other values ​​may be selected to obtain the corresponding test equivalent load.

[0129] After obtaining the test load amounts and the corresponding test equivalent load amounts of each group, they are stored in the corresponding storage units, and when it is necessary to construct the load equivalent model, they can be read therefrom.

[0130] In one embodiment, curve fitting can be performed with the corresponding test loads and the test equivalent loads as independent variables and dependent variables to obtain a fitting curve and the load equivalent model.

[0131] It can be seen that, by pre-storing the corresponding test loads and test equivalent loads, the load equivalent model can be directly obtained, providing a basis for the subsequent acquisition of the current maximum load.

[0132] In another specific implementation, the load equivalent model may also be constructed using load equivalent model parameters, that is, the step of constructing the load equivalent model may also include:

[0133] Acquire pre-stored load equivalent model parameters; and construct the load equivalent model according to the load equivalent model parameters.

[0134] It should be noted that the load equivalent model parameters described in this article refer to parameters representing the load equivalent model type and parameters required to construct the load equivalent model.

[0135] For example, when the load equivalent model is a quadratic polynomial, the load equivalent model parameters include the expression of the quadratic polynomial (y = ax 2 +bx+c), and the parameters of the quadratic polynomial: a, b, and c.

[0136] It is easy to understand that the load equivalent model parameters are acquired and stored in advance, and when it is necessary to construct the load equivalent model, they can be read out and used.

[0137] In some embodiments, the load equivalent model parameters can be stored in a one-time programmable circuit 213. The one-time programmable circuit 213 can well preserve and protect the obtained load equivalent model parameters, and will not damage the parameter data due to improper operation, thereby improving the security of the load equivalent model parameters.

[0138] In some other embodiments, the load equivalent model parameters may also be stored in a general storage unit of the integrated circuit.

[0139] After obtaining the load equivalent model parameters, the corresponding load equivalent model can be constructed based on the load equivalent model parameters.

[0140] For example, in the aforementioned case: when the parameters representing the quadratic polynomial are obtained, indicating that the load equivalent model is a quadratic polynomial, and then the parameter values ​​at each position in the quadratic polynomial are obtained, the load equivalent model can be directly constructed.

[0141] It can be seen that constructing a load equivalent model through load equivalent model parameters, on the one hand, requires less data to be stored, reducing the storage space occupied; on the other hand, it can also easily realize the construction of the model with less calculation amount.

[0142] It can be seen that the prerequisite for constructing a load equivalent model is to first obtain the pre-stored load equivalent model parameters. In a specific implementation, the load equivalent model parameters corresponding to each integrated circuit can be obtained according to the following steps:

[0143] The test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load condition is obtained, and the test equivalent load corresponding to each test load is obtained.

[0144] The load equivalent model parameters are obtained according to the mapping relationship between each of the test load amounts and each of the test equivalent load amounts.

[0145] For the specific steps of obtaining the corresponding test loads and test equivalent loads, please refer to the above description and will not be repeated here.

[0146] After obtaining the test equivalent loads corresponding to the test loads, a mapping relationship between the test loads and the test equivalent loads is established according to the test loads and the corresponding test equivalent loads, and the load equivalent model parameters are obtained according to the mapping relationship between the test loads and the test equivalent loads.

[0147] According to the obtained corresponding test load and test equivalent load, curve fitting is performed to obtain a fitting function. It is easy to understand that the fitting function is the load equivalent model, and the parameters of the fitting function are the parameters of the load equivalent model.

[0148] The load equivalent model parameters are extracted, and the obtained load equivalent model parameters are stored in a storage unit of the integrated circuit.

[0149] In this way, by obtaining the test power supply voltages of the integrated circuit and the test voltage equivalent values ​​corresponding to the test power supply voltages when the internal devices of the integrated circuit are not working, it is convenient to obtain the voltage equivalent model parameters to meet the storage requirements and subsequent use requirements.

[0150] When obtaining the load equivalent model, in order to improve the accuracy of the obtained load equivalent model parameters, different test temperatures can also be set to obtain the test equivalent load amounts corresponding to the test load amounts at different test temperatures. This is because the main factors affecting the state of the integrated circuit include process, voltage and temperature. The process has been determined after the integrated circuit is manufactured. Therefore, in order to obtain a more accurate voltage equivalent model during testing, thereby more accurately estimating the voltage of the internal devices of the integrated circuit, it is also necessary to consider the influence of temperature.

[0151] For example, five temperature test points within the test temperature range can be selected, namely T1, T2, T3, T4, and T5, where T1 and T5 are the endpoints of the lowest and highest temperatures corresponding to the test temperature range, respectively, and T2, T3, and T4 are evenly distributed between T1 and T5. After setting the test temperature points, the test equivalent load acquisition process corresponding to the above test load is executed to obtain the test equivalent loads corresponding to the test temperature points T1, T2, T3, T4, and T5, respectively, that is, the following can be obtained:

[0152] When the test temperature is T1, the corresponding test loads and the equivalent test loads.

[0153] When the test temperature is T2, the corresponding test loads and the equivalent test loads.

[0154] When the test temperature is T3, the corresponding test loads and the equivalent test loads.

[0155] When the test temperature is T4, the corresponding test loads and the equivalent test loads.

[0156] When the test temperature is T5, the corresponding test loads and the equivalent test loads.

[0157] Then, curve fitting is performed separately to obtain fitting functions equal to the number of test temperatures. Because there are multiple test temperatures, it is easy to understand that each temperature will obtain a load equivalent model, and a total of multiple load equivalent models will be obtained. The parameters of each fitting function are the parameters of each load equivalent model.

[0158] Parameters of each load equivalent model are extracted respectively, and the load equivalent model parameters at different test temperatures are obtained, and the obtained load equivalent model parameters at different temperatures are stored together with the corresponding temperature in a storage unit of the integrated circuit.

[0159] Of course, each test load amount and each test equivalent load amount corresponding to each other at different temperatures may also be directly stored.

[0160] In this way, a more accurate load equivalent model can be constructed by limiting the corresponding test temperature.

[0161] In order to improve the accuracy of the current maximum equivalent load amount obtained when constructing the load equivalent model at different temperatures, the step of obtaining the current maximum equivalent load amount of the integrated circuit load adjustment method provided in the embodiment of the present application may include:

[0162] The current maximum equivalent load and current temperature of the integrated circuit are obtained.

[0163] Specifically, in order to obtain the current temperature, a temperature sensor may be integrated in the integrated circuit and connected near the current maximum equivalent load acquisition unit.

[0164] It is easy to understand that the current maximum equivalent load and current temperature of the integrated circuit are the current maximum equivalent load and current temperature when the integrated circuit operates normally, and the integrated circuit load is not zero at this time.

[0165] The step of obtaining the current maximum allowable load according to the current maximum equivalent load and the pre-built load equivalent model includes:

[0166] The current maximum allowable load is obtained according to the current maximum equivalent load, the current temperature and a pre-built load equivalent model corresponding to each test temperature.

[0167] Specifically, the current maximum allowable load is obtained based on the current maximum equivalent load, the current temperature and the pre-built load equivalent models corresponding to each test temperature. The corresponding load equivalent model can be obtained based on the current temperature, and then the current maximum allowable load is obtained in combination with the current maximum equivalent load.

[0168] In this way, when constructing load equivalent models at different temperatures, a suitable load equivalent model can be selected to obtain the current maximum allowable load, thereby improving the accuracy of the obtained current maximum allowable load.

[0169] Since it is difficult to achieve a one-to-one correspondence between the current temperature and the temperature corresponding to the load equivalent model, in order to obtain the current maximum allowable load of each current temperature under the condition of a limited load equivalent model, in a specific implementation manner, the integrated circuit load adjustment method provided in the embodiment of the present application, according to the current maximum equivalent load, the current temperature and the pre-constructed load equivalent model corresponding to each test temperature, the step of obtaining the current maximum allowable load may include:

[0170] Obtain the temperature interval between each of the test temperatures; determine the temperature interval corresponding to the current temperature, obtain the current temperature interval, and obtain the temperature load equivalent model in each of the load equivalent models corresponding to the current temperature interval; obtain the current maximum allowable load at the interval endpoint based on the current maximum equivalent load and each of the temperature load equivalent models; obtain the current maximum allowable load based on the current temperature, the endpoint temperature of the current temperature interval, and the current maximum allowable load at the interval endpoint.

[0171] According to the above steps, first obtain the temperature range between each of the test temperatures. From the above example, it can be seen that if the selected test temperature points are T1, T2, T3, T4, and T5, the temperature range is T1-T2, T2-T3, T3-T4, and T4-T5.

[0172] Then determine the temperature interval corresponding to the current temperature, obtain the current temperature interval, obtain the temperature load equivalent model in each of the load equivalent models corresponding to the current temperature interval, assume that the current temperature is T6, within the temperature range of T1-T2, then the temperature interval T1-T2 is the current temperature interval, and obtain the temperature load equivalent model in each of the load equivalent models corresponding to the current temperature interval, that is, obtain the load equivalent models T1-load equivalent model and T2-load equivalent model corresponding to T1 and T2.

[0173] Next, according to the current maximum equivalent load and each of the temperature load equivalent models, the current maximum allowable load of the interval endpoint is obtained, that is: after obtaining the T1-load equivalent model and the T2-load equivalent model, the current maximum allowable load T1-M / N and T2-M / N values ​​of the endpoints corresponding to T1 and T2 can be obtained according to the T1-load equivalent model, T2-load equivalent model and the current maximum equivalent load (which can be the PSM value monitored in real time by the power supply monitor (PSM) 2110).

[0174] Finally, the current maximum allowable load is obtained according to the current temperature, the endpoint temperature of the current temperature interval and the current maximum allowable load at the interval endpoint, that is, the current maximum allowable load T6-M / N corresponding to T6 is obtained according to the current temperatures T6, T1, T2, T1-M / N, and T2-M / N. In a specific embodiment, the obtaining method includes:

[0175] Linear interpolation method: It is assumed that the line segments where T1, T2, and T6 are located have the same slope as the line segments where T1-M / N, T2-M / N, and T6-M / N are located. The calculation formula is:

[0176] (T6-T1) / (T2-T1)=((T6-M / N)-(T1-M / N)) / ((T2-M / N)-(T1-M / N))

[0177] The value of the current maximum allowable load T6-M / N can be obtained from the above formula.

[0178] You can also directly use the average method to obtain the current maximum allowable load T6-M / N value. The calculation formula is:

[0179] T6-M / N=((T2-M / N)+(T1-M / N)) / 2

[0180] It can be seen that the current maximum allowable load corresponding to any current temperature can be obtained through the above method, and the acquisition method is simple and diverse.

[0181] Through the above method, the load equivalent model corresponding to each test temperature is obtained according to the load equivalent model parameters corresponding to each test temperature, and the current maximum allowable load is obtained according to the current maximum equivalent load, the current temperature and the pre-constructed load equivalent model corresponding to each test temperature. It can be seen that obtaining the current maximum allowable load can accurately indicate the real-time load situation of the integrated circuit under actual application conditions, which provides a basis for the subsequent adjustment of the load of the integrated circuit based on the individual integrated circuit according to the real-time voltage drop of the integrated circuit, so that the integrated circuit always works under the maximum load condition, and improves the performance of each integrated circuit under the corresponding DIDT voltage drop condition.

[0182] In a specific implementation, in order to facilitate obtaining the load state adjustment signal, when the current maximum allowable load includes the M / N value, step S41: generating the load state adjustment signal of the integrated circuit according to the current maximum allowable load may include:

[0183] The most average M / N gating signal generating module of the integrated circuit generates a load state adjustment signal of the integrated circuit according to the M / N value.

[0184] When the current maximum allowable load is expressed by an M / N value, since M represents the number of cycle periods and N represents the number of effective control signals, the M / N value represents the number of effective control signals generated in the number of cycle periods, and the state of the internal device 19 of the integrated circuit can be adjusted according to the effective control signals generated. Therefore, different numbers of effective control signals can be obtained by taking different values ​​of the M / N value.

[0185] The most average M / N gating signal can ensure that N valid gating signals are generated in the most average manner in M ​​cycles. Therefore, the subsequent adjustment of the state of the internal device 19 of the integrated circuit can be more average, thereby improving the working performance of the integrated circuit.

[0186] Specifically, the most average M / N gating signal generating module may include a cycle counter and a valid control signal counter.

[0187] The step of generating the load state adjustment signal of the integrated circuit according to the M / N value by the most average M / N gating signal generating module of the integrated circuit may include:

[0188] When the most average M / N gating signal generating module of the integrated circuit obtains the M / N value and the cycle count value of the cycle counter is equal to M, the cycle count value of the cycle counter is adjusted to 0, and the control count value of the effective control signal counter is adjusted to -N;

[0189] Determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value by 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter to adjust the control count value of the effective control signal counter.

[0190] It can be seen that the cycle counter is used to record the number of cycle periods in the M / N value, and the effective control signal counter is used to record the control count value generated based on the value of N in the M / N value.

[0191] When the most average M / N gating signal generating module of the integrated circuit obtains the M / N value, and the cycle count value of the cycle counter is equal to M, the cycle count value of the cycle counter and the control count value of the effective control signal counter are adjusted. It can be seen that after the most average M / N gating signal generating module of the integrated circuit obtains the M / N value, the value of the effective control signal counter is not adjusted immediately, but the cycle count value of the cycle counter is first determined. Only when the cycle count value of the cycle counter is equal to M, the control count value of the effective control signal counter is adjusted. In this way, it can be ensured that when the entire process of generating the load state adjustment signal of the integrated circuit according to the effective control signal corresponding to the previous M / N value has been completed, a new load state adjustment signal of the integrated circuit is generated according to the obtained new M / N value, thereby improving the rationality of control.

[0192] And when adjusting the cycle count value of the cycle counter and the control count value of the effective control signal counter, the cycle count value of the cycle counter is adjusted to 0, and the control count value of the effective control signal counter is adjusted to -N. Then, based on the adjusted control count value, the value of the highest bit of the effective control signal counter is determined, so as to obtain the load state adjustment signal of the integrated circuit. That is to say, the value of the highest bit of the effective control signal counter is used as the load state adjustment signal. If the control count value is a negative number, the value of the highest bit is 1. If the control count value is a positive number, the value of the highest bit is 0, thereby generating different load state adjustment signals.

[0193] However, as time goes by, the clock cycle needs to change, and the load state adjustment signal also needs to be adjusted according to the clock cycle. Therefore, at the rising edge of each clock, the cycle count value needs to be adjusted by 1 to realize the counting of the cycle period, and it is necessary to obtain the corresponding adjustment rule based on the value of the highest bit of the effective control signal counter to adjust the control count value of the effective control signal counter to generate the load state adjustment signal corresponding to the next clock cycle.

[0194] It can be seen that after the cycle count value of the cycle counter is adjusted to 0, the cycle count value is adjusted to add 1 at the rising edge of each clock, so that the counting of the cycle can be realized, and based on the corresponding adjustment rules, the control count value of the effective control signal counter is adjusted to ensure the generation of the load state adjustment signal corresponding to the next clock cycle, thereby realizing the state adjustment of the internal device 19 of the integrated circuit.

[0195] In a specific implementation, in order to ensure the accuracy of the load state adjustment signal generated by each clock cycle and to ensure that the most average M / N gating signal can be easily obtained, the value of the highest bit of the effective control signal counter is determined to obtain the load state adjustment signal of the integrated circuit, and at the rising edge of each clock, the cycle count value is adjusted to add 1, and according to the value of the highest bit of the effective control signal counter, the corresponding adjustment rule is obtained, and the step of adjusting the control count value of the effective control signal counter may include:

[0196] When it is determined that the value of the highest bit of the effective control signal counter is 1, the effective control signal of the load state adjustment signal of the integrated circuit is obtained, and the cycle count value is adjusted to be increased by 1 at the rising edge of each clock, and according to the adjustment rule corresponding to the value of the highest bit of the effective control signal counter being 1, the control count value of the effective control signal counter is adjusted to be increased by MN.

[0197] When it is determined that the value of the highest bit of the valid control signal counter is 0, an invalid control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the valid control signal counter being 0, the control count value of the valid control signal counter is adjusted to be reduced by N.

[0198] That is, according to the different values ​​of the highest bit, the counting value is adjusted differently at the rising edge of each clock. If the value of the highest bit is 1, the counting value is increased by MN. If the value of the highest bit is 0, the counting value is decreased by N. This makes it easy to obtain the most average M / N gating signal.

[0199] To understand the above adjustment process, please refer to Figure 6 , Figure 6 A flowchart of obtaining the most average control signal of the integrated circuit load adjustment method provided in an embodiment of the present application.

[0200] In the embodiment of the present application, for the convenience of explanation, the cycle count value of the cycle counter is represented by Y, the control count value of the effective control signal counter is represented by X, and the effective control signal counter includes 8 bits.

[0201] Step S600: the integrated circuit is reset or M / N is obtained, and when Y=M, X<=0-N, Y<=0.

[0202] When the integrated circuit is reset or the cycle corresponding to the previous M / N value has been completed, a new M / N value is obtained, or there is no new M / N value to maintain the current M / N value, the control count value X of the effective control signal counter is adjusted to -N, and the cycle count value Y is adjusted to 0.

[0203] Step S601: Determine whether X[8] == 1, if yes, execute step S602, if not, execute step S605.

[0204] Determine whether the highest bit of the effective control signal counter is 1 when the control count value X is -N. When X[8] is 1, it indicates that the control count value is a negative number. When X[8] is not 1, it indicates that the control count value is a positive number. If X[8] == 1, that is, -N is a negative number and N is a positive number, that is, N effective control signals need to be generated in M ​​cycles, and execute step S602; otherwise, N is 0, X[8] is not 1, and 0 effective control signals need to be generated in M ​​cycles, working at full load, and execute step S605.

[0205] Step S602: Obtaining a valid control signal of the load state adjustment signal of the integrated circuit, EN==1.

[0206] When it is determined that the highest bit value of the effective control signal counter is 1, the effective control signal of the load state adjustment signal of the integrated circuit is obtained, and the load state adjustment signal effective control signal EN==1 is generated.

[0207] Through the above steps, it can be seen that when the integrated circuit is reset or obtains M / N, and Y=M, the control count value of the effective control signal counter X will be adjusted to -N. If N is a positive number, then X[8]==1. According to X[8]==1, a load state adjustment signal effective control signal EN==1 will be immediately generated. It can be seen that once the integrated circuit load state needs to be adjusted, an effective control signal will be immediately generated, and the response will be timely, so that the load of the integrated circuit can be adjusted in time.

[0208] Step S603: X<=X+(MN).

[0209] When X[8]==1, at the rising edge of the clock, the control count value of the effective control signal counter is adjusted to increase by MN, that is, the control count value X of the effective control signal counter is adjusted to X+(MN) of the previous cycle.

[0210] When X=-N in the previous cycle, the corresponding value is -N+MN, and then the process turns to step S601 to perform a new round of judgment. Of course, if M>2N, the control count value is a positive number, then X[8]==0.

[0211] Of course, at the rising edge of the clock, the cycle count value Y of the cycle counter needs to be adjusted, so the following is also executed at the same time:

[0212] Step S604: Y<=Y+1

[0213] At the rising edge of each clock, the cycle count value Y of the cycle counter is adjusted to increase by 1, that is, Y<==Y+1.

[0214] It is easy to understand that the adjustment of the cycle count value of the cycle counter is only related to the clock cycle, and after the adjustment, it is used as a judgment on whether to execute step S600 only when its value reaches M. At other times, it will not cause other operations.

[0215] Furthermore, there is no strict order in which steps S602 to S604 are executed, and they can be executed simultaneously.

[0216] Step S605: Obtaining an invalid control signal of the load state adjustment signal of the integrated circuit, EN==0.

[0217] When it is determined that the highest bit value of the valid control signal counter is 0, an invalid control signal of the load state adjustment signal of the integrated circuit is obtained, and a load state adjustment signal valid control signal EN==0 is generated.

[0218] In this case, there is no need to adjust the load state of the integrated circuit, so an invalid control signal is generated to ensure that the internal devices 19 of each integrated circuit work normally in this clock cycle.

[0219] Step S606: X<=XN.

[0220] When X[8]==0, at the rising edge of the clock, the control count value of the effective control signal counter is adjusted to decrease by N, that is, the control count value of the effective control signal counter X is adjusted to XN of the previous clock cycle, and the process goes to step S601.

[0221] Of course, in this case, at the rising edge of the clock, the cycle count value Y of the cycle counter also needs to be adjusted, so step S604 is also executed at the same time.

[0222] Until a new cycle arrives, that is, Y==M, step S600 is continued to be executed based on the latest M / N value according to whether a new M / N value is received.

[0223] Of course, there is no order in which step S605, step S606 and step S604 are executed, and they can be executed simultaneously.

[0224] According to the above steps, for example, assuming that the M / N value is 255 / 85, that is, within 255 cycles, 85 effective control signals of the load state adjustment signal are generated, that is, 85 EN==1 are generated.

[0225] First loop:

[0226] Step S600: when the M / N value is 255 / 85 and Y=255, the control count value of the effective control signal counter X is adjusted to -85, X<=-85, and the cycle count value is 0, Y<=0.

[0227] Step S601: Determine whether X[8]==1. Since the control count value X of the current valid control signal counter is -85, X[8]==1. Then, steps S602-S604 are executed.

[0228] Step S602: Obtaining the effective control signal of the load state adjustment signal of the integrated circuit, EN==1, and adjusting the state of the internal device 19 of the integrated circuit.

[0229] At the same time, step S603: X<=X+(MN).

[0230] At this time, the control count value of the effective control signal counter X is adjusted to -85+255-85=85.

[0231] Step S604: Y<=Y+1

[0232] The cycle count value Y of the cycle counter is adjusted to increase by 1, that is, Y<=0+1.

[0233] Second loop:

[0234] Step S601: Determine whether X[8]==1. Since the control count value of the current valid control signal counter X is 85, X[8] is not 1. Then, steps S605, S606 and S604 are executed.

[0235] Step S605: Obtaining a valid control signal of the load state adjustment signal of the integrated circuit, EN==0.

[0236] Step S606: X<=XN.

[0237] At this time, the control count value of the effective control signal counter X is adjusted to 85-85=0.

[0238] Step S604: Y<=Y+1

[0239] The cycle count value Y of the cycle counter is adjusted to increase by 1, that is, Y<=1+1.

[0240] Third cycle:

[0241] Step S601: Determine whether X[8]==1. Since the control count value of the current valid control signal counter X is 0, X[8] is not 1. Then, steps S605, S606 and S604 are executed.

[0242] Step S605: Obtaining a valid control signal of the load state adjustment signal of the integrated circuit, EN==0.

[0243] Step S606: X<=XN.

[0244] At this time, the control count value of the effective control signal counter X is adjusted to 0-85=-85.

[0245] Step S604: Y<=Y+1

[0246] The cycle count value Y of the cycle counter is adjusted to increase by 1, that is, Y<=2+1.

[0247] Fourth cycle:

[0248] Step S601: Determine whether X[8]==1. Since the control count value of the current valid control signal counter X is -85, X[8]==1. Therefore, X[8]==1. Then, execute steps S602-S604.

[0249] Step S602: Obtaining the effective control signal of the load state adjustment signal of the integrated circuit, EN==1, and adjusting the state of the internal device 19 of the integrated circuit.

[0250] At the same time, step S603: X<=X+(MN).

[0251] At this time, the control count value of the effective control signal counter X is adjusted to -85+255-85=85.

[0252] Step S604: Y<=Y+1

[0253] The cycle count value Y of the cycle counter is adjusted to increase by 1, that is, Y<=3+1.

[0254] The fourth cycle is the same as the first cycle, that is, one load state adjustment signal valid control signal EN==1 is generated every three cycles until 255 cycles are completed and 85 load state adjustment signal valid control signals EN==1 are generated.

[0255] It can be seen that the most average M / N control signal acquisition method provided in the present application can generate the most average effective control signal without generating dense and long-term effective control signals, thereby ensuring that the integrated circuit always operates in a high-performance state.

[0256] After obtaining the load state adjustment signal (including the most average M / N control signal), it is necessary to further adjust the load state of the integrated circuit based on the load state adjustment signal. In a specific implementation, in order to facilitate the adjustment of the load state of the integrated circuit, step S42: adjusting the load state of the integrated circuit according to the load state adjustment signal may include:

[0257] According to the load state adjustment signal, the state of the main channel gating module arranged between the upstream data processing module and the downstream data processing module of the integrated circuit is adjusted to control the data transmission between the upstream data processing module and the downstream data processing module.

[0258] That is, a main channel gating module is set between the upstream data processing module and the downstream data processing module of the integrated circuit. The state of the main channel gating module can be adjusted by the load state adjustment signal, thereby controlling the data transmission between the upstream data processing module and the downstream data processing module.

[0259] In this way, through the main channel gating module, the data transmission between the upstream data processing module and the downstream data processing module can be easily controlled. The failure of data transmission is equivalent to the internal devices of the integrated circuit being in a non-working state, thereby achieving the adjustment of the load state of the integrated circuit in a simple manner.

[0260] In a specific implementation, the step of adjusting the state of a main channel gating module disposed between an upstream data processing module and a downstream data processing module of the integrated circuit according to the load state adjustment signal, and controlling data transmission between the upstream data processing module and the downstream data processing module may specifically include:

[0261] According to the effective control signal of the load state adjustment signal, the state of the main channel gating module is adjusted to a non-conducting state, and the data transmission between the upstream data processing module and the downstream data processing module is stopped; according to the invalid control signal of the load state adjustment signal, the state of the main channel gating module is adjusted to a conducting state, and the data transmission between the upstream data processing module and the downstream data processing module is carried out.

[0262] In actual work, the upstream data processing module and the downstream data processing module on the main channel of the computing core control the data transmission between the upstream data processing module and the downstream data processing module through the ready-valid handshake signal. The upstream data processing module generates a valid signal to indicate that the current data is ready and can be transmitted to the downstream data processing module. The downstream data processing module generates a ready signal to indicate that the data of the upstream data processing module can be received. When the two signals are high at the same time, that is, ready and valid are both 1, the data is transmitted.

[0263] The main channel gating module is connected to the upstream data processing module and the downstream data processing module respectively. When receiving a valid control signal, the main channel gating module can control the ready and valid levels to invert their meanings, thereby preventing data transmission. Otherwise, the original ready and valid levels are maintained to maintain data transmission.

[0264] In this way, through the main channel gating module, the data transmission state can be easily adjusted based on the received valid control signal and invalid control signal, and the implementation scheme is simple.

[0265] In order to achieve the above control needs, the embodiment of the present application also provides a main channel gating module used to implement the integrated circuit load adjustment method. Please refer to Figure 7 , Figure 7 A schematic diagram of a load gating structure of an integrated circuit load adjustment method provided in an embodiment of the present application.

[0266] like Figure 7 As shown, the load gating structure includes: a most average M / N gating signal generating module 221 , a main channel gating module 231 , an upstream data processing module 191 and a downstream data processing module 192 .

[0267] The most average M / N gating signal generating module 221 is suitable for generating the most average effective control signal according to the M / N value, and sending the generated effective control signal and invalid control signal to the main channel gating module 231. The main channel gating module 231 is suitable for receiving the effective control signal and the invalid control signal, and controlling the data transmission between the upstream data processing module 191 and the downstream data processing module 192 through the effective control signal and the invalid control signal.

[0268] Specifically, the main channel gating module 231 includes:

[0269] The inverter 2310 is adapted to receive the load state adjustment signal, perform an inversion process, and obtain an inverted signal;

[0270] The first AND gate device 2311 is adapted to receive the negation signal and the upstream status signal of the upstream data processing module, perform a logic AND operation, and output a data signal indicating whether there is valid data upstream to the downstream data processing module;

[0271] The second AND gate device 2312 is adapted to receive the negated signal and the downstream status signal of the downstream data processing module, perform a logic AND operation, and output a status signal indicating whether the downstream can receive the valid data to the upstream data processing module.

[0272] When the most average M / N gating signal generating module 221 generates the most average effective control signal EN=1 according to the M / N value, the effective control signal EN=1 will be sent to the inverter 2310 in the main channel gating module 231. The inverter 2310 will logically invert EN=1 to EN=0 and send it to the first AND gate device 2311 and the second AND gate device 2312.

[0273] When the first AND gate device 2311 receives the inverted signal, it performs a logic AND operation with the upstream state valid signal of the upstream data processing module 191. At this time, no matter whether the valid signal is 0 or 1, after performing a logic AND operation with EN=0, the output valid signal is 0. From the perspective of the downstream data processing module 192, no matter whether data can be received, the valid signal sent by the upstream data processing module 191 is 0, indicating that the upstream data processing module 191 has no valid data to transmit. At this time, the state of the main channel gating module 231 is a non-conducting state, thereby stopping the data transmission between the upstream data processing module and the downstream data processing module.

[0274] When the second AND gate device 2312 receives the inverted signal, it will perform a logic AND operation with the downstream state ready signal of the downstream data processing module 192. At this time, no matter whether the ready signal is 0 or 1, after performing a logic AND operation with EN=0, the output ready signal is 0. From the perspective of the upstream data processing module 191, no matter whether the data is ready or not, the ready signal sent by the downstream data processing module 192 is 0, indicating that the downstream data processing module 192 is not ready to receive data. At this time, the state of the main channel gating module 231 is also a non-conducting state, thereby stopping the data transmission between the upstream data processing module 191 and the downstream data processing module 192.

[0275] When the most average M / N gating signal generating module 221 generates the most average invalid control signal EN=0 according to the M / N value, the valid control signal EN=0 will be sent to the inverter 2310 in the main channel gating module 231, and the inverter 2310 will logically invert EN=0 to EN=1, and send it to the first AND gate device 2311 and the second AND gate device 2312. When the first AND gate device 2311 and the second AND gate device 2312 receive EN=1 and perform a logical AND operation with the valid and ready signals, at this time, because EN=1, after the logical AND operation, the output valid and ready will maintain the original signal state. At this time, the state of the main channel gating module 231 is the original state, so it will not affect the data transmission between the upstream data processing module and the downstream data processing module.

[0276] It can be seen that by setting the inverter 2310, the first AND gate device 2311 and the second AND gate device 2312, the data transmission state between the upstream data processing module 191 and the downstream data processing module 192 can be adjusted very conveniently based on the load state adjustment signal to achieve the adjustment of the load state of the integrated circuit.

[0277] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0278] The embodiment of the present application also provides an integrated circuit load adjustment device, which can be considered as a functional module required to implement the integrated circuit load adjustment method provided in the embodiment of the present application. It is also partially explained in the previous description of the integrated circuit load adjustment device. The device content described below can be referenced to the method content described above and the aforementioned description of the device.

[0279] Please refer again Figure 2 , Figure 2A schematic diagram of the structure of an integrated circuit load adjustment device provided in an embodiment of the present application.

[0280] like Figure 2 As shown, the integrated circuit load adjustment device provided in the embodiment of the present application may include:

[0281] The current maximum allowable load acquisition module 21 is adapted to acquire the current maximum allowable load of the integrated circuit;

[0282] A load state adjustment signal generating module 22, adapted to generate a load state adjustment signal of the integrated circuit according to the current maximum allowable load;

[0283] The state adjustment module 23 is adapted to adjust the load state of the integrated circuit according to the load state adjustment signal.

[0284] In some embodiments, the current maximum allowable load acquisition module 21 may include:

[0285] A current maximum equivalent load acquisition unit 211, adapted to acquire the current maximum equivalent load of the integrated circuit;

[0286] The current maximum allowable load acquisition unit 212 is adapted to acquire the current maximum allowable load according to the current maximum equivalent load and a pre-built load equivalent model.

[0287] In some embodiments, the integrated circuit load adjustment device provided in the embodiments of the present application further includes: a first construction module of the load equivalent model, wherein the first construction module includes:

[0288] A model parameter acquisition unit, adapted to acquire pre-stored load equivalent model parameters;

[0289] The model building unit is adapted to build the load equivalent model according to the load equivalent model parameters.

[0290] In combination with the above description of the integrated circuit load adjustment device, it can be known that the first construction module can be considered as a part of the micro control unit, which is used to implement the construction of the load equivalent model.

[0291] The load equivalent model parameters are obtained through a parameter acquisition module, and the parameter acquisition module includes:

[0292] A first acquisition unit corresponding to the test load and the test equivalent load is adapted to acquire the test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load, and obtain the test equivalent load corresponding to each test load;

[0293] The load equivalent model parameter acquisition unit is adapted to obtain the load equivalent model parameters according to the mapping relationship between each of the test load amounts and each of the test equivalent load amounts.

[0294] Wherein, in some embodiments, the corresponding test load and test equivalent load acquisition unit is adapted to acquire the test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load, and obtain the test equivalent load corresponding to each test load, including:

[0295] Get the current test load and current voltage;

[0296] Obtaining the state of the integrated circuit under the current test load and the current voltage state, and reading the corresponding test equivalent load;

[0297] When it is determined that the state of the integrated circuit is normal, the voltage value of the current voltage is reduced until the state is abnormal, and the test equivalent load of the integrated circuit when the state is normal for the last time is obtained, and the current test equivalent load corresponding to the current test load is obtained;

[0298] The current test load and the current voltage are adjusted and used as new current test load and new current voltage until each test equivalent load corresponding to each test load of the integrated circuit is obtained.

[0299] In some embodiments, the current maximum equivalent load acquisition unit is adapted to acquire the current maximum equivalent load of the integrated circuit and includes:

[0300] Obtaining a current maximum equivalent load and a current temperature of the integrated circuit;

[0301] The current maximum allowable load acquisition unit is adapted to acquire the current maximum allowable load according to the current maximum equivalent load and a pre-built load equivalent model, and includes:

[0302] The current maximum allowable load is obtained according to the current maximum equivalent load, the current temperature and a pre-built load equivalent model corresponding to each test temperature.

[0303] In some embodiments, the current maximum allowable load acquisition unit is adapted to acquire the current maximum allowable load according to the current maximum equivalent load, the current temperature and a pre-built load equivalent model corresponding to each test temperature, and includes:

[0304] Obtaining a temperature interval between each of the test temperatures;

[0305] Determine the temperature interval corresponding to the current temperature, obtain the current temperature interval, and obtain the temperature load equivalent model in each load equivalent model corresponding to the current temperature interval;

[0306] According to the current maximum equivalent load and each of the temperature load equivalent models, obtaining the current maximum allowable load at the interval endpoint;

[0307] The current maximum allowable load is obtained according to the current temperature, the endpoint temperature of the current temperature interval and the current maximum allowable load at the endpoint of the interval.

[0308] Continue to combine Figure 2 In one embodiment, the integrated circuit load adjustment device provided in the embodiment of the present application further includes:

[0309] The one-time programmable circuit 213 is adapted to store the load equivalent model parameters.

[0310] In some embodiments, please combine Figure 2 refer to Figure 3 , the current maximum equivalent load acquisition unit 211 includes:

[0311] The power supply monitor 2110 is connected to the internal power supply network of the integrated circuit.

[0312] In some other embodiments, the integrated circuit load adjustment device provided in the embodiments of the present application further includes: a second construction module of the load equivalent model, wherein the second construction module includes:

[0313] A second acquisition unit corresponding to the test load and the test equivalent load is adapted to acquire the pre-stored test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load condition, and obtain the test equivalent load corresponding to each test load respectively;

[0314] The load equivalent model construction unit is adapted to construct the load equivalent model according to the test load amounts and the test equivalent load amounts that correspond to each other.

[0315] In combination with the above description of the integrated circuit load adjustment device, it can be known that the second construction module can be considered as a part of the micro control unit, which is used to implement the construction of the load equivalent model.

[0316] In some embodiments, the current maximum allowable load comprises an M / N value, wherein M represents the number of cycles, N represents the number of valid control signals, and the M / N value represents the number of valid control signals generated in the number of cycles.

[0317] In some embodiments, please combine Figure 2 refer to Figure 7 The load state adjustment signal generating module 22 in the integrated circuit load adjustment device provided in the embodiment of the present application includes:

[0318] The most average M / N gating signal generating module 221 is adapted to generate a load state adjustment signal of the integrated circuit according to the M / N value.

[0319] In some embodiments, the most average M / N gating signal generating module 221 includes a cycle period counter and a valid control signal counter;

[0320] The most average M / N gating signal generating module 221 is adapted to generate a load state adjustment signal of the integrated circuit according to the M / N value, including:

[0321] When the M / N value is obtained and the cycle count value of the cycle counter is equal to M, the cycle count value of the cycle counter is adjusted to 0, and the control count value of the effective control signal counter is adjusted to -N;

[0322] Determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value by 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter to adjust the control count value of the effective control signal counter.

[0323] In some embodiments, the most average M / N gating signal generating module 221 is adapted to determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value plus 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter, and the step of adjusting the control count value of the effective control signal counter includes:

[0324] When it is determined that the value of the highest bit of the effective control signal counter is 1, the effective control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the effective control signal counter being 1, the control count value of the effective control signal counter is adjusted to be increased by MN;

[0325] When it is determined that the value of the highest bit of the valid control signal counter is 0, an invalid control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the valid control signal counter being 0, the control count value of the valid control signal counter is adjusted to be reduced by N.

[0326] In some embodiments, please combine Figure 2 refer to Figure 7 , the state adjustment module 23 includes:

[0327] The main channel gating module 231 is arranged between the upstream data processing module 191 and the downstream data processing module 192 of the integrated circuit, and is suitable for adjusting the state according to the load state adjustment signal to control the data transmission between the upstream data processing module 191 and the downstream data processing module 192.

[0328] In some embodiments, the main channel gating module 231 is adapted to adjust the state according to the load state adjustment signal and control the data transmission between the upstream data processing module 191 and the downstream data processing module 192, including:

[0329] According to the effective control signal of the load state adjustment signal, the effective control signal is adjusted to a non-conducting state, and the data transmission between the upstream data processing module 191 and the downstream data processing module 192 is stopped;

[0330] According to the invalid control signal of the load state adjustment signal, the state is adjusted to be on, and data transmission is performed between the upstream data processing module 191 and the downstream data processing module 192 .

[0331] In some embodiments, the main channel gating module 231 includes:

[0332] The inverter 2310 is adapted to receive the load state adjustment signal, perform an inversion process, and obtain an inverted signal;

[0333] The first AND gate device 2311 is adapted to receive the negation signal and the upstream status signal of the upstream data processing module, perform a logic AND operation, and output a data signal indicating whether there is valid data upstream to the downstream data processing module;

[0334] The second AND gate device 2312 is adapted to receive the negated signal and the downstream status signal of the downstream data processing module, perform a logic AND operation, and output a status signal indicating whether the downstream can receive the valid data to the upstream data processing module.

[0335] It can be seen that the integrated circuit load adjustment device provided in the embodiment of the present application can provide hardware guarantee for the integrated circuit load adjustment method provided in the embodiment of the present application, and can adjust the load state by acquiring the current maximum allowable load of the specific integrated circuit in real time and generating a load state adjustment signal. It can be realized based on the individual integrated circuit, so that the integrated circuit can adjust the load of the integrated circuit according to the real-time voltage drop of the integrated circuit, so that it always works at the maximum load allowed by the current voltage drop, thereby improving the performance of each integrated circuit under the corresponding DIDT voltage drop.

[0336] Please continue to refer to Figure 2 , the embodiment of the present application further provides an integrated circuit, including:

[0337] An upstream data processing module 191 adapted to transmit data downstream;

[0338] A downstream data processing module 192, adapted to receive the data transmitted by the upstream data processing module;

[0339] The integrated circuit load adjustment device provided in the embodiment of the present application is connected between the upstream data processing module 191 and the downstream data processing module 192, and is suitable for adjusting the transmission status of the data between the upstream data processing module 191 and the downstream data processing module 192 according to the current maximum allowable load of the integrated circuit.

[0340] The upstream data processing module, the downstream data processing module and the integrated circuit load adjustment device cooperate with each other to achieve the goal of always working at the maximum load condition based on the individual integrated circuit, adjusting the load of the integrated circuit according to the real-time voltage drop of the integrated circuit, and improving the performance of each integrated circuit under the voltage drop condition.

[0341] The embodiment itself also provides an electronic device, including the integrated circuit provided by the embodiment of the present application.

[0342] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for adjusting integrated circuit load, characterized in that: include: Get the current maximum allowable load of the integrated circuit; generating a load state adjustment signal for the integrated circuit according to the current maximum allowable load; adjusting the load state of the integrated circuit according to the load state adjustment signal; The step of obtaining the current maximum allowable load of the integrated circuit includes: Obtaining the current maximum equivalent load of the integrated circuit, including: obtaining the current maximum equivalent load and current temperature of the integrated circuit; The current maximum allowable load is obtained according to the current maximum equivalent load and a pre-constructed load equivalent model, including: obtaining the current maximum allowable load according to the current maximum equivalent load, the current temperature and a pre-constructed load equivalent model corresponding to each test temperature.

2. The integrated circuit load adjustment method according to claim 1, wherein: The steps of constructing the load equivalent model include: Obtaining pre-stored load equivalent model parameters; The load equivalent model is constructed according to the load equivalent model parameters.

3. The integrated circuit load adjustment method according to claim 2, wherein: The step of acquiring the load equivalent model parameters comprises: Obtaining the test equivalent load of the integrated circuit at the minimum voltage at which the integrated circuit can work normally under each test load condition, and obtaining the test equivalent load corresponding to each test load; The load equivalent model parameters are obtained according to the mapping relationship between each of the test load amounts and each of the test equivalent load amounts.

4. The integrated circuit load adjustment method according to claim 3, characterized in that: The step of obtaining the test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load condition, and obtaining the test equivalent load corresponding to each test load respectively comprises: Get the current test load and current voltage; Obtaining the state of the integrated circuit under the current test load and the current voltage state, and reading the corresponding test equivalent load; When it is determined that the state of the integrated circuit is normal, the voltage value of the current voltage is reduced until the state is abnormal, and the test equivalent load of the integrated circuit when the state is normal for the last time is obtained, and the current test equivalent load corresponding to the current test load is obtained; The current test load and the current voltage are adjusted and used as new current test load and new current voltage until each test equivalent load corresponding to each test load of the integrated circuit is obtained.

5. The integrated circuit load adjustment method according to claim 1, wherein: The step of obtaining the current maximum allowable load according to the current maximum equivalent load, the current temperature and the pre-built load equivalent model corresponding to each test temperature includes: Obtaining a temperature interval between each of the test temperatures; Determine the temperature interval corresponding to the current temperature, obtain the current temperature interval, and obtain the temperature load equivalent model in each load equivalent model corresponding to the current temperature interval; According to the current maximum equivalent load and each of the temperature load equivalent models, obtaining the current maximum allowable load at the interval endpoint; The current maximum allowable load is obtained according to the current temperature, the endpoint temperature of the current temperature interval and the current maximum allowable load at the endpoint of the interval.

6. The integrated circuit load adjustment method according to claim 1, wherein: The load equivalent model parameters are stored in a one-time programmable circuit.

7. The integrated circuit load adjustment method according to claim 1, wherein: The step of obtaining the current maximum equivalent load of the integrated circuit comprises: The current maximum equivalent load of the integrated circuit is acquired by using a power supply monitor, and the power supply monitor is connected to an internal power supply network of the integrated circuit.

8. The integrated circuit load adjustment method according to claim 1, wherein: The steps of constructing the load equivalent model include: Acquire the pre-stored test equivalent load of the integrated circuit under each test load condition, at the minimum voltage at which the integrated circuit can work normally, and obtain the test equivalent load corresponding to each test load; The load equivalent model is constructed according to the test load amounts and the test equivalent load amounts that correspond to each other.

9. The integrated circuit load adjustment method according to any one of claims 1 to 8, characterized in that: The current maximum allowable load comprises an M / N value, wherein M represents the number of cycles, N represents the number of effective control signals, and the M / N value represents the number of effective control signals generated in the number of cycles.

10. The integrated circuit load adjustment method according to claim 9, characterized in that: The step of generating a load state adjustment signal of the integrated circuit according to the current maximum allowable load comprises: The most average M / N gating signal generating module of the integrated circuit generates a load state adjustment signal of the integrated circuit according to the M / N value.

11. The integrated circuit load adjustment method according to claim 10, wherein: The most average M / N gating signal generating module includes a cycle counter and a valid control signal counter; The step of generating the load state adjustment signal of the integrated circuit according to the M / N value by the most average M / N gating signal generating module of the integrated circuit comprises: When the most average M / N gating signal generating module of the integrated circuit obtains the M / N value and the cycle count value of the cycle counter is equal to M, the cycle count value of the cycle counter is adjusted to 0, and the control count value of the effective control signal counter is adjusted to -N; Determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value by 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter to adjust the control count value of the effective control signal counter.

12. The integrated circuit load adjustment method according to claim 11, characterized in that: The step of determining the value of the highest bit of the effective control signal counter, obtaining the load state adjustment signal of the integrated circuit, and adjusting the cycle count value by 1 at the rising edge of each clock, and obtaining the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter, and adjusting the control count value of the effective control signal counter includes: When it is determined that the value of the highest bit of the effective control signal counter is 1, the effective control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the effective control signal counter being 1, the control count value of the effective control signal counter is adjusted to be increased by MN; When it is determined that the value of the highest bit of the valid control signal counter is 0, an invalid control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the valid control signal counter being 0, the control count value of the valid control signal counter is adjusted to be reduced by N.

13. The integrated circuit load adjustment method according to claim 12, wherein: The step of adjusting the load state of the integrated circuit according to the load state adjustment signal comprises: According to the load state adjustment signal, the state of the main channel gating module arranged between the upstream data processing module and the downstream data processing module of the integrated circuit is adjusted to control the data transmission between the upstream data processing module and the downstream data processing module.

14. The integrated circuit load adjustment method according to claim 13, wherein: The step of adjusting the state of a main channel gating module disposed between an upstream data processing module and a downstream data processing module of the integrated circuit according to the load state adjustment signal, and controlling data transmission between the upstream data processing module and the downstream data processing module comprises: According to the effective control signal of the load state adjustment signal, adjusting the state of the main channel gating module to a non-conducting state, and stopping the data transmission between the upstream data processing module and the downstream data processing module; According to the invalid control signal of the load state adjustment signal, the state of the main channel gating module is adjusted to the on state, and data transmission is performed between the upstream data processing module and the downstream data processing module.

15. The integrated circuit load adjustment method according to claim 13, wherein: The main channel gating module comprises: An inverter, adapted to receive the load state adjustment signal, perform an inversion process, and obtain an inverted signal; A first AND gate device, adapted to receive the negation signal and the upstream status signal of the upstream data processing module, perform a logic AND operation, and output a data signal indicating whether there is valid data upstream to the downstream data processing module; The second AND gate device is adapted to receive the negated signal and the downstream status signal of the downstream data processing module, perform a logic AND operation, and output a status signal indicating whether the downstream can receive the valid data to the upstream data processing module.

16. An integrated circuit load adjustment device, characterized in that: include: A current maximum allowable load acquisition module, adapted to acquire the current maximum allowable load of the integrated circuit; A load state adjustment signal generating module, adapted to generate a load state adjustment signal of the integrated circuit according to the current maximum allowable load; a state adjustment module, adapted to adjust the load state of the integrated circuit according to the load state adjustment signal; Wherein, the current maximum allowable load acquisition module includes: The current maximum equivalent load acquisition unit is adapted to acquire the current maximum equivalent load of the integrated circuit, including: acquiring the current maximum equivalent load and the current temperature of the integrated circuit; The current maximum allowable load acquisition unit is suitable for acquiring the current maximum allowable load according to the current maximum equivalent load and a pre-built load equivalent model, including: acquiring the current maximum allowable load according to the current maximum equivalent load, the current temperature and a pre-built load equivalent model corresponding to each test temperature.

17. The integrated circuit load adjustment device according to claim 16, characterized in that: Also includes: The first building block of the load equivalent model comprises: A model parameter acquisition unit, adapted to acquire pre-stored load equivalent model parameters; The model building unit is adapted to build the load equivalent model according to the load equivalent model parameters.

18. The integrated circuit load adjustment device according to claim 17, characterized in that: The load equivalent model parameters are obtained by a parameter acquisition module, and the parameter acquisition module includes: A first acquisition unit corresponding to the test load and the test equivalent load is adapted to acquire the test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load, and obtain the test equivalent load corresponding to each test load; The load equivalent model parameter acquisition unit is adapted to obtain the load equivalent model parameters according to the mapping relationship between each of the test load amounts and each of the test equivalent load amounts.

19. The integrated circuit load adjustment device according to claim 18, characterized in that: The corresponding test load and test equivalent load acquisition unit is adapted to acquire the test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load condition, and obtain the test equivalent load corresponding to each test load, including: Get the current test load and current voltage; Obtaining the state of the integrated circuit under the current test load and the current voltage state, and reading the corresponding test equivalent load; When it is determined that the state of the integrated circuit is normal, the voltage value of the current voltage is reduced until the state is abnormal, and the test equivalent load of the integrated circuit when the state is normal for the last time is obtained, and the current test equivalent load corresponding to the current test load is obtained; The current test load and the current voltage are adjusted and used as new current test load and new current voltage until each test equivalent load corresponding to each test load of the integrated circuit is obtained.

20. The integrated circuit load adjustment device according to claim 16, characterized in that: The current maximum allowable load acquisition unit is adapted to acquire the current maximum allowable load according to the current maximum equivalent load, the current temperature and a pre-built load equivalent model corresponding to each test temperature, and includes: Obtaining a temperature interval between each of the test temperatures; Determine the temperature interval corresponding to the current temperature, obtain the current temperature interval, and obtain the temperature load equivalent model in each load equivalent model corresponding to the current temperature interval; According to the current maximum equivalent load and each of the temperature load equivalent models, obtaining the current maximum allowable load at the interval endpoint; The current maximum allowable load is obtained according to the current temperature, the endpoint temperature of the current temperature interval and the current maximum allowable load at the endpoint of the interval.

21. The integrated circuit load adjustment device according to claim 16, characterized in that: The current maximum equivalent load acquisition unit includes: A power supply monitor is connected to an internal power supply network of the integrated circuit.

22. The integrated circuit load adjustment device according to claim 16, characterized in that: Also includes: The second building block of the load equivalent model, the second building block comprising: A second acquisition unit corresponding to the test load and the test equivalent load is adapted to acquire the pre-stored test equivalent load of the integrated circuit under the minimum voltage at which the integrated circuit can work normally under each test load condition, and obtain the test equivalent load corresponding to each test load respectively; The load equivalent model construction unit is adapted to construct the load equivalent model according to the test load amounts and the test equivalent load amounts that correspond to each other.

23. The integrated circuit load adjustment device according to any one of claims 16 to 22, characterized in that: The current maximum allowable load comprises an M / N value, wherein M represents the number of cycles, N represents the number of effective control signals, and the M / N value represents the number of effective control signals generated in the number of cycles.

24. The integrated circuit load adjustment device according to claim 23, characterized in that: The load state adjustment signal generating module comprises: The most average M / N gating signal generating module is adapted to generate a load state adjustment signal of the integrated circuit according to the M / N value.

25. The integrated circuit load adjustment device according to claim 24, characterized in that: The most average M / N gating signal generating module includes a cycle counter and a valid control signal counter; The most average M / N gating signal generating module is adapted to generate a load state adjustment signal of the integrated circuit according to the M / N value, and includes: When the M / N value is obtained and the cycle count value of the cycle counter is equal to M, the cycle count value of the cycle counter is adjusted to 0, and the control count value of the effective control signal counter is adjusted to -N; Determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value by 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter to adjust the control count value of the effective control signal counter.

26. The integrated circuit load adjustment device according to claim 25, characterized in that: The most average M / N gating signal generating module is adapted to determine the value of the highest bit of the effective control signal counter, obtain the load state adjustment signal of the integrated circuit, and adjust the cycle count value plus 1 at the rising edge of each clock, and obtain the corresponding adjustment rule according to the value of the highest bit of the effective control signal counter. The step of adjusting the control count value of the effective control signal counter includes: When it is determined that the value of the highest bit of the effective control signal counter is 1, the effective control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the effective control signal counter being 1, the control count value of the effective control signal counter is adjusted to be increased by MN; When it is determined that the value of the highest bit of the valid control signal counter is 0, an invalid control signal of the load state adjustment signal of the integrated circuit is obtained, and at the rising edge of each clock, the cycle count value is adjusted to be increased by 1, and according to the adjustment rule corresponding to the value of the highest bit of the valid control signal counter being 0, the control count value of the valid control signal counter is adjusted to be reduced by N.

27. The integrated circuit load adjustment device according to claim 26, characterized in that: The state adjustment module comprises: The main channel gating module is arranged between the upstream data processing module and the downstream data processing module of the integrated circuit, and is suitable for adjusting the state according to the load state adjustment signal to control the data transmission between the upstream data processing module and the downstream data processing module.

28. The integrated circuit load adjustment device according to claim 27, characterized in that: The main channel gating module is adapted to adjust the state according to the load state adjustment signal and control the data transmission between the upstream data processing module and the downstream data processing module, and includes: According to the load state adjustment signal, the effective control signal is adjusted to a non-conducting state, and the data transmission between the upstream data processing module and the downstream data processing module is stopped; The invalid control signal of the load state adjustment signal is adjusted to a conducting state, and data transmission is performed between the upstream data processing module and the downstream data processing module.

29. The integrated circuit load adjustment device according to claim 27, characterized in that: The main channel gating module comprises: An inverter, adapted to receive the load state adjustment signal, perform an inversion process, and obtain an inverted signal; A first AND gate device, adapted to receive the negation signal and the upstream status signal of the upstream data processing module, perform a logic AND operation, and output a data signal indicating whether there is valid data upstream to the downstream data processing module; The second AND gate device is adapted to receive the negated signal and the downstream status signal of the downstream data processing module, perform a logic AND operation, and output a status signal indicating whether the downstream can receive the valid data to the upstream data processing module.

30. An integrated circuit, characterized in that: include: An upstream data processing module, suitable for transmitting data downstream; A downstream data processing module, adapted to receive the data transmitted by the upstream data processing module; The integrated circuit load adjustment device as described in any one of claims 16-29 is connected between the upstream data processing module and the downstream data processing module, and is suitable for adjusting the data transmission status between the upstream data processing module and the downstream data processing module according to the current maximum allowable load of the integrated circuit.

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