Mram sense amplifier and screening method

Abstract

The application provides a MRAM readout amplifier and screening method, which sets a composite switch control mechanism at the input end of a differential amplifier, controls the pre-charge of a storage unit and the enabling timing of the differential amplifier, and effectively reproduces the write state of the storage unit. On the other hand, during the production of the MRAM, by inputting a different potential to the input end and combining the reproduction condition of the differential amplifier, it can help to determine whether the storage unit is defective, and when it is defective, it can be replaced by a redundant unit, which can effectively improve the production yield of the MRAM.

Description

Technical Field

[0001] This application relates to the field of register technology, and in particular to an MRAM readout amplifier and a screening method. Background Technology

[0002] The sense amplifier in MRAM is a core unit in the circuit, with high requirements for speed, accuracy, and power consumption. Currently, there are relatively mature manufacturing technologies for common MRAM sense amplifiers. However, in high-capacity MRAM chips, there are always a small number of memory cells with very small resistance differences: for a 1T1M design, the resistance of some cells in the P-state or AP-state may be very close to the reference value; for a 2T2M design, the resistance difference between the left and right states of some cells may be too small in a certain state. Such memory cells are practically unreliable. Improving the accuracy of the sense amplifier over a wide operating temperature range is difficult, and noise can also affect the readout results with very small resistance differences.

[0003] For example, Chinese patent application CN201610079008.0 discloses a read amplifier in an MRAM read / write circuit. This patent connects the input terminals of the differential current output section to a reference cell and a storage cell respectively, and outputs a comparison result by comparing the currents at the two input terminals. However, this application still fails to solve the aforementioned read amplifier accuracy problem. Summary of the Invention

[0004] In order to solve the above-mentioned technical problems, the purpose of this application is to provide an MRAM readout amplifier with screening function and a screening method thereof.

[0005] The purpose of this application and the solution to its technical problems are achieved by the following technical solutions.

[0006] This application provides a method for screening magnetic random access memory (MRM) cells using a readout amplifier. The MLM cell includes an input circuit and a differential amplifier. The input circuit includes a memory cell with a magnetically coupled junction and a reference resistor, which are respectively connected to a first input terminal and a second input terminal of the differential amplifier. Two sets of read operation control switches are respectively connected to the first input terminal and the second input terminal. Each read operation switch includes a read operation switch and a switching transistor. The method includes: setting the write state of the memory cell such that the resistance values ​​of the memory cell and the reference resistor are different; setting the same read voltage to the drains of the two switching transistors; setting two precharge signals to the gates of the two switching transistors, wherein the voltage magnitude relationship of the two precharge signals is opposite to the resistance value relationship between the memory cell and the reference resistor, and the resistance values ​​of the two switching transistors are different, thereby adjusting the input voltage of the two switching transistors to the first input terminal and the input voltage to the second input terminal; and, based on the output of the differential amplifier, determining that the written state of the memory cell connected to the first input terminal cannot be reproduced, using a redundant circuit to replace the memory cell connected to the first input terminal.

[0007] Optionally, the first input terminal and the second input terminal are respectively provided with amplifier switching switches. The switch states are switched by the amplifier control signal, so that the differential amplifier, the storage unit and the reference resistor are electrically connected or electrically disconnected.

[0008] Optionally, during a write operation, the resistance of the storage cell connected to the first input terminal is higher than the resistance of the reference resistor connected to the second input terminal; during a read operation, the input voltage of the first input terminal is lower than the input voltage of the second input terminal.

[0009] Optionally, during a write operation, the resistance of the storage cell connected to the first input terminal is lower than the resistance of the reference resistor connected to the second input terminal; during a read operation, the input voltage of the first input terminal is higher than the input voltage of the second input terminal.

[0010] Optionally, the redundant circuit is formed by one or more magnetic follower junctions.

[0011] Optionally, the reference resistor is composed of a high-precision thin-film resistor circuit.

[0012] Optionally, the reference resistor can be replaced with a memory cell having a magnetic follow-through junction.

[0013] Optionally, the read operation control switch connected to the second input terminal can be replaced by a reference voltage.

[0014] This application also provides a readout amplifier for a magnetic random access memory (RAM) cell, including an input circuit and a differential amplifier. The input section includes a memory cell with a magnetic random access junction and a reference resistor, which are respectively connected to the two input terminals of the differential amplifier. Each of the two input terminals of the differential amplifier is provided with two amplifier switching switches. One amplifier switching switch has its other end electrically connected to a read operation control switch and the memory cell, while the other amplifier switching switch has its other end electrically connected to the read operation control switch and the reference resistor. Each amplifier switching switch is connected to... The amplifier control signal switches the state of the differential amplifier, the read operation control switch, the memory cell, and the reference resistor to form an electrically connected or electrically disconnected connection. The read operation control switch includes a read operation switch and a switching transistor. The gate of the switching transistor is connected to the precharge signal terminal, the drain is connected to the read voltage, and the source is connected to one end of the read operation switch. The read operation switch switches the state of the differential amplifier and the memory cell under the control of the read activation signal to form an electrically connected or electrically disconnected connection between the read operation control switch, the differential amplifier, and the memory cell. The memory cell includes a magnetic follow-channel junction and a field-effect transistor for connecting word lines and bit lines.

[0015] Optionally, in the filtering mode, during a write operation, the resistance of the memory cell connected to one of the two input terminals is higher than the resistance of the reference resistor connected to the other of the two input terminals; the same read voltage is set to the drain of the two switching transistors; two precharge signals are set to the gate of the two switching transistors, and the voltage relationship between the two precharge signals is opposite to the resistance relationship between the memory cell and the reference resistor, so that the resistance values ​​of the two switching transistors are different, thereby adjusting the two input terminals of the differential amplifier; if the output of the differential amplifier determines that the written state of the memory cell cannot be reproduced, a redundant circuit is used to replace the memory cell.

[0016] Optionally, if an analysis circuit connected to the magnetic random access memory unit determines that the written state of the memory unit cannot be correctly reproduced, the memory unit is reconnected to a redundant circuit, or the redundant circuit connected to the memory unit is enabled.

[0017] Optionally, in normal mode, the precharge signal terminals connected to the gates of each of the switching transistors are at the same potential. When the amplifier switching switch is off, after the row and column decoder of the magnetic random access memory cell selects a specific row and column position, the read operation switch is on, and the read voltage precharges the selected memory cell through the switching transistor. When each of the amplifier switching switches is on and each of the read operation switches is off, the differential amplifier reproduces the write state of the memory cell.

[0018] This application relates to an MRAM readout amplifier and screening method. A composite control switch at the input of the differential amplifier effectively controls the read operation of the memory cell by controlling the pre-charging of the memory cell and the activation timing of the differential amplifier, thereby improving the read accuracy of the readout amplifier. Furthermore, during MRAM production, by inputting different potentials to the input terminal and considering the reproduction pattern of the differential amplifier, it is helpful to determine whether a memory cell has failed, thus deciding whether to replace it with a redundant cell when the memory cell fails, thereby improving the production yield of MRAM. Attached Figure Description

[0019] Figure 1A This is a conceptual diagram of the 2T2M architecture of the MRAM readout amplifier circuit according to an embodiment of this application;

[0020] Figure 1B This is a conceptual diagram of the 1T1M architecture of the MRAM readout amplifier circuit according to an embodiment of this application;

[0021] Figure 2 This is a conceptual diagram of the 2T2M architecture of the MRAM readout amplifier circuit according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the alternative architecture of the MRAM readout amplifier circuit 1T1M / 2T2M according to an embodiment of this application;

[0023] Figure 4 This is a timing diagram of the MRAM readout amplifier according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of an MRAM readout amplifier combined with an adjustable precharge selection circuit, according to an embodiment of this application.

[0025] Symbol Explanation

[0026] 10: Register unit; 20: Differential amplifier circuit; 21: First inverter; 22: Second inverter; 31: First magnetic tunnel junction; 32: Second magnetic tunnel junction; 41: Node; Vdd: Power supply line; SL: Source line; BL: Bit line; RWL: Read word line; WWL: Write word line; N1: First NMOS transistor; P1: First PMOS transistor; N2: Second NMOS transistor; P2: Second PMOS transistor; N3: First switch; N4: Second switch; N5: Third switch; OUT: First output; OUT_n: Second output; R: Shared resistor. Detailed Implementation

[0027] Please refer to the figures in the accompanying drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments illustrated in this application and should not be construed as limiting other specific embodiments not detailed herein.

[0028] The following descriptions of the embodiments are with reference to the accompanying drawings, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes only, and not for limiting the scope of this application.

[0029] The terms "first," "second," "third," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in this way can be used interchangeably where appropriate. Furthermore, the terms "comprising" and "having," and their variations, are intended to cover non-exclusive inclusion.

[0030] The terminology used in this specification is used only to describe particular embodiments and is not intended to represent the concepts of this application. Unless the context clearly distinguishes them, singular expressions encompass plural expressions. In this specification, it should be understood that terms such as “comprising,” “having,” and “containing” are intended to describe the possibility of the presence of the features, numbers, steps, actions, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, numbers, steps, actions, or combinations thereof. Like reference numerals in the drawings refer to like parts.

[0031] The accompanying drawings and descriptions are intended to be illustrative in nature, not restrictive. In the drawings, structurally similar units are denoted by the same reference numerals. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, but this application is not limited thereto.

[0032] In the accompanying drawings, the configuration range of devices, systems, components, and circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when a component is referred to as being "on" another component, the component may be directly on the other component, or there may be an intermediate component present.

[0033] Additionally, in the specification, unless explicitly stated otherwise, the word "comprising" will be understood to mean including the stated component, but not excluding any other components. Furthermore, in the specification, "on" means located above or below the target component, and does not mean that it must be located on top based on the direction of gravity.

[0034] To further illustrate the technical means and effects adopted by this application to achieve the intended purpose of the invention, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, describes the specific structure, features and effects of an MRAM readout amplifier and screening method proposed in this application.

[0035] Figure 1A This is a conceptual diagram of the 2T2M architecture of the MRAM readout amplifier circuit according to an embodiment of this application. Figure 1B This is a conceptual diagram of the 1T1M architecture of an MRAM readout amplifier circuit according to an embodiment of this application. This application provides a readout amplifier for a magnetic random access memory cell, including an input circuit and a differential amplifier SA, wherein, as... Figure 1B The input section connects a memory cell (MR1) with a magnetic follow-through junction to a reference resistor RC, which are respectively connected to the two input terminals (Vin1, Vin2) of the differential amplifier SA, or as follows: Figure 1A The input section connects to two sets of memory cells (MR1, MR2) with magnetic follow-channel junctions; each of the two input terminals is equipped with two amplifier switches (T1, T2), the other end of each amplifier switch (T1, T2) is electrically connected to a read operation control switch and the memory cells (MR1, MR2), and each amplifier switch (T1, T2) switches its state through an amplifier control signal (SA_EN), so that the differential amplifier SA, the read operation control switch, and the memory cells (MR1, MR2) are electrically connected or electrically disconnected; the read operation control switch includes a read operation switch (T3, T4) and a switching transistor (nm3, nm4), the... The gates of the switching transistors (nm3, nm4) are connected to the precharge signal terminals (Vclamp_BL and Vclamp_BLb), the drains are connected to the read voltage (Vread), and the sources are connected to one end of the read operation switch. The other end of the read operation switch is connected to the input terminals (Vin1, Vin2) of the differential amplifier SA. The read operation switch switches its state under the control of the read activation signal (RE_EN), so that the switching transistors (nm3, nm4), the differential amplifier SA, and the memory cells (MR1, MR2) are electrically connected or electrically disconnected. The memory cells (MR1, MR2) include magnetic follow-channel junctions and field-effect transistors for connecting word lines and bit lines. For ease of illustration, a 2T2M architecture will be used for explanation in the following sections.

[0036] Figure 2 This is a schematic diagram of an MRAM readout amplifier circuit according to an embodiment of this application. In this embodiment, the differential amplifier includes two cross-connected inverters to form an unbalanced trigger circuit. One end of each inverter is connected to the power supply line VDD, and the other ends of each inverter serve as the aforementioned input terminals (Vin1, Vin2).

[0037] The two inverters are combinations of NMOS transistor nm1 connected in series with PMOS transistor pm3, and NMOS transistor nm2 connected in series with PMOS transistor pm4. The gates of NMOS transistor nm1 and PMOS transistor pm3 are simultaneously connected to the output node OA of another inverter; the gates of NMOS transistor nm2 and PMOS transistor pm4 are simultaneously connected to the output node OB of another inverter. The two PMOS transistors (pm1, pm2) are connected by their gates, their sources are connected to the power supply line VDD, and their drains are connected to the two output terminals (OA, OB), respectively. The two output nodes (OA, OB) then output signals (SOa, SOb) through inverters, which are used by the latch (SR Latch) for numerical output (Data_out). In some embodiments, the differential amplifier referred to in this application is applicable to any type of differential amplifier, without any limitation.

[0038] Figure 3 This is a schematic diagram of the alternative architecture of the MRAM read amplifier circuit 1T1M / 2T2M according to an embodiment of this application. In one embodiment of this application, the memory cells (MR1, MR2) are formed by combining magnetic tunnel junctions (MTJ1, MTJ2) with bit line switches (AC1, AC2), and bit line switches T5(j) and T7(j), and a combination of bit line switches T6(j) and T8(j) are connected to their respective sides. The ends of the memory cells (MR1, MR2) are also connected to ground through two source line switches (nm5, nm6). The gates of the source line switches (nm5, nm6) are connected to the read signal (RE), and the sources are connected to the source input / output signals (IO_SL, IO_SLb). The control terminals of bit line switches T5(j) and T7(j), and bit line switches T6(j) and T8(j) are connected to the bit lines (j), and the gates of the bit line switches (AC1, AC2) are connected to the word lines (i).

[0039] The sense amplifier has two input points (IO_BL and IO_BLb). In a 2T2M MRAM structure, these two input points (IO_BL and IO_BLb) are connected to one column j via bit line switches T5 and T6 in the column selection switch (MUX), respectively. The row decoder selects one row i. The two source lines of column j are connected to the two switching transistors nm5 and nm6 of the read circuit via source line switches in the column selection switch (MUX). During a read operation, the RE signal controls nm5 and nm6 to ground the two source lines. In the following... Figure 1B In the 1T1M MRAM structure, the input point (IO_BL or IO_BLb) connected to the reference resistor RC can be alternatively connected to a reference voltage.

[0040] Optionally, the redundant circuit is formed by one or more magnetic follower junctions.

[0041] Optional, such as Figure 3 As shown, the reference resistor is composed of a high-precision thin-film resistor.

[0042] Optional, such as Figure 3 As illustrated, during the manufacturing process, the memory cell structure (composed of magnetic tunnel junction MTJ2 and switching transistor AC2) can be replaced with the same 2T2M structure (composed of magnetic tunnel junction MTJx and switching transistor ACx) or with a 1T1M structure (composed of high-precision thin-film resistor Resistor and switching transistor ACx) as required. Alternatively, the aforementioned redundant circuit can be used depending on the screening structure.

[0043] Optionally, the read operation control switch connected to the second input terminal can be replaced by a reference voltage.

[0044] Figure 4 This is a timing diagram of the MRAM readout amplifier according to an embodiment of this application. Please refer to the foregoing diagram for better understanding. The readout amplifier is used normally in the following situations:

[0045] First, set the precharge signal terminals (Vclamp_BL and Vclamp_BLb) connected to the gates of each of the aforementioned switching transistors to the same potential.

[0046] Set the amplifier control signal (SA_EN) to a potential that disables the output of the differential amplifier SA (e.g., low level), so that the amplifier switching switches (T1, T2) are open, and the OA and OB signal outputs are high level.

[0047] Next, during the selection of a specific row and column position by the row and column decoder of the magnetic random access memory cell, Bit[j] is at a high level, the read excitation signal (RE_EN) is at a high level, the read operation switches (T3, T4) are connected, and the WL[i] level goes from low to high. At this time, IO_BL and IO_BLb establish the corresponding initial pre-charge voltage according to the cell resistance state and the reference resistor. That is, the read voltage (Vread) pre-charges the selected memory cell (MR1, MR2) through the switches (nm3, nm4).

[0048] When the read excitation signal (RE_EN) is set low, the pre-charge paths on both sides are disconnected. Then, the amplifier control signal (SA_EN) is set high, and the amplifier switching switches (T1, T2) are connected. At this time, OA and OB form two discharge paths. When the voltage on one side is lower than VDD-Vth (pm3 or pm4), positive feedback is formed. The differential amplifier reproduces the write state of the memory cell, and finally amplifies OA and OB to a recognizable high and low logic signal, which is then latched by the subsequent SR Latch.

[0049] The readout amplifier of this application can be used to screen defective memory cells during the production of magnetic random access memory (RAM) cells. This method is applicable to the aforementioned... Figures 1A to 3 The readout amplifier of the structure.

[0050] like Figure 1B Taking the 1T1M circuit architecture as an example, the magnetic random access memory unit includes an input circuit and a differential amplifier SA. The input part includes a memory cell (MR1) with a magnetic random access junction (MTJ1) and a reference resistor RC, which are respectively connected to the first input terminal Vin1 and the second input terminal Vin2 of the differential amplifier SA.

[0051] like Figure 1A , Figure 2 and Figure 3 Taking the 2T2M circuit architecture as an example, the magnetic random access memory unit includes an input circuit and a differential amplifier SA. The input part includes two sets of memory units (MR1, MR2) with magnetic random access junctions (MTJ1, MTJ2), which are respectively connected to the first input terminal Vin1 and the second input terminal Vin2 of the differential amplifier SA.

[0052] In the memory manufacturing process, the screening process using the read amplifier includes:

[0053] Step (S110): Disconnect the electrical connection between the input circuit and the differential amplifier SA.

[0054] Step (S120): Set the write state of the memory cell, where the resistance values ​​of the memory cell and the reference resistor are different; set the same read voltage to the drain of the two switching transistors; set two precharge signals to the gate of the two switching transistors, where the voltage magnitude relationship of the two precharge signals is obtained by the two switching transistors. Conversely, the resistance values ​​of the two switching transistors are different from the resistance magnitude relationship between the memory cell and the reference resistor, so as to adjust the input voltage of the two switching transistors to the first input terminal and the input voltage to the second input terminal.

[0055] In some embodiments, in a 1T1M architecture, different input voltages IO_BL of a first input terminal Vin1 and IO_BLb of a second input terminal Vin2 are set to pre-charge the storage cell (MR1), where the input voltage IO_BLb of the second input terminal is a reference voltage. Then, the electrical connection between the input circuit and the differential amplifier SA is turned on, and the input voltages (IO_BL, IO_BLb) of the first input terminal Vin1 and the second input terminal Vin2 are disconnected.

[0056] In some embodiments, in a 1T1M architecture, during a write operation of the storage cell (MR1), the resistance of the storage cell MR1 connected to the first input terminal Vin1 (IO_BL) is higher than the resistance of the reference resistor RC connected to the second input terminal Vin2 (IO_BLb). Then, a difference is set such that Vclamp_BL < Vclamp_BLb, so that the input voltage IO_BL of the first input terminal Vin1 is lower than the input voltage IO_BLb of the second input terminal Vin2, and then a read operation is performed. In such a configuration, the resistance of the MTJ connected to IO_BL must be higher than the resistance of the reference resistor RC on the other side by a certain threshold to reproduce the previously written state.

[0057] In some embodiments, in a 1T1M architecture, during a write operation of the storage cell (MR1), the resistance of the storage cell MR1 connected to the first input terminal Vin1 (IO_BL) is lower than the resistance of the reference resistor RC connected to the second input terminal Vin2 (IO_BLb). Then, a difference is set such that Vclamp_BL > Vclamp_BLb, so that the input voltage IO_BL of the first input terminal Vin1 is higher than the input voltage IO_BLb of the second input terminal Vin2, and then a read operation is performed. In such a configuration, the resistance of the MTJ connected to IO_BL must be lower than the resistance of the reference resistor RC on the other side by a certain threshold to reproduce the previously written state.

[0058] In some embodiments, in a 2T2M architecture, different input voltages IO_BL of a first input terminal Vin1 and IO_BLb of a second input terminal Vin2 are set to pre-charge the two groups of storage cells (MR1, MR2), where the input voltage IO_BLb of the second input terminal is a reference voltage. Then, the electrical connection between the input circuit and the differential amplifier SA is turned on, and the input voltages (IO_BL, IO_BLb) of the first input terminal Vin1 and the second input terminal Vin2 are disconnected.

[0059] In some embodiments, in a 2T2M architecture, during a write operation of the two sets of memory cells (MR1, MR2), the resistance of the memory cell MR1 connected to the first input terminal Vin1 (IO_BL) is higher than the resistance of the memory cell MR2 connected to the second input terminal Vin2 (IO_BLb). Then, a difference is set such that Vclamp_BL < Vclamp_BLb, so that the input voltage IO_BL of the first input terminal Vin1 is lower than the input voltage IO_BLb of the second input terminal Vin2, and then a read operation is performed. In such a configuration, the resistance of the MTJ connected to IO_BL must be higher than the resistance of the other side by a certain threshold to reproduce the previously written state.

[0060] In some embodiments, in a 2T2M architecture, during a write operation of the two sets of memory cells (MR1, MR2), the resistance of the memory cell MR1 connected to the first input terminal Vin1 (IO_BL) is lower than the resistance of the memory cell MR2 connected to the second input terminal Vin2 (IO_BLb). Then, a difference is set such that Vclamp_BL > Vclamp_BLb, so that the input voltage IO_BL of the first input terminal Vin1 is higher than the input voltage IO_BLb of the second input terminal Vin2, and then a read operation is performed. In such a configuration, the resistance of the MTJ connected to IO_BL must be lower than the resistance of the other side by a certain threshold to reproduce the previously written state.

[0061] Step (S130): When it is determined through the output of the differential amplifier SA that the previously written state of the memory cell MR1 connected to the first input terminal Vin1 cannot be reproduced, the redundant circuit is used to replace the memory cell MR1 connected to the first input terminal Vin1.

[0062] Optionally, when the input voltage IO_BL of the first input terminal is a reference voltage, or the first input terminal Vin1 is connected to a reference resistor RC, the redundant circuit is used to replace the memory cell MR2 connected to the second input terminal Vin2.

[0063] For any of the above read operations of the memory cell, if the previously written state cannot be reproduced, it is determined that the memory cell (MR1 / MR2) has failed, and the redundant circuit is used for replacement.

[0064] In some embodiments, the redundant circuit is formed by one or more magnetic tunnel junctions.

[0065] In the embodiments of this application, in the 2T2M architecture, the first input terminal Vin1 and the second input terminal Vin2 are respectively provided with amplifier switching switches (T1, T2). The switch states are switched by the amplifier control signal (SA_EN) to make the differential amplifier SA electrically connected or electrically disconnected from the two sets of memory cells (MR1, MR2). In the 1T1M architecture, either of the two sets of memory cells (MR1, MR2) can be replaced with the aforementioned reference resistor RC.

[0066] Figure 5 This is a schematic diagram of an adjustable precharge selection circuit according to an embodiment of this application. In some embodiments, the aforementioned sense amplifier (SA) can be combined with a screening circuit to form an adjustable precharge selection circuit. This structure includes: a low dropout regulator, a screen switch, the sense amplifier SA, a column selector, a word line power supply, a row decoder, and an MRAM array. The MRAM array has a plurality of memory cells, and the column selector and row decoder select the memory cell to write or read data. The low dropout regulator outputs a precharge voltage and its calibration potential (Vclamp, Vclamp_Trim) to the screen switch. The screen switch determines whether to enable the screening function through an activation signal (Screen_EN). When the screening function is not enabled, the two precharge signals (Vclamp_BL, Vclamp_BLb) output to the sense amplifier are at the same potential. If screening is enabled, based on the data and the previous precharge voltage and its calibration potential (Vclamp, Vclamp_Trim), two precharge signals (Vclamp_BL, Vclamp_BLb) with different potentials are output to the sense amplifier. The sense amplifier SA then performs testing and screening on the selected memory cells according to the aforementioned operation.

[0067] This application relates to an MRAM readout amplifier and screening method. A composite control switch at the input of the differential amplifier effectively controls the read operation of the memory cell by controlling the pre-charging of the memory cell and the activation timing of the differential amplifier, thereby improving the read accuracy of the readout amplifier. Furthermore, during MRAM production, by inputting different potentials to the input terminal and considering the reproduction pattern of the differential amplifier, it is helpful to determine whether a memory cell has failed, thus deciding whether to replace it with a redundant cell when the memory cell fails, thereby improving the production yield of MRAM.

[0068] The terms "in one embodiment of this application" and "in various embodiments" are used repeatedly. These terms do not usually refer to the same embodiment; however, they can also refer to the same embodiment. The terms "comprising," "having," and "including" are synonyms unless the context otherwise indicates otherwise.

[0069] The above description is merely a specific embodiment of this application and is not intended to limit this application in any way. Although this application has been disclosed above with specific embodiments, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for screening magnetic random access memory cells using a readout amplifier, wherein the readout amplifier circuit includes an input circuit and a differential amplifier, the input circuit including a memory cell with a magnetic random access junction and a reference resistor, which are respectively connected to a first input terminal and a second input terminal of the differential amplifier, and two sets of read operation control switches are respectively connected to the first input terminal and the second input terminal, each read operation switch including a read operation switch and a switching transistor, characterized in that, The method includes: Set the write state of the memory cell such that the resistance values ​​of the memory cell and the reference resistor are different; Set the same read voltage to the drain of both switching transistors; Two precharge signals are set to the gates of the two switching transistors. The two switching transistors obtain the voltage relationship between the two precharge signals. In contrast to the resistance relationship between the storage cell and the reference resistor, the resistance values ​​of the two switching transistors are different, so as to adjust the input voltage of the two switching transistors to the first input terminal and the input voltage of the second input terminal. When the output of the differential amplifier determines that the written state of the memory cell connected to the first input terminal cannot be reproduced, a redundant circuit is used to replace the memory cell connected to the first input terminal.

2. The method for screening magnetic random access memory cells using a readout amplifier as described in claim 1, characterized in that, The first input terminal and the second input terminal are respectively provided with amplifier switching switches. The switch states are switched by the amplifier control signal, so that the differential amplifier is electrically connected or electrically disconnected from the storage unit and the reference resistor.

3. The method for screening magnetic random access memory cells using a readout amplifier as described in claim 1, characterized in that, During a write operation, the resistance value of the storage cell connected to the first input terminal is higher than the resistance value of the reference resistor connected to the second input terminal; during a read operation, the input voltage of the first input terminal is lower than the input voltage of the second input terminal; or, During a write operation, the resistance value of the storage cell connected to the first input terminal is lower than the resistance value of the reference resistor connected to the second input terminal. During a read operation, the input voltage at the first input terminal is higher than the input voltage at the second input terminal.

4. The method for screening magnetic random access memory cells using a readout amplifier as described in claim 1, characterized in that, The reference resistor is composed of a high-precision thin-film resistor, or the reference resistor can be replaced by a memory cell with a magnetic channel junction.

5. The method for screening magnetic random access memory cells using a readout amplifier as described in claim 1, characterized in that, The read operation control switch connected to the second input terminal can be replaced by a reference voltage.

6. A readout amplifier for a magnetic random access memory cell, comprising an input circuit and a differential amplifier, characterized in that, The input section includes a memory cell with a magnetic follow-through junction and a reference resistor, which are respectively connected to the two input terminals of the differential amplifier; The differential amplifier has two amplifier switching switches at its two input terminals. One amplifier switching switch is electrically connected to a read operation control switch and a storage unit, while the other amplifier switching switch is electrically connected to another read operation control switch and a reference resistor. Each amplifier switching switch switches its state via an amplifier control signal, thereby electrically connecting or disconnecting the differential amplifier, the read operation control switch, the storage unit, and the reference resistor. The read operation control switch includes a read operation switch and a switching transistor. The gate of the switching transistor is connected to a precharge signal terminal, the drain is connected to a read voltage, and the source is connected to one end of the read operation switch. The read operation switch switches its state via a read activation signal, thereby electrically connecting or disconnecting the read operation control switch, the differential amplifier, and the storage unit. The memory cell includes a magnetic trailing junction and a field-effect transistor for connecting word lines and bit lines; In the filtering mode, during a write operation of each memory cell, the storage resistor connected to one of the two input terminals is higher than the reference resistor connected to the other of the two input terminals; the same read voltage is set to the drain of the two switching transistors; two precharge signals are set to the gate of the two switching transistors, and the voltage relationship between the two precharge signals is opposite to the resistance relationship between the memory cell and the reference resistor, so that the resistance values ​​of the two switching transistors are different, thereby adjusting the two input terminals of the differential amplifier; if the output of the differential amplifier determines that the written state of the memory cell cannot be reproduced, a redundant circuit is used to replace the memory cell.

7. The readout amplifier for the magnetic random access memory cell as described in claim 6, characterized in that, In normal mode, the precharge signal terminals connected to the gates of each of the switching transistors are at the same potential; when the amplifier switching switch is off, after the row and column decoder of the magnetic random access memory cell selects a specific row and column position, the read operation switch is on, and the read voltage precharges the selected memory cell through the switching transistor; when each of the amplifier switching switches is on and each of the read operation switches is off, the differential amplifier reproduces the write state of the memory cell.

8. The readout amplifier for the magnetic random access memory cell as described in claim 6, characterized in that, The reference resistor is composed of a high-precision thin-film resistor, or the reference resistor can be replaced by a memory cell with a magnetic channel junction.

9. The readout amplifier for the magnetic random access memory cell as described in claim 6, characterized in that, The read operation control switch connected to the other amplifier switching switch can be alternatively connected to the reference voltage.

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