Chip curing method, device, equipment and storage medium for improving wafer utilization rate

Abstract

The present invention relates to the field of chip technology, and specifically discloses a chip curing method, device, equipment and storage medium for improving the utilization rate of wafers. Among them, the method includes the following steps: equally dividing the die after redundant replacement into multiple storage areas; performing built-in self-test on the die to obtain the result information of each storage area, and the result information is used to mark whether the corresponding storage area is available; curing the available storage areas in the die according to the result information. This method divides the die into multiple storage areas, obtains the result information of all storage areas, and then cures the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding cured storage areas, so that even if there are a certain number of unavailable storage areas in the die, the capacity specification can still be adjusted downward for use, so as to improve the utilization rate of wafers.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular, to a chip curing method, device, equipment and storage medium for improving the utilization rate of wafers. Background Art

[0002] In the manufacturing process of wafers, various manufacturing defects will inevitably be introduced due to factors such as processes, so that the die on the wafer (wafer) is not 100% available, but there are certain defective products.

[0003] In traditional wafer testing, if there are still errors after redundant replacement of the die, the die will be determined to be a defective product. Even if there are only a small number of errors in the die, it will be discarded as a defective product, which restricts the utilization rate of the wafer.

[0004] In view of the above problems, there is currently no effective technical solution. Summary of the Invention

[0005] The purpose of this application is to provide a chip curing method, device, equipment and storage medium for improving the utilization rate of wafers, so that the die can still be used with a reduced capacity specification even if there are a certain number of unavailable storage areas, in order to improve the utilization rate of the wafer.

[0006] In a first aspect, this application provides a chip curing method for improving the utilization rate of wafers, which is used to cure the die. The method includes the following steps:

[0007] Divide the die after redundant replacement into multiple storage areas equally;

[0008] Perform built-in self-test on the die to obtain the result information of each storage area, and the result information is used to mark whether the corresponding storage area is available;

[0009] Cure the available storage areas in the die according to the result information.

[0010] A chip curing method for improving the utilization rate of wafers in this application divides the die into multiple storage areas, obtains the result information of all storage areas, and then cures the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding cured storage areas, so that the die can still be used with a reduced capacity specification even if there are a certain number of unavailable storage areas, in order to improve the utilization rate of the wafer.

[0011] In the described chip curing method for improving the utilization rate of wafers, the step of dividing the die after redundant replacement into multiple storage areas equally includes:

[0012] Divide the die after redundancy replacement into two equal storage areas.

[0013] In the chip solidification method for improving wafer utilization rate in this example, dividing the die into two equal storage areas can match the storage capacity specification of the chip and simplify the solidification logic.

[0014] In the described chip solidification method for improving wafer utilization rate, the step of dividing the die after redundancy replacement into multiple storage areas includes:

[0015] Divide the die after redundancy replacement into multiple storage areas according to address continuity.

[0016] In the described chip solidification method for improving wafer utilization rate, the step of performing built-in self-test on the die to obtain the result information of each storage area includes:

[0017] Perform built-in self-test on the multiple storage areas in sequence according to address continuity to obtain the result information of each storage area in sequence.

[0018] The chip solidification method for improving wafer utilization rate in this example tests the storage areas sequentially and independently, that is, the result information of multiple storage areas is independent of each other and does not affect each other, and each result information only reflects the test result of the corresponding storage area.

[0019] In the described chip solidification method for improving wafer utilization rate, the step of solidifying the available storage areas in the die according to the result information includes:

[0020] Generate capacity constraint information according to all the result information;

[0021] Write the capacity constraint information into the configuration bits of the die to solidify the available storage areas to achieve the capacity solidification of the die.

[0022] The chip solidification method for improving wafer utilization rate in this example writes the capacity constraint information as non-volatile data into the configuration bits of the die as the configuration information of the die, so that the final chip made based on this die can determine the capacity specification of the chip and obtain the storage units that can perform read / write / erase operations in the chip by reading the non-volatile capacity constraint information in the configuration bits.

[0023] In the described chip solidification method for improving wafer utilization rate, the step of generating capacity constraint information according to all the result information includes:

[0024] Write all the result information into the corresponding configuration bits of the die so that the corresponding configuration bits of the die generate non-volatile result information;

[0025] Obtain all the non-volatile result information, and generate capacity constraint information according to all the non-volatile result information.

[0026] The chip curing method for improving wafer utilization rate as described above, wherein the capacity constraint information is flag bit data, and the number of bits thereof is equal to the number of the storage areas.

[0027] In the chip curing method for improving wafer utilization rate in this example, the data of each flag bit in the capacity constraint information can represent whether the corresponding storage area is available.

[0028] In a second aspect, the present application further provides a chip curing device for improving wafer utilization rate, which is used for curing a die. The device includes:

[0029] A partitioning module, which is used for equally dividing the die after redundant replacement into a plurality of storage areas;

[0030] A testing module, which is used for performing built-in self-test on the die to obtain the result information of each of the storage areas, and the result information is used to mark whether the corresponding storage area is available;

[0031] A curing module, which is used for curing the available storage areas in the die according to the result information.

[0032] The chip curing device for improving wafer utilization rate of the present application uses the partitioning module to divide the die into a plurality of storage areas, obtains the result information of all the storage areas through the testing module, and then adopts the curing module to cure the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding cured storage areas, so that even if there are a certain number of unavailable storage areas in the die, the capacity specification can still be adjusted downward for use, so as to improve the utilization rate of the wafer.

[0033] In a third aspect, the present application further provides an electronic device, which includes a processor and a memory. The memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method provided in the first aspect as described above are run.

[0034] In a fourth aspect, the present application further provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the method provided in the first aspect as described above are run.

[0035] As can be seen from the above, the present application discloses a chip curing method, device, equipment and storage medium for improving the utilization rate of wafers. Among them, the chip curing method for improving the utilization rate of wafers divides the bare chip area into multiple storage areas, obtains the result information of all storage areas, and then cures the available storage areas in the bare chip according to all the result information, so that the capacity specification of the bare chip is determined according to the corresponding cured storage areas, so that even if there are a certain number of unavailable storage areas in the bare chip, the capacity specification can still be adjusted downward for use, so as to improve the utilization rate of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flowchart of the chip curing method for improving the utilization rate of wafers provided by an embodiment of the present application.

[0037] Figure 2 It is a schematic structural diagram of the chip curing device for improving the utilization rate of wafers provided by an embodiment of the present application.

[0038] Figure 3 It is a schematic structural diagram of the electronic device provided by an embodiment of the present application.

[0039] Reference numerals: 201, partitioning module; 202, testing module; 203, curing module; 3, electronic device; 301, processor; 302, memory; 303, communication bus. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0041] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions, and cannot be understood as indicating or implying relative importance.

[0042] A wafer generally contains multiple regularly arranged bare chips (bare DIEs).

[0043] A die is a chip produced in a foundry, that is, a chip that has not been packaged after the wafer has been cut and tested. There are only bonding pads (pads) for packaging on this die and it cannot be directly applied to an actual circuit. A die is extremely vulnerable to damage from the temperature, impurities, and physical forces in the external environment. Therefore, the die must be enclosed in a sealed space and corresponding pins must be led out to be used as a basic component.

[0044] Chip Probing (CP) is to use the pins of all the dies at this time and connect them to a test machine through fine test probes for testing before the wafer is diced and packaged. The purpose of CP is to screen out the available dies after the wafer production is completed and before packaging, improve the yield of the chips, and reduce the costs of subsequent packaging and testing.

[0045] Due to process and other factors, various manufacturing defects will inevitably be introduced, resulting in a certain number of bad memory cells in some dies (mainly manifested as read errors); during the wafer production process, spare memory cells are generally used to perform redundant replacement on these bad memory cells to salvage these dies so that their storage capacity can reach the expected capacity. Dies whose storage capacity still does not reach the expected capacity after redundant replacement (the number of spare memory cells is not enough to completely replace the bad memory cells) are regarded as defective products.

[0046] In a first aspect, please refer to Figure 1 , Figure 1 which is a method for curing chips to improve the utilization rate of wafers in some embodiments of the present application and is used to cure dies. The method includes the following steps:

[0047] S1. Divide the die after redundant replacement into multiple storage areas equally;

[0048] Specifically, from the foregoing content, it can be known that redundant replacement is to use spare memory cells to replace the bad memory cells in the die. This operation of redundant replacement is only used for memory cell replacement and does not include the detection of the result after replacement, that is, the result of whether there are still bad memory cells in the die after redundant replacement is unknown. Therefore, it is necessary to test the availability of the die after redundant replacement subsequently.

[0049] More specifically, this step divides the die into multiple storage areas equally, that is, the number of memory cells in each storage area is the same, and it can be used as the operation unit for die curing processing.

[0050] S2. Perform built-in self-test on the die to obtain the result information of each storage area. The result information is used to mark whether the corresponding storage area is available;

[0051] Specifically, the traditional built-in self-test (BIST) obtains test results by testing whether there are still defective memory cells in the entire die after redundant replacement, so as to determine whether the die is defective. In the embodiments of the present application, the built-in self-test is improved to test multiple memory regions in the die and obtain corresponding result information. For example, when a die is equally divided into two memory regions, performing a built-in self-test on the die will generate two result information, which are respectively used to mark whether the two memory regions are available.

[0052] More specifically, in the embodiments of the present application, the built-in self-test can directly generate result information, that is, the built-in self-test is to specifically detect the memory regions in the die to obtain corresponding result information; the built-in self-test can also indirectly generate result information, that is, the built-in self-test still tests the entire die to obtain the test results of the entire die, and then the method of the embodiments of the present application analyzes the test results to obtain the result information corresponding to multiple memory regions.

[0053] More specifically, the built-in self-test determines whether the corresponding memory cell is available (whether a read error occurs) through write and read operations, so as to obtain result information on whether there are unavailable memory cells in the corresponding memory region.

[0054] S3. Solidify the available memory regions in the die according to the result information.

[0055] Specifically, the result information obtained in step S2 reflects which memory regions in the entire die are available (memory regions where all memory cells can be used normally) and which memory regions are unavailable (memory regions where there are still defective memory cells). Step S3 only solidifies these available memory regions, so that the capacity specification of the die is set by these available memory regions, enabling the die to be used with a reduced capacity specification appropriately, so as to salvage the die and improve the wafer utilization rate. For example, when a 4Mb-capacity die is equally divided into two 2Mb memory regions and only one memory region is available, solidify this available memory region, so that the die is regarded as having a 2Mb capacity for use, so as to salvage the die and improve the wafer utilization rate; if all the memory regions of the 4M-capacity die are available, it is normally solidified to 4M capacity for use; if all the memory regions of the 4M-capacity die are unavailable, it is regarded as a defective product and discarded.

[0056] More specifically, the solidification process is to write information about which memory regions are available into the configuration file (configuration information bit, cfg) of the die, so as to limit the operation region of the die, that is, in the chip finally made from the die, operations such as reading, writing, and erasing are limited to be performed in the available memory regions.

[0057] A chip curing method for improving the utilization rate of wafers in an embodiment of the present application divides the bare die into multiple storage areas, obtains the result information of all storage areas, and then cures the available storage areas in the bare die according to all the result information, so that the capacity specification of the bare die is determined according to the corresponding cured storage areas, so that the bare die can still be used with a reduced capacity specification even if there are a certain number of unavailable storage areas, so as to improve the utilization rate of the wafer.

[0058] In some preferred embodiments, step S1 includes:

[0059] Divide the bare die after redundant replacement into 2-4 storage areas equally.

[0060] Specifically, the method in the embodiment of the present application aims to improve the utilization rate of wafers, but it needs to be carried out on the basis of not increasing the wafer test load as much as possible. When the number of storage areas into which the bare die is split is too large, too much result information will be generated and the computational complexity of the curing process will increase. Therefore, the embodiment of the present application sets the number of split storage areas to 2-4.

[0061] In some preferred embodiments, step S1 includes:

[0062] Divide the bare die after redundant replacement into two storage areas equally.

[0063] Specifically, the storage capacity specification of the chip is generally a power of 2, such as 2Mb, 4Mb, 8Mb, and 16Mb, etc. Dividing the bare die into two storage areas equally can match the storage capacity specification of the chip and simplify the curing logic.

[0064] In some preferred embodiments, step S1 includes:

[0065] Divide the bare die after redundant replacement into multiple storage areas according to address continuity.

[0066] Specifically, the addresses of flash chips are generally continuous. To ensure that the bare die can be used as a normal flash chip after curing, the bare die is divided equally according to address continuity.

[0067] More specifically, the address continuity refers to the position distribution characteristics of the storage units in the bare die, rather than being limited to representing the specific addresses of the storage units. The purpose of step S1 is to split the bare die into multiple continuously distributed storage areas; for the convenience of understanding the above equal division process, the storage unit addresses of the bare die can be assumed. For example, a bare die is defined to include storage units with addresses 0000-1111 according to the array position of the storage units. When the method in the embodiment of the present application divides the bare die into two equal parts, one storage area includes storage units with addresses 0000-0111, and the other storage area includes storage units with addresses 1000-1111.

[0068] In actual operation, the prerequisite for executing step S3 is that the result information obtained in step S2 marks the existence of available storage areas, that is, step S3 includes: when there are available storage areas, solidify the available storage areas in the die according to the result information. Therefore, in some preferred embodiments, when the result information obtained in step S2 marks that all storage areas are unavailable, the method of the embodiment of the present application further includes the following steps:

[0069] S4. When all storage areas are unavailable, divide each storage area into multiple sub-storage areas equally, obtain sub-result information corresponding to the sub-storage areas, the sub-result information is used to mark whether the corresponding sub-storage area is available, and solidify the available sub-storage areas in the die according to the sub-result information.

[0070] Specifically, the method of the embodiment of the present application can further split the die with all unavailable storage areas according to the above steps to adjust the capacity specification of the die again to save the die.

[0071] More specifically, the method of the embodiment of the present application can also split the die multiple times according to step S4. However, the capacity specification of the die itself is limited. After splitting the die multiple times, the capacity of each split area is too small, resulting in the cost of saving the die being much greater than the value of the saved die. Therefore, in the embodiment of the present application, the die is preferably split at most twice.

[0072] In some preferred embodiments, step S2 includes:

[0073] Perform built-in self-tests on multiple storage areas in sequence according to address continuity to obtain the result information of each storage area in sequence.

[0074] Specifically, the method of the embodiment of the present application tests the storage areas sequentially and independently, that is, the result information of multiple storage areas is independent of each other and does not affect each other, and each result information only reflects the test result of the corresponding storage area.

[0075] In some preferred embodiments, step S2 includes:

[0076] Perform built-in self-tests on multiple storage areas in increasing or decreasing order according to address continuity to obtain the result information of each storage area in sequence.

[0077] More specifically, when the die is equally divided into multiple storage areas in step S1, different marks are assigned to different storage areas. For example, when it is equally divided into two storage areas, they are respectively defined as the low-order area and the high-order area according to the location characteristics of the storage areas (or area numbers are set according to the location characteristics, such as area 1 and area 2). Correspondingly, by performing built-in self-test on multiple storage areas in increasing or decreasing order of address continuity, the result information of each storage area can be obtained in sequence, making the order of obtaining the result information correspond to the mark sorting of the storage areas, which is beneficial to the integration of data information and also conducive to the solidification process of the die.

[0078] In some preferred embodiments, step S3 includes:

[0079] S31. Generate capacity constraint information according to all result information;

[0080] Specifically, the result information can reflect whether the corresponding storage area is available and can be used as a guiding parameter for the solidification process. The capacity constraint information generated based on all result information is used to directly constrain the usable area of the die.

[0081] S32. Write the capacity constraint information into the configuration bits of the die to solidify the available storage areas, so as to achieve the capacity solidification of the die.

[0082] Specifically, the capacity constraint information is volatile data and needs to be written into the configuration bits of the die to become non-volatile data, thereby limiting the storage units that can be used normally in the die. These storage units that can be used normally correspond to all available storage areas.

[0083] More specifically, the capacity constraint information can be specific constraint data for constraining the storage units that can be used normally in the die, and the capacity constraint information can also be a flag bit data for flagging the storage units that can be used normally in the die.

[0084] The method of the embodiment of the present application writes the capacity constraint information as non-volatile data into the configuration bits of the die as the configuration information of the die, so that the finally manufactured chip based on the die can determine the capacity specification of the chip and obtain the storage units that can perform read, write, and erase operations in the chip by reading the non-volatile capacity constraint information in the configuration bits.

[0085] In some preferred embodiments, the step of generating capacity constraint information according to all result information includes:

[0086] S311. Write all result information into the corresponding configuration bits of the die so that the corresponding configuration bits of the die generate non-volatile result information;

[0087] Specifically, the data information generated during the CP test is all volatile data, that is, the result information belongs to volatile data. To avoid problems such as data loss caused by power failure and other reasons and facilitate subsequent detection and repair of the die, this step writes the result information of the volatile data into the corresponding configuration bits of the die, so that the die itself carries non-volatile result information about whether the storage area is available.

[0088] More specifically, the data in the configuration bits of the die is updatable data. Writing the result information and the capacity constraint information into the die configuration bits can enable the finally obtained chip product to check and update its normally usable storage units according to the data in the configuration bits.

[0089] S312. Obtain all non-volatile result information and generate capacity constraint information according to all non-volatile result information.

[0090] More specifically, in other embodiment modes, the step of generating capacity constraint information according to the result information includes: directly generating capacity constraint information according to the result information obtained in step S2; this step skips the process of writing the result information into the die configuration bits and directly generates capacity information according to the volatile result information, saving the process of writing the result information and obtaining the non-volatile result information, and can improve the solidification efficiency of the whole method; but relatively, the die does not store non-volatile result information, resulting in the die being unable to check the capacity constraint information written in the configuration bits according to the non-volatile result information after the solidification is completed.

[0091] In some preferred embodiment modes, the capacity constraint information is flag bit data, and the number of its bits is equal to the number of storage areas.

[0092] Specifically, the result information of the storage area includes two states: available and unavailable. Therefore, 0 and 1 in a flag bit data can respectively represent the test results of the storage area. That is, in the application embodiment, the result information is a flag bit data of 0 or 1; when the result information corresponds to n storage areas, there are 2 n combinations. Correspondingly, the die equally divided into n storage areas has 2 n -1 (excluding the result that all storage areas are unavailable) solidification forms. Therefore, setting the capacity constraint information to have the same number of bits as the number of storage areas enables the capacity constraint information to have 2 nA combined form that can correspond to the result information representing all storage areas, thereby restricting the capacity of the die, enabling the data of each flag bit in the capacity constraint information to represent whether the corresponding storage area is available. For example, when the die is equally divided into two storage areas, the capacity constraint information is a two-bit binary data, that is, it includes a total of 4 results: 00, 01, 10, and 11 (one of the results is discarded as a test result for the die being unavailable). The data 1 or 0 at the corresponding bit can restrict whether the corresponding storage area is available. When a chip made using this die is in use, by reading the capacity constraint information at this configuration bit, the storage units that can be used normally are determined.

[0093] In a second aspect, please refer to Figure 2 , Figure 2 which is a chip curing device for improving the utilization rate of wafers provided in some embodiments of the present application and is used to cure dies. The device includes:

[0094] A partitioning module 201 for equally dividing the die after redundancy replacement into multiple storage areas;

[0095] A testing module 202 for performing a built-in self-test on the die to obtain the result information of each storage area, and the result information is used to mark whether the corresponding storage area is available;

[0096] A curing module 203 for curing the available storage areas in the die according to the result information.

[0097] A chip curing device for improving the utilization rate of wafers according to an embodiment of the present application uses the partitioning module 201 to divide the die into multiple storage areas, obtains the result information of all storage areas through the testing module 202, and then uses the curing module 203 to cure the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding cured storage areas, thereby enabling the die to still reduce the capacity specification for use even if there are a certain number of unavailable storage areas, so as to improve the utilization rate of the wafer.

[0098] In actual operation, the curing module 203 is used to cure the available storage areas in the die according to the result information when there are available storage areas. Therefore, in some preferred embodiments, the device according to the embodiment of the present application further includes:

[0099] A secondary curing module for equally dividing each storage area into multiple sub-storage areas when all storage areas are unavailable, obtaining the sub-result information corresponding to the sub-storage areas, and curing the available sub-storage areas in the die according to the sub-result information, and the sub-result information is used to mark whether the corresponding sub-storage area is available.

[0100] Specifically, the device according to the embodiments of the present application can further split a die with unavailable storage areas through a secondary curing module to adjust the capacity specification of the die again and save the die.

[0101] In some preferred embodiments, the chip curing device for improving the wafer utilization rate is used to execute the chip curing method for improving the wafer utilization rate in the first aspect above.

[0102] For a third aspect, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of an electronic device provided by the embodiments of the present application. The present application provides an electronic device 3, including: a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other through a communication bus 303 and / or other forms of connection mechanisms (not marked). The memory 302 stores a computer program executable by the processor 301. When the computing device runs, the processor 301 executes the computer program to execute the method in any optional implementation manner of the above embodiments.

[0103] For a fourth aspect, the embodiments of the present application provide a storage medium, on which a computer program is stored. When the computer program is executed by a processor, it executes the method in any optional implementation manner of the above embodiments. Among them, the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (abbreviated as SRAM), electrically erasable programmable read-only memory (abbreviated as EEPROM), erasable programmable read-only memory (abbreviated as EPROM), programmable read-only memory (abbreviated as PROM), read-only memory (abbreviated as ROM), magnetic memory, flash memory, magnetic disk or optical disc.

[0104] Embodiment 1

[0105] During the wafer preparation process, a CP test device is used to perform a good or bad test and curing process on a die (an unpackaged chip), and the die has completed the redundant replacement process. Among them, the good or bad test process includes:

[0106] A1. Power on and send an instruction to enter the good or bad test mode;

[0107] A2. Send a read instruction and perform a read operation on the entire address space.

[0108] A3. Configure the test mode register tm_novol_rd_sel, and use this register tm_novol_rd_sel to obtain multiple result information in combination with the read operation result. The result information corresponds to the storage areas that are equally divided into different address segments according to the address space in advance;

[0109] A4. Use the test mode register tm_novol_rd_sel to write all the result information into the die in one key, so as to realize the solidification of volatile result information into non-volatile result information, and mark whether the corresponding storage area is available;

[0110] A5. Power off and exit.

[0111] Among them, the solidification process includes:

[0112] B1. Power on again and send an instruction to enter the solidification processing mode;

[0113] B2. Configure the test mode registers tm_only_pass_en and density (capacity constraint information);

[0114] B3. Read the non-volatile result information of the die, and use the configured test mode register tm_only_pass_en to send a one-key solidification instruction. When the non-volatile result information corresponds to the density, write the value of the density into the die to solidify the die. If they do not correspond, return to B2;

[0115] B4. Power off and exit.

[0116] Specifically, when step B3 returns to step B2, configure other combined forms of density and the test mode register tm_only_pass_en in sequence until step B3 completes the die solidification or traverses all available densities.

[0117] In summary, the embodiments of the present application disclose a chip solidification method, device, equipment and storage medium for improving the wafer utilization rate. Among them, the chip solidification method for improving the wafer utilization rate divides the die area into multiple storage areas, obtains the result information of all storage areas, and then solidifies the available storage areas in the die according to all the result information, so that the capacity specification of the die is determined according to the corresponding solidified storage areas, so that even if there are a certain number of unavailable storage areas in the die, the capacity specification can still be adjusted down for use, so as to improve the utilization rate of the wafer.

[0118] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical or other forms.

[0119] In addition, the units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] Furthermore, in each embodiment of this application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0121] In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0122] The above are only the embodiments of this application and are not used to limit the protection scope of this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.

Claims

1. A chip curing method for improving wafer utilization rate, which is used to cure bare chips, Characterized in that, The method includes the following steps: Dividing the bare chip after redundant replacement into multiple storage areas equally; Performing built-in self-test on the bare chip to obtain the result information of each storage area, and the result information is used to mark whether the corresponding storage area is available; When there are available storage areas, curing the available storage areas in the bare chip according to the result information; When all storage areas are unavailable, each storage area is divided into multiple sub-storage areas equally, obtaining sub-result information corresponding to the sub-storage areas, the sub-result information is used to mark whether the corresponding sub-storage area is available, and curing the available sub-storage areas in the bare chip according to the sub-result information.

2. The chip curing method for improving wafer utilization rate according to claim 1, Characterized in that, The step of dividing the bare chip after redundant replacement into multiple storage areas equally includes: Dividing the bare chip after redundant replacement into two storage areas equally.

3. The chip curing method for improving wafer utilization rate according to claim 1, Characterized in that, The step of dividing the bare chip after redundant replacement into multiple storage areas equally includes: Dividing the bare chip after redundant replacement into multiple storage areas equally according to address continuity.

4. The chip curing method for improving wafer utilization rate according to claim 3, Characterized in that, The step of performing built-in self-test on the bare chip to obtain the result information of each storage area includes: Performing built-in self-test on the multiple storage areas sequentially according to address continuity to obtain the result information of each storage area in turn.

5. The chip curing method for improving wafer utilization rate according to claim 1, Characterized in that, The step of curing the available storage areas in the bare chip according to the result information includes: Generating capacity constraint information according to all the result information; Writing the capacity constraint information into the configuration bits of the bare chip to cure the available storage areas, so as to realize the capacity curing of the bare chip.

6. The chip curing method for improving wafer utilization rate according to claim 5, Characterized in that, The step of generating capacity constraint information according to all the result information includes: Writing all the result information into the corresponding configuration bits of the bare chip, so that the corresponding configuration bits of the bare chip generate non-volatile result information; Obtaining all the non-volatile result information, and generating capacity constraint information according to all the non-volatile result information.

7. The chip curing method for improving wafer utilization rate according to claim 5, Characterized in that, The capacity constraint information is flag bit data, and the number of bits is equal to the number of storage areas.

8. A chip curing device for improving wafer utilization rate, which is used to cure bare chips, Characterized in that, The device includes: A partitioning module, which is used to divide the bare chip after redundant replacement into multiple storage areas equally; A test module for performing built-in self-test on the die to obtain result information of each of the storage areas, the result information being used to mark whether the corresponding storage area is available; A curing module for, when there is an available storage area, curing the available storage areas in the die according to the result information, and when all storage areas are unavailable, equally dividing each storage area into a plurality of sub-storage areas, obtaining sub-result information corresponding to the sub-storage areas, the sub-result information being used to mark whether the corresponding sub-storage area is available, and curing the available sub-storage areas in the die according to the sub-result information.

9. An electronic device, characterized in that, it includes a processor and a memory, the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in any one of the methods according to claims 1-7 are run.

10. A storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, the steps in any one of the methods according to claims 1-7 are run.

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