Single Hall Latch Sensor and Electronics

Abstract

The present application discloses a single Hall latch sensor and electronic device, the single Hall latch sensor comprising: a Hall sensing module for switching the control end and output end of the Hall element according to a first cycle, and inputting a threshold control current to each signal end in sequence according to a second cycle, so that the Hall sensing module has two magnetic field thresholds; a comparison module for receiving a sensing signal and outputting a corresponding comparison signal, wherein the comparison signal flips when the external magnetic field reaches the magnetic field threshold; a latch module connected to the output end of the comparison module, for performing a latch logic operation on the comparison signal output by the comparison module, and outputting a control signal, wherein when one of the comparison signals flips, the control signal flips and latches the current state until another comparison signal flips and the comparison signal level flips again. The output signal of the above-mentioned single Hall latch sensor is highly reliable and has a small area and power consumption.

Description

Technical Field

[0001] The present application relates to the field of Hall sensor technology, and in particular to a single Hall latch sensor and electronic equipment. Background Art

[0002] A Hall device is a magnetic sensor based on the Hall effect principle. The Hall effect is a type of electromagnetic effect. When current passes through a conductor perpendicular to the external magnetic field, an additional electric field is generated inside the conductor perpendicular to the direction of the current and magnetic field, thereby generating a potential difference between the two ends of the conductor. This phenomenon is the Hall effect, and this potential difference is called the Hall potential difference.

[0003] The Hall sensor integrates the Hall element. This type of sensor device has the characteristics of low power consumption, high sensitivity, and high input and output isolation. It has been widely used in industries such as industry, communications, and instrument manufacturing.

[0004] To expand the application range of Hall sensors, they are typically required to be able to sense all polarities, meaning they can sense both the South Pole and the North Pole magnetic fields. In existing technologies, two Hall elements are required to sense magnetic fields in the North Pole and South Pole directions, respectively. Since the output signal of a Hall sensor is easily affected by external magnetic field jitter, the presence of two Hall elements makes the output signal more susceptible to external magnetic field jitter, further reducing the reliability of the Hall sensor's output signal. Furthermore, the presence of two Hall elements results in a larger chip area and greater power consumption for the Hall sensor. Summary of the Invention

[0005] In view of this, the present application provides a single Hall latch sensor and an electronic device to solve the problem of insufficient reliability of the control signal of the existing Hall sensor.

[0006] The present application provides a single Hall latch sensor, comprising: a Hall sensing module including a single Hall element, the Hall element having two pairs of signal terminals, one pair of signal terminals serving as two control terminals connected to a control voltage terminal for inputting a control voltage, and the other pair of signal terminals serving as two output terminals for outputting sensing signals related to an external magnetic field; the Hall sensing module configured to switch the control terminal and the output terminal of the Hall element according to a first cycle, and sequentially input a threshold control current to each signal terminal according to a second cycle, so that the Hall sensing module has two magnetic field thresholds; a comparison module configured to receive the sensing signal and output a corresponding comparison signal based on the sensing signal, wherein the comparison signal flips when the external magnetic field reaches the corresponding magnetic field threshold; and a latch module connected to the output terminal of the comparison module, configured to perform a logical operation on the comparison signal output by the comparison module and output a control signal, wherein when one of the comparison signals flips, the level of the control signal flips and latches the current state until the other comparison signal flips, at which point the level of the control signal flips again.

[0007] Optionally, the latch module includes a shift register and a logic operation unit connected to the output end of the shift register; the shift register is used to output the two comparison signals output serially by the comparison module in parallel as signals Q1 and Q2; the logic operation unit is used to operate on the signals Q1 and Q2 and output the control signal Q3, wherein the operation logic is: the n+1th control signal

[0008] Optionally, the shift register includes a first trigger and a second trigger, the input end of the first trigger is connected to the output end of the comparison module, the output end of the first trigger is connected to the input end of the second trigger, and the clock ends of the first trigger and the second trigger are used to connect to the first clock signal.

[0009] Optionally, the logic operation unit includes a first NOT gate, a second NOT gate, an AND gate, an OR gate and a third trigger, the two output ends of the shift register are respectively connected to the input ends of the first NOT gate and the second NOT gate; one input end of the AND gate is connected to the output end of the first NOT gate, and the output end of the AND gate is connected to an input end of the OR gate; the other input end of the OR gate is connected to the output end of the second NOT gate, and the output end of the OR gate is connected to the output end of the third trigger; the output end of the third trigger is connected to the other input end of the AND gate, and the clock end of the third trigger is used to connect to the second clock signal; the rising edge moment of the second clock signal is located between every two rising edges of the first clock signal.

[0010] Optionally, the first period and the second period are the same.

[0011] Optionally, the comparison module includes a first amplifier and a comparator connected to the output end of the first amplifier; the two input ends of the first amplifier are respectively connected to the two output ends of the Hall element, for amplifying the sensing voltage between the two output ends and outputting it to the comparator as the differential input signal of the comparator; the comparator outputs a corresponding comparison signal according to the size of the input differential input signal; a capacitor is connected in series between the positive output end of the first amplifier and the negative input end of the comparator, and a switch is connected in series between the negative input end and the output end of the comparator, and the negative input end of the first amplifier is connected to the positive input end of the comparator.

[0012] Optionally, the Hall sensing module includes: a control current providing unit, a current switching unit and a control voltage switching unit; the control current providing unit is used to provide a threshold control current; the current switching unit is used to switch the on-off state between the current output end of the control current providing unit and the various signal ends of the Hall element according to the second cycle; the control voltage switching unit is used to switch the control end and the output end of the Hall element according to the first cycle.

[0013] Optionally, the control current providing unit includes: a clamp amplifier, the positive input terminal of the clamp amplifier is connected to the control voltage terminal, the negative input terminal is connected to the fixed potential terminal, and the output terminal of the clamp amplifier is connected to the negative input terminal of the clamp amplifier.

[0014] Optionally, a switch element is further connected between the fixed potential end and the current switching unit, and the output end of the clamp amplifier is connected to the control end of the switch element.

[0015] Optionally, the control current providing unit further includes: a current limiting resistor connected in series between the power supply voltage and the fixed potential terminal, and the electron mobility of the current limiting resistor is the same as that of the Hall element at the same temperature.

[0016] Optionally, the current switching unit includes: a current path connected between the current output end and each signal end of the Hall element, and each circuit path is provided with a switch to control the on-off state of each current path.

[0017] Optionally, the control voltage switching unit includes four switches, two of which are respectively connected between the control voltage terminal and two adjacent signal terminals of the Hall element; and the other two switches are respectively connected between the other two signal terminals of the Hall element and the ground terminal.

[0018] The present application also provides an electronic device, comprising: a single Hall latch sensor as described in any one of the above items.

[0019] The single Hall latch sensor of the present application has only a single Hall element. By periodically switching the control end and the output end of the Hall element, and inputting the threshold control current to each signal end in turn, the output control signal corresponds to two magnetic field thresholds, realizing omnipolar sensing, and performing latch logic processing on the South Pole comparison signal and the North Pole comparison signal to realize the latching of the control signal, avoiding the problem of unstable magnetic field threshold caused by external magnetic field jitter, eliminating the influence of external magnetic field jitter on the output control signal, so that the single Hall latch sensor can output a more stable and reliable control signal.

[0020] Furthermore, the single Hall latch sensor has a single Hall element, which reduces the area and power consumption of the Hall latch sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 This is a schematic structural diagram of a single Hall latch sensor according to an embodiment of the present application;

[0023] Figure 2a 1 is a schematic structural diagram of a Hall element of a single Hall latch sensor according to an embodiment of the present application;

[0024] Figure 2b 1 is an equivalent schematic diagram of a Hall element of a single Hall latch sensor according to an embodiment of the present application;

[0025] Figure 3 1 is a schematic structural diagram of a latch logic module of a single Hall latch sensor according to an embodiment of the present application;

[0026] Figure 4 This is a schematic structural diagram of a single Hall latch sensor according to an embodiment of the present application;

[0027] Figure 5 1 is a partial structural diagram of a single Hall latch sensor according to an embodiment of the present application;

[0028] Figure 6 This is a functional schematic diagram of a single Hall latch sensor according to an embodiment of the present application;

[0029] Figure 7 1 is a timing diagram of various switch control signals and clock signals of a single Hall latch sensor according to an embodiment of the present application;

[0030] Figure 8a 1 is a circuit diagram of a single Hall latch sensor in cycle 1 during operation of the present application;

[0031] Figure 8b This is a circuit diagram of cycle 2 during the operation of the single Hall latch sensor of the present application;

[0032] Figure 8c 1 is a circuit diagram of a single Hall latch sensor of the present application during operation in cycle 3;

[0033] Figure 8d This is a circuit diagram of cycle 4 during the operation of the single Hall latch sensor of the present application. DETAILED DESCRIPTION

[0034] The present invention provides a new single Hall latch sensor, which improves the reliability of the control signal output by the Hall sensor.

[0035] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0036] Please refer to Figure 1 , is a schematic structural diagram of a single Hall latch sensor according to an embodiment of the present invention.

[0037] The single Hall latch sensor includes a Hall sensing module 110 , a comparison module 120 and a latch module 140 .

[0038] The Hall sensor module 110 includes: a single Hall element, which is used to generate a corresponding Hall voltage according to the change of the external magnetic field. In this embodiment, the Hall element is a Hall disk (see Figure 2a ), the Hall element is a square Hall disk, and the two pairs of signal terminals are located at two opposite corners. There are two pairs of signal terminals, one pair of signal terminals is H1 and H3, and the other pair of signal terminals is H2 and H4. One pair of signal terminals serves as two control terminals, connected to the control voltage terminal for inputting a control voltage, and the other pair of signal terminals serves as two output terminals, which are used to output sensing signals related to the external magnetic field. In this embodiment, the two control terminals and the two output terminals are located at two opposite corners of the square Hall disk, and the direction of the control current between the control terminals is 90° out of phase with the induced current between the output terminals.

[0039] The Hall sensor module 110 is also used to switch the control end and the output end of the Hall element according to the first cycle, and input a fixed threshold control current to each signal end in turn according to the second cycle, so that when the control signal is reversed, the external magnetic field corresponds to any one of the two magnetic field thresholds in opposite directions. Since the Hall sensor is equivalent to a resistor, for example, a square Hall disk is equivalent to a Wheatstone bridge (see Figure 2b ), the resistance of each bridge arm is R H , the equivalent resistance of the entire Hall plate is R H When the threshold control current is input at one end, the output sensor signal can be adjusted. When the magnetic field changes, the sensor signal output between the two output ends is the Hall voltage V H The threshold voltage generated by the superimposed threshold control current is V'. Therefore, by adjusting the threshold control current, the output sensor signal can be adjusted. By inputting the threshold control current in different directions, two threshold voltages with opposite phases are generated, namely V' and -V'. Then the sensor signals output between the two output terminals are V H +V', and V H -V'.

[0040] In one embodiment, the magnitude of the sensing signal output between the two output terminals can be adjusted by inputting a threshold control current, and the magnitude of the sensing signal output from the two output terminals is used as the differential signal input to the comparison module 120. When the differential signal between the two output terminals is 0, that is, V H +V'=0 and V H When -V'=0, the signal flips, which corresponds to two Hall voltage thresholds, namely V H =-V', V H =V', which in turn corresponds to two opposite polarity magnetic field thresholds, Bop = B0 and Brp = -B0, corresponding to the South Pole and North Pole magnetic fields, respectively, thus achieving omnipolar Hall sensing. By periodically switching the input and control terminals of the Hall element, the comparison results with the South Pole magnetic field threshold and the North Pole magnetic field threshold can be achieved respectively.

[0041] The comparison module 120 is configured to receive the sensing signal and output a corresponding comparison signal VO1 based on the sensing signal. When the external magnetic field reaches a magnetic field threshold, the comparison signal flips. The comparison signal is 0 (low level) or 1 (high level). The flipping of the comparison signal includes flipping from 0 to 1 or from 1 to 0.

[0042] The latch module 140 is connected to the output of the comparison module 120 and is used to receive the comparison signal VO1 output by the comparison module 120. Based on the switching cycle of the input and control terminals of the Hall element, the comparison module 120 sequentially outputs comparison signals corresponding to the comparison results of the external magnetic field with the south pole magnetic field threshold and the north pole magnetic field threshold. The latch module 140 performs a latching logic operation on the two comparison signals corresponding to the comparison results of the south pole magnetic field threshold and the north pole magnetic field threshold, and outputs the corresponding control signal. When one of the comparison signals flips, the control signal flips and latches the current state until the other comparison signal flips, at which point the control signal level flips again, ultimately achieving the latching function.

[0043] Please refer to Figure 3 , which is a schematic diagram of the functional module structure of a latch module implemented in one embodiment of the present invention.

[0044] In some embodiments, the latch module 140 includes a shift register 141 and a logic operation unit 142 connected to the output end of the shift register 141; the shift register 141 is used to obtain the comparison signal VO1 of the two serial inputs outputted by the comparison module 120 in sequence, and output them in parallel as signals Q1 and Q2; the logic operation unit 132 is used to operate the signals Q1 and Q2 and then output the control signal Q3, and the operation logic implemented by the logic operation unit 132 is: the n+1th control signal

[0045] Due to the diversity of digital logic operation implementations, in other embodiments, the latch module 140 may also adopt other functional module structures or other operation logics, as long as it can ultimately achieve the logic operation function implemented by the latch module 140 in this application.

[0046] Please refer to Figure 4 , is a schematic structural diagram of a single Hall latch sensor according to an embodiment of the present invention.

[0047] In this embodiment, the Hall sensor module 110 includes a control voltage switching unit, a control current providing unit 131 and a current switching unit 132 .

[0048] The control voltage switching unit is used to switch the on-off state between the control voltage terminal A and the two pairs of signal terminals of the Hall element according to the threshold control signal in a first cycle to switch the control terminal and the output terminal of the Hall element.

[0049] In this embodiment, the control voltage switching unit includes switches S1a, S2a, S2e, and S1e. Switches S1a and S2a are respectively connected between the control voltage terminal A and two adjacent signal terminals H1 and H4 of the Hall element. The other two signal terminals H2 and H3 of the Hall element are grounded via switches S2e and S1e, respectively. When switches S1a and S1e are on and switches S2a and S2e are off, signal terminal H1 is connected to the control voltage terminal A, signal terminal H3 is grounded, H1 and H3 serve as control terminals, and the two signal terminals H2 and H4 serve as signal output terminals. When switches S2a and S2e are on and switches S1a and S1e are off, signal terminal H4 is connected to the control voltage terminal A, signal terminal H2 is grounded, H4 and H2 serve as control terminals, and the two signal terminals H1 and H3 serve as signal output terminals.

[0050] The periodic switching between the control end and the output end can be achieved by periodically controlling the on and off states of the switches S1a, S2a, S1e, and S2e.

[0051] In this embodiment, a first resistor R0 is connected in series between the control voltage terminal A and the power supply voltage VDD, and the control current flowing through the Hall element 110 is limited by the first resistor R0. H ,but

[0052] The control current providing unit 131 is used to provide a fixed threshold control current I1, and the current switching unit 132 is used to periodically switch the on / off state between the current output terminal of the control current providing unit 131 and each signal terminal of the Hall element according to the threshold control signal, thereby periodically inputting the threshold control current to each signal terminal in sequence. In this embodiment, the control current providing unit 131 includes a current limiting resistor R1 connected in series between the power supply voltage VDD and the fixed potential terminal B, and the fixed potential terminal B has a fixed potential V B , the fixed potential terminal B is the current output terminal of the control current providing unit 131. The threshold control current

[0053] The fixed potential terminal B can be connected to a constant voltage power supply or a clamping circuit so that the fixed potential terminal B has a fixed potential. In this embodiment, the potential of the fixed potential terminal B is clamped to the potential VA of the control voltage terminal A by a clamping amplifier, that is, VB=VA. Specifically, in this embodiment, the control current providing unit also includes: a clamping amplifier AP2, the positive input terminal of the clamping amplifier AP2 is connected to the control voltage terminal A, the negative input terminal is connected to the fixed potential terminal B, and the output terminal of the clamping amplifier AP2 is connected to the negative input terminal of the clamping amplifier AP2. The clamping amplifier AP2 clamps the potential VB of the negative input terminal, i.e., the fixed potential terminal B, to the potential V of the control voltage terminal A. A ,Right now

[0054] The threshold control current I1 between the current limiting resistor R1 and the fixed potential terminal B

[0055]

[0056] Furthermore, in this embodiment, a switching element is connected between the fixed potential terminal B and the output terminal of the clamping amplifier AP2, with the output terminal of the clamping amplifier AP2 connected to the control of the switching element. The switching element is turned on only when the clamping amplifier AP2 is in normal operation, connecting the fixed potential terminal B to the Hall element. In this embodiment, the switching element is a PMOS transistor M0. The output terminal of the clamping amplifier AP2 is connected to the gate of the PMOS transistor M0, the source of the PMOS transistor M0 is connected to the negative input terminal of the clamping amplifier AP2, and the drain of the PMOS transistor M0 is connected to the current switching unit 132. In other embodiments, the switching element may be omitted, and the fixed potential terminal B may be directly connected to the input terminal of the current switching unit 132.

[0057] In other embodiments, the potential of the fixed potential terminal B may be limited to a fixed potential value by other clamping circuits. The specific structure of the clamping circuit is not limited here, and those skilled in the art may make a reasonable selection according to needs.

[0058] Furthermore, the current switching unit 132 includes a current path connected between the current output terminal B and each signal terminal. Each circuit path is provided with a switch to control the on / off state of each current path. Specifically, switches S3a and S2b are connected in series between the current output terminal and the signal terminal H1, switches S4a and S2c are connected in series between the current output terminal and the signal terminal H2, switches S3a and S1c are connected in series between the current output terminal and the signal terminal H3, and switches S3a and S1b are connected in series between the current output terminal and the signal terminal H4.

[0059] The current switching unit 132 may further include a switch connected to the connection path between the Hall element and the comparison module 120, and configured to connect the switched output terminal of the Hall element to the comparison module 120 when the output terminal of the Hall element switches. Specifically, a switch S2d is connected in series between the signal terminal H1 and the positive input terminal of the first amplifier AP1, a switch S1d is connected in series between the signal terminal H4 and the positive input terminal of the first amplifier AP1, a switch S1f is connected in series between the signal terminal H2 and the negative input terminal of the first amplifier AP1, and a switch S2f is connected in series between the signal terminal H3 and the negative input terminal of the first amplifier AP1.

[0060] The on-off state of each switch in the control voltage switching unit and the current switching unit 132 can be controlled by a threshold control signal, and the on-off state of each switch is periodically controlled, thereby switching the input end and the control end of the Hall element according to the first cycle, and inputting the threshold control current I1 to each signal end of the Hall element in turn according to the second cycle.

[0061] In this embodiment, the comparison module 120 includes a first amplifier AP1 and a comparator COMP connected to the output of the first amplifier AP1. The first amplifier AP1 has two inputs connected to the two outputs of the Hall element, amplifying the sensing signal between the two outputs and outputting it to the comparator COMP as a differential input signal for the comparator COMP. The comparator COMP outputs a corresponding comparison signal Vo1 based on the magnitude of the differential input signal. The first amplifier AP1 has two outputs connected to the two inputs of the comparator COMP, a capacitor C0 connected between one output of the first amplifier AP1 and the negative input of the comparator COMP, and a switch S2g connected between the negative input of the comparator COMP and the output of the comparator COMP. The first amplifier AP1 amplifies the mixed signal of the Hall voltage and the threshold voltage and stores the amplified signal in capacitor C0. The comparator COMP then determines whether the current magnetic field has reached the set threshold voltage.

[0062] Please refer to further Figure 5 , is a structural diagram of a first amplifier AP1 according to an embodiment of the present invention.

[0063] The first amplifier AP1 internally includes a third amplifier AP3 and a fourth amplifier AP4; the positive input terminal of the third amplifier AP3 is connected to one output terminal of the Hall element and receives an input voltage V1; a resistor R4 is connected in series between the negative input terminal of the third amplifier AP3 and the positive input terminal of the fourth amplifier AP4; the negative input terminal of the fourth amplifier AP4 is connected to the other output terminal of the Hall element and receives an input voltage V2; the output terminal of the third amplifier AP3 outputs a voltage V3, and a resistor R3 is connected in series between the output terminal and its negative input terminal; the output terminal of the fourth amplifier AP4 outputs a voltage V4, and the output terminal is connected to its positive input terminal.

[0064] according to Figure 5 The circuit can be obtained as follows:

[0065]

[0066] V4=V2;

[0067] From the above formula, we know that V3>>V4. Relative to V3, V4 can be regarded as a DC signal. Therefore, the first amplifier can amplify the differential signals V1 and V2 into differential signals V3 and V4. A1 is the amplification factor of the third amplifier AP3.

[0068] In other embodiments, the first amplifier AP1 may also adopt other circuit structures capable of performing differential amplification on input signals.

[0069] Please continue to refer to Figure 4 In this embodiment, the shift register 141 (not shown) of the latch module 140 is composed of two connected flip-flops. Specifically, the shift register 141 includes a first flip-flop T1 and a second flip-flop T2. The input terminal D1 of the first flip-flop T1 is connected to the output terminal of the comparison module 120, and the output terminal of the first flip-flop T1 is connected to the input terminal D2 of the second flip-flop T2. The clock terminals C1 and C2 of the first flip-flop T1 and the second flip-flop T2 are used to connect to the first clock signal CK1. When the first clock signal CK1 rises, the first flip-flop T1 and the second flip-flop T2 respectively output the signals at their respective input terminals and pass them backward.

[0070] In the initial state, the initial states of the output ends of the first trigger T1 and the second trigger T2 are both 0. At the first rising edge of the first clock signal CK1, the first trigger T1 outputs the currently received comparison signal VO1-1 and serves as the input end signal of the second trigger T2; when the next rising edge of the first clock signal CK1 arrives, the first trigger T1 outputs the currently received comparison signal VO1-2, and the second trigger T2 simultaneously outputs the comparison signal VO1-1, thereby achieving the parallel output of the two signals VO1-1 and VO1-2 at the second rising edge of CK1.

[0071] In this embodiment, the first trigger T1 and the second trigger T2 are both D-type triggers; in other embodiments, the first trigger T1 and the second trigger T2 may also be other types of triggers such as JK triggers and T-type triggers.

[0072] The logic operation unit 142 of the latch module 140 (please refer to Figure 3 ) includes a first NOT gate INV1, a second NOT gate INV2, an AND gate AND, an OR gate OR and a third flip-flop T3, the two output ends of the shift register 141 are respectively connected to the input ends of the first NOT gate INV1 and the second NOT gate INV2; one input end of the AND gate AND is connected to the output end of the first NOT gate INV1, and the output end is connected to an input end of the OR gate OR; the other input end of the OR gate OR is connected to the output end of the second NOT gate INV2, and the output end of the OR gate OR is connected to the output end of the third flip-flop T3; the output end of the third flip-flop T3 is connected to the other input end of the AND gate AND, and the clock end of the third flip-flop T3 is used to be connected to the second clock signal CK2; the rising edge of the second clock signal CK2 is located between every two rising edges of the first clock signal CK1, and the signal transferred from the first flip-flop T1 to the second flip-flop T2 at the second rising edge of CK1 is output at the rising edge of the second clock signal CK2.

[0073] The first trigger T1 receives the comparison signal VO1 output by the comparison module 120, and outputs a signal Q1 at the rising edge of the first clock signal CK1. Q1 is output as The output signal Q3 of the third trigger T3 is used as the input signal of the AND gate AND, and the output signal is As an input signal of the OR gate OR; and the signal Q2 output by the second trigger T2 is output through the second NOT gate INV2 As another input signal of the OR gate OR; the OR gate OR and Perform an OR operation to obtain the input signal D3 of the third flip - flop T3. When the second clock signal CK2 is at a high level, output the next - moment Q3. From this analysis, it can be obtained that

[0074] In this embodiment, the latch module 140 is also connected to the output module 150, and is used to invert and amplify the control signal Q3 output by the latch module 140 and output it as the control signal VOUT. The output module 150 includes a transistor M and a resistor R2. In this embodiment, the transistor M is an NMOS transistor. One end of the resistor R2 is connected to the power supply voltage VDD, and the other end is connected to the source of the transistor M. The gate of the transistor M is connected to the output end of the latch module 140, and the drain is grounded. The source of the transistor M is used as the output end to output the control signal VOUT. When Q3 is at a high level, the transistor M is turned on, and VOUT is at a low level; when Q3 is at a low level, the transistor M is turned off, and VOUT is at a high level.

[0075] The truth table of the above - mentioned logical operation and the output signal VOUT is as follows:

[0076]

[0077] Since Q2 is the comparison result of the south pole and Q1 is the comparison result of the north pole, for the functional diagram, please refer to Figure 6 .

[0078] When the external magnetic field B is greater than the south - pole magnetic - field threshold BOP, that is, B > Bop, the output signal VOUT is at a low level; when the external magnetic field gradually decreases from Bop to the range where Brp < B < BOP, VOUT still remains at a low level until the magnetic - field direction of B is reversed and greater than the north - pole magnetic - field threshold Brp, then the level of VOUT flips to a high level. Similarly, when the magnetic - field B is directed northward and less than the north - pole magnetic - field threshold Brp, VOUT is at a high level and remains so until the magnetic - field B is reversed and greater than the south - pole magnetic - field threshold Bop, then the level of VOUT flips to a low level.

[0079] Please refer to Figure 7 , which is the timing diagram of the switching control signals of each switch in the control - voltage switching unit and the current - switching unit 132, and the timing diagram of each clock signal in an embodiment of the present invention.

[0080] Figure 7 In, a high level of each switching control signal corresponds to the switch being turned on, and a low level corresponds to the switch being turned off. Specifically, the switches S3a and S4a switch the switch state with a period T1, and other switches switch the switch state with a period T2, where T1 = 2T2.

[0081] Next, the circuit states corresponding to each period are specifically described.

[0082] Please refer to Figure 8a In cycle 1, switch S3a is turned on, switch S4a is turned off, switches S2a to S2g are turned on, and switches S1a to S1f are turned off. The control voltage terminal A is connected to the signal terminal H4, H2 is grounded, and the signal terminals H4 and H2 serve as control terminals; the signal terminals H1 and H3 serve as output terminals, respectively connected to the positive input terminal and negative input terminal of the first amplifier AP1, and output the sensing signal Vin to the comparison module 120. The threshold control current I1 of the control current providing unit 131 flows to the signal terminal H1. In this cycle, the Hall element generates a Hall voltage -V H ; S3a switch is turned on, the threshold control current I1 generates a threshold voltage 0.5I1R superimposed on the Hall between the output terminals H , where R H is the equivalent resistance of the Hall device, then the input signal Vin of the first amplifier AP1 is -V H +0.5I1R H ; Switch S2g is turned on, and capacitor C0 stores the mixed signal V of the amplified Hall voltage signal and the threshold voltage during cycle 1 C1 ,V C1 =A1*(-V H +0.5I1R H ).

[0083] Please refer to Figure 8b In cycle 2, switch S3a is turned on, switch S4a is turned off, switches S1a to S1f are turned on, switches S2a to S2g are turned off, and the voltage V A Applied to H1 and H3 of the Hall device, H1 and H3 are control terminals, H2 and H4 are output terminals connected to the two input terminals of the first amplifier AP1. The Hall voltage generated by the Hall element in cycle 2 is V H ; Switches S3a and S1c are turned on, and the threshold control current I1 flows to the signal terminal H3 of the Hall device. The threshold voltage generated in cycle 2 is -0.5I1R H , then the input signal Vin of the first amplifier AP1 is V H -0.5I1R H , the amplified signal is V C2 =A1*(V H -0.5I1R H ); Switch S2g is disconnected, and the comparator COMP starts to compare, and the comparison signal is V C2 -V C1 =A1*(V H -0.5I1R H )-A1*(-V H +0.5I1R H )=A1*(2VH -I1R H ). When V C2 -V C1 = 0, the control signal output by the comparator COMP is reversed, corresponding to the Hall voltage threshold V H1 =0.5I1R H .

[0084] Please refer to Figure 8c In cycle 3, switch S3a is turned off, switch S4a is turned on, switches S2a to S2f are turned on, switches S1a to S1f are turned off, and the voltage V A Applied to H4 and H2 of the Hall element, H4 and H2 serve as control terminals, and H1 and H3 serve as output terminals. In cycle 3, the Hall voltage generated by the Hall device is -VH; S4a switch is turned on, and the threshold control current I1 flows to the H2 terminal of the Hall device, generating a threshold voltage of -0.5I1R H , then the input signal Vin of amplifier 1 is -V H -0.5I1R H ; Switch S2g is turned on, and capacitor C0 stores the mixed signal of the amplified Hall voltage signal and the voltage threshold during cycle 3, V C3 =A1*(-V H -0.5I1R H ).

[0085] Please refer to Figure 8d In cycle 4, switches S1a to S1f are turned on, switches S2a to S2f are turned off, and voltage VA is applied to both ends of H1 and H3 of the Hall device. In cycle 4, the Hall voltage generated by the Hall device is VH; switch S4a is turned on, current I1 flows to the signal end H4 of the Hall device, and the threshold voltage generated is 0.5I1R H , then the input signal of amplifier 1 Vin=V H +0.5I1R H , amplified signal V C4 =A1*(V H +0.5I1R H ); Switch S2g is disconnected, and the comparator COMP starts to compare, and the comparison signal is V C4 -V C3 =A1*(V H +0.5I1R H )-A1*(-V H -0.5I1R H )=A1*(2V H +I1R H ). When V C4 -V C3 = 0, the control signal output by the comparator COMP is reversed, corresponding to the Hall voltage threshold VH2 =-0.5I1R H .

[0086] It can be seen that the two Hall voltage thresholds corresponding to the reversal of the comparator COMP output signal are the south pole threshold voltage Vop = V H1 =0.5I1R H , and the north pole threshold voltage Vrp = V H2 =-0.5I1R H , corresponding to two magnetic field thresholds Bop and Brp in opposite directions respectively.

[0087] The first clock signal CK1 generates a rising edge at the end of cycle 1 (the start of cycle 2) and the end of cycle 3 (the start of cycle 4), so as to output the comparison signal output by the comparison module 120 in each cycle to the logic operation unit.

[0088] After cycle 4 ends, the states of the switch control signals remain unchanged for a period of time. During this period, the second clock signal CK2 generates a rising edge to trigger the latch module 140 to complete the logic operation and output the corresponding signal.

[0089] This single Hall latch sensor periodically switches the control and output terminals of the Hall element and sequentially inputs threshold control currents to each signal terminal. This outputs a comparison signal corresponding to two magnetic field thresholds, one for the south pole and one for the north pole. This enables omnipolar sensing with only one Hall element, reducing the size and power consumption of the Hall latch sensor.

[0090] Furthermore, the Hall element is equivalent to a Wheatstone bridge (see Figure 2b ), the resistance of each bridge arm is R H , the Hall voltage V is generated between the two output terminals due to the magnetic field B H ,

[0091]

[0092] Due to the input of the threshold control current I1, when the differential voltage Vin=0 is input to the input terminal of the first amplifier AP1, Vop=0.5I1R H , Vrp=-0.5I1R H .

[0093] because The corresponding two magnetic field thresholds are as well as

[0094] The current limiting resistor R1 is a block resistor.

[0095]

[0096] Where q is the charge constant, n is the electron concentration, and u n is the electron mobility, w is the width of the resistor, L is the length of the resistor, and d is the thickness of the resistor.

[0097] Under constant voltage conditions (i.e. V A Under the condition of constant, the sensitivity of the Hall element can be expressed as:

[0098]

[0099] where u n is the electron mobility of the Hall element. At the same temperature, the electron mobility of the Hall element is the same as the mobility of the current limiting resistor R1. v is the charge movement speed, W' is the width of the Hall element 110, and L' is the length of the Hall element 110. n Inversely proportional, K H with u n Proportional, R1 and K H Multiplying them together just cancels out u n impact.

[0100] According to the above formula, the flip point magnetic field threshold of the comparator COMP can be obtained: as well as

[0101] It can be seen that the only temperature-related parameter of the flip-point magnetic field B is the resistance of the first resistor R0, and it has nothing to do with the temperature coefficient of the Hall element. Even if the electron mobility of the Hall element changes with temperature, causing the sensitivity of the Hall element to change, the magnitude of the flip-point magnetic field will not change with the sensitivity of the Hall element, thereby improving the detection accuracy of the single Hall latch sensor. In order to minimize the impact of temperature changes on the flip-point magnetic field, the first resistor R0 can be a resistor type with a very small temperature coefficient, such as a low-temperature drift resistor, including: foil resistors, thin film resistors, foil resistors, metal film resistors, and molded resistors. The magnitude of the flip-point magnetic field of the comparator COMP changes less with temperature, and a stable magnetic field flip point can be obtained, thereby improving the stability of the single Hall latch sensor.

[0102] An embodiment of the present invention further provides an electronic device comprising: a single Hall latch sensor as described in any of the above embodiments. Because the control signal output by the single Hall latch sensor of the present invention is highly reliable, has a small footprint, and consumes low power, it can further improve the reliability and integration of the electronic device and reduce power consumption.

[0103] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A single Hall latch sensor, characterized in that: include: A Hall sensor module includes a single Hall element having two pairs of signal terminals, one pair of which serves as two control terminals connected to a control voltage terminal for inputting a control voltage, and the other pair of signal terminals serving as two output terminals for outputting sensing signals related to an external magnetic field. The Hall sensor module is configured to switch the control terminal and the output terminal of the Hall element according to a first cycle and sequentially input a threshold control current to each signal terminal according to a second cycle, so that the Hall sensor module has two magnetic field thresholds. The Hall sensor module includes: a control current providing unit and a current switching unit; the control current providing unit is used to provide a threshold control current; the current switching unit is used to switch the on-off state between the current output end of the control current providing unit and each signal end of the Hall element according to a second period; a comparison module, configured to receive the sensing signal and output a corresponding comparison signal according to the sensing signal, wherein the comparison signal is flipped when the external magnetic field reaches a corresponding magnetic field threshold; A latch module is connected to the output end of the comparison module, and is used to perform logical operations on the comparison signals output by the comparison module and output a control signal. When one of the comparison signals is flipped, the level of the control signal is flipped and the current state is latched until another comparison signal is flipped and the level of the control signal is flipped again.

2. The single Hall latch sensor according to claim 1, characterized in that: The latch module includes a shift register and a logic operation unit connected to the output end of the shift register; the shift register is used to output the two comparison signals output serially by the comparison module in parallel as signals Q1 and Q2; the logic operation unit is used to operate on the signals Q1 and Q2 and output the control signal Q3, wherein the operation logic is: the n+1th control signal 3. The single Hall latch sensor according to claim 2, characterized in that: The shift register includes a first trigger and a second trigger, the input end of the first trigger is connected to the output end of the comparison module, the output end of the first trigger is connected to the input end of the second trigger, and the clock ends of the first trigger and the second trigger are used to connect to a first clock signal.

4. The single Hall latch sensor according to claim 3, characterized in that: The logic operation unit includes a first NOT gate, a second NOT gate, an AND gate, an OR gate, and a third flip-flop. The two output terminals of the shift register are respectively connected to the input terminals of the first NOT gate and the second NOT gate; one input terminal of the AND gate is connected to the output terminal of the first NOT gate, and the output terminal of the AND gate is connected to one input terminal of the OR gate; the other input terminal of the OR gate is connected to the output terminal of the second NOT gate, and the output terminal of the OR gate is connected to the output terminal of the third flip-flop; the output terminal of the third flip-flop is connected to the other input terminal of the AND gate, and the clock terminal of the third flip-flop is used to be connected to a second clock signal; A rising edge of the second clock signal is located between every two rising edges of the first clock signal.

5. The single Hall latch sensor according to claim 1, characterized in that: The first period and the second period are the same.

6. The single Hall latch sensor according to claim 1, characterized in that: The comparison module includes a first amplifier and a comparator connected to the output end of the first amplifier; the two input ends of the first amplifier are respectively connected to the two output ends of the Hall element, and is used to amplify the sensing voltage between the two output ends and output it to the comparator as the differential input signal of the comparator; the comparator outputs a corresponding comparison signal according to the size of the input differential input signal; a capacitor is connected in series between the positive output end of the first amplifier and the negative input end of the comparator, and a switch is connected in series between the negative input end and the output end of the comparator, and the negative input end of the first amplifier is connected to the positive input end of the comparator.

7. The single Hall latch sensor according to claim 1, characterized in that: The Hall sensor module further includes: a control voltage switching unit; the control voltage switching unit is used to switch the control end and the output end of the Hall element according to a first cycle.

8. The single Hall latch sensor according to claim 7, characterized in that: The control current providing unit includes: a clamp amplifier, a positive input terminal of the clamp amplifier is connected to the control voltage terminal, a negative input terminal is connected to the fixed potential terminal, and an output terminal of the clamp amplifier is connected to the negative input terminal of the clamp amplifier.

9. The single Hall latch sensor according to claim 8, characterized in that: A switch element is further connected between the fixed potential end and the current switching unit, and the output end of the clamp amplifier is connected to the control end of the switch element.

10. The single Hall latch sensor according to claim 7, characterized in that: The control current providing unit further includes: a current limiting resistor connected in series between the power supply voltage and the fixed potential terminal, wherein the electron mobility of the current limiting resistor is the same as that of the Hall element at the same temperature.

11. The single Hall latch sensor according to claim 7, characterized in that: The current switching unit includes: a current path connected between the current output end and each signal end of the Hall element, and each circuit path is provided with a switch to control the on-off state of each current path.

12. The single Hall latch sensor according to claim 7, characterized in that: The control voltage switching unit includes four switches, two of which are respectively connected between the control voltage terminal and two adjacent signal terminals of the Hall element; and the other two switches are respectively connected between the other two signal terminals of the Hall element and the ground terminal.

13. An electronic device, characterized in that: include: The single Hall latch sensor according to any one of claims 1 to 12.

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