Method and apparatus for predicting kernel tuning parameters

Abstract

A processing device that improves processing performance is provided that includes a memory configured to store data and a processor in communication with the memory. The processor is configured to receive tuning parameters, each tuning parameter having a value, for executing a portion of a program on an identified hardware device, and convert the values of the tuning parameters to words. The processor is further configured to predict, using one or more machine language learning algorithms, which combination of the words executes the portion of the program on the identified hardware device based on performance efficiency, and convert the predicted combination of the words to corresponding values for executing the portion of the program on the identified hardware device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 16 / 560,954, filed September 4, 2019, entitled “METHOD AND APPARATUS FOR PREDICTING KERNEL TUNING PARAMETERS,” the entire contents of which are hereby incorporated by reference herein. Background Art

[0003] For example, the performance efficiency of a program depends on the speed or amount of time that the program instructions execute on hardware (e.g., an integrated circuit (IC) or chip). The physical characteristics and specifications of the hardware vary between different generations or versions of the hardware. Therefore, the performance efficiency of a program often varies significantly between different generations of hardware devices. Programs often include tuning parameters that are used to change the performance efficiency of the program for different hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A more detailed understanding may be obtained from the following description given by way of example in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of an example device that may implement one or more features of the present disclosure;

[0006] Figure 2 yes Figure 1 a block diagram of the apparatus showing additional details;

[0007] Figure 3 is a block diagram illustrating an exemplary method of predicting program tuning parameters; and

[0008] Figure 4 Shows the implementation Figure 3 An exemplary method of language learning and prediction is shown. DETAILED DESCRIPTION

[0009] Before the program is deployed for execution on the identified hardware device, the program is typically profiled for the identified hardware by executing the program using different combinations of program tuning parameters to produce different performance efficiencies. The program tuning parameters for the identified hardware are selected based on the resulting performance efficiencies.

[0010] The performance efficiency of a program varies based on the values ​​of the tuning parameters in the program. A program typically includes multiple tuning parameters (e.g., 10 parameters), each of which has multiple different selectable values ​​(e.g., 10 values). Although different combinations of these tuning parameter values ​​produce the correct result, the performance efficiency of these results varies.

[0011] Conventional profiling systems determine tuning parameter values for programs (e.g., GPU compute kernels) via search algorithms that traverse the solution space. For example, for matrix multiplication instructions, conventional systems must constantly search through a database of stored tuning parameter values for each combination of matrix sizes to be multiplied.

[0012] These search algorithms are costly and time consuming. For example, these conventional search algorithms often require a large amount of expensive computing resources and a large amount of time to tune a program (e.g., a kernel). Additionally, the tuning only applies to the selected program. Execution of programs that are not selected often results in decreased performance, and users selecting to tune their own kernels will experience long delays. Furthermore, these conventional search algorithms do not provide tuning parameter values that take into account different input sizes for each program and different types of problems that the program is trying to solve.

[0013] The apparatus and methods described herein effectively determine tuning parameter values for programs that will be executed on identified hardware by using a machine learning algorithm to predict tuning parameter values based on input values, without using inefficient search algorithms (e.g., input tensor values, including image sizes, matrix dimensions, number of color channels, number of operations to be performed).

[0014] In contrast to conventional machine learning models that output numerical values based on input numerical values, the machine learning algorithm described herein converts input numerical values into words (i.e., one or more letters of a language) and uses a language model to predict parameters from the input words. The language learning algorithm learns to translate a source language (e.g., input words or sequences of words converted from one or more numerical values) into a target language (e.g., output sequences of words). The output words are then converted back into numerical values to obtain executable tuning parameter values.

[0015] The tuning parameter values are predicted based on tuning parameter values that are sequentially (as opposed to in parallel) input to the program and are encoded as discrete words instead of scalar numbers. Neural machine language translation techniques are then used to translate the discrete words (e.g., techniques that translate sentences from one language to another using a combination of multilayer perceptrons (MLPs) and other ML primitives such as convolutions, activations, batch normalization, dropout, and recurrent neural networks (RNNs)).

[0016] In contrast to conventional language models, the machine learning language algorithms described herein predict tuning parameter values (e.g., combinations of parameter values that are invalid, each thread is allocated a maximum number of registers, and each thread has access to a certain amount of memory) based on predetermined (i.e., determined prior to run time) constraints. The constraints prevent values that cannot exist simultaneously or would produce invalid results from being predicted as tuning parameter values. Thus, the constraints facilitate a more efficient prediction process because the tuning parameter values are predicted from a smaller space (i.e., a smaller number of possible parameter values) and also provide more accurate predictions because the selected tuning parameter values avoid invalid results.

[0017] A processing apparatus to improve processing performance is provided that includes a memory configured to store data and a processor in communication with the memory. The processor is configured to receive tuning parameters, each tuning parameter having a numerical value, for executing a portion of a program on an identified hardware apparatus, and convert the numerical values of the tuning parameters into words. The processor is further configured to predict, using one or more machine language learning algorithms, which combination of words to execute the portion of the program on the identified hardware apparatus based on performance efficiency, and convert the predicted combination of words into corresponding numerical values for executing the portion of the program on the identified hardware apparatus.

[0018] A method to improve processing performance is provided that includes receiving tuning parameters, each tuning parameter having a numerical value, for executing a portion of a program on an identified hardware apparatus, and converting the numerical values of the tuning parameters into words. The method further includes predicting, using one or more machine language learning algorithms, which combination of words to execute the portion of the program on the identified hardware apparatus based on performance efficiency, and converting the predicted combination of words into corresponding numerical values for executing the portion of the program on the identified hardware apparatus.

[0019] A non-transitory computer-readable storage medium is provided that includes instructions for causing a computer to perform a method that includes receiving tuning parameters, each tuning parameter having a numerical value, for executing a portion of a program on an identified hardware apparatus, and converting the numerical values of the tuning parameters into words. The method further includes predicting, using one or more machine language learning algorithms, which combination of words to execute the portion of the program on the identified hardware apparatus based on performance efficiency, and converting the predicted combination of words into corresponding numerical values for executing the portion of the program on the identified hardware apparatus.

[0020] As used herein, programming includes any sequence of instructions executed using one or more processors to perform a process or routine (e.g., operations, calculations, functions, processes, jobs). As used herein, executing programming instructions (e.g., an application program, a driver program, an operating system, or other software) on a processor includes any of a number of stages, such as but not limited to fetching, decoding, scheduling for execution, beginning execution, and executing a particular portion of the programming instructions (e.g., presenting a video on a full screen). Programming instructions include tuning parameters and tuning parameter settings having tunable (i.e., changeable) values for controlling performance efficiency of programs executing on hardware devices.

[0021] Figure 1 is a block diagram of an exemplary device 100 in which one or more features of the present disclosure can be implemented. Device 100 can include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. Device 100 can also optionally include an input driver 112 and an output driver 114. It is understood that device 100 can include Figure 1 additional components not shown in FIG. 1.

[0022] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or a cache.

[0023] Storage 106 includes a fixed or removable storage, such as a hard disk drive, a solid state drive, an optical disk, or a flash drive. Input devices 108 include, without limitation, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, without limitation, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0024] The input driver 112 communicates with the processor 102 and the input device(s) 108 and allows the processor 102 to receive input from the input device(s) 108. The output driver 114 communicates with the processor 102 and the output device(s) 110 and allows the processor 102 to send output to the output device(s) 110. Note that the input driver 112 and the output driver 114 are optional components, and the device 100 will operate in the same manner if the input driver 112 and the output driver 114 are not present. The output driver 116 includes an accelerated processing device (“APD”) 116 coupled to the display device 118. The APD is configured to accept compute commands and graphics rendering commands from the processor 102, process those compute commands and graphics rendering commands, and provide pixel output to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units configured to perform computations according to a single-instruction-multiple-data (“SIMD”) paradigm. Thus, while various functionality is described herein as being performed by or in connection with the APD 116, in various alternatives, functionality described as being performed by the APD 116 is additionally or alternatively performed by other computing devices having similar functionality that are not driven by a host processor (e.g., the processor 102) and that are not configured to provide graphics output to a display device 118. For example, it is contemplated that any processing system that performs processing tasks according to a SIMD paradigm can be configured to perform the functionality described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to a SIMD paradigm perform the functionality described herein.

[0025] Figure 2is a block diagram of the device 100 showing additional details related to performing processing tasks on the APD 116. The APD 116 includes a plurality of compute units 132, a processing pipeline (e.g., a graphics processing pipeline) 134, and a scheduler 136. The processor 102 maintains one or more control logic modules in the system memory 104 for execution by the processor 102. The control logic modules include an operating system 120, a kernel mode driver 122, and an application 126. These control logic modules control various features of the operation of the processor 102 and the APD 116. For example, the operating system 120 communicates directly with hardware and provides an interface between other software executing on the processor 102 and the hardware. The kernel mode driver 122 controls the operation of the APD 116 by, for example, providing an application programming interface (“API”) to software (e.g., the application 126) executing on the processor 102 to access various functions of the APD 116. The kernel mode driver 122 also includes a just-in-time compiler that compiles programs for execution by processing components of the APD 116, such as the SIMD units 138 discussed in further detail below.

[0026] The APD 116 executes commands and programs related to selected functions, such as graphics operations and non-graphics operations that can be suitable for parallel processing. The APD 116 can be used to perform graphics pipeline operations, such as pixel operations, geometry calculations, and rendering of images to the display device 118, based on commands received from the processor 102. The APD 116 also performs compute processing operations that are not directly related to graphics operations, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks, based on commands received from the processor 102.

[0027] The APD 116 includes compute units 132 that include one or more SIMD units 138 configured to perform operations in a parallel manner upon request by the processor 102 according to a SIMD paradigm. The SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter, and thus execute the same program, but are able to execute the program with different data. In one example, each SIMD unit 138 includes sixteen lanes, where each lane executes the same instruction as the other lanes in the SIMD unit 138 at the same time, but can execute the instruction with different data. If not all lanes need to execute a given instruction, lanes can be turned off with a predicate. Predicates can also be used to execute programs with divergent control flow. More specifically, for programs with conditional branches or other instructions in which the control flow is based on a computation performed by a single lane, the predicate of a lane corresponding to a control flow path that is not currently executed, along with serial execution of different control flow paths, allows for arbitrary control flow.

[0028] The basic unit of computation in the compute units 132 is a work item. Each work item represents a single instance of a program that is to be executed in parallel in a particular wavefront. A work item can be executed simultaneously as a "wavefront" on a single SIMD processing unit 138. One or more wavefronts are included in a "workgroup," which includes a set of work items that are designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. In the alternative, wavefronts are executed sequentially on a single SIMD unit 138, or partially or completely in parallel on different SIMD units 138. A wavefront can be viewed as the largest set of work items that can be executed simultaneously on a single SIMD unit 138. Thus, if a command received from the processor 102 indicates that a particular program is to be parallelized to an extent that the program cannot be executed simultaneously on a single SIMD unit 138, the program is broken up into wavefronts that are parallelized on two or more SIMD units 138 or serialized on the same SIMD unit 138 (or parallelized and serialized as needed). The scheduler 136 is configured to perform operations related to scheduling various wavefronts on different compute units 132 and SIMD units 138.

[0029] The parallelism provided by the compute units 132 is suitable for graphics-related operations, such as pixel value computation, vertex transformation, and other graphics operations. Thus, in some instances, the graphics pipeline 134, which accepts graphics processing commands from the processor 102, provides compute tasks to the compute units 132 for parallel execution.

[0030] The compute units 132 are also used to execute compute tasks that are not related to graphics or that are not performed as part of the "normal" operation of the graphics pipeline 134 (e.g., custom operations that are performed to supplement the processing performed for the operation of the graphics pipeline 134). An application 126 or other software executing on the processor 102 transmits programs that define such compute tasks to the APD 116 for execution.

[0031] Figure 3 is a block diagram illustrating an exemplary method 300 of predicting tuning parameters for programs executed on identified hardware devices. Each portion of the method 300, such as encoding, conversion, language learning, comparison, and prediction, is performed, for example, by a processor such as the APD 116.

[0032] Tuning parameters include parameters that are categorical in nature (e.g., parameters representing options provided to a program to alter the program's performance efficiency) and parameters that have numerical values ​​for tuning specific parameters, such as a certain amount of data to be accessed from a memory (e.g., main memory), a number of parallel memory accesses (e.g., reads, writes) to be performed across a link, a number of channels of an input image (e.g., color channels of an image), a number of output channels (e.g., output channels of a hyperspectral image), and pipeline depth (e.g., input depth and output depth). Target values ​​for the tuning parameters are determined based on input parameters such as image height, image width, the total number of input channels, the total number of output channels, and the number of images to be processed at a time. Furthermore, tuning parameters can vary, in part because the parameters are interpreted differently from program to program.

[0033] like Figure 3 As shown at 302 in , method 300 includes receiving numerical values ​​of a plurality of tuning parameters of a program to be executed on an identified hardware device (eg, an identified version of the hardware device). For example, each numerical tuning parameter value is received sequentially (ie, continuously) by APD 116.

[0034] like Figure 3 As shown in 304, method 300 includes encoding the numerical values ​​in the tuning parameter sequence. The encoding is performed by converting the tuning parameter values ​​from numerical values ​​to words in a language. The conversion of the tuning parameter values ​​includes converting a numerical value to a word, converting one or more numerical values ​​to words, and converting a numerical value to multiple words. Examples of encoding include one-hot encoding and a dense vector created based on the one-hot encoding.

[0035] Each converted word is provided to a machine language model 312 and predicted based on constraints 314 as part of a language learning and prediction process 306 that uses a machine language learning and prediction algorithm to predict which words to use to execute a program on the identified hardware device based on performance efficiency. That is, the machine language learning algorithm predicts which combination of words (corresponding to digital tuning parameter values) will result in efficient execution of a portion of the program on the identified hardware device (e.g., which combination of words will result in execution of the portion of the program faster than other combinations of words or in a shorter time than other combinations of words).

[0036] The machine language model 312 processes the converted word values ​​of the tuning parameters according to one or more machine learning primitives. Examples of machine learning primitives include: convolutional neural networks (CNNs); convolution and pooling layers; recurrent neural networks (RNNs) including unidirectional and bidirectional long short-term memory (LSTM) units or gated recurrent units (GRUs); and densely connected deep neural networks with dropout and different activation functions.

[0037] The word is predicted based on constraints 314, including, for example, that the combination of parameter values is invalid, that each thread is allocated a maximum number of registers, and that each thread has access to a certain amount of memory. The constraints 314 prevent the prediction of tuning parameter values that cannot exist simultaneously with one or more other tuning parameter values or that would produce an invalid result. Because the prediction is performed in a smaller space, the constraints facilitate improved efficiency. Moreover, the constraints improve the accuracy of the prediction because the predicted tuning parameter values do not produce invalid results.

[0038] As shown at 308 in Figure 3 The method 300 includes decoding the predicted tuning parameter values. The decoding is performed by converting the predicted tuning parameter word values back to numerical values. As shown at 310 in Figure 3 The predicted tuning parameter numerical values are then provided as predicted executable tuning parameter values. The predicted executable tuning parameter values are used to execute the portion of the program on the identified hardware device.

[0039] Reference is now made to Figure 4 An example of the language learning and prediction process 306 is described in more detail. As described above, in contrast to conventional systems for determining tuning parameters that receive multiple tuning parameter values in parallel, according to features of the present disclosure, the tuning parameter values are predicted based on tuning parameter values that are sequentially input to the program. That is, each input tuning parameter value is received sequentially (i.e., consecutively) and the tuning parameter values are predicted as a sequence.

[0040] Figure 4 An example method 400 of implementing the language learning and prediction shown at 306 in Figure 3 As described in more detail below, Figure 4 Stages of predicting the sequence are shown, including filtering intermediate tuning parameter value candidates using constraints 314 and predicting a next tuning parameter value candidate in the sequence using the predicted tuning parameter value candidate (e.g., a candidate determined to be more likely to execute the portion of the program with better performance efficiency than other tuning parameter value candidates). Each portion of the method 400, such as encoding, converting, language learning, comparing, filtering, determining, and predicting, is performed, for example, by a processor such as the APD 116.

[0041] As shown at 308 in Figure 4As shown, each word 402(1) to 402(n) of an input word sequence 402 is received. A representation learning process 404 is performed on each word 402(1) to 402(n) according to one or more machine learning primitives (e.g., one or more of the machine learning primitives described above) to determine an internal representation 406 (e.g., a compressed representation of the word 402(1) to 402(n) within the machine language model 312). Each block of the representation learning 404 represents, for example, a memory cell used to determine the internal representation of a corresponding word of the input word sequence 402.

[0042] For example, during representation learning 404, the internal representation of first word 402(1) is output (e.g., temporarily stored) as internal representation 406 of first word 402(1). The internal representation of first word 402(1) is also provided upstream of the memory cells for second word 402(2) (indicated by the left-to-right arrows between the memory cells for first word 402(1)) and used to determine the internal representation of second word 402(2).

[0043] An intermediate internal representation of the second word 402(2) is determined based on the first word 402(1) and the internal representation of the second word 402(2). The intermediate internal representation of the second word 402(2) is then output (e.g., temporarily stored) as an internal representation 406 of the second word 402(2). The internal representation of the second word 402(2) is also provided upstream of the memory cell of the third word 402(3) (indicated by the left-to-right arrow between the memory cells of the second word 402(2) and the third word 402(3)) and is used to determine the internal representation of the third word 402(3). The process continues upstream (i.e., in the direction of the left-to-right arrow of representation learning 404) for each remaining word in the input word sequence 402.

[0044] exist Figure 4 In the example shown, representation learning 404 includes bidirectional learning. That is, the internal representation of each word 402(1) to 402(n) is also provided downstream (i.e., in the direction of the right-to-left arrow of representation learning 404). Thus, the internal representation of each word 402(1) to 402(n-1) is determined based on the upstream words of the input word sequence 402 (i.e., directly based on the next upstream word in the sequence and indirectly based on other upstream words of the input word sequence 402). For example, features of the present disclosure are also implemented via unidirectional (i.e., in the direction of the left-to-right arrow) learning.

[0045] Using the internal representation 406 of the word, a sequence of words is predicted to execute a portion of the program on the identified hardware device. The prediction process includes generating an intermediate word sequence 408 and an output word sequence 410. As described below, a plurality of tuning parameter candidates, including candidates determined to be more likely to result in better performance efficiency than other candidates, are used to predict the sequence of words for execution. For example, if a first candidate does not satisfy one or more constraints 314, the next possible candidate is used to predict the words in the sequence.

[0046] In one example, the number of tuning parameter candidates used in the prediction process is predetermined (i.e., determined prior to run time). For example, a predetermined number of k predictions are propagated, resulting in k predictions.

[0047] The internal representation of the words 402(1) through 402(n) in the word sequence 402 is then provided to a similar machine learning structure to generate the intermediate word sequence 408. Figure 4 Each block of the intermediate word sequence 408 in represents, for example, a memory unit used to intermediate predict the corresponding word 408(1) through 408(n) of the intermediate word sequence 408.

[0048] Based on the one or more machine learning primitives described above, a first word 408(1) of the intermediate word sequence 408 (i.e., a first candidate) is intermediate predicted for executing a portion of the program on the identified hardware device. The internal representation of the first word 408(1) is analyzed based on the one or more constraints 314 of the portion of the program (e.g., the portion of the kernel). That is, when the first word 408(1) satisfies each of the one or more constraints 314, the first word 408(1) is intermediate predicted as a parameter value candidate of the output word sequence 410. When the first word 408(1) does not satisfy each of the one or more constraints 314, the first word 408(1) is not selected as a parameter value candidate of the output word sequence 410.

[0049] The internal representation of the first word 408(1) is also provided to a next memory unit (i.e., a next upstream memory unit) for determining a second word 408(2) of the intermediate word sequence 408. When the second word 408(2) satisfies each of the one or more constraints 314 in place of the first word 408(1), the second word 408(2) is intermediate predicted as a parameter value candidate of the output word sequence 410. When the second word 408(2) does not satisfy each of the one or more constraints 314, the second word 408(2) is not selected as a parameter value candidate of the output word sequence 410. The process continues for each remaining word in the intermediate word sequence 408.

[0050] The prediction process also includes an attention mechanism that compares the tuning parameter values to other tuning parameter values to predict which combination of tuning parameter values will result in a higher performance efficiency of the portion of the program executing on the identified hardware device than other combinations of tuning parameter value candidates.

[0051] For example, the tuning parameter value candidates 410(1) through 410(n) in the output word sequence 410 are compared and ordered according to their likelihood of performing the portion of the program with better performance efficiency than other tuning parameter value candidates. One or more of the tuning parameter value candidates of the output word sequence 410 (e.g., the tuning parameter value candidates determined to be more likely to result in better performance efficiency than other candidates) are provided back to the memory cells of the intermediate word sequence 408 to predict one or more words 408(1) through 408(n) of the intermediate word sequence 408. Thus, the machine learning algorithm learns to predict tuning parameter values based on input tuning parameter values (e.g., the values of the input word sequence 402) and the predicted tuning parameter value candidates fed back to the machine learning algorithm.

[0052] The predicted tuning parameter value candidates 410(1) through 410(n) in the output word sequence 410 are then converted back to numerical values, as shown in block 308, and provided as predicted executable tuning parameter values 310, as shown in block 312, for use in executing the portion of the program on the identified hardware device. Figure 3 Figure 3

[0053] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. It will be appreciated that some embodiments can comprise only some of the features and elements, not all of the rest of the features and elements are required, individual elements can be present in various embodiments, and embodiments of this application can be directed to less than all of the features and elements present in one or more embodiments.

[0054] The methods provided can include implementation in hardware, software, and / or firmware. For example, certain processes can be implemented in, for example, one or more computer programs executing on one or more computers or processors, which can be provided by or on behalf of the disclosed methods. Embodiments of the methods can be implemented in software, firmware, hardware, or any combination thereof. Embodiments of the methods can also be implemented by a processor executing instructions stored in a memory. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGAs) circuits, any other type of integrated circuit (IC), and / or a state machine. A processor in association with software can be used to implement the methods described herein. The software programmed can be transitory or non-transitory. The software can include, but is not limited to, firm-ware, one or more applications, program code, and / or data. The one or more applications can form a primary executable work product independent of the other features and elements of one or more embodiments. The one or more applications can include associated documentation (e.g., APIs, guidebooks, instruction manuals, etc.). The one or more applications and associated documentation can be distributed as an electronic submission via, for example, the Internet. The one or more applications and associated documentation can be stored on a non-transitory computer readable medium or media at the time of authorization and / or distribution. Examples of non-transitory computer readable media include a hard disk, a CD-ROM, a DVD, a Blu-ray Disc, a flash drive, and / or a solid state drive. The one or more applications and associated documentation can be stored on a transitory computer readable medium or media at the time of authorization and / or distribution. Examples of transitory computer readable media include a wire or cable, a computer network, or a wireless signal.

[0055] ​​The various functional units shown in the figures and / or described herein (including, but not limited to, the processor 102, input driver 112, input device 108, output driver 114, output device 110, acceleration processing device 116, scheduler 136, graphics processing pipeline 134, compute unit 132, SIMD unit 138) can be implemented as a general purpose computer, processor, or processor core, or as a program, software, or firmware, stored in a non-transitory computer readable medium or another medium, executable by a general purpose computer, processor, or processor core.

[0056] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer readable storage medium or another medium for execution by a general purpose computer or processor. Examples of non-transitory computer readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. A processing device comprising: a memory configured to store data; a processor in communication with the memory configured to: receive tuning parameters, each tuning parameter having a numerical value, for configuring a program to execute on an identified hardware device; convert the numerical values of the tuning parameters to one or more words; predict a particular combination of the words using one or more machine language learning algorithms, the prediction based on performance efficiency of the program when the program is executed on the identified hardware device; convert the particular predicted combination of the words to a corresponding numerical value to form a predicted tuning parameter; and execute the program on the identified hardware device using the predicted tuning parameter.

2. The processing device of claim 1, wherein the processor is further configured to sequentially determine a machine language learning representation of each of the words inputted in a sequence of words.

3. The processing device of claim 2, wherein the processor is further configured to determine the machine language learning representation of a word in the sequence of words based on the determined machine language learning representation of another word in the sequence of words.

4. The processing device of claim 2, wherein the processor is configured to: predict an intermediate sequence of words based on the machine language learning representation of each of the words; determine a word in the intermediate sequence of words as a candidate word for the particular combination of the words when the word satisfies each of one or more predetermined constraints; and determine that the word in the intermediate sequence of words is not a candidate word for the particular combination of the words when the word does not satisfy each of the one or more predetermined constraints.

5. The processing device of claim 4, wherein each of the one or more predetermined constraints indicates whether a combination of the words results in an invalid result due to execution of the program.

6. The processing device of claim 4, wherein the processor is configured to: determine a plurality of the words in the intermediate sequence of words as candidate words for the particular combination of the words; and predict a next word in the intermediate sequence of words based on one of the candidate words determined to be more likely than other ones of the candidate words to execute the program with better performance efficiency.

7. The processing device of claim 1, wherein the performance efficiency is a measure of speed or amount of time to execute the program, and the processor is configured to determine that the particular combination of the words executes the program on the identified hardware device based on the performance efficiency by predicting that the particular combination of the words results in the program being executed faster or in a shorter amount of time than other combinations of the words.

8. The processing device of claim 1, wherein the received numerical values of the plurality of tuning parameters are tensor input values. ​ 9. The processing device of claim 1, wherein the one or more machine language learning algorithms comprise at least one of a convolutional neural network, a recurrent neural network, and a connectionist neural network.

10. A method of improving processing performance, comprising: receiving tuning parameters, each tuning parameter having a value, for configuring a program to execute on an identified hardware device; converting the values of the tuning parameters to one or more words; predicting a particular combination of the words using one or more machine language learning algorithms, the prediction based on performance efficiency of the program when the program is executed on the identified hardware device; converting the particular combination of the words to a corresponding value to form a predicted tuning parameter; and executing the program on the identified hardware device using the predicted tuning parameter.

11. The method of claim 10, further comprising sequentially determining a machine language learning representation of each of the words inputted in a sequence of words.

12. The method of claim 11, further comprising determining the machine language learning representation of a word in the sequence of words based on the determined machine language learning representation of another word in the sequence of words.

13. The method of claim 10, further comprising: predicting an intermediate sequence of words based on the machine language learning representation of each of the words; determining a word in the intermediate sequence of words as a candidate word for the particular combination of the words when the word satisfies each of one or more predetermined constraints; and determining that the word in the intermediate sequence of words is not a candidate word for the particular combination of the words when the word does not satisfy each of the one or more predetermined constraints.

14. The method of claim 13, wherein each of the one or more predetermined constraints indicates whether a combination of the words produces an invalid result due to execution of the program.

15. The method of claim 13, further comprising: determining a plurality of the words in the intermediate sequence of words as candidate words for the particular combination of the words; and predicting a next word in the intermediate sequence of words based on one of the candidate words determined to be more likely than other ones of the candidate words to execute the program with better performance efficiency.

16. The method of claim 15, further comprising ranking each of the plurality of the words in the intermediate sequence of words according to a likelihood of a candidate word to execute the program with better performance efficiency than the other candidate words.

17. The method of claim 11, wherein the performance efficiency is a measure of speed or amount of time to execute the program, and ​ The method further includes determining, based on the performance efficiency, that the particular combination of words causes the program to execute faster or in less time than other combinations of the words, by predicting that the particular combination of words will cause the program to execute faster or in less time than other combinations of the words.

18. The processing method of claim 11, wherein the received values of the plurality of tuning parameters are tensor input values.

19. The processing method of claim 11, wherein the one or more machine language learning algorithms include at least one of a convolutional neural network, a recurrent neural network, and a connectionist neural network.

20. A non-transitory computer-readable storage medium having instructions for causing a computer to perform a method, the method comprising: receiving tuning parameters, each tuning parameter having a value, for configuring a program to execute on an identified hardware device; converting the values of the tuning parameters to one or more words; predicting, using one or more machine language learning algorithms, a particular combination of the words, the prediction based on performance efficiency of the program when executing on the identified hardware device; converting the particular combination of the words to corresponding values to form predicted tuning parameters; and executing the program on the identified hardware device using the predicted tuning parameters.

21. The method of claim 20, wherein the one or more machine language learning algorithms include at least one of a convolutional neural network, a recurrent neural network, and a connectionist neural network.

22. The method of claim 20, wherein the received values of the plurality of tuning parameters are tensor input values.

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