Substrate processing method and substrate processing apparatus

Abstract

The present invention provides a substrate processing apparatus and a substrate processing method capable of appropriately reducing metal contamination on the back surface of a substrate during plasma processing. The substrate processing apparatus includes: a processing container for processing a substrate inside the processing container; a plasma generation space formed inside the processing container; a processing space communicating with the plasma generation space via a partition plate; a mounting table disposed inside the processing space for mounting a substrate on an upper surface of the mounting table; and a lifting mechanism for lifting and lowering the substrate on the mounting table, wherein during plasma processing of the substrate in the processing space, the lifting mechanism is used to lift and lower the substrate to cause a potential change in the substrate during the plasma processing.

Description

Technical Field

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus. Background Art

[0002] Patent Document 1 discloses a substrate processing apparatus having: a high-frequency power supply that supplies high-frequency energy to the inside of a processing container; a gas supply source that introduces gas into the inside of the processing container; a stage for placing a substrate; and a partition plate that divides the inside of the processing container into a plasma generation space and a substrate processing space.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-157778 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] The technology related to the present disclosure appropriately reduces metal contamination on the back surface of a substrate during plasma processing.

[0008] Solutions to the Problems

[0009] One aspect of the present disclosure is a method of processing a substrate using a substrate processing apparatus, the substrate processing apparatus having: a processing container for processing a substrate inside the processing container; a plasma generation space formed inside the processing container; a processing space communicating with the plasma generation space via a partition plate; a stage provided inside the processing space for placing a substrate on an upper surface of the stage; and a lifting mechanism for lifting and lowering the substrate on the stage, wherein during plasma processing of the substrate in the processing space, the lifting mechanism is used to lift and lower the substrate to cause a potential change in the substrate during the plasma processing.

[0010] Effects of the Invention

[0011] According to the present disclosure, metal contamination on the back surface of a substrate during plasma processing can be appropriately reduced. Brief Description of the Drawings

[0012] Figure 1 is a longitudinal sectional view showing an example of the structure of a plasma processing apparatus.

[0013] Figure 2 is a cross-sectional view showing an example of the structure of a plasma processing apparatus.

[0014] Figure 3It is a flowchart showing the main processes of wafer processing according to this embodiment.

[0015] Figure 4 It is a graph showing an example of the change in Vdc of a wafer in plasma processing according to this embodiment.

[0016] Figure 5 It is an explanatory diagram showing a case where a wafer is held by lift pins.

[0017] Figure 6 It is a graph showing an example of the change in Vdc of a wafer in plasma processing according to other embodiments.

[0018] Figure 7 It is an explanatory diagram schematically showing other methods for reducing metal contamination on the back surface of a wafer.

[0019] Figure 8 It is an explanatory diagram schematically showing an example of the formation of a coating film.

[0020] Explanation of reference numerals

[0021] 1: Plasma processing apparatus; 10: Processing chamber; 11: Partition plate; 40: Mounting table; 61: Lift pin; G: Plasma generation space; S: Processing space; W: Wafer. Detailed embodiments

[0022] Silicon-containing films in semiconductor devices are widely used for various purposes. For example, Si-containing films such as silicon germanium (SiGe) films and silicon (Si) films are used for gate electrodes, seed layers, etc. Moreover, conventionally, in the manufacturing process of gate-all-around (GAA) transistors such as nanosheets or nanowires, plasma processing such as etching processing, diffusion processing, or film formation processing is performed on a semiconductor wafer (hereinafter simply referred to as "wafer") which is a substrate formed with such a Si-containing film.

[0023] The technique disclosed in Patent Document 1 described above is a method for etching a wafer formed with a Si-containing film as described above. As also described in Patent Document 1, the etching process is performed on the wafer disposed in the chamber by plasma processing, and in this plasma processing, a processed gas excited by plasma is supplied.

[0024] In addition, in the plasma processing of such wafers, when starting to supply high-frequency (RF: Radio Frequency) power for generating plasma (hereinafter sometimes referred to as "when RF-ON"), there is a concern about metal contamination on the back surface of the wafer to be processed. It is considered that the reason for the metal contamination on the back surface of the wafer is, for example, that fine particles are generated due to the reaction of metals such as the stage for placing the wafer, which are arranged in the chamber, with the plasma, and due to the change in the wafer potential (Vdc) at the time of RF-ON, these fine particles are electrostatically adsorbed on the back surface.

[0025] Therefore, the inventors of the present invention found through in-depth discussion that in the plasma processing of the wafer to be processed, when the lift pins used for transferring the wafer inside the chamber are actuated, the Vdc changes. That is, it was newly discovered that by changing the charging state of the wafer by utilizing the operation of the lift pins, it may be possible to remove the fine particles attached to the back surface. Moreover, this view is not described in Patent Document 1 either.

[0026] The technology related to the present disclosure was completed based on the above view, and appropriately reduces the metal contamination on the back surface of the substrate in plasma processing. Hereinafter, a plasma processing apparatus as a substrate processing apparatus according to the present embodiment and a plasma processing method as a substrate processing method using the plasma processing apparatus will be described with reference to the drawings. In addition, in this specification and the drawings, elements having substantially the same functional structure are denoted by the same reference numerals, and thus redundant description is omitted.

[0027] <Plasma Processing Apparatus>

[0028] Figure 1 is a longitudinal sectional view schematically showing the outline of the structure of the plasma processing apparatus 1. In the plasma processing apparatus 1, arbitrary plasma processing such as etching processing, diffusion processing, or film formation processing is performed on the surface of the wafer W. In addition, in the following description, the surface of the wafer W on which the plasma processing is performed is sometimes referred to as the "surface", and the surface on the opposite side to the surface and held by the stage 40 described later is referred to as the "back surface".

[0029] As Figure 1 shown, the plasma processing apparatus 1 includes a processing container 10 having a closed structure for housing the wafer W. The processing container 10 is made of, for example, aluminum or an aluminum alloy, is open at the upper end, and the upper end of the processing container 10 is closed by a lid 10a serving as the top. A carry-in / carry-out port (not shown) for the wafer W is provided on the side surface of the processing container 10, and the processing container 10 is connected to the outside via the carry-in / carry-out port. The carry-in / carry-out port is configured to be opened and closed freely by a gate valve (not shown).

[0030] The interior of the processing container 10 is divided by a partition plate 11 into an upper plasma generation space G and a lower processing space S. That is, the plasma processing apparatus 1 according to the present embodiment is configured as a remote plasma processing apparatus in which the plasma generation space G and the processing space S are separated.

[0031] The partition plate 11 has at least two plate-like members 12, 13 that are arranged overlappingly from the plasma generation space G toward the processing space S. A spacer 14 for adjusting the interval between the plate-like members 12, 13 is arranged between the plate-like members 12, 13. In addition, the plate-like members 12, 13 each have slits 12a, 13a formed through the overlapping direction. The slits 12a, 13a are arranged so as not to overlap in a plan view. Thus, the partition plate 11 functions as a so-called ion trap. When plasma is generated in the plasma generation space G, the ion trap suppresses ions in the plasma from passing through to the processing space S. More specifically, a slit arrangement structure in which the slit 12a and the slit 13a are arranged so as not to overlap, that is, a labyrinth structure, is used to block the movement of anisotropically moving ions. On the other hand, isotropically moving radicals are allowed to pass through.

[0032] In addition, in other words, the plasma generation space G and the processing space S are connected via the partition plate 11 configured as described above in a manner that communicates via the slits 12a, 13a. Thus, when plasma processing of the wafer W is performed in the processing space S as described later, the potential of the wafer W is changed (Vdc change) by the operation of a lift pin 61 described later.

[0033] Furthermore, the structure of the partition plate 11 is not limited to the illustrated example, and any structure can be adopted as long as the Vdc change of the wafer W can be caused by the operation of the lift pin 61 described later.

[0034] The plasma generation space G has: a gas supply unit 20 that supplies a processing gas into the processing container 10; and a plasma generation unit 30 that plasmatizes the processing gas supplied into the processing container 10.

[0035] The gas supply unit 20 is connected to a plurality of gas supply sources (not shown), and these gas supply sources supply a processing gas including a fluorine-containing gas (e.g., NF3 gas), an oxygen-containing gas (e.g., O2 gas), and a dilution gas (e.g., Ar gas) into the interior of the processing container 10. In addition, the types of the fluorine-containing gas, the oxygen-containing gas, and the dilution gas are not limited thereto, and can be arbitrarily selected.

[0036] In addition, a flow regulator (not shown) for adjusting the supply amount of the processing gas supplied to the plasma generation space G is provided in the gas supply unit 20. The flow regulator has, for example, an on-off valve and a mass flow controller.

[0037] The plasma generation unit 30 is configured as an inductively coupled type device using an RF antenna. The lid 10a of the processing chamber 10 is formed of, for example, a quartz plate and configured as a dielectric window. An RF antenna 31 for generating inductively coupled plasma in the plasma generation space G of the processing chamber 10 is formed above the lid 10a, and the RF antenna 31 is connected to a high-frequency power supply 33 via a matcher 32.

[0038] The matcher 32 has a matching circuit (not shown) with variable reactance, which is used to match the impedance on the high-frequency power supply 33 side with the impedance on the load (RF antenna 31, plasma) side.

[0039] The high-frequency power supply 33 outputs high-frequency power at a fixed frequency (usually 13.56 MHz or higher) suitable for generating plasma by inductively coupled high-frequency discharge with an arbitrary output value.

[0040] The processing space S has: a stage 40 for placing a wafer W in the processing chamber 10; and an exhaust unit 50 for exhausting the processing gas in the processing chamber 10.

[0041] The stage 40 has: an upper stage 40a having a placement surface (hereinafter referred to as "wafer placement surface") for placing the wafer W on its upper surface; and a lower stage 40b fixed to the bottom surface of the processing chamber 10 and supporting the upper stage 40a from below. The stage 40 is made of, for example, a metal such as aluminum or an aluminum alloy.

[0042] A plurality of proximity pins (Japanese: プロキシピン) 41 for holding the wafer W are provided on the wafer placement surface of the upper stage 40a, and in this embodiment, there are, for example, three of them. The wafer W placed on the stage 40 is held on the wafer placement surface in a state of being slightly lifted from the wafer placement surface by the proximity pins 41. As Figure 2 shown, the proximity pins 41 are provided at equal intervals along the circumference of the stage 40 (wafer placement surface).

[0043] In addition, a temperature adjustment mechanism 42 and a lifter 60 are provided inside the stage 40.

[0044] The temperature adjustment mechanism 42 is provided inside the upper stage 40a and adjusts the wafer W during plasma processing to a desired temperature. As the temperature adjustment mechanism 42, it may include a heater, a flow path, or a combination thereof. A temperature control fluid such as a refrigerant or a heat transfer gas flows through the flow path.

[0045] The lifter 60 as a lifting mechanism raises and lowers the wafer W on the stage 40. The lifter 60 has a lift pin 61, a support member 62, and a drive unit 63.

[0046] The lifting pin 61 is a columnar member that moves up and down in such a way that its upper end projects or retracts relative to the wafer placement surface, and is arranged so as to penetrate the upper stage 40a in the thickness direction thereof. As Figure 2 shown, three or more lifting pins 61 are arranged at intervals in the circumferential direction of the placement stage 40 (wafer placement surface). The lifting pins 61 are arranged at equal intervals in the circumferential direction, for example.

[0047] The support member 62 is arranged inside the lower stage 40b and supports a plurality of lifting pins 61. The drive unit 63 generates a driving force for moving the support member 62 up and down, causing the plurality of lifting pins 61 to move up and down. The drive unit 63 has a motor (not shown) for generating the above driving force.

[0048] The elevator 60 is configured such that, by the operation of the drive unit 63, the lifting pins 61 are moved up and down via the support member 62, enabling the lifting pins 61 to move freely between the wafer W transfer position (the position where the upper end projects from the wafer placement surface) and the standby position (the position where the upper end does not project from the wafer placement surface). In other words, it is configured such that, by the operation of the drive unit 63, the wafer W held by the lifting pins 61 can move freely between the transfer position (the position where transfer is performed with the wafer transfer mechanism) and the processing position (the position where it is placed on the wafer placement surface).

[0049] In addition, the configuration and structure of the elevator 60 are not limited to the illustrated example and can be arbitrarily configured.

[0050] The exhaust unit 50 is connected to an exhaust mechanism (not shown), such as a vacuum pump, via an exhaust pipe provided at the bottom of the processing container 10 on the outer side of the placement stage 40. An automatic pressure control valve (APC) is provided on the exhaust pipe. The pressure inside the processing container 10 is controlled using these exhaust mechanism and the automatic pressure control valve.

[0051] A control device 70 as a control unit is provided for the above-described plasma processing apparatus 1. The control device 70 is a computer having, for example, a CPU, a memory, etc., and has a program storage unit (not shown). Programs for controlling the processing of the wafer W in the plasma processing apparatus 1 are stored in the program storage unit. In addition, programs for controlling the operations of the above-described various components to achieve the wafer processing described later in the plasma processing apparatus 1 are also stored in the program storage unit. Further, the above programs may also be programs recorded on a computer-readable storage medium H and installed from the storage medium H into the control device 70.

[0052] <Plasma Processing>

[0053] The plasma processing apparatus 1 according to the present embodiment is configured as described above. Next, the plasma processing performed using the plasma processing apparatus 1 will be described.Figure 3 is a flowchart showing the main processes of the plasma processing according to the present embodiment. In addition, Figure 4 is a graph showing an example of the potential change (Vdc change) that occurs in the wafer W during the plasma processing. In the following description, the case of etching the Si film formed on the surface of the wafer W is described as an example, but the type of Si-containing film formed on the surface of the wafer W (for example, SiN film, SiO2 film, etc.) can be arbitrarily determined. In addition, the plasma processing performed on the wafer W is not limited to the etching process.

[0054] First, using a wafer transfer mechanism (not shown) provided outside the plasma processing apparatus 1, the wafer W to be processed is transferred into the processing space S inside the processing container 10 ( Figure 3 step S1). After the wafer W is transferred into the inside of the processing space S, the lift pins 61 are raised from the standby position to the handover position by the operation of the drive unit 63 ( Figure 3 step S2), and the wafer W is handed over from the wafer transfer mechanism (not shown) to the lift pins 61 ( Figure 3 step S3). In addition, as Figure 5 shown, at the handover position, the back side of the wafer W is held at the upper end of the lift pins 61 in a state where the wafer W does not contact the wafer mounting surface (approach pins 41) of the mounting table 40 and is away from the wafer mounting surface (approach pins 41) of the mounting table 40.

[0055] After the wafer W is handed over to the lift pins 61, plasma processing of the wafer W is started ( Figure 3 step S4). Specifically, a processing gas (NF3 gas, O2 gas, and Ar gas in the present embodiment) is supplied from the gas supply unit 20 to the plasma generation space G, and high-frequency power (RF-ON) is supplied to the RF antenna 31 to generate inductively coupled plasma, that is, plasma containing oxygen and fluorine. In other words, the generated plasma contains fluorine radicals (F*) and oxygen radicals (O*).

[0056] In addition, when the plasma processing performed in the plasma processing apparatus 1 is, for example, an etching process for the Si film formed on the wafer W as described above, the pressure (vacuum degree) in the plasma generation space G is preferably 10 mTorr to 5 Torr, more preferably 25 mT to 800 mT. In addition, the temperature in the plasma generation space G is preferably 60°C to 120°C, more preferably 100°C. In addition, the flow rate ratio [sccm] of the processing gas is preferably NF3:O2:Ar = 3 to 100:0 to 1000:50 to 300.

[0057] Here, when the wafer W is disposed at the processing position at the start of the above-described plasma processing, since the back surface of the wafer W is disposed in close proximity to the mounting table 40 (wafer mounting surface), metal contamination may occur on the back surface of the wafer W. More specifically, due to the influence of the change in the magnetic field (electric field) in the plasma generation space G at the start of the supply of high-frequency power (RF-ON), a Vdc change occurs in the wafer W, and thus metal particles P on the wafer mounting surface (mainly Cr when the mounting table 40 is made of aluminum, for example) are electrostatically adsorbed to the back surface of the wafer W.

[0058] Regarding this point, in the present embodiment, at the start of the supply of high-frequency power (RF-ON), the wafer W is disposed at the transfer position after being raised by the lift pins 61, as Figure 5 shown, and the wafer W is physically separated from the wafer mounting surface (proximity pins 41) of the mounting table 40. Thereby, compared with the case where the supply of high-frequency power is started in a state where the wafer W is disposed at the processing position, the electrostatic attachment of particles to the back surface of the wafer W can be appropriately reduced. In other words, by suppressing the influence of the Vdc change of the wafer W from reaching the particles on the wafer mounting surface, the attachment of particles to the back surface is reduced.

[0059] The plasma generated in the plasma generation space G is supplied to the processing space S via the partition plate 11. Here, since the maze structure is formed in the partition plate 11 as described above, only the radicals generated in the plasma generation space G penetrate into the processing space S. Then, by allowing the radicals supplied to the processing space S to act on the wafer W, the wafer W is subjected to plasma processing. Further, as described above, since the plasma processing is started in a state where the wafer W is separated from the wafer mounting surface, as Figure 4 shown in the "Pin-Up" region, at the initial stage of this plasma processing, the Vdc value of the wafer W negatively shifts on the negative side.

[0060] After the plasma processing of the wafer W is started, then, the lift pins 61 are lowered by the operation of the drive unit 63, whereby the wafer W is lowered from the transfer position to the processing position ( Figure 3 step S5). When the wafer W is mounted on the wafer mounting surface (proximity pins 41) by moving the wafer W to the processing position, the Vdc value of the wafer W changes accordingly. Specifically, as Figure 4 shown in the "Pin-Down" region, by electrically connecting the wafer W to the mounting table 40, the Vdc value that has been shifting on the negative side during "pin-up" changes to a positive value and then stably shifts near zero. In other words, due to the lowering operation of the wafer W by the lift pins 61, the charging state of the wafer W before and after the lowering changes.

[0061] In this embodiment, by lowering the wafer W using the lift pins 61 during plasma processing to change the Vdc value, the charged state of the wafer W is changed. Thereby, for example, even when fine particles are attached to the back surface of the wafer W at the start of high-frequency power supply, the attached fine particles can be detached from the back surface using the change in the charged state.

[0062] In addition, the timing for lowering the lift pins 61 only needs to be within the period from the start of plasma processing (RF-ON) of the wafer W to the end of the plasma processing (RF-OFF), and can be arbitrarily determined. However, when the wafer W is raised using the lift pins 61, it may not be possible to appropriately adjust the temperature of the wafer W using the temperature adjustment mechanism 42. In view of the above, it is preferable to shorten the rising time for raising the wafer W using the lift pins 61. That is, it is preferable to move the wafer W to the processing position immediately after the start of plasma processing of the wafer W (after the start of high-frequency power supply).

[0063] After moving the wafer W to the processing position by lowering the lift pins 61, plasma processing of the wafer W is continued. At this time, as shown in the "pin lowering" region of Figure 4 , the Vdc value of the wafer W fluctuates around zero. After that, when the desired plasma processing result is obtained for the wafer W, the supply of the processing gas to the plasma generation space G is stopped, and the supply of high-frequency power from the RF antenna 31 is stopped (RF-OFF), and the plasma processing in the plasma processing apparatus 1 is completed ( Figure 3 step S6).

[0064] When the plasma processing of the wafer W is completed, the lift pins 61 are raised by the operation of the drive unit 63, and the wafer W is moved from the processing position to the transfer position ( Figure 3 step S7). Then, after the wafer W is transferred from the lift pins 61 to a wafer transfer mechanism (not shown) provided outside the plasma processing apparatus 1 ( Figure 3 step S8), the wafer W is carried out to the outside of the processing container 10 ( Figure 3 step S9). In addition, when the wafer W is carried out from the processing container 10, the lift pins 61 are moved from the transfer position to the standby position by the operation of the drive unit 53. By doing so, a series of plasma processing in the plasma processing apparatus 1 is completed.

[0065] <Effects of the wafer processing according to this embodiment>

[0066] According to the above-described embodiment of the present invention, a processing space S for plasma processing of a wafer W is provided to communicate with a plasma generation space G via a partition plate 11 formed with a slit. Therefore, when plasma processing is performed in the processing space S, the wafer W is lifted and lowered by the lift pins 61, whereby the Vdc value of the wafer W can be changed. Moreover, since the charged state of the wafer W can be changed (inverted) as the Vdc of the wafer W changes, fine particles electrostatically adsorbed to the back surface of the wafer W can be appropriately detached. That is, metal contamination on the back surface of the wafer W can be reduced.

[0067] In addition, in a state where the lift pins 61 are raised to electrically disconnect the wafer W from the wafer mounting surface, plasma processing is started, and more specifically, high-frequency power supply (RF-ON) is started, whereby attachment of fine particles on the wafer mounting surface to the back surface can be suppressed, and metal contamination on the back surface can be further appropriately reduced.

[0068] Furthermore, in the above-described embodiment, plasma processing is started in a state where the wafer W is disposed at the transfer position, and then the wafer W is moved (lowered) to the processing position during the plasma processing. However, the pin operation during the plasma processing is not limited to this. For example, plasma processing may be started in a state where the wafer W is disposed at the processing position, and then the wafer W may be moved (raised) to the transfer position during the plasma processing. Figure 6 It is a graph showing an example of the Vdc change during the plasma processing in the above case.

[0069] As Figure 6 shown, when the wafer W is moved (raised) from the processing position to the transfer position during the plasma processing, the Vdc value that steadily changes near zero when the pins are lowered changes to a positive value and then steadily changes on the negative side by moving the wafer W and the mounting table 40 away from each other (electrically disconnecting). In other words, due to the raising operation of the wafer W by the lift pins 61, the charged state of the wafer W before and after the raising changes.

[0070] As described above, when plasma processing is started in a state where the wafer W is disposed at the processing position, fine particles may be electrostatically adsorbed to the back surface of the wafer W. However, by changing the Vdc by moving the wafer W from the processing position (raising) to the transfer position during the plasma processing, the charged state of the wafer W can be changed, whereby the fine particles attached to the back surface can be detached to appropriately reduce metal contamination on the back surface of the wafer W. In addition, since the back surface of the wafer W at the transfer position is physically away from the wafer mounting surface of the mounting table 40, attachment of fine particles to the back surface of the wafer W after being disposed at the transfer position can be appropriately suppressed.

[0071] In addition, as described above, it is considered that the cause of metal contamination on the back surface of the wafer W is that fine particles are generated due to the reaction of free radicals supplied to the processing space S with metals such as aluminum constituting the stage 40, and these fine particles adhere to the back surface of the wafer W. Therefore, as Figure 7 shown, a coating film C can also be formed on the surface of metals such as aluminum, which are the sources of the above-mentioned fine particles, using a material that is at least more resistant to free radicals than the metal, so as to suppress the generation of fine particles during plasma processing and reduce the metal contamination on the back surface of the wafer W. For example, when the metal is aluminum, yttrium fluoride (YF3), yttrium oxyfluoride (YOF), or Teflon (registered trademark), etc. can be selected as the coating material.

[0072] In addition, the thickness of the coating film C formed on the metal surface can be arbitrarily determined. However, from the viewpoints of stably forming the coating film C on the metal surface and also suppressing the peeling of the formed coating film C due to its own weight or the like, the thickness of the coating film C is preferably about 100 μm to 170 μm. In addition, when the coating film C is formed on the wafer mounting surface of the stage 40, the thickness of the coating film C formed on the wafer mounting surface is preferably at least less than the height of the proximity pin 41.

[0073] In addition, for example, when the coating film C is formed on the surface of the stage 40, the coating film can be formed on the entire surface (upper surface and side surface) of the stage 40 as Figure 7 shown, or the coating film C can be formed at least only on the wafer mounting surface of the upper stage 40a as Figure 8 shown. As long as it is possible to at least suppress the generation of fine particles from the wafer mounting surface that faces directly the back surface when the wafer W is mounted, the metal contamination on the back surface of the wafer W during plasma processing can be reduced.

[0074] In addition, as Figure 8 shown, when the coating film C is formed only on the wafer mounting surface of the stage 40, in addition to reducing the metal contamination on the back surface of the wafer W, the in-plane uniformity of the plasma processing performed on the wafer W can also be improved.

[0075] Specifically, when a coating film C is formed on the surface of the stage 40 exposed to the plasma environment in the processing space S, O* supplied to the processing space S becomes less likely to be deactivated compared to the case where the surface is made of aluminum. Generally, the plasma processing of the central portion of the wafer W progresses earlier than that of the peripheral portion. However, by forming the coating film C on the wafer mounting surface of the stage 40, the deactivation rate of O* in the central portion of the wafer W becomes smaller than that of O* in the peripheral portion. Since O* generally acts to hinder plasma processing, by reducing the deactivation rate of O* in the central portion of the wafer W in this way, the plasma processing speed can be suppressed and balanced with the plasma processing speed of the peripheral portion of the wafer W. That is, the deviation in the plasma processing speed between the central portion and the peripheral portion of the wafer W can be suppressed, and as a result, the in-plane uniformity of the plasma processing can be improved.

[0076] In addition, when the lift pins 61 are made of a metal such as aluminum, for example, radicals act on the lift pins 61, and as a result, particles may be generated and metal contamination may occur on the back surface of the wafer W. Therefore, when the lift pins 61 are made of a metal, in addition to forming the aforementioned coating film, the lift pins 61 may be made of a member having radical-resistant properties, or instead of forming the aforementioned coating film, the lift pins 61 may be made of a member having radical-resistant properties. As a member constituting the lift pins 61, for example, nickel (Ni), ceramics, or Teflon (registered trademark) can be selected.

[0077] In addition, in the above-described embodiment, the case where the Vdc value of the wafer W is changed by the operation of the elevator 60 as a lifting mechanism, more specifically, by the operation of the lift pins 61, has been described. However, as described above, the structure of the elevator 60 is not limited to this. That is, any structure can be adopted as long as the wafer W and the stage 40 can be electrically disconnected during plasma processing to remove the particles attached to the back surface of the wafer W.

[0078] In addition, in the plasma processing in the above-described embodiment, NF3, O2, and Ar are supplied as processing gases, but Ar gas can also be additionally supplied as an Add gas.

[0079] In addition, according to the above-described embodiment, NF3 is selected as the fluorine-containing gas including the processing gas. However, the type of the fluorine-containing gas is not limited to this. For example, SF6 gas or F2 gas can also be selected. In addition, the type of the dilution gas is not limited to Ar gas, and any gas including at least one of H2 gas and noble gases can be selected.

[0080] In addition, the plasma source in the plasma generation space G is not limited to the inductively coupled plasma as in this embodiment, and any structure such as microwave plasma can be adopted. However, since the Vdc value of the wafer W is changed by the operation of the lift pin 61 as described above, and further the charged state of the wafer W is changed, in any case of adopting a plasma source, it is desirable that the plasma processing apparatus 1 has a structure in which the plasma generation space G and the processing space S are partitioned by the partition plate 11.

[0081] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The above embodiments can be omitted, replaced, and changed in various ways without departing from the scope of the appended claims and their gist.

Claims

1. A substrate processing method is a method of processing a substrate using a substrate processing apparatus. The substrate processing apparatus includes: A processing container for processing the substrate inside the processing container; A plasma generation space formed inside the processing container; A processing space communicating with the plasma generation space via a partition plate; A stage disposed inside the processing space for placing the substrate on the upper surface of the stage; And A lifting mechanism for lifting and lowering the substrate on the stage, wherein, in the plasma processing for etching, diffusing, or film-forming the substrate in the processing space, the lifting mechanism is used to lift and lower the substrate so that the substrate changes from a state away from the stage to a state of being placed on the stage, thereby causing a potential change in the substrate during the plasma processing. wherein the plasma processing is started in a state where the substrate is lifted away from the stage by the lifting mechanism, and during the plasma processing, the substrate is lowered by the lifting mechanism and placed on the stage.

2. The substrate processing method according to claim 1, wherein The substrate is lowered by the lifting mechanism immediately after the start of the plasma processing.

3. The substrate processing method according to claim 1 or 2, wherein The lifting mechanism is a lift pin that holds the substrate when loading and unloading the substrate with respect to the substrate processing apparatus.

4. The substrate processing method according to claim 1 or 2, wherein At least the holding surface of the stage for holding the substrate is coated with a coating material that is more resistant to free radicals than the metal material constituting the stage.

5. The substrate processing method according to claim 4, wherein The lifting mechanism is also coated with the coating material.

6. The substrate processing method according to claim 4, wherein The coating material is at least one material selected from YF3 and YOF.

7. The substrate processing method according to claim 1 or 2, wherein The lifting mechanism is constituted by a constituent member that is at least more resistant to free radicals than the metal material constituting the stage.

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