Preparation Method of Doped Semiconductor Device and Semiconductor Device

Abstract

The present application relates to a method for manufacturing a doped semiconductor device and a semiconductor device. The method for manufacturing the doped semiconductor device includes: providing a substrate, and growing a first oxide layer on the front and back surfaces of the substrate respectively; etching away the first oxide layer on the back surface of the substrate and the first oxide layer on the peripheral side of the front surface of the substrate by wet etching; coating the front and back surfaces of the substrate and the front and side surfaces of the first oxide layer to generate a first doping region; performing high-temperature diffusion on the front and back surfaces of the substrate, and growing a second oxide layer on the front surface of the first oxide layer, the front surface of the first doping region, and the back surface of the first doping region respectively; etching away the first oxide layer and the second oxide layer on the front surface of the substrate by dry etching; performing diffusion treatment on the front surface of the substrate to generate a second doping region. The double-sided coating method in the present application has a low equipment cost, better etching uniformity, and saves processes.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to a method for manufacturing a doped semiconductor device and a semiconductor device. Background Art

[0002] Currently, with the increasing popularity of electronic products in daily life, the manufacturing of semiconductor devices has increasingly become a hot topic of concern.

[0003] For the preparation of the doped region of a semiconductor device, ion implantation is generally used as the doping method. Ion implanters are expensive and need to be imported from abroad. Moreover, the purchase of advanced ion implantation equipment is restricted, and the procurement cycle is long. In addition, the ion implantation method requires ion implantation to be carried out separately from the front and back sides of the wafer. That is, when ion implantation is carried out on the front side, the back side needs to be blocked, and when ion implantation is carried out on the back side, the front side needs to be blocked, resulting in a cumbersome processing process for semiconductor devices. In addition, during ion implantation, wet etching is often combined to etch the oxide layer, which will cause the problem of side etching and affect the final output quality of semiconductor devices. Summary of the Invention

[0004] This application aims to provide a method for manufacturing a doped semiconductor device and a semiconductor device to solve the problems such as expensive ion implantation equipment, cumbersome process, and side etching.

[0005] In a first aspect, an embodiment of this application proposes a method for manufacturing a doped semiconductor device, including:

[0006] Providing a substrate, and growing a first oxide layer on the front and back sides of the substrate respectively;

[0007] Etching away the first oxide layer on the back side of the substrate and the first oxide layer on the peripheral side of the front side of the substrate by means of wet etching;

[0008] Coating the front and back sides of the substrate and the front and side surfaces of the first oxide layer to generate a first doped region;

[0009] Performing high-temperature drive-in on the front and back sides of the substrate, and growing a second oxide layer on the front surface of the first oxide layer, the front surface of the first doped region, and the back surface of the first doped region respectively;

[0010] Etching away the first oxide layer and the second oxide layer on the front side of the substrate by means of dry etching;

[0011] Performing diffusion treatment on the front side of the substrate to generate a second doped region.

[0012] In the step of performing double-sided coating on the front side of the substrate, the back side of the substrate, and the front side of the first oxide layer, a p-type impurity diffusion composition is coated on the front and back sides of the substrate by means of a spin coater in a spin coating manner.

[0013] Wherein, the first doping region is a P+ doping region, and the second doping region is an N+ doping region.

[0014] After the step of performing diffusion treatment on the front surface of the substrate to form the second doping region, the method further includes: growing sacrificial layers on the front surface of the second doping region, the front surface of the second oxide layer, and the back surface of the second oxide layer by performing high-temperature push-annealing in a furnace.

[0015] Wherein, the thickness of the sacrificial layer is 300A - 600A.

[0016] After the step of growing sacrificial layers on the front surface of the second doping region, the front surface of the second oxide layer, and the back surface of the second oxide layer by performing high-temperature push-annealing in a high-temperature furnace, the method further includes: removing the sacrificial layer, a part of the second oxide layer, and the organic matter remaining on the surface of the second oxide layer by pickling.

[0017] After the step of removing the sacrificial layer, a part of the second oxide layer, and the organic matter remaining on the surface of the second oxide layer by pickling, the method further includes: forming an antireflection layer on the front surface of the second doping region and the front surface of the second oxide layer by chemical vapor deposition.

[0018] After the step of depositing the antireflection layer on the front surface of the second doping region and the front surface of the second oxide layer, the method further includes: etching lead holes in the antireflection layer by wet etching.

[0019] After the step of etching lead holes in the antireflection layer by wet etching, the method further includes: growing a first electrode on the lead holes and growing a second electrode on the back surface of the first doping region.

[0020] In a second aspect, an embodiment of the present application further provides a semiconductor device, which is manufactured by using the preparation method of the doped semiconductor device. The semiconductor device includes: a substrate; a first doping region doped on the back surface of the substrate and the periphery of the front surface of the substrate; a second doping region doped at the center position of the front surface of the substrate; a first oxide layer formed on the front surface of the substrate; and a second oxide layer formed on a side of the first oxide layer away from the substrate.

[0021] A method for preparing a doped semiconductor device and a semiconductor device according to an embodiment of the present application. The method for preparing the doped semiconductor device replaces ion implantation by means of coating and diffusion, greatly reducing the equipment cost. Moreover, coating and diffusion are completed in one step respectively, without the need for step-by-step completion. Coating and diffusion will not damage the substrate. Therefore, there is no need to thin the substrate thickness, no substrate material will be wasted, and the process steps are saved, improving the working efficiency. When performing the first photolithography, wet etching is used for the front and back surfaces of the substrate, which can achieve large-area and rapid etching. When performing the second photolithography, dry etching is used for the central position of the front surface of the substrate, which can achieve anisotropy in the etching profile, prevent side etching, reduce photoresist peeling or adhesion, have good etching uniformity, reduce the use of chemicals during etching, and have good safety and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference numerals. The drawings are not drawn to actual scale and are only used to illustrate the relative positional relationship. The layer thickness of some parts is exaggerated in the drawing for ease of understanding, and the layer thickness in the drawings does not represent the proportional relationship of the actual layer thickness.

[0023] Figure 1 A flowchart showing a method for preparing a doped semiconductor device provided by the present application;

[0024] FIG. 2(a) shows a schematic diagram of the state of the front and back surfaces of the substrate after growing the first oxide layer in a method for preparing a doped semiconductor device provided by the present application;

[0025] FIG. 2(b) shows a schematic diagram of the state of the first oxide layer after one photolithography in a method for preparing a doped semiconductor device provided by the present application;

[0026] FIG. 2(c) shows a schematic diagram of the state of the substrate after double-sided coating in a method for preparing a doped semiconductor device provided by the present application;

[0027] FIG. 2(d) shows a schematic diagram of the state of the substrate generating the first doped region in a method for preparing a doped semiconductor device provided by the present application;

[0028] FIG. 2(e) shows a schematic diagram of the state of the substrate after generating the first doped region and then performing high-temperature push-junction to grow the second oxide layer in a method for preparing a doped semiconductor device provided by the present application;

[0029] FIG. 2(f) shows a schematic diagram of the state of the substrate after the second photolithography and then performing diffusion to generate the second doped region in a method for preparing a doped semiconductor device provided by the present application;

[0030] FIG. 2(g) shows a schematic diagram of the state of a sacrificial layer generated by high-temperature diffusion after a second doping region is formed on a substrate in a method for manufacturing a doped semiconductor device provided by the present application;

[0031] FIG. 2(h) shows a schematic diagram of the state of a substrate in a method for manufacturing a doped semiconductor device provided by the present application after a sacrificial layer is removed by a third photolithography and an antireflection layer is grown;

[0032] FIG. 2(i) shows a schematic diagram of the state of a lead hole formed by a fourth photolithography on an antireflection layer of a substrate in a method for manufacturing a doped semiconductor device provided by the present application;

[0033] Figure 3 FIG. shows a cross-sectional view of a semiconductor device provided by the present application.

[0034] Description of the reference numerals:

[0035] 1. Substrate; 21. First doping region; 22. Second doping region; 31. First electrode; 32. Second electrode; 4. First oxide layer; 5. Second oxide layer; 6. Sacrificial layer; 7. Antireflection layer; 71. Lead hole. Detailed Description of the Embodiment

[0036] Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application. In the drawings and the following description, at least some of the well-known structures and technologies are not shown in order to avoid unnecessarily obscuring the present application; and, for clarity, the dimensions of the regional structures may be exaggerated. In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0037] The orientation terms appearing in the following description are all the directions shown in the figures, and do not limit the specific structure of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "mounted" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be directly connected or indirectly connected. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0038] A semiconductor device is an electronic device whose conductivity is between that of a good conductor and an insulator, and uses the special electrical properties of semiconductor materials to perform specific functions.

[0039] Semiconductor devices in the prior art mainly include P-type photosensitive products and N-type photosensitive products. Among them, in the main region of the P-type photosensitive product, there is a substrate and a P-type epitaxial layer, and P+ doped regions and N+ doped regions are formed in the P-type epitaxial layer; in the main region of the N-type photosensitive product, there is a substrate and an N-type epitaxial layer, and P+ doped regions and N+ doped regions are formed in the N-type epitaxial layer.

[0040] Taking the P-type photosensitive product as an example below, the preparation method and layered structure of its doped regions will be described.

[0041] First Embodiment

[0042] Figure 1 The flowchart showing a preparation method of a doped semiconductor device provided by the present application is shown.

[0043] Please refer to Figure 1 As shown, an embodiment of the present application provides a preparation method of a doped semiconductor device, including the following steps:

[0044] S001. Provide a substrate 1, and grow a first oxide layer 4 on the front and back surfaces of the substrate 1 respectively;

[0045] S002. Etch away the first oxide layer 4 on the back surface of the substrate 1 and the first oxide layer 4 on the peripheral side of the front surface of the substrate 1 by wet etching;

[0046] S003. Coat the front and back surfaces of the substrate 1 and the front and side surfaces of the first oxide layer 4 to generate a first doped region 21;

[0047] S004. Perform high-temperature diffusion on the front and back surfaces of the substrate 1, and grow a second oxide layer 5 on the front surface of the first oxide layer 4, the front surface of the first doped region 21, and the back surface of the first doped region 21 respectively;

[0048] S005. Etch away the first oxide layer 4 and the second oxide layer 5 on the front surface of the substrate 1 by dry etching;

[0049] S006. Perform diffusion treatment on the front surface of the substrate 1 to generate a second doped region 22.

[0050] In step S001, the material of the substrate 1 is polysilicon, specifically a P-type zone-melted wafer. The thickness of the substrate 1 is 300 μm. Compared with 600 μm in the prior art, the thickness of the substrate 1 in the present application is thinner. During the preparation process, since double-sided coating does not cause scratches or other damages to the substrate 1, the thickness of the substrate 1 does not need to be thinned during the preparation process. Therefore, a substrate 1 with a thickness of 300 μm can be selected. Compared with ion implantation in the prior art, the process steps are reduced and the working efficiency is improved.

[0051] Figure 2(a) shows a schematic diagram of the state after the first oxide layer 4 is grown on the front and back of the substrate 1 of a method for preparing a doped semiconductor device provided by the present application.

[0052] Referring to Figure 2(a), in step S001, the thickness of the first oxide layer 4 on both the front and back of the substrate 1 is 6300 Å ± 500 Å. The first oxide layer 4 can be grown on both the front and back of the substrate 1 by the diffusion method of introducing nitrogen and oxygen into a high-temperature furnace. The first oxide layer 4 is mostly made of silicon oxide.

[0053] Figure 2(b) shows a schematic diagram of the state after the first oxide layer 4 of a method for preparing a doped semiconductor device provided by the present application is subjected to lithography once.

[0054] Referring to Figure 2(b), through the cutoff ring lithography, the position of the first oxide layer 4 corresponding to the first doping region 21 is etched away, that is, the first oxide layer 4 on the back of the substrate 1 and the first oxide layer 4 on the peripheral side of the front of the substrate 1 are etched away, and then the photoresist is removed by wet etching. Since the coverage area of the photoresist is large, the redundant photoresist can be removed by wet etching, which is time-saving and efficient.

[0055] Figure 2(c) shows a schematic diagram of the state after the substrate 1 of a method for preparing a doped semiconductor device provided by the present application is coated on both sides.

[0056] Referring to Figure 2(c), in step S003, the p-type impurity diffusion composition is coated on the front and back of the substrate 1 by a spin coating method using a spin coater, thereby forming the first doping region 21. Among them, the main raw material of the p-type impurity diffusion composition is boron 30 (B30). The spin coater has low equipment cost, fast coating speed, uniform coating, and high output.

[0057] Figure 2(d) shows a schematic diagram of the state of the substrate 1 of a method for preparing a doped semiconductor device provided by the present application when the first doping region 21 is formed.

[0058] Referring to Figure 2(d), in step S003, after B30 is coated on the substrate 1, it diffuses into a relatively shallow position of the substrate 1, thereby forming the first doping region 21. Then it is sent into a diffusion furnace for deposition, the temperature is 1000 °C, and the junction depth of the first doping region 21 is 1.7 μm.

[0059] Figure 2(e) shows a schematic diagram of the state of the substrate 1 of a method for preparing a doped semiconductor device provided by the present application when the second oxide layer 5 is grown by high-temperature diffusion after the first doping region 21 is formed.

[0060] Referring to FIG. 2(e), in step S004, the substrate 1 is subjected to high-temperature diffusion at a temperature of 1100 °C to form a second oxide layer 5 with a thickness of 3000 Å - 5000 Å. The second oxide layer 5 is made of silicon oxide material.

[0061] FIG. 2(f) shows a schematic diagram of the state of the substrate 1 after the second lithography in the preparation method of a doped semiconductor device provided by the present application, followed by diffusion to form a second doped region 22.

[0062] Referring to FIG. 2(f), in steps S005 and S006, the first oxide layer 4 and the second oxide layer 5 on the front surface of the substrate 1 are removed by dry etching, and then the substrate is sent into a diffusion furnace and phosphorus oxychloride is introduced for high-temperature diffusion to form a second doped region 22. The junction depth of the second doped region 22 is 3 μm.

[0063] Specifically, dry etching is anisotropic during the etching profile, which can prevent side etching, has good etching uniformity, and dry etching does not cause problems such as photoresist peeling or adhesion. Compared with wet etching, dry etching uses fewer chemicals, is safer, and has lower costs.

[0064] FIG. 2(g) shows a schematic diagram of the state of the substrate 1 after forming a second doped region 22 and then performing high-temperature diffusion to form a sacrificial layer 6 in the preparation method of a doped semiconductor device provided by the present application.

[0065] Referring to FIG. 2(g), after forming the second doped region 22, by means of high-temperature diffusion, using nitrogen as a raw material, a sacrificial layer 6 is grown on the front surface of the second doped region 22, the front surface of the second oxide layer 5, and the back surface of the second oxide layer 5 respectively. Specifically, the thickness of the sacrificial layer 6 is 300 Å - 600 Å.

[0066] FIG. 2(h) shows a schematic diagram of the state of the substrate 1 after the third lithography to remove the sacrificial layer 6 and grow an antireflection layer 7 in the preparation method of a doped semiconductor device provided by the present application.

[0067] Referring to FIG. 2(h), after the step of growing the sacrificial layer 6, it further includes: removing the sacrificial layer 6, a part of the second oxide layer 5, and the organic matter remaining on the surface of the second oxide layer 5 by pickling. An antireflection layer 7 is deposited on the front surface of the second doped region 22 and the front surface of the second oxide layer 5. The thickness of the antireflection layer 7 is 1000 Å - 1600 Å, and the function of the antireflection layer 7 is to reduce light reflection and increase the light absorption rate of the P-type photosensitive device.

[0068] Specifically, the anti-reflection layer 7 is formed by chemical vapor deposition (CVD for short). Chemical vapor deposition refers to a gas-phase reaction at high temperatures. For example, thermal decomposition of metal halides, organometals, hydrocarbons, etc., hydrogen reduction, or chemical reactions of its mixed gas at high temperatures to precipitate inorganic materials such as metals, oxides, and carbides. The formation of the anti-reflection layer 7 does not require the step of photolithography, reducing the manufacturing cost, shortening the manufacturing cycle, and saving time costs.

[0069] Fig. 2(i) shows a schematic diagram of the state where the lead hole is formed after the fourth photolithography of the anti-reflection layer 7 of the substrate 1 in a method for manufacturing a doped semiconductor device provided by the present application.

[0070] Referring to Fig. 2(i) shown, after the step of depositing the anti-reflection layer 7, it further includes: etching a lead hole on the anti-reflection layer 7 by wet etching.

[0071] Figure 3 Shows a cross-sectional view of a semiconductor device provided by the present application.

[0072] Please refer to Figure 3 Shown, after the step of etching the lead hole 71 on the anti-reflection layer 7 by photolithography, it further includes: growing a first electrode 31 on the lead hole 71 and growing a second electrode 32 on the back of the first doped region 21. The first electrode 31 is the positive electrode, and the positive electrode is formed by depositing metal aluminum. The thickness of the first electrode 31 is 2 μm - 2.4 μm. The second electrode 32 is the negative electrode, and the negative electrode is formed by depositing metal silver from bottom to top through metal titanium, metal nickel, and metal silver in sequence.

[0073] In summary, since the present application uses a double-sided coating process to fabricate the first doped region 21, and the area occupied by the first doped region 21 is relatively large, therefore, before fabricating the first doped region 21, it is necessary to quickly etch a part of the first oxide layer 4 on the front and back of the substrate 1 by wet etching. When fabricating the second doped region 22, since the area occupied by the second doped region 22 is relatively small, dry etching is used for directional etching, and there will be no side etching, which does not affect other structures. Finally, by the above method, only four steps of photolithography are required to form, and there is no need to thin the substrate 1. The steps are few, the process is simple, and the cost is low.

[0074] It should be noted that in the above photolithography steps: first select the material layer, coat the photoresist, expose, develop to remove the photoresist, perform dry etching or wet etching, and finally remove the remaining photoresist. This is a complete photolithography process.

[0075] In addition, the above high-temperature furnaces are all atmospheric-pressure diffusion furnace tubes, which are one of the important process equipment in the front process of the semiconductor production line and are used for processes such as diffusion, oxidation, annealing, alloying, and sintering in industries such as large-scale integrated circuits, discrete devices, power electronics, optoelectronic devices, and optical fibers.

[0076] The process steps not elaborated in detail in the process are all conventional process processes, such as lead hole lithography, lead hole etching, acid floating, diffusion, lithography, dry etching, etc., and will not be described in detail in this application.

[0077] Second Embodiment

[0078] Please continue to refer to Figure 3 As shown, this embodiment provides a semiconductor device, which is made by using the preparation method of the doped semiconductor device. The semiconductor device includes: a substrate 1; a first doped region 21 doped on the back surface of the substrate 1 and the peripheral side of the front surface of the substrate 1; a second doped region 22 doped at the central position of the front surface of the substrate 1; a first oxide layer 4 formed on the front surface of the substrate 1; and a second oxide layer 5 formed on the side of the first oxide layer 4 facing away from the substrate 1.

[0079] Among them, the first doped region 21 is a P+ doped region, and the second doped region 22 is an N+ doped region. A P+ doped region is doped on the back surface of the substrate 1, and an N+ doped region is generated at the central position of the front surface of the substrate 1. The outer periphery of the N+ doped region is a P+ doped region, so that when the semiconductor device works, a good voltage division effect can be achieved.

[0080] Furthermore, the semiconductor device further includes: an oxide layer, an antireflection layer 7, a first electrode 31, and a second electrode 32. The antireflection layer 7 is formed on the front surface of the substrate 1, and a lead hole is formed in the antireflection layer 7. The first electrode 31 is located in the lead hole, the second electrode 32 is located on the back surface of the first doped region 21, and the oxide layer is located on the front surface of the substrate 1, which includes the first oxide layer 4 on the front surface of the substrate 1 and the second oxide layer 5 formed on the side of the first oxide layer 4 facing away from the substrate 1.

[0081] Among them, the first electrode 31 is a positive electrode, which is formed by depositing metal aluminum, and the thickness of the first electrode 31 is 2 μm - 2.4 μm. The second electrode 32 is a negative electrode, which is formed by depositing metal silver, and the negative electrode is deposited with metal titanium, metal nickel, and metal silver from bottom to top in sequence.

[0082] In addition, the raw material of the substrate 1 is polysilicon, and the material of the oxide layer is silicon oxide. The thickness of the substrate 1 is 300 μm. Compared with 600 μm in the prior art, the thickness of the substrate 1 in this application is thinner. During the preparation process, since the double-sided coating does not cause scratches or other damages to the substrate 1, the substrate 1 does not need to be thinned during the preparation process. Therefore, it is sufficient to select the substrate 1 with a thickness of 300 μm. Compared with the ion implantation in the prior art, the process steps are reduced and the working efficiency is improved.

[0083] It should be noted that the semiconductor device in this embodiment may further include other layer structures, such as a barrier layer, an epitaxial layer, etc., which will not be elaborated here.

[0084] The technical solution of this application can be widely applied to the preparation of various semiconductor devices, such as discrete device categories including Schottky Barrier Diode (SBD), Fast Recovery Diode (FRD), Transient Voltage Suppressor (TVS), switch diode, Rectifier Diode, light-emitting triode, thyristor rectifier element, small-signal triode, etc. The above-mentioned solution is applicable to all of them.

[0085] It should be easily understood that the terms "on...", "above...", and "over..." in this application should be interpreted in the broadest manner, so that "on..." not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above..." or "over..." not only includes the meaning of "above or over something", but may also include the meaning of "above or over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0086] The term "layer" used herein may refer to a portion of a material including a region having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of lateral planes at the top surface and the bottom surface. The layer may extend laterally, vertically, and / or along a conical surface. The semiconductor device may be a layer, may include one or more layers therein, and / or may have one or more layers located thereon, above it, and / or below it. The layer may include multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a doped semiconductor device, characterized in that, include: Providing a substrate, and growing a first oxide layer on the front side and the back side of the substrate respectively; Etch away the first oxide layer on the back side of the substrate and the first oxide layer on the peripheral side of the front side of the substrate by wet etching; Coating the front and back sides of the substrate and the front and side surfaces of the first oxide layer to generate a first doped region; Performing high-temperature push-bonding at 1100° C. on the front and back sides of the substrate, and growing a second oxide layer on the front side of the first oxide layer, the front side of the first doped region, and the back side of the first doped region, respectively; Only the first oxide layer and the second oxide layer at the center of the front side of the substrate are etched away by dry etching, while the first oxide layer and the second oxide layer located on the first doping region are retained; A diffusion process is performed on the front side of the substrate to generate a second doping region, wherein the second doping region is formed in the substrate between the first doping regions.

2. The method for preparing a doped semiconductor device according to claim 1, characterized in that, In the step of double-sided coating the front side of the substrate, the back side of the substrate and the first oxidized front side, the p-type impurity diffusion composition is coated on the front side and the back side of the substrate by a spin coater in a spin coating manner.

3. The method for preparing a doped semiconductor device according to claim 1, characterized in that, The first doping region is a P+ doping region, and the second doping region is an N+ doping region.

4. The method for preparing a doped semiconductor device according to claim 1, wherein, After the step of performing diffusion treatment on the front side of the substrate to generate the second doped region, the method further includes: performing high-temperature push-knotting in a furnace to grow sacrificial layers on the front side of the second doped region, the front side of the second oxide layer, and the back side of the second oxide layer.

5. The method for preparing a doped semiconductor device according to claim 4, wherein The thickness of the sacrificial layer is 300Å-600Å.

6. The method for preparing a doped semiconductor device according to claim 4 or 5, characterized in that, After the step of growing a sacrificial layer respectively on the front side of the second doping region, the front side of the second oxide layer and the back side of the second oxide layer by performing high-temperature push-joining in a high-temperature furnace, it also includes: removing the sacrificial layer, part of the second oxide layer and residual organic matter on the surface of the second oxide layer by acid bleaching.

7. The method for preparing a doped semiconductor device according to claim 6, characterized in that, After the step of removing the sacrificial layer, part of the second oxide layer and organic matter remaining on the surface of the second oxide layer by acid bleaching, the method further includes: forming an anti-reflection layer by chemical vapor deposition on the front side of the second doping region and the front side of the second oxide layer.

8. The method for preparing a doped semiconductor device according to claim 7, characterized in that, After the step of depositing an anti-reflection layer on the front side of the second doping region and the front side of the second oxide layer, the method further includes: etching lead holes on the anti-reflection layer by wet etching.

9. The method for preparing a doped semiconductor device according to claim 8, wherein, After the step of etching a lead hole on the anti-reflection layer by wet etching, the method further includes: growing a first electrode on the lead hole, and growing a second electrode on the back side of the first doped region.

10. A semiconductor device is fabricated by using the method for fabricating a doped semiconductor device according to any one of claims 1-9, wherein, The semiconductor device comprises: substrate; A first doping region, doped on the back side of the substrate and the peripheral side of the front side of the substrate; A second doping region, doped at the center of the front side of the substrate; A first oxide layer is formed on the front surface of the substrate; and The second oxide layer is formed on a side of the first oxide layer facing away from the substrate.

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