Isolation unit and chip

Abstract

The embodiment of the present application provides a kind of isolation unit and chip, belong to integrated circuit technical field.The isolation unit includes: isolation holding unit, for isolating the signal interaction between power-off region and live region, wherein the signal output to the live region of the power-off region is to be isolated signal;And sampling control unit, for when isolation instruction signal indicates that the power-off region is powered off isolation, control the isolation holding unit isolation and latch the to be isolated signal.The isolation unit provided by the embodiment of the present application can increase the data holding function of isolation unit under the condition of meeting the chip power-off isolation function.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an isolation unit and a chip. Background Technology

[0002] With the continuous promotion of technologies such as mobile communication and the Internet of Things, the application of chips in the mobile field is becoming increasingly prominent. Most mobile devices are battery-powered and are highly sensitive to chip power consumption. Many chips employ techniques to reduce power consumption by partially de-energizing certain areas. This technique requires inserting isolation units between the de-energized and energized areas to ensure that the chip does not leak current.

[0003] Currently, the widely used isolation unit structure uses AND gates or OR gates for isolation. In terms of design, the signal output from the power-down region can only be fixed to a single high level or low level, and it is impossible to maintain the original state of the signal before power loss. This has great limitations in use and may even cause some functions to fail. Sometimes, it is even necessary to put the module that should be powered down into the powered area, resulting in a waste of chip power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide an isolation unit that can maintain the signal in the power-down region in the state before the power failure.

[0005] To achieve the above objectives, embodiments of the present invention provide an isolation unit, which includes: an isolation holding unit for isolating signal interaction between a power-down region and a power-on region, wherein the signal output from the power-down region to the power-on region is a signal to be isolated; and a sampling control unit for controlling the isolation holding unit to isolate and latch the signal to be isolated when an isolation indication signal indicates that the power-down region is power-down isolated.

[0006] Optionally, the sampling control unit includes a clock gating unit and a delay unit. The clock gating unit takes the isolation indication signal and the sampling clock signal as inputs and outputs a first clock signal or a low level; the delay unit takes the isolation indication signal as input and outputs the delayed isolation indication signal.

[0007] Optionally, the clock gating unit outputs the first clock signal or a low level, including: outputting the first clock signal when the isolation indication signal does not indicate power-down isolation of the power-down region; and outputting a low level when the isolation indication signal indicates power-down isolation of the power-down region.

[0008] Optionally, the isolation holding unit includes: a gate unit, which takes the signal to be isolated and the delayed isolation indication signal as inputs, and is used to isolate the signal to be isolated according to the indication of the delayed isolation indication signal; a trigger, whose input terminals are respectively connected to the output terminals of the gate unit and the clock gating unit, and is used to latch the signal to be isolated during power-down isolation; and an isolation holding unit output terminal, wherein the output terminals of the trigger and the gate unit are respectively connected to the isolation holding unit output terminal, and the isolation holding unit output terminal is also connected to a energized area, and is used to switch the output signal of the output gate unit and the output signal of the trigger.

[0009] Optionally, the door unit includes one of an AND door and an OR door.

[0010] Optionally, the output of the isolation and holding unit is a selector.

[0011] Optionally, the switching output signal of the output gate unit and the output signal of the trigger include: when the isolation indication signal does not indicate power-off isolation of the power-off region, the level of the isolation indication signal remains unchanged; the clock gating unit outputs the first clock signal to control the sampling clock of the trigger to be turned on, and the trigger collects the output signal of the gate unit; the selector selects to output the output signal of the gate unit.

[0012] Optionally, the switching of the output signal of the output gate unit and the output signal of the trigger includes: when the isolation indication signal indicates that the power-down area is power-down isolated, the level of the isolation indication signal changes; the clock gating unit outputs a low level to control the sampling clock of the trigger to be turned off, and the trigger stops acquiring the output signal of the gate unit; the isolation indication signal is output to the gate unit through the delay unit to control the isolation of the signal to be isolated; and the selector selects to output the output signal of the trigger.

[0013] Optionally, the switching of the output signal of the output gate unit and the output signal of the trigger further includes: after the power-off region is powered on again, the level of the isolation indication signal changes to the level before the power-off isolation; the clock gating unit outputs the first clock signal to control the sampling clock of the trigger to be turned on, and the trigger collects the output signal of the gate unit; the selector selects to output the output signal of the gate unit.

[0014] Optionally, the clock gating unit is further configured to output a second clock signal, and the sampling control unit further includes: a pulse generation unit located on the line between the isolation indication signal and the clock gating unit, configured to: output a low level when the isolation indication signal does not indicate power-down isolation of the power-down region, so as to control the clock gating unit to output a low level; and output a high-level pulse signal when the isolation indication signal indicates power-down isolation of the power-down region, so that the sampling clock signal and the high-level pulse signal pass through the clock gating unit to output the second clock signal.

[0015] Optionally, the switching output signal of the output gate unit and the output signal of the trigger include: when the isolation indication signal does not indicate power-down isolation of the power-down region, the level of the isolation indication signal remains unchanged; the clock gating unit outputs a low level to keep the sampling clock of the trigger off; and the selector selects to output the output signal of the gate unit.

[0016] Optionally, the switching of the output signal of the output gate unit and the output signal of the trigger includes: when the isolation indication signal indicates that the power-down region is power-down isolated, the level of the isolation indication signal changes; the clock gating unit outputs the second clock signal to control the sampling clock of the trigger to be turned on; the trigger acquires the output signal of the gate unit; after the acquisition is completed, the clock gating unit outputs a low level to turn off the sampling clock of the trigger; the isolation indication signal is output to the gate unit through the delay unit to control the isolation of the signal to be isolated; and the selector selects to output the output signal of the trigger.

[0017] Optionally, the switching output signal of the output gate unit and the output signal of the trigger further include: after the power-off region is powered on again, the level of the isolation indication signal changes to the level before the power-off isolation; the selector selects to output the output signal of the gate unit.

[0018] Optionally, the isolation unit includes two or more isolation holding units, and the sampling control unit can control the two or more isolation holding units to isolate and latch the signal to be isolated.

[0019] This invention also provides a chip that includes the isolation unit described above.

[0020] Through the above technical solution, the isolation unit provided in this embodiment of the invention includes an isolation holding unit for isolating the interaction between power-down region signals and power-on region signals, wherein the power-down region signal is the signal of the signal to be isolated when it is powered down; and a sampling control unit for controlling the isolation holding unit to latch and isolate the power-down region signal. The isolation unit provided in this embodiment of the invention can, while satisfying the chip's power-down isolation function, add a data retention function to the isolation unit, enabling the power-down region of the chip to maintain the level of the signal to be isolated before power-down when power-down isolation is required.

[0021] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0023] Figure 1A , Figure 1B This is a schematic diagram of the structure of a general-purpose isolation unit;

[0024] Figure 2 This is an example diagram of inter-power domain interaction signals;

[0025] Figure 3 This is a schematic diagram of the structure of the isolation unit provided in an embodiment of the present invention;

[0026] Figure 4A , Figure 4B This is a schematic diagram of the preferred isolation unit provided in an embodiment of the present invention;

[0027] Figure 5 yes Figure 4A and Figure 4B The diagram shows the timing sequence of the isolation unit.

[0028] Figure 6A yes Figure 4A Schematic diagram of the improved isolation unit structure;

[0029] Figure 6B yes Figure 4B Schematic diagram of the improved isolation unit structure;

[0030] Figure 7 It is 6A and Figure 6B The diagram shows the timing sequence of the isolation unit.

[0031] Figure 8 This is a schematic diagram of the structure of the extended isolation unit provided in an embodiment of the present invention;

[0032] Figure 9 yes Figure 8 A schematic diagram illustrating an application example of an extended isolation unit.

[0033] Explanation of reference numerals in the attached figures

[0034] 10 power failure zones 20 isolation retention units

[0035] 30 sampling control units, 21 gate units

[0036] 22-Flip-Flop, 23-Selector

[0037] 31 Clock gating unit 32 Delay unit

[0038] 33 pulse generation unit Detailed Implementation

[0039] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0040] Before describing the embodiments of the present invention in detail, a brief introduction will be given to the prior art and the design concept of the embodiments of the present invention.

[0041] Figure 1A and Figure 1B This is a schematic diagram of a general-purpose isolation unit. Please refer to it. Figure 1A , Figure 1B DATA_POWER_OFF represents the output signal of the power-down region, denoted as the signal to be isolated. ISO_EN and QOUT are signals of the powered region. After the signal to be isolated is powered down, due to the induction effect of nearby signals, the signal DATA_POWER_OFF may become in an indeterminate state (i.e., the level is neither high nor low). If this signal is connected to a powered region, it may cause chip leakage, and in severe cases, it may burn out the chip.

[0042] To solve the above problem, when power is required internally within the chip, the signal output from the power-down region to the power-on region can be fixed at a high or low level. ISO_EN represents the isolation indicator signal; please refer to [reference needed]. Figure 1A When ISO_EN is high, it does not interfere with the DATA_POWER_OFF signal. When ISO_EN changes from high to low, the chip's power-down region is about to lose power, and the DATA_POWER_OFF signal is kept low by the AND gate outputting the QOUT signal. (See also...) Figure 1BWhen ISO_EN is high, it does not interfere with the DATA_POWER_OFF signal. When ISO_EN changes from high to low, the power-down region of the chip is about to lose power, and the DATA_POWER_OFF signal is maintained at a high level by outputting the QOUT signal through an OR gate. Therefore, the uncertain state signal of the power-down region can be fixed at a high or low level, achieving signal isolation between the power-down region and the powered region.

[0043] In current common isolation unit structures, since AND gates or OR gates are used for isolation, the design can only fix the signal output from the power-down region to a single high or low level, and cannot maintain the original state of the signal before power loss. This has great limitations in use and may even cause some functions to fail. Sometimes it is even necessary to put the module that should be powered down into the powered area, resulting in wasted chip power consumption.

[0044] Please refer to the example provided. Figure 2 When complex signal interactions are required between power domains, different signal values ​​represent different chip operating modes (CHIP_MODE). For example, CHIP_MODE: 0 indicates the chip operates in mode 0; 1 indicates mode 1; 2 indicates mode 2; and 3 indicates mode 3. The power-down region of the chip sends a 2-bit wide CHIP_MODE signal to the powered region. In existing technology, after the power-down region of the chip loses power, the CHIP_MODE signal can only be fixed to one of the values ​​0-3. After the power-down region loses power, the chip can only operate in one of these modes, and other modes cannot be used. When CHIP_MODE is a 4-bit or wider signal, the possible combinations of modes are 16 or more, further limiting its application.

[0045] This invention provides an isolation unit that, while satisfying the isolation function, allows the signal output from the power-down region to the power-on region to maintain its original level after the power-down region of the chip is powered down, without affecting the timing relationship of the electrical signals corresponding to the normal operating mode, and without increasing the dynamic power consumption of the chip during normal operation.

[0046] Figure 3 This is a schematic diagram of the isolation unit provided in an embodiment of the present invention. Please refer to it. Figure 3 The isolation unit includes: an isolation holding unit 20, used to isolate signal interaction between a power-down region and a power-on region, wherein the signal output from the power-down region to the power-on region is a signal to be isolated; and a sampling control unit, used to control the isolation holding unit to isolate and latch the signal to be isolated when the isolation indication signal indicates that the power-down region is power-down isolated.

[0047] The power-down region 10 can be considered as the area on the chip that requires power-down isolation. The signal output from the power-down region 10 to the charged region can be represented as the isolation signal DATA_POWER_OFF. When power-down isolation is not required (i.e., normal operating state), the level of the isolation signal DATA_POWER_OFF will not be uncertain; when power-down isolation is required, the level of the isolation signal DATA_POWER_OFF may be uncertain, in which case the power-down region 10 needs to be isolated from the charged region.

[0048] For example, when power-down region 10 does not require power-down isolation, the signal to be isolated, DATA_POWER_OFF, is directly output after passing through the isolation holding unit 20; when power-down isolation is required, the signal to be isolated, DATA_POWER_OFF, is isolated through the isolation holding unit 20, and at the same time, the sampling control unit 30 controls the power-down isolation unit 20 to isolate and latch the signal data of the signal to be isolated, DATA_POWER_OFF, before power-down.

[0049] Figure 4A , Figure 4B This is a schematic diagram of the preferred isolation unit provided in an embodiment of the present invention. Please refer to it. Figure 4A , Figure 4B First, let's explain the signals: the isolation indicator signal ISO_EN and the sampling clock signal SMP_CLK are the signals for the energized region; the output terminal QOUT is connected to the energized region; the signal to be isolated DATA_POWER_OFF is the output signal for the de-energized region.

[0050] Preferably, the sampling control unit 30 may include a clock gating unit 31 and a delay unit 32. The clock gating unit 31 takes the isolation indication signal ISO_EN and the sampling clock signal SMP_CLK as inputs and is used to: output a first clock signal SMP_CLKGS or a low level; the delay unit 32 takes the isolation indication signal ISO_EN as input and is used to delay the output of the isolation indication signal, and then outputs the delayed isolation indication signal ISO_EN_DLY.

[0051] Specifically, the clock gating unit outputs the first clock signal or a low level, including: outputting the first clock signal SMP_CLKGS when the isolation indicator signal does not indicate power-down isolation of the power-down region; and outputting a low level when the isolation indicator signal indicates power-down isolation of the power-down region.

[0052] For example, when power-down region 10 does not require power-down isolation, clock gating unit 31 outputs the first clock signal SMP_CLKGS, which can be used as the sampling clock for trigger 22; when power-down region 10 requires isolation, clock gating unit 31 outputs a low level, which can control trigger 22 to stop signal acquisition.

[0053] Preferably, the isolation holding unit 20 may include: a gate unit 21, which takes the signal to be isolated DATA_POWER_OFF and the delayed isolation indication signal ISO_EN_DLY as inputs, and is used to isolate the signal to be isolated DATA_POWER_OFF according to the indication of the delayed isolation indication signal ISO_EN_DLY; a trigger 22, whose input terminals are respectively connected to the output terminal of the gate unit 21 and the output terminal of the clock gating unit 31, and is used to latch the signal to be isolated DATA_POWER_OFF when power-down isolation occurs; and an isolation holding unit output terminal (preferably a selector 23), whose input terminals are respectively connected to the output terminal of the trigger 22 and the output terminal of the gate unit 21, and whose output terminal (preferably the selector 23) QOUT is connected to the energized area, and the selector 23 is used to switch the output signal DATAD of the output gate unit 21 and the output signal QD of the trigger 22.

[0054] Preferably, the door unit 21 includes a door (e.g., Figure 4A (as shown) and or gates (e.g.) Figure 4B (as shown) one of them.

[0055] When gate unit 21 is an AND gate, the isolation indicator signal ISO_EN is high when the power-down region 10 does not need isolation, and the isolation indicator signal ISO_EN changes from high to low when the power-down region 10 is about to be powered down. The AND gate isolates the signal interaction between the power-down region and the power-on region.

[0056] Specifically, when gate unit 21 is an OR gate, the isolation indicator signal ISO_EN is low when isolation is not required in the power-down region 10, and changes from low to high when power-down region 10 is about to be powered down. This OR gate isolates the signal interaction between the power-down region and the powered region. Detailed timing instructions are described below. Optionally, an inverter can be installed on the line between the OR gate and delay unit 32. In this case, the power-down isolation control via the OR gate is consistent with the power-down isolation control via the AND gate; that is, the isolation indicator signal ISO_EN is high when isolation is not required in the power-down region 10, and changes from high to low when power-down region 10 is about to be powered down.

[0057] For the data retention function of the isolation unit provided in this embodiment of the invention, please refer to... Figure 5 , Figure 5yes Figure 4A and Figure 4B The diagram shows the timing sequence of the isolation unit. (Combined with...) Figure 4A , Figure 5 The working principle of the isolation unit in this embodiment of the invention is described in detail.

[0058] As shown in the figure, when the power-down region 10 is operating normally, the signal to be isolated, DATA_POWER_OFF, carries signal data (e.g., datax). When the power-down region 10 is operating normally, the signal to be isolated, DATA_POWER_OFF, is directly output after passing through the isolation unit provided in this embodiment of the invention. When the power-down region 10 loses power, the signal data is lost (the signal to be isolated, DATA_POWER_OFF, is in an uncertain state). After power-on, the signal to be isolated, DATA_POWER_OFF, remains as it was before the power-down.

[0059] Preferably, the selector 23 switches the output signal of the output gate unit 21 and the output signal of the trigger 22, including: when the isolation indicator signal ISO_EN does not indicate the power-down isolation of the power-down region, the level of the isolation indicator signal ISO_EN remains unchanged; the clock gating unit 31 outputs the first clock signal SMP_CLKGS to control the sampling clock of the trigger 22 to be turned on, and the trigger 22 collects the output signal DATAD of the gate unit 21; the selector 23 selects to output the output signal DATAD of the gate unit 21.

[0060] In selector 23, QOUT equals A when the S terminal is 1, and QOUT = B when the S terminal is 0.

[0061] The following example illustrates the timing sequence of each signal during normal operation:

[0062] 1) The isolation indicator signal ISO_EN remains high, and the delayed isolation indicator signal ISO_EN_DLY output after passing through the delay unit 32 also remains high.

[0063] The signal to be isolated, DATA_POWER_OFF, is output as signal DATAD through gate unit 21 (for example, the ISO_EN signal is kept high, and the DATAD signal has the same level as the signal to be isolated, DATA_POWER_OFF).

[0064] 2) The clock gating unit 31 outputs the first clock signal SMP_CLKGS to control the sampling clock of the flip-flop 22 to start, and the flip-flop 22 collects the output signal DATAD of the gate unit 21.

[0065] 3) The isolation indication signal ISO_EN is connected to the output terminal QOUT through gate unit 21 and selector A, without changing the timing relationship of the signal to be isolated DATA_POWER_OFF.

[0066] Preferably, the switching of the output signal DATAD of the output gate unit 21 and the output signal QD of the trigger 22 includes: when the isolation indicator signal ISO_EN indicates that the power-down region is power-down isolated, the level of the isolation indicator signal ISO_EN changes; the clock gating unit 31 outputs a low level to control the sampling clock of the trigger 22 to turn off, and the trigger 22 stops acquiring the output signal DATAD of the gate unit 21; the isolation indicator signal ISO_EN is output to the gate unit 21 through the delay unit 32 to control the isolation of the signal to be isolated DATA_POWER_OFF; and the selector 23 selects to output the output signal QD of the trigger 22.

[0067] It should be noted that when power-down area 10 is about to lose power, the level of the isolation indicator signal ISO_EN changes, for example, from high level to low level. At this time, power-down area 10 and other areas of the chip will respond to the power-down event and prepare for power-down in advance. That is, there will be a delay between the change of the level of the isolation indicator signal ISO_EN and the power-down area 10 losing power.

[0068] The following example illustrates the timing sequence of each signal during power-down isolation:

[0069] 1) When the power-down region 10 of the chip is about to lose power, the isolation indicator signal ISO_EN changes from high level to low level.

[0070] When the isolation indicator signal ISO_EN changes from high to low, the power-down region 10 will continue to output a normal signal for a period of time to provide buffer time for other modules in the chip. After a period of time, the power-down region 10 will be powered off, and the isolation signal DATA_POWER_OFF may be in an uncertain state.

[0071] 2) The clock gating unit 31 outputs a low level to control the sampling clock of the flip-flop 22 to turn off, and the flip-flop 22 stops acquiring the output signal DATAD of the gate unit 21.

[0072] 3) During the delay period, the delay isolation indicator signal ISO_EN_DLY output by delay unit 32 remains high.

[0073] When the delay isolation indicator signal ISO_EN_DLY goes low, the signal to be isolated, DATA_POWER_OFF, is isolated through an AND gate.

[0074] 4) The ISO_EN_DLY delay isolation indicator signal controls selector 23 to select the output signal QD of trigger 22 at its B terminal, which is then connected to the energized area at the QOUT terminal. The output signal QD of trigger 22 can retain the signal data of the signal to be isolated, DATA_POWER_OFF, before it was powered off.

[0075] Preferably, the switching of the output signal DATAD of the output gate unit 21 and the output signal QD of the trigger 22 further includes: after the power-down region 10 is powered on again, the level of the isolation indicator signal ISO_EN changes to the level before the power-down isolation; the clock gating unit 31 outputs the first clock signal SMP_CLKGS to control the sampling clock of the trigger 22 to be turned on, and the trigger 22 collects the output signal DATAD of the gate unit 21; the selector 23 selects to output the output signal DATAD of the gate unit 21.

[0076] For example, after the chip's power-down region 10 is powered on again, the isolation signal DATA_POWER_OFF returns to its original level, and the isolation indicator signal ISO_EN changes from low to high. At this time, the clock gating unit 31 outputs the first clock signal SMP_CLKGS, and the flip-flop 22 continues to sample the output signal DATAD of the gate unit. The isolation indicator signal ISO_EN_OFF becomes high after passing through the delay unit 32 to generate the delayed isolation indicator signal ISO_EN_DLY. The selector 23 selects the output signal DATAD of the gate output unit 21 at terminal A. That is, the isolation signal DATA_POWER_OFF reaches the QOUT terminal after passing through the AND gate and the selector 23, and the chip enters the normal operating mode.

[0077] Specifically, when gate unit 21 is an OR gate, the isolation indicator signal ISO_EN is low when isolation is not required in the power-down region 10, and changes from low to high when power-down region 10 is about to be de-energized. This OR gate isolates the signal interaction between the power-down region and the energized region. Detailed timing instructions are omitted. Optionally, an inverter can be installed on the line between the OR gate and delay unit 32. In this case, the power-down isolation control via the OR gate is consistent with the power-down isolation control via the AND gate; that is, the isolation indicator signal ISO_EN is high when isolation is not required in the power-down region 10, and changes from high to low when power-down region 10 is about to be de-energized.

[0078] Further preferably, the clock gating unit is also used to output a second clock signal SMP_CLKG, and the sampling control unit further includes: a pulse generation unit 33, located on the line between the isolation indication signal ISO_EN and the clock gating unit 31, used to: output a low level when the isolation indication signal ISO_EN does not indicate the power-down isolation of the power-down region 10, so as to control the clock gating unit 31 to output a low level; and output a high-level pulse signal CLK_EN when the isolation indication signal ISO_EN indicates the power-down isolation of the power-down region 10, so that the sampling clock signal SMP_CLK and the high-level pulse signal CLK_EN pass through the clock gating unit 31 to output the second clock signal SMP_CLKG.

[0079] Figure 6A , Figure 6B They are respectively Figure 4A , Figure 4B Schematic diagram of the improved isolation unit structure; Figure 7 for Figure 6A and Figure 6B The diagram shows the timing sequence of the isolation unit. (Combined with...) Figure 6A , Figure 6B , Figure 7 When the isolation indicator signal ISO_EN changes level (i.e., when isolation is indicated), the pulse generation unit 33 generates a pulse signal CLK_EN that lasts for several clock cycles (clock cycles are 1 to n, n = 1, 2, 3...). The pulse signal CLK_EN is used to control the sampling clock signal SMP_CLK to be turned on, and to turn on the clock gating unit 31. The second clock signal SMP_CLKG output by the clock gating unit 31 serves as the sampling clock for the trigger 22.

[0080] Preferably, the switching of the output signal DATAD of the output gate unit 21 and the output signal QD of the trigger 22 includes: when the isolation indicator signal ISO_EN does not indicate the power-down region is power-down isolated, the level of the isolation indicator signal ISO_EN remains unchanged; the clock gating unit 31 outputs a low level to keep the sampling clock of the trigger 22 off; and the selector 23 selects to output the output signal DATAD of the gate unit 21.

[0081] like Figure 7As shown, when the power-down region 10 is operating normally, the signal to be isolated, DATA_POWER_OFF, carries signal data (e.g., datax). When the power-down region 10 is operating normally, the signal to be isolated, DATA_POWER_OFF, is directly output after passing through the isolation unit provided in this embodiment of the invention. When the power-down region 10 loses power, the signal data is lost (the signal to be isolated, DATA_POWER_OFF, is in an uncertain state). After power-on, the signal to be isolated, DATA_POWER_OFF, remains as it was before the power-down.

[0082] The following example illustrates the timing sequence of each signal during normal operation:

[0083] 1) The isolation indicator signal ISO_EN remains high, and the delayed isolation indicator signal ISO_EN_DLY output after passing through the delay unit 22 also remains high.

[0084] The signal to be isolated, DATA_POWER_OFF, is output as signal DATAD through gate unit 21 (for example, the ISO_EN signal is kept high, and the DATAD signal has the same level as the signal to be isolated, DATA_POWER_OFF).

[0085] 2) When the sampling clock signal SMP_CLK is not enabled, the clock gating unit 31 outputs a low level.

[0086] Preferably, when the isolation indicator signal ISO_EN does not indicate power-down isolation of the power-down region 10, the step of not controlling the sampling clock signal SMP_CLK to be turned on and the clock gating unit 31 to output a low level includes: when the pulse generating unit 33 detects that the isolation indicator signal ISO_EN does not indicate power-down isolation of the power-down region 10, the pulse generating unit 33 outputs a low level; this low level is output as a low level through the clock gating unit 31.

[0087] 3) The sampling clock of the trigger is turned off, which will not generate additional dynamic power consumption.

[0088] 4) The signal to be isolated, DATA_POWER_OFF, passes through gate unit 21 and selector A to the output terminal QOUT, without changing the timing relationship of the signal to be isolated, DATA_POWER_OFF.

[0089] Preferably, the switching of the output signal DATAD of the output gate unit 21 and the output signal QD of the trigger 22 includes: when the isolation indicator signal ISO_EN indicates power-down isolation of the power-down region, the level of the isolation indicator signal ISO_EN changes; the clock gating unit 31 outputs the second clock signal SMP_CLKG to control the sampling clock of the trigger 22 to be turned on; the trigger 22 acquires the output signal DATAD of the gate unit 21; after the acquisition is completed, the clock gating unit 31 outputs a low level to turn off the sampling clock of the trigger 22; the isolation indicator signal ISO_EN is output to the gate unit 21 through the delay unit 32 to control the isolation of the signal to be isolated DATA_POWER_OFF; the selector 23 selects to output the output signal QD of the trigger 22.

[0090] The following example illustrates the timing sequence of each signal during power-down isolation:

[0091] 1) When the power-down region 10 of the chip is about to lose power, the isolation indicator signal ISO_EN changes from high level to low level.

[0092] 2) When the sampling clock signal SMP_CLK is enabled, the clock gating unit 31 outputs the second clock signal SMP_CLKG.

[0093] After the pulse generation unit 33 detects a change in the isolation indicator signal ISO_EN, it generates a high-level pulse signal CLK_EN. The clock gating unit 31 of the sampling control unit 30 then opens, outputting the second clock signal SMP_CLKG. For example... Figure 7 In the middle, the second clock signal SMP_CLKG has 3 cycles.

[0094] 3) The second clock signal SMP_CLKG controls the sampling clock of the flip-flop 22 to start. The flip-flop 22 samples the output signal DATAD of the gate unit 21. At this time, the delay isolation indicator signal ISO_EN_DLY output by the delay unit 32 is still at a high level. The output signal DATAD of the AND gate is at the same level as the signal to be isolated DATA_POWER_OFF.

[0095] 4) After the flip-flop 22 completes sampling of the output signal DATAD of the gate unit 21, the high-level pulse signal CLK_EN becomes low, and the clock gate unit 31 of the sampling control unit 30 stops outputting the second clock signal SMP_CLKG.

[0096] When the delay isolation indicator signal ISO_EN_DLY goes low, the delay isolation indicator signal ISO_EN_DLY is isolated from the unisolated signal DATA_POWER_OFF through an AND gate.

[0097] At the same time, the delay isolation indicator signal ISO_EN_DLY controls the selector 23 to select the output signal QD of the trigger 22 at its B terminal, and connects it to the energized area at the QOUT terminal.

[0098] After power is restored in the power-off area, the level of the isolation indication signal ISO_EN changes to the level before power-off isolation; the signal to be isolated DATA_POWER_OFF passes through the gate unit 21, and the selector 23 selects and outputs the output signal DATAD of the gate unit 21.

[0099] As illustrated by the example, after the chip's power-down region is powered on again, the isolation signal DATA_POWER_OFF returns to its original level, i.e., it reverts to the isolation signal DATA_POWER_OFF; the isolation indicator signal ISO_EN changes from low to high. At this time, the signal CLK_EN output by the pulse generation unit 33 remains low, the clock gating unit 31 does not generate a clock signal, and the flip-flop 22 does not sample the output signal DATAD of the gate unit. The delayed isolation indicator signal ISO_EN_DLY generated by the delay unit 32 after the isolation indicator signal ISO_EN_EN becomes high, and the selector selects the output signal DATAD of the gate unit at terminal A to pass through. That is, the isolation signal DATA_POWER_OFF reaches the QOUT terminal through the AND gate and the selector, and the chip enters the normal operating mode.

[0100] It should be noted that the above content is an example of the working timing of gate unit 21 as an AND gate. The working timing principle of gate unit 21 as an OR gate is roughly the same as that of gate unit 21 as an AND gate. The difference is that gate unit 21 performs power-down isolation of the signal to be isolated, DATA_POWER_OFF, by controlling it with a high level or a low level. Furthermore, in this embodiment of the invention, it is preferable to set an inverter on the line between the OR gate and the delay unit 32. Then, the working timing of the isolation unit selected by gate unit 21, the OR gate and the AND gate, can be exactly the same. The details will not be repeated.

[0101] It needs to be explained that, Figure 4A , Figure 4B , Figure 6A , Figure 6B The preferred structure of the isolation unit provided in this embodiment of the invention can be simplified. For example, the isolation holding unit 20 can remove the selector 23 and directly output the output signal QD of the flip-flop 22. In this case, during normal operation, the timing of the QOUT signal is one SMP_CLK cycle later than the signal to be isolated, DATA_POWER_OFF. Therefore, the structure of the isolation unit can be selected according to the actual application scenario.

[0102] Figure 8Please refer to the structural schematic diagram of the extended isolation unit provided in the embodiment of the present invention. Figure 8 The isolation unit includes two or more isolation holding units 20, and the sampling control unit 30 can control the two or more isolation holding units 20 to latch and isolate the power-down area signal.

[0103] For example, the signal to be isolated, DATA_POWER_OFF, may be a set of signals. The first clock signal, SMP_CLKG, and the delay isolation indicator signal, ISO_EN_DLY, can be multiplexed. This allows for maintaining the original signal level after power loss, even in situations with complex signal interactions between power domains (such as a large number of inter-power domain interaction signals).

[0104] In this embodiment of the invention, while satisfying the isolation function, an isolation unit data retention function is added, which can maintain the level of the original isolation signal; no special processing is required for the interactive signals that need to be retained when the chip is powered down and powered down, which simplifies the design difficulty of the power-down system in chip design, and more modules and logic can be placed in the power-down area, which can further reduce the power consumption of the chip in some designs.

[0105] The isolation unit provided in this embodiment of the invention can also solve the problem of complex signal interaction between power domains, as well as the problem of the energized area needing to use the power-down level signal of the power-down area. Figure 9 yes Figure 8 Please refer to the schematic diagram illustrating an application example of the extended isolation unit. Figure 9 The isolation unit provided in this embodiment of the invention can maintain the working mode (WORK_MODE) data before power failure. After power failure in the power-down area, the working mode of the live area remains unchanged, allowing for flexible application. The working mode (WORK_MODE) can include 2... n+1 Modes: 0 indicates the chip is operating in mode 0; 1 indicates the chip is operating in mode 1; 2 indicates the chip is operating in mode 2. n +1 This indicates that the chip is operating in mode 2. n+1 Meanwhile, controlling multiple isolation and holding units with a single sampling control unit can reduce the increased logic circuit area caused by the isolation scheme.

[0106] Furthermore, embodiments of the present invention also provide a chip, the chip including the isolation unit described above.

[0107] Accordingly, the isolation unit provided in this embodiment of the invention can add a data retention function to the isolation unit while satisfying the chip's power-down isolation function. This allows the power-down region of the chip to maintain the level of the signal to be isolated before power-down when power-down isolation is required. It also enables the interaction between the power-down region signal and the charged region signal to maintain the original level signal after power-down.

[0108] In the isolation unit of the preferred embodiment of the present invention, the clock signal of its trigger is turned off in normal working mode, so no additional dynamic power consumption is generated; the signal to be isolated is transmitted directly to the charged area through the selector without being sampled by the trigger in normal working mode, so as not to affect the timing relationship of the signal to be isolated.

[0109] Furthermore, in the design of the chip power-down system, there is no need to perform special processing on the interactive signals that need to be retained when the chip is powered down and the powered area. This simplifies the design difficulty of the power-down system and allows more modules and logic to be placed in the power-down area, which can further reduce the power consumption of the chip.

[0110] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0111] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An isolation unit, characterized in that, The isolation unit includes: An isolation and holding unit is used to isolate signal interaction between a power-down region and a power-on region, wherein the signal output from the power-down region to the power-on region is the signal to be isolated; and The sampling control unit is used to control the isolation holding unit to isolate and latch the signal to be isolated when the isolation indication signal indicates that the power-down area is power-down isolated. The sampling control unit includes: The clock gating unit takes the isolation indication signal and the sampling clock signal as inputs and outputs a first clock signal or a low level. The delay unit takes the isolation indication signal as input, delays the output of the isolation indication signal, and outputs the delayed isolation indication signal. The isolation maintenance unit includes: A gate unit, taking the signal to be isolated and the delayed isolation indication signal as inputs, is used to isolate the signal to be isolated according to the indication of the delayed isolation indication signal; The trigger has its input terminals connected to the output terminals of the gate unit and the clock gate unit, respectively, and is used to latch the signal to be isolated during power-down isolation. The output terminal of the isolation and holding unit is connected to the output terminal of the trigger and the output terminal of the gate unit, respectively. The output terminal of the isolation and holding unit is also connected to a energized area for switching the output signal of the output gate unit and the output signal of the trigger.

2. The isolation unit according to claim 1, characterized in that, The clock gating unit outputs the first clock signal or a low level, including: When the isolation indication signal does not indicate power-off isolation of the power-off area, the first clock signal is output; When the isolation indication signal indicates that the power-down area is power-down isolated, a low level is output.

3. The isolation unit according to claim 1, characterized in that, The gate unit includes either an AND gate or an OR gate.

4. The isolation unit according to claim 1, characterized in that, The output of the isolation and maintenance unit is a selector.

5. The isolation unit according to claim 4, characterized in that, The output signals of the switching output gate unit and the output signals of the trigger include: When the isolation indication signal does not indicate power-off isolation of the power-off area, the level of the isolation indication signal remains unchanged; The clock gating unit outputs the first clock signal to control the sampling clock of the flip-flop to be turned on, and the flip-flop collects the output signal of the gate unit; The selector selects the output signal of the gate unit.

6. The isolation unit according to claim 5, characterized in that, The output signals of the switching output gate unit and the output signals of the trigger include: When the isolation indication signal indicates that the power-down area is power-down isolated, the level of the isolation indication signal changes; The clock gating unit outputs a low level to control the sampling clock of the flip-flop to turn off, and the flip-flop stops acquiring the output signal of the gate unit; The isolation indication signal is output to the gate unit through the delay unit to control the isolation of the signal to be isolated; The selector selects the output signal of the trigger.

7. The isolation unit according to claim 6, characterized in that, The output signal of the switching output gate unit and the output signal of the trigger also include: After the power is restored to the power-off area, the level of the isolation indication signal changes to the level before the power-off isolation. The clock gating unit outputs the first clock signal to control the sampling clock of the flip-flop to be turned on, and the flip-flop collects the output signal of the gate unit; The selector selects the output signal of the gate unit.

8. The isolation unit according to claim 1, characterized in that, The clock gating unit is also used to output a second clock signal, and the sampling control unit further includes: A pulse generation unit, located on the line between the isolation indication signal and the clock gating unit, is used for: When the isolation indication signal does not indicate power-down isolation of the power-down area, a low level is output to control the clock gating unit to output a low level; When the isolation indication signal indicates that the power-down area is power-down isolated, a high-level pulse signal is output so that the sampling clock signal and the high-level pulse signal pass through the clock gating unit to output the second clock signal.

9. The isolation unit according to claim 8, characterized in that, The output signals of the switching output gate unit and the output signals of the trigger include: When the isolation indication signal does not indicate power-off isolation of the power-off area, the level of the isolation indication signal remains unchanged; The clock gating unit outputs a low level to keep the sampling clock of the trigger off; The selector selects the output signal of the gate unit.

10. The isolation unit according to claim 9, characterized in that, The output signals of the switching output gate unit and the output signals of the trigger include: When the isolation indication signal indicates that the power-down area is power-down isolated, the level of the isolation indication signal changes; The clock gating unit outputs the second clock signal to control the sampling clock of the trigger to be turned on; The trigger acquires the output signal of the gate unit; After the data acquisition is completed, the clock gating unit outputs a low level to turn off the sampling clock of the trigger. The isolation indication signal is output to the gate unit through the delay unit to control the isolation of the signal to be isolated; The selector selects the output signal of the trigger.

11. The isolation unit according to claim 10, characterized in that, The output signal of the switching output gate unit and the output signal of the trigger also include: After the power is restored to the power-off area, the level of the isolation indication signal changes to the level before the power-off isolation. The selector selects the output signal of the gate unit.

12. The isolation unit according to claim 1, characterized in that, The isolation unit includes two or more isolation retention units. The sampling control unit can control two or more isolation holding units to isolate and latch the signal to be isolated.

13. A chip, characterized in that, The chip includes the isolation unit as described in any one of claims 1-12.

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