MIPI circuit for high-speed mode

Abstract

The present invention provides a MIPI circuit applied to high-speed mode, including an output unit, a driving unit, and a matching unit. The matching unit is used to generate a driving voltage that makes the on-impedance of a MOS tube identical to a target impedance, and uses the driving voltage to power the driving unit. The driving unit is used to receive an initial high-speed differential signal, generate a high-speed differential signal under the driving voltage voltage domain, and drive the output unit to output a target high-speed differential signal, so that the voltage domain of the target high-speed differential signal is the high-speed differential signal under the driving voltage voltage domain, thereby making the target high-speed differential signal correlated with the target impedance, thereby reducing the influence of the MOS tube process, voltage, and temperature on the MIPI circuit applied to high-speed mode.

Description

Technical Field

[0001] The present invention relates to the field of MIPI interface technology, and in particular to a MIPI circuit applied to a high-speed mode. Background Art

[0002] The Mobile Industry Processor Interface (MIPI) is a common data interface type, and its operating states include high-speed (HS) mode and low-power (LP) mode.

[0003] In the MIPI protocol, the high-speed mode output common-mode voltage (Vcm) ranges from 150mV to 250mV, and the high-speed differential signal voltage (Vod) output in high-speed mode ranges from 140mV to 270mV, with a maximum voltage not exceeding 360mV. Traditional MIPI circuits used in high-speed mode experience significant waveform variations in their output waveforms due to the influence of process, voltage, and temperature on MOS transistors, often exceeding the protocol requirements.

[0004] Therefore, it is necessary to provide a new type of MIPI circuit applied to high-speed mode to solve the above problems existing in the prior art. Summary of the Invention

[0005] The object of the present invention is to provide a MIPI circuit applied to high-speed mode, reducing the influence of MOS tube process, voltage and temperature on the MIPI circuit applied to high-speed mode.

[0006] To achieve the above-mentioned purpose, the MIPI circuit applied to high-speed mode of the present invention is applied to the MIPI interface, including an output unit, a driving unit and a matching unit. The matching unit is used to generate a driving voltage that makes the on-impedance of the MOS tube the same as the target impedance, and uses the driving voltage to power the driving unit. The driving unit is used to receive the initial high-speed differential signal and generate a high-speed differential signal under the driving voltage voltage domain to drive the output unit to output the target high-speed differential signal.

[0007] The beneficial effect of the MIPI circuit applied to high-speed mode is that: the matching unit is used to generate a driving voltage that makes the on-impedance of the MOS tube the same as the target impedance, and uses the driving voltage to power the driving unit; the driving unit is used to receive an initial high-speed differential signal and generate a high-speed differential signal under the driving voltage voltage domain to drive the output unit to output a target high-speed differential signal, so that the voltage domain of the target high-speed differential signal is the high-speed differential signal under the driving voltage voltage domain, thereby making the target high-speed differential signal correlated with the target impedance, thereby reducing the influence of the MOS tube process, voltage and temperature on the MIPI circuit applied to high-speed mode.

[0008] Optionally, the matching unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a current source, a first resistor, a first NMOS transistor, and a first operational amplifier. The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor form a current mirror. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to an operating voltage. The drain of the first PMOS transistor is connected to the negative electrode of the current source, the positive electrode of the current source is grounded, the drain of the second PMOS transistor is connected to one end of the first resistor and the inverting input of the first operational amplifier, the other end of the first resistor is grounded, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor and the non-inverting input of the first operational amplifier, the output of the first operational amplifier is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is grounded. This facilitates generating a voltage that varies with the process temperature of the first NMOS transistor while maintaining a constant on-resistance of the first NMOS transistor.

[0009] Optionally, the matching unit includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a current source, a first resistor, a first NMOS transistor and a first operational amplifier, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor forming a current mirror, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are grounded, the drain of the sixth NMOS transistor is connected to the positive electrode of the current source, the negative electrode of the current source is connected to the operating voltage, the drain of the seventh NMOS transistor is connected to one end of the first resistor and the inverting input end of the first operational amplifier, the other end of the first resistor is connected to the operating voltage, the drain of the eighth NMOS transistor is connected to the source of the first NMOS transistor and the non-inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the operating voltage.

[0010] Optionally, the matching unit further includes a low-dropout linear regulator, the input of which is connected to the output of the first operational amplifier, and the output of which is used to output the driving voltage. This advantageously ensures the driving capability of the driving voltage.

[0011] Optionally, the first resistor is a variable resistor, which has the beneficial effect of facilitating the maintenance of the impedance of the first resistor and preventing the first resistor from being affected by the process, voltage, and temperature.

[0012] Optionally, the output unit includes a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, the drain of the second NMOS tube and the drain of the third NMOS tube are connected to the operating voltage, the source of the fourth NMOS tube and the source of the fifth NMOS tube are grounded, the source of the second NMOS tube and the drain of the fourth NMOS tube are connected, the source of the third NMOS tube and the drain of the fifth NMOS tube are connected, and the gates of the second NMOS tube, the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected to the high-speed differential signal under the driving voltage domain.

[0013] Optionally, the output unit further includes a fourth PMOS transistor, a second operational amplifier, a second resistor, and a third resistor. The source of the fourth PMOS transistor is connected to an operating voltage, the gate of the fourth PMOS transistor is connected to the output of the second operational amplifier, the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the drain of the third NMOS transistor, the inverting input of the second operational amplifier is connected to a reference voltage, the non-inverting input of the second operational amplifier is connected to one end of the second resistor and one end of the third resistor, the other end of the second resistor is connected to the source of the second NMOS transistor, and the other end of the third resistor is connected to the source of the third NMOS transistor. This advantageous effect is that negative feedback is formed to stabilize the common-mode voltage.

[0014] Optionally, the driving unit includes a first buffer and a second buffer, the power supply end of the first buffer and the power supply end of the second buffer are connected to the driving voltage, the input end of the first buffer and the input end of the second buffer are used to receive the initial high-speed differential signal, and the output end of the first buffer and the output end of the second buffer are used to output the high-speed differential signal under the driving voltage domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a circuit diagram of a conventional MIPI circuit used in high-speed mode;

[0016] Figure 2 is a circuit diagram of a load circuit;

[0017] Figure 3 Schematic diagram of a MIPI circuit in high-speed mode according to the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0019] Figure 1 This is a circuit diagram of a traditional MIPI circuit used in high-speed mode. Figure 1The conventional MIPI circuit for high-speed mode includes a ninth NMOS transistor NM6, a tenth NMOS transistor NM7, an eleventh NMOS transistor NM8, a twelfth NMOS transistor NM9, a third buffer buf3, and a fourth buffer buf4. The drain of the ninth NMOS transistor NM6 and the drain of the tenth NMOS transistor NM7 are connected to the power supply voltage VDD, the source of the eleventh NMOS transistor NM8 and the source of the twelfth NMOS transistor NM9 are grounded GND, the source of the ninth NMOS transistor NM6 is connected to the drain of the eleventh NMOS transistor NM8, and the tenth NMOS transistor NM The source of the first NMOS transistor NM7 is connected to the drain of the twelfth NMOS transistor NM9, the input end of the third buffer buf3 and the input end of the fourth buffer buf4 are used to receive the initial high-speed differential signal, the output end of the third buffer buf3 is connected to the gate of the ninth NMOS transistor NM6 and the gate of the twelfth NMOS transistor NM9, the output end of the fourth buffer buf4 is connected to the gate of the tenth NMOS transistor NM7 and the gate of the eleventh NMOS transistor NM8, and the source of the ninth NMOS transistor NM6 and the source of the tenth NMOS transistor NM7 output the target high-speed differential signal. Specifically, the initial high-speed differential signal includes a first sub-initial high-speed differential signal VIP and a second sub-initial high-speed differential signal VIN. The input end of the third buffer buf3 is used to receive the first sub-initial high-speed differential signal VIP, and the input end of the fourth buffer buf4 is used to receive the second sub-initial high-speed differential signal VIN. The target high-speed differential signal includes a first sub-target high-speed differential signal OUTP and a second sub-target differential signal OUTN. The source of the ninth NMOS tube NM6 is the first sub-target high-speed differential signal OUTP, and the source of the tenth NMOS tube NM7 is the second sub-target high-speed differential signal OUTN.

[0020] Figure 2 This is the circuit diagram of the load circuit. Figure 1 and Figure 2 The load circuit includes a fourth resistor R4, a fifth resistor R5, and a capacitor C. One end of the fourth resistor R4 and one end of the fifth resistor R5 are connected to one end of the capacitor C. The other end of the fourth resistor R4 is connected to the source of the ninth NMOS transistor NM6. The other end of the fifth resistor R5 is connected to the source of the tenth NMOS transistor NM7. The other end of the capacitor C is grounded.

[0021] Reference Figure 1 and Figure 2The impedance of the fourth resistor R4 and the impedance of the fifth resistor R5 are both R, the on-resistance of the ninth NMOS transistor NM6 is Ron1, and the on-resistance of the twelfth NMOS transistor NM9 is Ron2. Since the circuit parameters of the conventional MIPI circuit applied to the high-speed mode are symmetrical, the on-resistance of the tenth NMOS transistor NM7 is Ron1, and the on-resistance of the eleventh NMOS transistor NM8 is Ron2.

[0022] Reference Figure 1 and Figure 2 When the first sub-initial high-speed differential signal VIP is high and the second sub-initial high-speed differential signal VIN is low, the ninth NMOS transistor NM6 and the twelfth NMOS transistor NM9 are turned on, and the tenth NMOS transistor NM7 and the eleventh NMOS transistor NM8 are turned off, current flows from the power supply voltage VDD through the ninth NMOS transistor NM6, the fourth resistor R4, the fifth resistor R5, and the twelfth NMOS transistor NM6 to the ground GND. At this time, the first sub-target high-speed differential signal OUTP is high and the second sub-target high-speed differential signal OUTN is low. The current of the conventional MIPI circuit applied in high-speed mode is i0. The voltage of the first sub-target high-speed differential signal OUTP is Voutp, Voutp=i0·(R+R+R on2 )=i0·(2R+R on2 ), the voltage of the second sub-target high-speed differential signal OUTN is Voutn, Voutn=i0·R on2 Therefore, the high-level voltage output by the conventional MIPI circuit applied in high-speed mode is VH, VH=i0·(2R+R on2 ), the low-level voltage output by the conventional MIPI circuit applied in high-speed mode is VL, VL=i0·R on2 The common mode voltage of the conventional MIPI circuit used in high-speed mode is Vcm, Vcm=i0·(R+R on2 ), it can be seen that the output current, high-level voltage, low-level voltage and common-mode voltage of the conventional MIPI circuit applied in high-speed mode are all determined by the parameters of the ninth NMOS transistor NM6 and the twelfth NMOS transistor NM9 and the power supply voltage VDD, and are affected by the process, temperature and power supply voltage of the ninth NMOS transistor NM6 and the twelfth NMOS transistor NM9, so that the output signal of the conventional MIPI circuit applied in high-speed mode can easily exceed the provisions of the MIPI protocol.

[0023] Reference Figure 1 and Figure 2When the first sub-initial high-speed differential signal VIP is at a low level and the second sub-initial high-speed differential signal VIN is at a high level, the tenth NMOS transistor NM7 and the eleventh NMOS transistor NM8 are turned on, and the ninth NMOS transistor NM6 and the twelfth NMOS transistor NM9 are turned off, current flows from the power supply voltage VDD through the tenth NMOS transistor NM7, the fourth resistor R4, the fifth resistor R5, and the eleventh NMOS transistor NM8 to ground GND. At this time, the first sub-target high-speed differential signal OUTP is at a low level and the second sub-target high-speed differential signal OUTN is at a high level. The current of the conventional MIPI circuit applied in high-speed mode is i0. The voltage of the first sub-target high-speed differential signal OUTP is Voutp, Voutp=i0·R on2 , the voltage of the second sub-target high-speed differential signal OUTN is Voutn, Voutn=i0·(R+R+R on2 )=i0·(2R+R on2 ). Therefore, the high-level voltage output by the conventional MIPI circuit applied to high-speed mode is VH, VH=i0·(2R+R on2 ), the low-level voltage output by the conventional MIPI circuit applied in high-speed mode is VL, VL=i0·R on2 The common mode voltage of the conventional MIPI circuit used in high-speed mode is Vcm, Vcm=i0·(R+R on2 ), it can be seen that the output current, high-level voltage, low-level voltage and common-mode voltage of the conventional MIPI circuit applied in high-speed mode are all determined by the parameters of the tenth NMOS transistor NM7 and the eleventh NMOS transistor NM8 and the power supply voltage VDD, and are affected by the process, temperature and power supply voltage of the tenth NMOS transistor NM7 and the eleventh NMOS transistor NM8, so that the output signal of the conventional MIPI circuit applied in high-speed mode can easily exceed the provisions of the MIPI protocol.

[0024] In view of the problems existing in the prior art, the embodiments of the present invention provide a MIPI circuit applied to high-speed mode, which is applied to the MIPI interface. Figure 3 The MIPI circuit 100 applied to the high-speed mode includes an output unit 101, a driving unit 102 and a matching unit 103.

[0025] In some embodiments, the matching unit is used to generate a driving voltage that makes the on-impedance of the MOS tube the same as the target impedance, and uses the driving voltage to power the driving unit. The driving unit is used to receive the initial high-speed differential signal and generate a high-speed differential signal under the voltage domain of the driving voltage to drive the output unit to output the target high-speed differential signal. The initial high-speed differential signal includes a first sub-initial high-speed differential signal and a second sub-initial high-speed differential signal. The target high-speed differential signal includes a first sub-target high-speed differential signal and a second sub-target high-speed differential signal.

[0026] In some embodiments, the matching unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a current source, a first resistor, a first NMOS transistor and a first operational amplifier, wherein the first PMOS transistor, the second PMOS transistor and the third PMOS transistor constitute a current mirror, the source of the first PMOS transistor, the source of the second PMOS transistor and the source of the third PMOS transistor are connected to an operating voltage, the drain of the first PMOS transistor is connected to the negative electrode of the current source, the positive electrode of the current source is grounded, the drain of the second PMOS transistor is connected to one end of the first resistor and the inverting input end of the first operational amplifier, the other end of the first resistor is grounded, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor and the non-inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is grounded.

[0027] In some optional embodiments, the matching unit includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a current source, a first resistor, a first NMOS transistor, and a first operational amplifier. The sixth, seventh, and eighth NMOS transistors form a current mirror. The sources of the sixth, seventh, and eighth NMOS transistors are grounded. The drain of the sixth NMOS transistor is connected to the positive electrode of the current source, and the negative electrode of the current source is connected to an operating voltage. The drain of the seventh NMOS transistor is connected to one end of the first resistor and the inverting input of the first operational amplifier, and the other end of the first resistor is connected to the operating voltage. The drain of the eighth NMOS transistor is connected to the source of the first NMOS transistor and the non-inverting input of the first operational amplifier. The output of the first operational amplifier is connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the operating voltage. The gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the drain of the sixth NMOS transistor.

[0028] In some embodiments, the matching unit further includes a low voltage dropout linear regulator, the input end of the low voltage dropout linear regulator is connected to the output end of the first operational amplifier, and the output end of the low voltage dropout linear regulator is used to output the driving voltage.

[0029] In some embodiments, the impedance of the first resistor is 50Ω. Preferably, the first resistor is a variable resistor, which facilitates adjusting the impedance of the first resistor so that the impedance of the first resistor can be maintained at 50Ω when affected by process, voltage and temperature.

[0030] Reference Figure 3 The matching unit 103 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a current source 1031, a first resistor R1, a first NMOS transistor NM1, a first operational amplifier 1032, and a low-voltage dropout linear regulator 1033. The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, and the drain of the first PMOS transistor PM1. The source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, and the source of the third PMOS transistor PM3 are connected to the operating voltage. The drain of the first PMOS transistor PM1 is connected to the current source. The negative electrode of the current source 1031 is connected to the positive electrode of the current source 1031, the positive electrode of the current source 1031 is grounded, the drain of the second PMOS transistor PM2 is connected to one end of the first resistor R1 and the inverting input terminal of the first operational amplifier 1032, the other end of the first resistor R1 is grounded, the drain of the third PMOS transistor PM3 is connected to the drain of the first NMOS transistor NM1 and the non-inverting input terminal of the first operational amplifier 1032, the output terminal of the first operational amplifier 1032 is connected to the gate of the first NMOS transistor NM1, the source of the first NMOS transistor NM1 is grounded, and the input terminal of the low-voltage difference linear regulator 1033 is connected to the output terminal of the first operational amplifier 1032.

[0031] In some embodiments, the output unit includes a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, the drain of the second NMOS tube and the drain of the third NMOS tube are connected to the operating voltage, the source of the fourth NMOS tube and the source of the fifth NMOS tube are grounded, the source of the second NMOS tube and the drain of the fourth NMOS tube are connected, the source of the third NMOS tube and the drain of the fifth NMOS tube are connected, and the gates of the second NMOS tube, the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected to the high-speed differential signal under the driving voltage domain.

[0032] In some embodiments, the output unit further includes a fourth PMOS tube, a second operational amplifier, a second resistor and a third resistor, the source of the fourth PMOS tube is connected to the operating voltage, the gate of the fourth PMOS tube is connected to the output end of the second operational amplifier, the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube and the drain of the third NMOS tube, the inverting input end of the second operational amplifier is connected to the reference voltage, the non-inverting input end of the second operational amplifier is connected to one end of the second resistor and one end of the third resistor, the other end of the second resistor is connected to the source of the second NMOS tube, and the other end of the third resistor is connected to the source of the third NMOS tube.

[0033] In some embodiments, the reference voltage is 200 mV.

[0034] Reference Figure 3 The output unit 101 includes a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a fourth PMOS transistor PM4, a second operational amplifier 1011, a second resistor R2, and a third resistor R3. The source of the fourth PMOS transistor PM4 is connected to the operating voltage, the gate of the fourth PMOS transistor PM4 is connected to the output terminal of the second operational amplifier 1011, the drain of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3, and the An inverting input terminal of the second operational amplifier 1011 is connected to a reference voltage VREF. A non-inverting input terminal of the second operational amplifier 1011 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the second resistor R2 is connected to the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4. The other end of the third resistor R3 is connected to the source of the third NMOS transistor NM3 and the drain of the fifth NMOS transistor NM5. The source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are grounded GND.

[0035] Reference Figure 3 , one end of the second resistor R2 and one end of the third resistor R3 are at a common mode voltage Vcm.

[0036] Optionally, the driving unit includes a first buffer and a second buffer, the power supply end of the first buffer and the power supply end of the second buffer are connected to the driving voltage, the input end of the first buffer and the input end of the second buffer are used to receive the initial high-speed differential signal, and the output end of the first buffer and the output end of the second buffer are used to output the high-speed differential signal under the driving voltage domain.

[0037] Reference Figure 3 The driving unit 102 includes a first buffer buf1 and a second buffer buf2, the input end of the first buffer buf1 is used to receive the first sub-initial high-speed differential signal VIP, the output end of the first buffer buf1 is connected to the gate of the second NMOS transistor NM2 and the gate of the fifth NMOS transistor NM5, the input end of the second buffer buf2 is used to receive the second high-speed differential signal VIN, the output end of the second buffer buf2 is connected to the gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4, and the power supply end of the first buffer buf1 and the power supply end of the second buffer buf2 are connected to the output end of the low-voltage difference linear regulator 1033.

[0038] Reference Figure 3 The other end of the second resistor R2 is the first sub-target high-speed differential signal OUTP, and the other end of the third resistor R3 is the second sub-target high-speed differential signal OUTN.

[0039] Reference Figure 2 and Figure 3 , the load circuit is applied to the MIPI circuit 100 for high-speed mode, the other end of the fourth resistor R4 is connected to the other end of the second resistor R2, and the other end of the fifth resistor R5 is connected to the other end of the third resistor R3. Optionally, the impedance of the fourth resistor R4 and the fifth resistor R5 are both 50Ω. Further optionally, the fourth resistor R4 and the fifth resistor R5 are both variable resistors to facilitate adjustment of the impedance of the fourth resistor R4 and the impedance of the fifth resistor R5, so that the impedance of the fourth resistor R4 and the fifth resistor R5 can be maintained at 50Ω when affected by process, voltage, and temperature.

[0040] Reference Figure 2 and Figure 3 The first PMOS transistor PM1, the second PMOS transistor PM2, and the third PMOS transistor PM3 form a current mirror. Therefore, the current in the branch where the first PMOS transistor PM1 is located, the DC current in the branch where the second PMOS transistor PM2 is located, and the current in the branch where the third PMOS transistor PM3 is located are equal, and the current flowing through the first resistor R1 is equal to the current flowing through the first NMOS transistor NM1.

[0041] Reference Figure 2 and Figure 3The first operational amplifier 1032 dynamically adjusts the gate voltage of the first NMOS transistor NM1, thereby making the positive input terminal voltage and the negative input terminal voltage of the first operational amplifier 1032 equal, that is, the voltage of the first resistor R1 and the voltage of the first NMOS transistor NM1 equal. Because the current flowing through the first resistor R1 is equal to the current flowing through the first NMOS transistor NM1, the on-resistance of the first NMOS transistor NM1 is equal to the impedance of the first resistor R1.

[0042] Reference Figure 2 and Figure 3 The voltage on the gate of the first NMOS transistor NM1 is supplied to the first buffer buf1 and the second buffer buf2 via the low-dropout linear regulator 1033. The first buffer buf1 is used to drive the gates of the second NMOS transistor NM2 and the fifth NMOS transistor NM5, and the second buffer buf2 is used to drive the gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4. Therefore, the on-resistance of the fourth NMOS transistor NM4 and the on-resistance of the fifth NMOS transistor NM5 are both the same as the on-resistance of the first NMOS transistor NM1, that is, the same as the impedance of the first resistor R1, where the impedance of the first resistor R1 is R1.

[0043] Reference Figure 3 The common-mode voltage Vcm is clamped by the second operational amplifier 1011, and the second operational amplifier 1011 changes the tail current by adjusting the gate voltage of the fourth PMOS tube, so that the common-mode voltage Vcm is equal to the reference voltage VREF.

[0044] Reference Figure 2 and Figure 3When the first sub-initial high-speed differential signal VIP is high and the second sub-initial high-speed differential signal VIN is low, the second NMOS transistor NM2 and the fifth NMOS transistor NM5 are turned on, and the third NMOS transistor NM3 and the fourth NMOS transistor N4 are turned off, current flows from the power supply voltage VDD through the fourth PMOS transistor PM4, the second NMOS transistor NM2, the fourth resistor R4, the fifth resistor R4, and the fifth NMOS transistor NM5 to ground GND. At this time, the first sub-target high-speed differential signal OUTP is high and the second sub-target high-speed differential signal OUTN is low. The high-level voltage output by the conventional MIPI circuit for high-speed mode is VH. The common-mode voltage Vcm of the MIPI circuit for high-speed mode is stabilized by negative feedback and is a fixed value, as determined by the formula Vcm = i1·(R+R1). It is possible to calculate the current i1 of the MIPI circuit applied to high-speed mode, and then it is possible to calculate that the voltage of the first sub-target high-speed differential signal OUTP output by the conventional MIPI circuit applied to high-speed mode is VH, and the voltage of the second sub-target high-speed differential signal OUTN output by the conventional MIPI circuit applied to high-speed mode is VL, VH = i1·(2R+R1), VL = i1·R1. Therefore,

[0045] Similarly, when the first sub-initial high-speed differential signal VIP is at a low level and the second sub-initial high-speed differential signal VIN is at a high level,

[0046] It can be seen from the above that the high-level voltage, low-level voltage and common-mode voltage of the MIPI circuit applied to the high-speed mode are independent of the parameters of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 and the power supply voltage VDD.

[0047] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A MIPI circuit used in high-speed mode, characterized in that: The device comprises an output unit, a driving unit, and a matching unit. The matching unit is used to generate a driving voltage that makes the on-impedance of the MOS tube the same as the target impedance, and uses the driving voltage to power the driving unit. The driving unit is used to receive an initial high-speed differential signal, generate a high-speed differential signal in the voltage domain of the driving voltage, and drive the output unit to output a target high-speed differential signal. The matching unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a current source, a first resistor, a first NMOS transistor and a first operational amplifier, wherein the first PMOS transistor, the second PMOS transistor and the third PMOS transistor form a current mirror, the source of the first PMOS transistor, the source of the second PMOS transistor and the source of the third PMOS transistor are connected to an operating voltage, the drain of the first PMOS transistor is connected to the negative electrode of the current source, the positive electrode of the current source is grounded, the drain of the second PMOS transistor is connected to one end of the first resistor and the inverting input end of the first operational amplifier, the other end of the first resistor is grounded, the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor and the non-inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the gate of the first NMOS transistor, and the source of the first NMOS transistor is grounded; Alternatively, the matching unit includes a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a current source, a first resistor, a first NMOS transistor, and a first operational amplifier, wherein the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor constitute a current mirror, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor, and the source of the eighth NMOS transistor are grounded, the drain of the sixth NMOS transistor is connected to the positive electrode of the current source, the negative electrode of the current source is connected to an operating voltage, the drain of the seventh NMOS transistor is connected to one end of the first resistor and the inverting input terminal of the first operational amplifier, the other end of the first resistor is connected to the operating voltage, the drain of the eighth NMOS transistor is connected to the source of the first NMOS transistor and the non-inverting input terminal of the first operational amplifier, the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the operating voltage.

2. The MIPI circuit for high-speed mode according to claim 1, wherein: The matching unit further includes a low voltage dropout linear regulator, the input end of the low voltage dropout linear regulator is connected to the output end of the first operational amplifier, and the output end of the low voltage dropout linear regulator is used to output the driving voltage.

3. The MIPI circuit for high-speed mode according to claim 1, wherein: The first resistor is a variable resistor.

4. The MIPI circuit for high-speed mode according to claim 1, wherein: The output unit includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, the drain of the second NMOS transistor and the drain of the third NMOS transistor are connected to the operating voltage, the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are grounded, the source of the second NMOS transistor and the drain of the fourth NMOS transistor are connected, the source of the third NMOS transistor and the drain of the fifth NMOS transistor are connected, and the gates of the second NMOS transistor, the gates of the third NMOS transistor, the gates of the fourth NMOS transistor and the gates of the fifth NMOS transistor are connected to the high-speed differential signal under the driving voltage domain.

5. The MIPI circuit for high-speed mode according to claim 4, wherein: The output unit also includes a fourth PMOS transistor, a second operational amplifier, a second resistor and a third resistor. The source of the fourth PMOS transistor is connected to the operating voltage, the gate of the fourth PMOS transistor is connected to the output end of the second operational amplifier, the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the drain of the third NMOS transistor, the inverting input end of the second operational amplifier is connected to the reference voltage, the non-inverting input end of the second operational amplifier is connected to one end of the second resistor and one end of the third resistor, the other end of the second resistor is connected to the source of the second NMOS transistor, and the other end of the third resistor is connected to the source of the third NMOS transistor.

6. The MIPI circuit for high-speed mode according to claim 1, wherein: The driving unit includes a first buffer and a second buffer, the power supply end of the first buffer and the power supply end of the second buffer are connected to the driving voltage, the input end of the first buffer and the input end of the second buffer are used to receive the initial high-speed differential signal, and the output end of the first buffer and the output end of the second buffer are used to output the high-speed differential signal under the driving voltage voltage domain.

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