Memory devices and methods for monitoring performance of memory devices

Abstract

The present disclosure relates to a method for checking a read phase of a non-volatile memory device including at least an array of memory cells and having associated decoding and sensing circuitry and a memory controller, the method comprising: storing at least an internal block variable and a known pattern in a dummy row associated with a memory block; performing a read of the dummy row; comparing a result of the read with the known pattern; trimming parameters of the read and / or swapping used memory blocks based on the result of the comparison.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more specifically, to methods for setting operating parameters of integrated memory circuits.

[0002] More specifically, the present disclosure relates to memory devices and corresponding methods for trimming operating parameters of memory devices and for monitoring performance and health of memory devices. BACKGROUND

[0003] Memory devices are well known in the electronic arts to store digital information and allow access to digital information. Generally, different categories of semiconductor memory devices can be incorporated into more complex systems including non-volatile memory components and / or volatile memory components, for example, into so-called systems-on-chip (SoC) in which the aforementioned memory components are embedded.

[0004] However, nowadays, real-time operating systems are required, especially for automotive applications, requiring SoCs to constantly improve their performance and efficiency, known solutions no longer being able to meet these demands.

[0005] Non-volatile memory can provide permanent data by retaining stored data when not powered and can include NAND flash memory or NOR flash memory, among others. NAND flash also has a reduced number of erase and write cycles and requires less chip area per cell, thus allowing for greater storage density and lower cost per bit than NOR flash.

[0006] One important feature of flash memory is the fact that it can be erased in blocks, rather than one byte at a time. However, one key disadvantage of flash memory is that it can only undergo a relatively small number of write and erase cycles in a particular block.

[0007] A flash memory device can include a large array of memory cells, often organized into rows and columns, for storing data. Individual memory cells and / or ranges of memory cells can be addressed by their row and column. When a memory array is addressed, there can be one or more address translation layers to translate, for example, between logical addresses utilized by a host device (i.e., SoC) and physical addresses corresponding to locations in the memory array.

[0008] While uncommon, it is also possible for address information provided to a memory device on its command / address bus to be corrupted due to an error, such that internal operations of the memory device (e.g., read operations, write operations, erase operations, etc.) can be performed on a physical address different from the physical address targeted by the host device or controller of the memory device.

[0009] Thus, there is a need for ways to verify that memory operations have been performed at the intended address, and the present disclosure focuses on methods of checking the correctness of the read phase. SUMMARY

[0010] In one aspect, the present application provides a non-volatile memory device including at least a memory cell array with associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises: a plurality of sub-arrays; a plurality of memory blocks in each sub-array; at least one dummy row for each block, the dummy row for storing at least an internal block variable of a read phase and at least one known pattern.

[0011] In another aspect, the present application provides a system including: a host device; a non-volatile memory device coupled to the host device and including at least a memory cell array with associated decoding and sensing circuitry and a memory controller; a plurality of sub-arrays in the memory array; a plurality of memory blocks in each sub-array; at least one dummy row for each block, the dummy row for storing at least an internal block variable of a read phase and at least one known pattern.

[0012] In yet another aspect, the present application provides a method for monitoring the performance or status of a non-volatile memory device including at least a memory cell array with memory blocks and having associated decoding and sensing circuitry and a memory controller, the method comprising: storing at least an internal block variable and a known pattern in a dummy row associated with the memory blocks; performing a read of the dummy row; comparing the results of the read with the known pattern; trimming parameters of the read based at least in part on the results of the comparison.

[0013] In still another aspect, the present application provides a method for checking the status of a non-volatile memory device including at least a memory cell array with memory blocks and having associated decoding and sensing circuitry and a memory controller, the method comprising: storing at least an internal block variable and a known pattern in a dummy row; performing a read of at least the dummy row; comparing the results of the read with the known pattern; based on the results of the comparison, swapping the memory blocks used. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 A schematic diagram showing a system including a memory component and a controller associated with the memory device exchanging data, address, and control signals;

[0015] Figure 2 A schematic diagram of a memory component according to the present disclosure;

[0016] Figure 3 is a schematic layout diagram of an example of a memory component according to an embodiment of the disclosure;

[0017] Figure 4 is a schematic diagram of a memory block formed of a plurality of rows of a memory array according to one embodiment of the disclosure;

[0018] Figure 5 is a schematic diagram of a group of address registers for a memory page in a memory component of the disclosure;

[0019] Figure 6 is a schematic diagram showing the distribution of correctly erased / programmed cells (1 bit / cell);

[0020] Figure 7 is a diagram showing the distribution of cells corresponding to Figure 6 is a diagram reporting an enlarged distribution of shifts towards a worn-out state (negative Vth) due to aging, temperature, and stress;

[0021] Figure 8 is a block diagram showing an example of a method step of the disclosure. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description are not meant to be limiting. Other embodiments can be used, and other changes can be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0023] Several embodiments of the disclosure are directed to memory devices, systems including memory devices, and methods of operating memory devices for the purpose of avoiding potential problems of aging, temperature, and process drift during memory operations.

[0024] In one embodiment of the disclosure, a new memory architecture is provided to improve the security and performance of the data erase phase in a non-volatile memory device.

[0025] More specifically, the disclosure relates to a non-volatile memory device including at least a memory cell array and associated decoding and sensing circuitry and a memory controller, wherein the memory array comprises:

[0026] - a plurality of sub-arrays;

[0027] - a plurality of memory blocks in each sub-array;

[0028] - at least one dummy row for each block, said dummy row being located inside or outside the address space of each block for storing at least an internal block variable of the read phase and at least one known pattern.

[0029] The known pattern mentioned above is also stored in the memory controller.

[0030] The internal block variable is a parameter used during the read phase of a memory block.

[0031] More specifically, the internal block variable is a parameter such as a read pulse and / or a target voltage applied to a memory block during the read phase.

[0032] The dummy row is physically implemented close to the relevant memory block that will undergo the same drift due to temperature and aging of the memory device.

[0033] Moreover, before starting a read algorithm on a memory block, the internal block variable of the previous read phase is retrieved from the dummy row.

[0034] For a better understanding of the present disclosure, it should be noted that flash memory has evolved as a ubiquitous source of non-volatile memory for various electronic applications.

[0035] Flash memory generally uses a base storage element; for example, a transistor as a storage element is used in all technologies employing floating gates, charge trapping, split gates, etc. Other technologies such as 3D XPoint or PCM memory employ another category of base storage elements. However, in both cases, there is a need to maintain the stored data over time and to read such data in a faster way.

[0036] When a memory array is addressed, there can be one or more address translation layers, e.g. translation between logical addresses for use by a host device and physical addresses corresponding to locations in the memory array.

[0037] Moreover, it can happen that temperature variations inside the same device can create a read offset known as a ghost temperature problem.

[0038] The drawbacks related to such temperature variations and / or device aging affect the real bit distribution detected by the sense amplifier, as a shift occurs with respect to the ideal center value it was programmed against.

[0039] In some cases, such offset and / or expanded threshold voltage distribution can cause the same problems as an incomplete erase operation during a read, as will be presented in the following description.

[0040] Just to provide a practical example, if the programming phase has been performed at -40°C, it can happen that at 120°C the reading results contain a number of errors. This is a real problem for all chips incorporated into automotive devices, where temperature increases during vehicle operation must be taken into account.

[0041] Therefore, the reading phase of the memory device is never performed in environmental conditions similar to the original programming phase; the same applies to the erasing phase.

[0042] The memory device can be defined as a certain "real time" device in the sense that it must release reliable data in all environmental operating conditions, regardless of whether it has been tested at the factory, reporting approval as a result of the positive outcome of the test.

[0043] Furthermore, the device ages further increasing the drift due to temperature and the memory devices incorporated into the system on chip of a driving autonomous vehicle are particularly sensitive to this problem.

[0044] Figure 1 A schematic example of a system 10 incorporating a flash memory device or component 100 is illustrated. The system also includes a memory controller 101 coupled to the memory device 100.

[0045] The controller 101 is shown as being coupled to the memory device 100 on a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus can be a 64-bit and / or 128-bit wide double data rate (DDR) bus.

[0046] Figure 1 The system device 10 illustrated in the center can be a host device or a system on chip coupled to the memory component 100, as presented in the description of other embodiments made by the present disclosure with reference to other figures. In any case, the system on chip 10 and the memory device 100 are implemented on respective dies obtained by different photolithography techniques and manufacturing processes.

[0047] Figure 2 is a schematic view of a memory component according to the present disclosure. The memory component 100 is a standalone structure but it is strictly associated with a host device or with a SoC structure. More specifically, the memory device 100 is associated and linked with a SoC structure partially overlapping with such structure, while the corresponding semiconductor area of the SoC structure has been used for other logic circuits, and to provide support for the standalone memory device 100 on the partially overlapping structure, for example by means of a plurality of pillars or other similar alternative connectors (e.g. ball grid) or by means of a technology similar to flip-chip.

[0048] More specifically, this non-volatile memory component 100 comprises an array 90 of flash memory cells and circuitry located around or below the memory array. The coupling between the SoC structure 10 and the memory component 100 is obtained by interconnecting a plurality of respective pads or pin terminals facing each other in the circuit layout in which the pad alignment is maintained even in case of a modified size of the memory component.

[0049] In one embodiment of the present disclosure, the arrangement of pads of the memory component has been implemented on the surface of the memory component 100, indeed, on top of the array. More specifically, the pads are arranged above the array so that when the memory component 100 is inverted, its pads face the corresponding pads of the host or SoC structure 10. Through the pads described above, the signals of the data (105), command (106) and address (107) buses are transmitted; the pads can also be used for power supply voltages and other signals and / or voltages.

[0050] Finally, memory devices 100 ranging from at least 128 Mbits to 512 Mbits or even more are manufactured according to the user's needs. More specifically, the proposed external architecture allows to exceed the limits of current eFlash (i.e. embedded flash technology) to allow the integration of larger memories, which can be 512 Mbits and / or 1 Gbit and / or even more, depending on the memory technology and technology node.

[0051] More specifically referring to the example of Figure 2 The main structure of the memory component 100 according to an embodiment of the present disclosure will be disclosed.

[0052] The memory component 100 comprises at least: an I / O circuit 5, a microsequencer 3, an array 90 of memory cells, a voltage and current reference generator 7, a charge pump 2 and decoding circuitry 8 located at the periphery of the array or below the array, a sense amplifier 9 and corresponding latches, a command user interface, e.g. CUI block 4.

[0053] The array 90 of memory cells comprises non-volatile flash memory cells. The cells can be erased in blocks, rather than one byte at a time. Each erasable memory block includes a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating voltages and timing on the access lines and data lines.

[0054] In order to write and erase the memory cells of the array 90, it is provided with a dedicated logic circuit portion comprising a simplified reduced instruction set computer (RISC) controller or a modified finite state machine or logic circuitry for handling programming and erasing algorithms.

[0055] To read the memory cells of the array 90, a dedicated circuit portion is provided for it, which includes an optimized read finite state machine to ensure high read performance, such as branch prediction, fetch / prefetch, interrupt management, etc. Error correction is left as an operation to the SoC 10; extra bits are provided to the controller 101 to store any possible ECC syndrome associated with a page. The ECC unit allows the host controller to understand if a corruption is occurring on the data plus address content.

[0056] Errors affecting the address information provided to the memory device on the command or address bus can cause memory operations to be performed on memory addresses different from the intended address.

[0057] In this regard, the controller is configured to receive a data word to be stored in an array of memory cells at an address. The controller is further configured to command the array to read the data word from the address, receive response data from the array, and verify that a location tag of the response data corresponds to the intended address.

[0058] If the location tag does not correspond to the address, the controller is configured to indicate an error. This error is detected in the metadata that includes ECC information.

[0059] The ECC information is stored adjacent to the data for which the error correction capability is provided.

[0060] Now looking more closely at the internal structure of the memory component 100, it should be noted that the architecture of the array 90 is built as a series of sub-arrays 120, as schematically shown in Figure 3

[0061] The sense amplifiers SA at the output of each sub-array 120 are directly connected to the modified JTAG unit 140 to integrate the JTAG structure and the sense amplifiers in a single circuit portion. This allows to reduce as much as possible the delay when propagating the output of the memory array to the SoC.

[0062] Each sub-array 120 contains a number of memory blocks 160, which will be referred to later. Figure 4 The disclosed number of memory blocks 160.

[0063] In this way, having a smaller sector compared to known solutions significantly reduces the access time and improves the overall throughput of the memory component.

[0064] ​Each sub-array 120 can be independently addressed inside the memory device 100. Moreover, the memory array 90 is structured with, for example, at least four memory sub-arrays 120, one for each communication channel of the host device or SoC 10 with a corresponding core. Different numbers of cores and / or sub-arrays can be used. The host device or system-on-chip 10 normally contains more than one core and each core is coupled to a corresponding bus or channel for receiving and transmitting data to the memory component 100.

[0065] Therefore, in the present embodiment, each sub-array 120 can access a corresponding channel to communicate with a corresponding core of the system-on-chip 10.

[0066] It is also noted that each sub-array 120 contains an address register connected to a data buffer register, similar to the architecture used in DRAM memory devices.

[0067] Moreover, according to one embodiment of the present disclosure, at least one dummy row 300 is associated with each block 160 of the memory sub-array 120.

[0068] This dummy row 300 is located inside or outside the address space of the memory array 90 and is used for read, write and erase parameter optimization.

[0069] Moreover, this dummy row is used for erase robustness monitoring, for the smooth completion of the modification operation and for other purposes.

[0070] According to another embodiment, the dummy row of a block 160 is provided in another block of the memory sub-array 120; this can allow keeping a single dummy row updated for a plurality of memory blocks that can be subjected to the same environmental change conditions.

[0071] The skilled person can appreciate that such dummy row can also be in a dedicated portion of the memory array (for example, not in a sub-array coupled to the SoC). Moreover, if the content of this "external" row is invalid, it must be updated, for example rewritten, and therefore erased, but such operation implies the erasing of the entire block in which such "external" row is located in a NAND memory.

[0072] The dummy row 300 can contain information suitable for tracking parameters that can be used during the read and erase phases of the memory component 100 and / or to store some parameters for finding a possible occurrence of a power loss.

[0073] The dummy row 300 contains a pattern known by the controller 101 of the memory device 100.

[0074] It is assumed that in the dummy row 300 a known pattern value in hexadecimal form is recorded, such as 0x55 or 0xAA. This value is very suitable for the reason that it contains the same amount of "0" logical values and "1" logical values stored in two distinct flash memory cells having two different thresholds inside the array.

[0075] In another embodiment, the above well-known pattern is not limited to a value in hexadecimal form such as 0x55 or 0xAA, for example, but also contains an update of the erase parameters, for example: the amplitude / number of the step pulses and / or the update of the erase / wear-out check levels.

[0076] In any case, since those values are also known a priori by the memory controller, the system will perform some read cycles changing the read trim parameter up to the moment when said values will be read correctly. The changed trim parameter read correctly will correspond to the set temperature value recorded in the programmable register. In the case of a multi-level cell memory (N levels), it is possible to select that the value to be stored overwrites all N levels present in the memory array. For example, the known pattern can contain cells programmed in all available levels of the multi-level cell memory device.

[0077] Only when the trim parameter set for the read phase allows the retrieval of the correct known value completely, then the read phase of the other memory blocks of the subarray 120 can be performed.

[0078] In one embodiment of the present disclosure, the output of the generic subarray 120 is formed by an extended page combining data cells, address cells and ECC cells. In this example, the total bit amount will involve 168 pads per channel, as Figure 5 shown.

[0079] The combined string of data cells + address cells + ECC cells allows the implementation of a complete safety coverage of the bus according to the standard requirements of the regulation ISO 26262, for the reason that the ECC covers the entire bus communication (data cells + address cells), while the presence of the address cells provides the confidence that the data is coming from the addressed location of the controller accurately.

[0080] Furthermore, each memory subarray 120 is structured in memory blocks 160. The memory block architecture comprising each location of the memory array can be defined as an extended page 150. The extended page is a 128-bit I / O required by the SoC and a 16-bit ECC involving 24-bit addressing (up to 2Gbit of available space).

[0081] An illustration of the sense amplifier SA through the output of the modified JTAG cell 140 is shown in Figure 5 where it can be appreciated that, as a non-limiting example, the composition of the extended page 150 has 168 bits.

[0082] In other words, the 128-bit atomic page used for padding the communication channel with the SoC device 10 has been enlarged in the present implementation to contain the stored address and the ECC forming a 168-bit extended page in each sub-array 120. Two extended pages 150 form a "super-page".

[0083] Each memory block 160 contains 256 rows and each row 135 contains sixteen extended pages of the above size. Each super-page contains two 168 bits as a combination of data bits, addressing bits and ECC bits. Thus, each row 135 of the memory array 90 can contain up to eight double pages of 128 bits each, plus the address and ECC correction sub- spare bits for each page.

[0084] For the sake of numbers only, the extended page is formed by 128+16+24=168 bits and each row 135 of sixteen extended pages respectively comprises 168*16=2688 bits.

[0085] Thus, each row 150 of the memory block 160 contains at least sixteen pages comprising a memory word plus corresponding address bits and corresponding ECC bits. Obviously, another size can be chosen and the reported values are only for the sake of illustration of a non-limiting example. The final result of the block is directly driven to the host device or SoC 10 without the need to use high power output buffers and without the need to optimize the path.

[0086] According to the present disclosure, the memory component 100 itself, using the stored reference, can detect the temperature and aging drifts affecting the memory array 90.

[0087] By using the well-known drift information of the stored pattern, it is possible to set the optimal parameters that will be used on the next erase operation. In particular, such information can be used to properly trim all the voltage values and timings (i.e. signal shapes) that will be used in each phase of the erase algorithm.

[0088] In general, the correct voltage levels and timings to be used in each erase phase must follow technical guidelines. Such guidelines are provided by flash cell technologists as a mapping between the degree of aging and the associated voltage values / timings to be used. According to such guidelines, a number of well-known or predefined parameters can be defined a priori for a given technology and stored in the die. For example, such parameters can be further adjusted during the electrical testing of the die to account for process variations.

[0089] In another embodiment of the present disclosure, the adjusted or unadjusted parameters and / or known patterns can be stored in the dummy row 300 during electrical wafer sorting or at electrical testing in some embodiments, and / or updated during the field operating lifetime, e.g. after a correct completion of an erase operation.

[0090] Now let's see the erase procedure according to this method:

[0091] The well known pattern is read from dummy row 300 and processed by the internal controller in order to determine the best parameters to be used in the next steps. The erase algorithm can then start.

[0092] If a power loss occurs during the precedent erase operation, the parameters can not be present in dummy row 300. This event has to be recovered by erasing the whole block. Otherwise, the block cannot be programmed or read correctly. The absence of parameters in the dummy row can be confirmed by a mismatch between the pattern (also present in dummy row 300 as will be explained in more details later) and the expected known pattern.

[0093] Under normal operating conditions, a pre-programming phase, also called programming allO, is usually provided for erasing this kind of memory device.

[0094] Normally, before starting the erase phase, the threshold of the cells to be erased is moved towards the programmed state. This is done by issuing some blind (i.e. no verify) program pulses.

[0095] By this procedure, the number of pre-programming pulses to be issued and / or the voltage to be used are determined according to the previous read step of the dummy row.

[0096] During the erase pulse phase, the voltage and pulse duration can be set to quickly and safely erase the cells in the block (according to the previous erase phase).

[0097] If the block is cycled (a number of program-erase cycles estimated by using the drift information), some appropriate strong voltage and pulse duration are used. Normally, the block is erased by applying a number of different erase pulses (negative for the gate voltage and / or positive for the body-source). This sequence can be called a ladder.

[0098] Once the erase pulses are issued (as described above), the erase cell state is verified by applying the appropriate cell gate voltage value that will be used to perform the erase verify, in order to guarantee a good erased cell distribution with enough margin.

[0099] In other words, the first step #1 is based on the erase pulses in the ladder, while the second step #2 is based on the erase verify. The drift information can be used to select the right erase verify value.

[0100] For example, Figure 6A schematic showing the threshold voltage distribution of cells that are correctly erased / programmed (1 bit / cell). All cell threshold groups are correctly enclosed within the assigned boundaries (i.e. programmed '0' with threshold voltage higher than the reference program verify level PV, or erased '1' with threshold voltage between the wear verify DV reference value and the erase verify level EV reference voltage). Steps #1 and #2 (erase pulse and erase verify) are repeated until all cells meet the erase verify criteria.

[0101] Once all cells are correctly (erased) verified, it is also checked if there are cells with too low threshold. In Figure 6 this is shown by the label wear verify DV.

[0102] In case of wear-out, a soft program operation is issued on the needed cells. The parameters to be used to perform the soft drift of the cells in order to correctly place the threshold inside the erased cell distribution can be selected according to the aging degree of the cells.

[0103] A wrong selection of such parameters can cause a bad placement of the threshold of the cells outside the erased distribution (higher than the erase verify value) and this would imply that the block has to be erased again from the above step #1 of providing the erase pulse (which is time consuming).

[0104] Once the erase is completed (phase above is finished), the well known patterns or even erase parameters (i.e. ladder pulse amplitude / number and / or erase / wear verify levels, etc.) to be used for the next erase cycle are written in row 300. In particular, by using appropriate program pulses (whose voltage and timing depend on the current aging degree of the block), the program and verify the selected pattern (e.g. threshold voltage higher than Figure 6 the program verify level PV in).

[0105] By using the drift information provided in the erase phase (step #1 above) and the number of erase pulses, it is possible to infer that the block is close to its end of life.

[0106] This information can be used as a warning to the customer or as a flag for an internal algorithm in order to trigger possible block wear leveling or On Field Block Redundancy (OFBR) operations when implemented. OFBR consists in replacing a block with a spare block.

[0107] For a better understanding of the present disclosure, it can be appreciated that it is a common practice to use a block wear leveling feature as a method to improve the reliability of the stored information, also in NOR memories. This method consists in spreading a number of program / erase cycles over all the blocks in the memory array.

[0108] This permits blocks to age consistently, to avoid the phenomenon of some blocks being newer (less used) while others are used frequently (many cycles).

[0109] If a host device overuses one block, then this block is internally (automatically) swapped for a less used block.

[0110] Within the device, there is a non-volatile mapping between physical block addresses and logical block addresses (used by the host). Initially, in such a mapping, the physical and logical addresses can be consistent, for example:

[0111] Physical block address | Logical block address, for example:

[0112] 0x1000 | 0x1000

[0113] 0x3000 | 0x3000

[0114] and so on for all blocks.

[0115] If a host device wants to use the block at address 0x3000, then the device can recover the physical address in such a mapping and work internally at the physical address.

[0116] Once a block is detected to be overused ("cycled"), this block can be "swapped" for a less used block. In practice, the above mapping is updated this way, for example:

[0117] Physical block address | Logical block address

[0118] 0x1000 | 0x1000

[0119] 0x6000 (newer block, or less aged block) | 0x3000

[0120] 0x3000 (aged block) | 0x6000 (newer)

[0121] Now starting from the context in which the host device is referring to block 0x3000, internally, the choice provides for the use of block 0x6000 and vice versa (swapped). Repeating this mechanism permits balancing the number of erasures / programmings among the different blocks on the entire array.

[0122] In known solutions, this method is based on the counting of the number of erase cycles that actually exist on each block; however, the drawback is the need for a non-volatile counter for each block, which would increase the cost of the device.

[0123] Instead, the solution proposed by the present disclosure is based on real block aging, which takes into account not only the number of program-erase cycles, but also other possible stress conditions such as temperature cycling. In another perspective, the method disclosed herein is based on real measurements of aging, not on potential aging estimations.

[0124] Once the device is manufactured, a number of bits 0 / 1 are stored in the dummy row 300 as a well-known pattern. Possible examples of well-known patterns are hexadecimal values such as 0x55 or 0xAA. Figure 4

[0125] The bits representing those values do not need to be necessarily the same as the other bits used on the other patent groups; for example, different dummy rows can be used for different features.

[0126] Those bits are used as a measure of aging.

[0127] Figure 7 A diagram corresponding to Figure 6 is shown, but the enlarged distribution due to aging, temperature and / or stress is reported. Under aging, temperature and / or stress, the threshold voltage distribution tends to enlarge, e.g. to widen, and to drift. According to the method of the present disclosure, it is possible to track the distribution enlargement and the cell degradation and to use this information to correct the following erase pulses. This permits to improve the reliability and performance of the erase phase.

[0128] The trimming sequence to perform the read phase of the memory array at different temperatures or different aging of the memory device can be defined in the laboratory during the technology development phase and / or product testing and stored in programmable registers of the memory controller 101.

[0129] According to the present invention, the adjustment of the parameters used during the erase phase can be performed in a similar way during the field operation.

[0130] The real temperature value at which the read phase is performed is not important for the correct reading of the content. Such temperature can be higher (even much higher) or lower than the temperature at which the program phase of known values is performed.

[0131] The system is automatically protected from any thermal drift, since the read trimming parameters are selected only after a correct read of the known pattern stored in the dummy row 300 has been performed and the trimming parameters for the subsequent data read have been set accordingly.

[0132] ​The program allows to identify more appropriate read trim parameters for the correct reading phase at a specific temperature value. It is not necessary to repeat such a program at each reading phase or access. On the contrary, such a program can be performed periodically (for example after a predefined duration has elapsed, or based on a triggering event, for example the detection of a temperature change) or in a more appropriate manner (for example with the ECC bits increased in an exceptional manner) when a possible problem is detected.

[0133] The following can happen: the number of ECC bits increased reports an excessive error reading from the memory device. In such a case, the system can automatically start detecting a possible thermal drift and then needs to change the program of the trim parameters. It should be noted that the disclosed solution is not limited to compensate for temperature variations, but can also take into account durability (for example, high cycle) effects and other possible sources of errors.

[0134] The dummy row 300 can also be used as an indication of possible failure for the erase operation.

[0135] The method of the disclosure allows to properly check the status of the memory component 100, or better still, the status of the memory block 160.

[0136] One embodiment of the disclosure relates to a method for monitoring the performance or status of a non-volatile memory device, said non-volatile memory device comprising at least one array of memory cells and having associated decoding and sensing circuitry and a memory controller, said method comprising:

[0137] - storing at least an internal block variable of a known pattern in a dummy row associated with said memory block;

[0138] - performing a read of at least said dummy row;

[0139] - comparing the read result with the known pattern;

[0140] - swapping the memory block used according to the comparison result.

[0141] The read of the dummy row can be performed on a memory device isolated from the external environment.

[0142] The stages of the method 800 for monitoring the performance or status of a memory device according to the disclosure are schematically illustrated in the example of Figure 8 The first stage 810 is dedicated to storing at least an internal block variable of a read operation in a dummy row 300. This first storage stage is performed when the memory device is manufactured. Such a storage stage can be repeated during the device field operation to update the internal block variable.

[0143] In another method stage 820, a read stage of the dummy row 300 of at least one memory block 160 is performed.

[0144] Subsequently, in a later stage 830, the pattern read from the dummy row 300 is compared with a known (to the memory controller) pattern.

[0145] Based on said comparison, in case there is a significant discrepancy between the known expected parameters and the read results, the memory block can be swapped or shifted. This is verified in step 840.

[0146] The content of the dummy row 300 also contains at least a known pattern, which means the previously mentioned known hexadecimal value. As an alternative, examples of known patterns are the following: 0x0, 0x1, 0x2,..., 0xF, or any other sequence involving a number of bits set to zero and a similar number set to one, for example: 0x55, 0xAA, 0x33, etc. As previously mentioned, in case the multi-level cells store more than a single bit in one physical cell, the corresponding known pattern should be chosen to take into account the correct detection of all possible threshold voltage levels.

[0147] The content of the dummy row 300 can also contain parameters for the read stage, but also parameters used during the erase stage of the block, for example: erase pulse, target voltage, etc.

[0148] Furthermore, periodically, for example at the request of the host, or automatically at power-up, or at each erase command, etc., the status of such well-known patterns is checked by performing a read operation (like a program verify) with an appropriate (variable) gate voltage Vgate.

[0149] Such operation serves to determine the less programmed bits in the programmed well-known initial pattern (PV_worst in Figure 7 In fact, after aging and / or at different temperature conditions, the actual threshold voltage of the memory cells can vary with respect to the original value; by knowing the pattern (for example, the stored logical value), it is possible to trim the read voltage until the correct read.

[0150] Such information (amount of drift of the threshold voltage distribution towards lower voltages, for example the dashed distribution in Figure 7 with respect to the initial threshold voltage distribution, for example the solid distribution in Figure 7 is used to estimate the aging degree of the block (due to its usage, temperature cycles, etc.) from a map associated with the technology parameters.

[0151] The degree of aging is used as a criterion to decide which blocks must be swapped with which blocks (newer blocks, as is customary in the art). This replacement can be done either at the request of the host or automatically (e.g. hidden on the next erase command issued). For example, when the difference between the initial program verify level and the worst program verify level exceeds a predefined threshold, a swap or replacement can be triggered.

[0152] Reference is now made to how an erase operation is performed according to the method of the present disclosure.

[0153] Importantly, at each block erase operation, the aging information will be reprogrammed on the row 300 group at the end of the algorithm.

[0154] Before starting a block erase, the PV_worst value (i.e. the voltage threshold of the worst programmed cell) is determined and stored in a non-volatile location (backup area) to avoid losing it in case of incomplete erase.

[0155] Once the erase algorithm or any other conventional procedure is completed, the well-known pattern is reprogrammed (on the dummy 300 row) but its distribution is placed around the PV_worst value determined above, which takes into account the current degree of aging.

[0156] The backup area is cleared so that it can be used for future erases.

[0157] In case of incomplete erase, such values are recovered from the backup area and, once the incomplete erase condition is recovered by resuming the erase (either automatically or upon a host command), such values are stored in the dummy row 300 of Figure 4 or in an alternative memory dummy area of another block, as previously disclosed.

[0158] In this regard, as non-volatile, either a block dedicated to this purpose can be used or any other location providing non-volatile registers in the memory device can be used.

[0159] A preliminary step of the read algorithm is to invalidate (e.g. flag, overwrite or delete anyway) the content of the dummy row for storing the new read variables in the dummy row 300 at the end of the read phase.

[0160] The content of the dummy row 300 comprises at least internal block variables, by which is meant parameters used during the read phase of the block, such as: read pulse, target voltage, etc.

[0161] Furthermore, the content of the dummy row 300 also comprises at least a known pattern, by which is meant the known hexadecimal value mentioned previously. As an alternative, examples of known patterns are the following: 0x0, 0x1, 0x2,..., 0xF.

[0162] The method of the present disclosure enables the execution of a read algorithm using specific parameters. In other words, before starting a read algorithm on a memory block 160, the internal block variables of a previous read phase are retrieved from the dummy row 300.

[0163] The completion of the read algorithm is manifested by the storage of the erase key parameter and the known pattern.

[0164] In fact, the storage of the key parameter can provide feedback on the health of the block and also determine the way wear leveling must be applied to the blocks 160 of the subarray 120.

[0165] The presence of the known pattern at the end of the dummy row ensures the correctness of the read operation.

[0166] The method of the present disclosure allows to obtain a periodic check of the state of the memory device and possibly to shift the use of the memory block in case of problems due to the aging of the block itself, since it is possible to obtain a safe feedback of the correctness of the read or erase operation even in different operating environmental conditions.

[0167] The architecture and method of the present disclosure make it possible to follow any drift due to the aging of the memory device and / or the system to which the memory device or the memory device is coupled. It also compensates for correct reading in different temperature conditions.

[0168] Moreover, the system is programmable and updatable, since it is possible to delete and reprogram the dummy row 300 in which the known values are recorded according to the needs, even according to the environmental changes of the memory device.

[0169] While specific embodiments have been shown and described in the present disclosure, it will be understood by those skilled in the art that other arrangements can be devised to implement the same results. The present disclosure is intended to cover modifications or variations in various embodiments of the present disclosure. It should be understood that the above description is illustrative, but not restrictive. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims, along with their full scope of equivalents, and not limited to the embodiments described above.

Claims

1. A non-volatile memory device comprising a memory cell array and associated decoding and sensing circuitry and a memory controller, wherein the memory cell array comprises: - Multiple subarrays; - Multiple memory blocks in each subarray; as well as - A dummy line for each corresponding block, the dummy line being used to store internal block variables and a first known pattern during the read phase, wherein each corresponding dummy line experiences the same drift attributed to temperature and aging of the non-volatile memory device, and wherein the memory controller is configured to: Determine the voltage threshold of the worst-case programming cell in which the first known pattern is stored in at least one corresponding dummy row; and A second known pattern is written into the at least one corresponding dummy line, wherein the second known pattern includes information about the voltage distribution corresponding to the voltage threshold placed around the worst programming cell storing the first known pattern.

2. The non-volatile memory device according to claim 1, wherein the first known mode and the second known mode are further stored in the memory controller.

3. The non-volatile memory device of claim 1, wherein the internal block variables include parameters used during the read phase.

4. The non-volatile memory device of claim 1, wherein the internal block variable includes a read pulse, a target voltage, or both the read pulse and the target voltage applied during the read phase.

5. The non-volatile memory device according to claim 1, configured as follows: Retrieve the internal block variable from the previous read phase from the dummy row; and Another read phase of the memory block is initiated, at least in part, based on the internal block variables of the previous read phase.

6. The non-volatile memory device of claim 1, wherein the dummy row is disposed in another block of the memory subarray.

7. The non-volatile memory device of claim 1, wherein each memory block comprises at least 256 rows of memory cells.

8. The non-volatile memory device of claim 7, wherein each row comprises at least sixteen extended pages, each extended page being formed by a combination of data bits, address bits, and error correction code (ECC) bits of a memory location.

9. A memory system comprising: - Main unit; - A non-volatile memory device coupled to the host device and including at least one memory cell array with associated decoding and sensing circuitry and a memory controller; - Multiple subarrays in the memory cell array; - Multiple memory blocks in each subarray; as well as - A dummy line for each corresponding block, the dummy line being used to store at least internal block variables and at least a first known pattern during the read phase, wherein each corresponding dummy line is not in one of the plurality of subarrays but experiences the same drift attributable to temperature and aging of the non-volatile memory device, wherein the memory controller is configured to: Determine the voltage threshold of the worst-case programming cell in which the first known pattern is stored in at least one corresponding dummy row; and A second known pattern is written into the at least one corresponding dummy line, wherein the second known pattern includes information about the voltage distribution around the voltage threshold corresponding to the worst programming unit placed in the first known pattern.

10. The system of claim 9, wherein the first known mode and the second known mode are stored in the memory controller.

11. The system of claim 9, wherein the internal block variable includes parameters used during the read phase.

12. The system of claim 9, wherein the internal block variable includes a read pulse and / or a target voltage applied to the memory block during the read phase.

13. The system of claim 9, wherein the non-volatile memory device is configured to retrieve an internal block variable from the dummy line of the previous read phase and to begin a subsequent read phase on the memory block based at least in part on the internal block variable of the previous read phase.

14. The system according to claim 9, wherein: Each memory block contains at least 256 rows of memory cells; and Each row contains at least sixteen extended pages, each of which is formed by a combination of data bits, address bits, and error correction code (ECC) bits in its own memory location.

15. The system of claim 9, wherein the read phase of the dummy row is performed on the memory device isolated from the external environment.

16. A method for checking the state of a non-volatile memory device, the non-volatile memory device comprising an array of memory cells having memory blocks and having associated decoding and sensing circuitry and a memory controller, the method comprising: - Store at least the internal block variables and the first known pattern in a dummy row, which is not in one of the multiple subarrays of the memory cell array, but is physically implemented close to each corresponding block, such that each corresponding dummy row experiences the same drift attributable to the temperature and aging of the non-volatile memory device. - Perform at least the reading of the dummy rows; - Compare the result of the reading with a copy of the first known pattern; - Determine the voltage threshold of the worst-case programming cell that stores the first known pattern in at least one corresponding dummy row; - Write a second known pattern into the at least one corresponding dummy line, wherein the second known pattern includes information about the voltage distribution around the voltage threshold corresponding to the worst-case programming cell placed in the first known pattern; and - Based on the results of the comparison, the memory blocks used are swapped.

17. The method of claim 16, further comprising periodically updating the contents of the dummy row.

18. The method of claim 17, wherein periodically updating the contents of the dummy row comprises storing new internal block variables in the dummy row, the new internal block variables comprising a read pulse, a target voltage, or both the read pulse and the target voltage applied to the memory block during the read.

19. The method of claim 16, further comprising retrieving the previously erased internal block variable from the dummy row and initiating a read on a memory block different from the memory block used.

20. The method of claim 16, further comprising obtaining an indication of the health of the memory block at least in part based on the comparison.

21. The method of claim 16, wherein the storage includes storing the at least internal block variables and the known schema in the dummy row during the manufacturing stage of the memory device.

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