Preventing bridging between solder joints

Abstract

A method of manufacturing a connection structure is disclosed. The method includes providing a substrate having a top surface and including a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to portions of the top surface of the substrate proximate the pads and to the pad surfaces of each pad to make at least a portion of the top surface of the pads and the pad surfaces rougher.

Description

BACKGROUND

[0001] The present invention relates generally to techniques for soldering, and more particularly, to a method of manufacturing a connection structure, a connection structure, and an electronic device.

[0002] In response to the increasing demand for broadband signal transmission between chips, fine pitch interconnections using lead-free solder have been developed to enhance the performance of electronic devices. As the pitch width of the interconnections becomes finer, bridging across adjacent solder joints has become one of the major defects in various assembly techniques, including BGA (ball grid array), QFP (quad flat package), flip chip, etc. SUMMARY

[0003] According to an embodiment of the present invention, a method of manufacturing a connection structure is provided. The method includes providing a substrate having a top surface and including a set of pads for soldering, wherein each pad has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to at least a portion of the top surface of the substrate proximate to the pads and to the pad surface of each pad to make at least a portion of the top surface of the pads and the pad surface rougher.

[0004] The connection structure manufactured by the method provided by the embodiments of the present invention can prevent the solder joints formed on adjacent pads from bridging during soldering. The surface treatment is applied to enhance the roughness of the surfaces, to improve the wettability of the pad surfaces of the pads and the de-wettability of the top surface of the substrate with respect to molten solder. Thus, the reliability of the solder joints can be improved even if the pitch between the solder joints becomes finer. In addition, the production cost of the connection structure can be reduced and the production yield can be improved, and thus, the electronic device including the connection structure can be improved.

[0005] In preferred embodiments, the top surface of the substrate has a low wettability and the pad surface of each pad has a high wettability with respect to molten solder. The application of the surface treatment changes the different wettability characteristics of the exposed surfaces in respective directions of enhancement. The top surface of the substrate having a low wettability becomes more non-wettable, while the pad surface having a high wettability becomes more wettable.

[0006] In specific embodiments, at least a portion of the top surface of the substrate after the surface treatment is applied has a roughness parameter (Ra) greater than 0.4 μm and less than 2 μm.

[0007] In particular embodiments, the pads include a metallic material and at least a portion of the top surface proximate to the pads includes an organic material. In further specific embodiments, the portion including the organic material is provided from a group including an organic substrate, a dielectric layer disposed on the substrate, a solder resist layer disposed on the substrate, an adhesive disposed on the substrate, and combinations thereof.

[0008] In preferred embodiments, the surface treatment includes sandblasting. Sandblasting mechanically and physically changes the exposed surface without significantly changing the chemical surface conditions. Furthermore, by using appropriate abrasive particles, the roughness of the pad surface of the pads and the portion of the top surface of the substrate can be controlled more precisely with a wider control range.

[0009] In particular embodiments, the method further includes forming a set of solder joints, each solder joint disposed on a corresponding one of the pads.

[0010] In preferred embodiments, forming the set of solder joints includes applying solder to the pad surface of the pads and to at least a portion of the top surface of the substrate that has been applied with the surface treatment. Forming the set of solder joints further includes heating the solder to form the set of solder joints. The pad surface of the pads surrounded by the portion of the top surface of the substrate that has been applied with the surface treatment is suitable for a soldering process, wherein the applied solder is heated to complete the solder joint.

[0011] In preferred embodiments, the substrate further includes an interconnect layer disposed on the substrate, the interconnect layer having a set of side connection pads positioned proximate to an edge of the set of pads and including a set of side connection pads located at and exposed at the edge of the interconnect layer, each side connection pad disposed relative to a corresponding pad disposed on the substrate. The introduction of the new side connection improves the routing flexibility with the interconnect layer routing. Thus, the performance of an electronic device using the interconnect structure can be improved since the routing can be optimized according to the improved routing flexibility. Furthermore, it relaxes the restriction on the terminal layout of the chip using the interconnect layer. Since the side connection bridge formed on the adjacent pads can be prevented, the yield and reliability of such electronic device is improved.

[0012] In preferred embodiments, each side connection pad has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at the edge of the interconnect layer, wherein the edge surface faces the corresponding one of the pads. Thus, since both the edge surface and the top surface are involved in the side connection to increase the contact area, the reliability and manufacturing yield of the side connection can be improved.

[0013] In particular embodiments, the method further includes forming a set of solder joints to connect the side connection pads of the interconnect layer with the pads disposed on the substrate, respectively.

[0014] According to other embodiments of the present invention, a method of manufacturing a connection structure is provided. The method includes providing a substrate having a top surface and including a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate. The top surface of the substrate has at least a portion proximate to the pads that has been applied with a surface treatment that increases the surface roughness. The pad surface of each pad has at least a portion that has been applied with the surface treatment. The method further includes forming a set of solder joints, each solder joint disposed on a corresponding one of the pads.

[0015] The connection structure manufactured by the method according to the embodiment of the present application can prevent the bridging of the solder joints formed on the adjacent pads at the time of soldering. The application of the surface treatment that enhances the surface roughness improves the wettability of the pad surface of the pad and the de-wettability of the top surface of the substrate with respect to the molten solder. Thus, the reliability of the solder joint can be improved even if the pitch between the solder joints becomes finer. In addition, the manufacturing cost can be reduced and the production yield of the connection structure and the electronic device including the connection structure can be improved.

[0016] According to another embodiment of the present application, there is provided a connection structure including a substrate having a top surface and a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate. In the connection structure, a portion of the top surface near the pads is rougher than other portions of the top surface, and the pad surface of each pad is rougher than exposed surfaces of other conductive materials formed on the substrate.

[0017] According to another embodiment of the present application, there is provided a connection structure including a substrate having a top surface and a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate. In the connection structure, at least a portion of the top surface of the substrate is subjected to a surface treatment that enhances the surface roughness. In addition, each pad has at least a portion of the pad surface to which the surface treatment has been applied.

[0018] The connection structure according to the embodiment of the present application can prevent the bridging of the solder joints formed on the adjacent pads at the time of soldering. The treatment of the surface treatment that enhances the surface roughness improves the wettability of the pad surface of the pad and the de-wettability of the top surface of the substrate with respect to the molten solder. Thus, the reliability of the solder joint can be improved even if the pitch between the solder joints becomes finer.

[0019] According to another embodiment of the present application, there is provided an electronic device including a substrate having a top surface and a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate. In the electronic device, the substrate has a portion of the top surface to which a surface treatment that enhances the surface roughness has been applied, and each pad has a portion of the pad surface to which the surface treatment has been applied.

[0020] The electronic device according to the embodiment of the present application can improve the reliability with respect to the solder joints formed on the adjacent pads. The application of the surface treatment that enhances the surface roughness improves the wettability of the pad surface of the pad and the de-wettability of the top surface of the substrate with respect to the molten solder. Thus, the reliability of the solder joint can be improved even if the pitch between the solder joints becomes finer.

[0021] In a particular embodiment, the electronic device comprises a set of soldering points, each soldering point being disposed on a corresponding one of the pads, and one or more electronic components mounted on the substrate. Each electronic component uses at least one soldering point.

[0022] Additional features and advantages are realized through the techniques of the present application. Other embodiments and aspects of the application are described in detail herein and are considered a part of the claimed application. BRIEF DESCRIPTION OF DRAWINGS

[0023] What is being claimed as being subject matter of the present application is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features and advantages of the application are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

[0024] Figure 1A A schematic view of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0025] Figure 1B A schematic view of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0026] Figure 2 A schematic view of an interconnection layer carrying structure for transferring an interconnection layer onto a target substrate according to an exemplary embodiment of the application is shown.

[0027] Figure 3A A cross-sectional view of a structure obtained during a manufacturing process of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0028] Figure 3B A cross-sectional view of a structure obtained during a manufacturing process of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0029] Figure 3C A cross-sectional view of a structure obtained during a manufacturing process of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0030] Figure 4A A cross-sectional view of a structure obtained during a manufacturing process of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0031] Figure 4B A cross-sectional view of a structure obtained during a manufacturing process of an interconnection substrate according to an exemplary embodiment of the application is shown.

[0032] Figure 4CA cross-sectional view of a structure obtained when forming a solder joint during the manufacturing process of an interconnection substrate according to an exemplary embodiment of the present application is shown.

[0033] Figure 5A A cross-sectional view of a structure obtained when forming a solder joint during the manufacturing process of an interconnection substrate according to an exemplary embodiment of the present application is shown.

[0034] Figure 5B A cross-sectional view of a structure obtained when forming a solder joint during the manufacturing process of an interconnection substrate according to an exemplary embodiment of the present application is shown.

[0035] Figure 5C A cross-sectional view of a structure obtained when forming a solder joint during the manufacturing process of an interconnection substrate according to an exemplary embodiment of the present application is shown.

[0036] Figure 6 A schematic view of a surface treatment for enhancing surface roughness according to an exemplary embodiment of the present application is described.

[0037] Figure 7A A schematic view of a solder joint expected to be formed on a side connection pad and a conductive pad, respectively, without a surface treatment for enhancing surface roughness and with a surface treatment for enhancing surface roughness according to an exemplary embodiment of the present application is described.

[0038] Figure 7B A schematic view of a solder joint expected to be formed on a side connection pad and a conductive pad, respectively, without a surface treatment for enhancing surface roughness and with a surface treatment for enhancing surface roughness according to an exemplary embodiment of the present application is described.

[0039] Figure 8A A contact angle measured under various conditions is shown.

[0040] Figure 8B A contact angle measured under various conditions is shown.

[0041] Figure 8C A contact angle measured under various conditions is shown.

[0042] Figure 8D A contact angle measured under various conditions is shown.

[0043] Figure 8E A contact angle measured under various conditions is shown.

[0044] Figure 8F A contact angle measured under various conditions is shown.

[0045] Figure 9A A graph of roughness parameters (Ra, Rq) versus surface conditions is shown.

[0046] Figure 9B A graph showing roughness parameters (Ra, Rq) versus surface conditions is shown.

[0047] Figure 10A A top view and a cross-sectional view of a modeling structure for a computational fluid dynamics simulation are shown, respectively.

[0048] Figure 10B A top view and a cross-sectional view of a modeling structure for a computational fluid dynamics simulation are shown, respectively.

[0049] Figure 11A Simulation results performed at various contact angles of the surface of the resin part in the modeling structure shown in FIG. 10 are shown.

[0050] Figure 11B Simulation results performed at various contact angles of the surface of the resin part in the modeling structure shown in FIG. 10 are shown.

[0051] Figure 11C Simulation results performed at various contact angles of the surface of the resin part in the modeling structure shown in FIG. 10 are shown.

[0052] Figure 12 A cross-sectional view of an electronic device around an interconnection layer according to an exemplary embodiment of the present application is shown.

[0053] Figure 13A A cross-sectional view of a structure obtained during the manufacturing process of an electronic device according to an exemplary embodiment of the present application is shown.

[0054] Figure 13B A cross-sectional view of a structure obtained during the manufacturing process of an electronic device according to an exemplary embodiment of the present application is shown.

[0055] Figure 13C A cross-sectional view of a structure obtained during the manufacturing process of an electronic device according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] Hereinafter, the present application will be described with reference to the specific embodiments, but those skilled in the art will understand that the following described embodiments are mentioned only as examples and are not intended to limit the scope of the present application. When referring to the drawings, like reference numerals refer to like elements throughout the description of the drawings. Figures 1A-13C When describing embodiments, a plurality of identical elements can be designated by a common reference numeral, while each individual element of the plurality of identical elements can be designated by an individual index reference numeral added to the common reference numeral, for example, Figure 1A The plurality of bonding pads shown in FIG. 1 are collectively referred to by reference numeral 112 and each individual bonding pad is referred to by reference numerals 112-1 and 112-2.

[0057] One or more embodiments according to the present application relate to a connection structure, an electronic device including the connection structure, a method of manufacturing the connection structure, wherein a pad surface for soldering and a portion of a substrate surface close to the pad surface are subjected to a surface treatment for enhancing surface roughness to improve wettability of the pad surface for molten solder and dewettability of the portion of the substrate surface for molten solder.

[0058] Hereinafter, referring to Figure 1A and Figure 1B , a schematic view of an interconnection structure before mounting of a chip according to an exemplary embodiment of the present application is described.

[0059] Figure 1A and Figure 1B a schematic view of an interconnection substrate 100 for interconnecting a chip mounted thereon is shown. The wiring substrate 100 corresponds to a connection structure after soldering. Figure 1A and Figure 1B respectively show a cross-sectional view and a top view of the interconnection substrate 100. It is to be noted that the cross-sectional view shown in Figure 1A corresponds to the cross-section indicated by "X" in the top view of Figure 1B .

[0060] As shown in Figure 1A , the interconnection substrate 100 includes an organic base substrate 110, a plurality of bond pads 112 formed on the organic base substrate 110 for chip bonding, a set of conductive pads 114 formed on the organic base substrate 110 for side connection, and an interconnection layer 130 disposed on the organic base substrate 110.

[0061] The organic base substrate 110 can be a build-up substrate having a core (e.g., a glass epoxy core) and an appropriate number of wiring layers (with inter-layer dielectric) and can be manufactured by any standard build-up process. The bond pads 112 and the conductive pads 114 can be the outermost layers of the build-up substrate. Each bond pad 112 is connected to a signal line via a write-in in the organic base substrate 110. Each conductive pad 114 is connected to a power or ground line via a write-in in the organic base substrate 110, which can be used as a signal return current path, which is the path taken by current returning to the source. The bond pads 112, the conductive pads 114, and the wiring are made of any of a metal material (e.g., Cu, Al, etc.) and other conductive materials. In a specific embodiment, metallic copper can be used. It is noted that the internal structure inside the organic base substrate 110 is omitted from the drawings for illustration purposes. It is also noted that the organic base substrate 110 is used as the substrate in the described embodiments. However, an inorganic substrate such as a glass substrate can also be used as the substrate.

[0062] In a specific embodiment, the interconnection substrate 100 further includes a solder resist layer 116 formed on the organic base substrate 110. Each of the bond pads 112 can be covered by the solder resist layer 116 and exposed from the solder resist layer 116 through an opening formed therein. Each of the bond pads 112 can have a pre-solder 118 formed within the opening of the solder resist layer 116. Also, each of the conductive pads 114 can be partially covered by the solder resist layer 116 and exposed from the solder resist layer 116 at one edge close to the interconnection layer 130 disposed on the organic base substrate 110. The thickness of the pads 112, 114 can generally be in the range of 1 to 20 micrometers. The thickness of the solder resist layer 116 can be in the range of its sufficient film thickness and can generally be in the range of from 2 micrometers to 50 micrometers. It is noted that the solder resist layer 116, which can be an organic material, can serve as an insulating layer disposed on the organic base substrate. However, instead of using the solder resist layer 116, a dielectric layer of an insulating material other than a solder resist material, such as an inorganic insulating material, is also contemplated.

[0063] The plurality of bond pads 112 can be divided into a plurality of groups. One group of bond pads (hereinafter, referred to as a first group) 112-1 is positioned at a flip chip region (referred to as a first flip chip region) 110b-1 on the interconnection substrate 100. Other groups of bond pads (hereinafter, referred to as a second group) 112-2 are located at different flip chip regions (referred to as a second flip chip region) 110b-2 on the interconnection substrate 100. The second group of bond pads 112-2 can be located at a distance from the first group of bond pads 112-1. It is noted that the first flip chip region 110b-1 and the second flip chip region 110b-2 can be located at a distance from each other. Figure 1B The pre-solders 118-1, 118-2 formed on the bond pads 112-1, 112-2 are described in a top view of FIG. 1. The first flip chip region 110b-1 and the second flip chip region 110b-2 are regions where one chip (hereinafter, referred to as a first chip) and other chip (hereinafter, referred to as a second chip) are to be mounted after a subsequent chip mounting process.

[0064] The interconnection layer 130 is disposed on a top surface of the organic base substrate 110 and within a defined region 110a between the first and second groups of bond pads 112-1, 112-2. The defined region 110a where the interconnection layer 130 is disposed does not have a solder resist. The interconnection layer 130 can be precisely positioned at the defined region 110a and attached to the organic base substrate 110 by using appropriate alignment marks. It is noted that the defined region 110a of the interconnection layer 130 partially overlaps both the first flip chip region 110b-1 and the second flip chip region 110b-2. Further, the defined region 110a where the interconnection layer 130 is disposed can be recessed to adjust a level of a top surface of the interconnection layer 130 and a top surface of the solder resist layer 116.

[0065] The interconnect layer 130 is bonded to the top surface of the organic base substrate 110 by an adhesive 132. The adhesive 132 can use a paste or liquid type or a film type adhesive material.

[0066] Further referring to Figure 1A The structure of the interconnect layer 130 is described in further detail. The interconnect layer 130 includes an organic insulating material 134, a conductive pattern 136 embedded in the organic insulating material 134, and a plurality of pads 140, 141, and 142 exposed at a top surface 130a of the interconnect layer 130, which can be provided by the organic insulating material 134. The pads 140, 141, and 142 of the interconnect layer 130 are classified into two types. The first type is a side connection pad 140 for side connection, and the second type is a bonding pad 141, 142 for die bonding.

[0067] Note that, in the described embodiment, the organic insulating material 134 is used as the insulating material of the interconnect layer 130. The organic material is preferable for the case of using the organic base substrate 110 in order to mitigate the CTE mismatch between the interconnect layer 130 and the organic base substrate 110, which is commonly used as a package substrate. However, the insulating material is not limited to the organic material. In other embodiments, an inorganic insulating material can also be employed as the insulating material.

[0068] In the described embodiment, as representatively described for the first flip-chip region 110b-1, the interconnect layer 130 has edges El and E2, which are located close to a set of conductive pads 114-1 and 114-2 arranged on the organic base substrate 110. The set of side connection pads 140-1 is located and exposed at the edge El. Each side connection pad 140-1 is arranged with respect to a corresponding one of the conductive pads 114-1 disposed on the organic base substrate 110. When the set of conductive pads 114-1 is arranged in a row along one edge close to the interconnect layer 130 at a predetermined interval (e.g., pitch width), the set of side connection pads 140-1 is also arranged in a row along the edge El of the interconnect layer 130 at a predetermined interval (e.g., pitch width) matching the interval of the conductive pads 114-1. Although not particularly limited, in a particular embodiment, the side connection pads 140-1 and the conductive pads 114-1 have a one-to-one relationship.

[0069] Each side-connect pad 140 has a top surface TS exposed at the top surface 130a of the interconnect layer 130 and an edge surface ES exposed at one edge (e.g., E1 and E2) of the interconnect layer 130. The top surface TS is parallel to the top surface of the organic substrate 110, while the edge surface ES is perpendicular to the top surface of the organic substrate 110 and faces a corresponding conductive pad 114. In a preferred embodiment, the edge surface ES and / or the top surface TS of each side-connect pad 140 have a barrier metal layer. Examples of barrier metal layers include Au / Pd / Ni stacks and Au / Ni stacks (where the first element (e.g., Au in both cases) is at the top of the stack), Au layers, and Pd layers. Note that symbols such as Au, Pd, Ni, etc., denote the main element contained in each layer of the stack, which may contain small or trace amounts of other elements to form an alloy and / or small or trace amounts of additives due to the manufacturing process. It should also be noted that each of the bonding pads 112 and conductive pads 114 disposed on the organic substrate 110 may or may not have a similar barrier metal layer.

[0070] like Figure 1A and Figure 1B As shown, the interconnect substrate 100 may further include a set of solder points 119, each solder point connecting one side connection pad 140 of the interconnect layer 130 to a corresponding conductive pad 114 disposed on the organic substrate 110. Each solder point 119 contacts the exposed surface (upper surface TS and edge surface ES) of the side connection pad 140 and the conductive pad 114. It should be noted that in Figure 1B The top view also depicts solder joints 119-1 and 119-2 formed on conductive pads 114-1 and 114-2 and side connection pads 140-1 and 140-2. The symbol 'G' indicates ground, while the symbol 'P' indicates power.

[0071] In the described embodiments, pads 112, 114, and the substrate have respective surfaces (pad surfaces PS of conductive pads 114 and bonding pads 112, and substrate surfaces SS surrounding conductive pads 114 and bonding pads 112), which have undergone surface treatments to enhance surface roughness. In one or more embodiments, the surface treatment includes sandblasting and / or plasma treatment. Thus, conductive pad 114 has a pad surface PS that is exposed from the substrate surface SS and is rougher than the exposed surfaces of other untreated pads. Bonding pad 112 also has a pad surface PS that is exposed from the substrate surface SS and is rougher than the exposed surfaces of other untreated pads. Furthermore, a portion of the substrate surface SS near conductive pads 114 and bonding pads 112 is rougher than other portions of the substrate surface.

[0072] It is noted that the substrate surface SS is defined as the surface that includes the portion of the organic base substrate 110 that is the substrate body and the solder resist layer 116 formed on the substrate body. The substrate surface SS can at least partially include the upper surface of the solder resist layer 116, the upper surface of the organic base substrate 110 that is free of solder resist, the surface that is free of the interconnect layer and free of adhesive, and / or the adhesive 132.

[0073] The substrate surface SS can be provided by the organic material of the solder resist layer 116, the organic base substrate 110, and / or the adhesive 132, and has a low wettability for molten solder. The pad surface PS of each of the conductive pads 114 and the bond pads 112 has a high wettability for molten solder. It is noted that the term "low wettability" refers to a surface having a contact angle greater than 90 degrees (90° < Θ ≤ 180°), while the term "high wettability" refers to a surface having a contact angle less than 90 degrees (0 < Θ < 90°). It is further noted that the contact angle (Θ) is the angle at which a liquid-air interface meets a solid-liquid interface, where the liquid is molten solder and the solid is the conductive material of the pads 112, 114 or the organic material of the substrate, and provides a reverse measure of wettability.

[0074] In a specific embodiment, the roughness parameter (Ra) of the portion of the substrate surface SS after applying the surface treatment is greater than 0.4 μm and less than 2 μm, more preferably greater than 0.5 μm and less than 1 μm, where Ra represents the arithmetic average roughness, provided that the thickness of the solder resist layer after the surface treatment is sufficiently maintained. In terms of other roughness parameters, the portion of the substrate surface SS can have a roughness parameter (Rq) that is greater than 700 nm and less than 4 μm, more preferably greater than 0.8 μm and less than 2 μm, where Rq represents the root mean square roughness. The same applies to the pad surface PS.

[0075] It is further noted that each of the pads 140, 141, 142 of the interconnect layer 130 can also have a pad surface that is exposed from the top surface 130a of the interconnect layer 130 and is rougher than the exposed surface of other untreated pads that have not been subjected to a surface enhancement treatment. In addition, the portion of the top surface 130a of the interconnect layer 130 that is proximate to the pads 140, 141, 142 can be rougher than other portions of the interconnect layer 130 that have not been subjected to the surface treatment that enhances surface roughness.

[0076] In the described embodiment, as representatively described for the first flip-chip region 110b-1, the side connection pads 140-1, the conductive pads 114-1, and correspondingly the solder joints 119-1 are located within the flip-chip region 110b-1. This is equally applicable to the other flip-chip regions 110b-2. However, the location of the side connections (side connection pads 140, conductive pads 114, and solder joints 119) is not limited. In other embodiments, these side connections are placed at locations away from these flip-chip regions 110b, as these side connections are not directly involved in the die bonding.

[0077] Here, again focusing on the structure of the interconnect layer 130, the bond pads 141, 142 are exposed from the organic insulating material 134 at the top surface 130a of the interconnect layer 130. The bond pads 141, 142 of the interconnect layer 130 are used to mount the chips disposed thereon together with the bond pads 112 disposed on the organic base substrate 110. In the described embodiment, the bond pads 141, 142 of the interconnect layer 130 are functionally divided into two types. The first type is the first bond pads 141 for power or ground, and the second type is the second bond pads 142 for signal transmission between the chips.

[0078] Each first bond pad 141 for power or ground is connected to a corresponding side connection pad 140 by a wire (which is part of the conductive pattern 136) embedded in the organic insulating material 134, which is further connected to a power line or a ground line of the organic base substrate 110 through the solder joint 119.

[0079] The bond pads 141, 142 of the interconnect layer 130 are also divided into multiple groups in terms of connection groups. One group of bond pads (hereinafter referred to as a first group) 141-1, 142-1 is positioned at the first flip-chip region 110b-1, and the other group of bond pads (hereinafter referred to as a second group) 141-2, 142-2 is positioned at the second flip-chip region 110b-2. Although not shown in Figure 1A In the described embodiment, as representatively described for the first flip-chip region 110b-1, the side connection pads 140-1, the conductive pads 114-1, and correspondingly the solder joints 119-1 are located within the flip-chip region 110b-1. This is equally applicable to the other flip-chip regions 110b-2. However, the location of the side connections (side connection pads 140, conductive pads 114, and solder joints 119) is not limited. In other embodiments, these side connections are placed at locations away from these flip-chip regions 110b, as these side connections are not directly involved in the die bonding.

[0080] In Figure 1AThe text describes a bonding pad 141-1 connected to a side bonding pad 140-1 located within the same flip chip region 110b-1, but not connected to another side bonding pad 140-2 located in a different flip chip region 110b-2. However, because power and ground lines can be shared among multiple chips, the power or ground line for the first chip can be connected to the same line for the second chip.

[0081] Note that for Figure 1B Each chip in the array has only four bonding pads 141 and 142, two solder points 119 (two side connection pads 140 and two conductive pads 114), and two bonding pads 112 on the organic substrate 110. However, the number of bonding pads, solder points (and thus the number of side connection pads and conductive pads) on the organic substrate 110 for each chip is not limited and can depend on the chip specifications. The number of flip chip regions is also not limited to two.

[0082] As described later, the first set of bonding pads 141-1, 142-1 of the interconnect layer 130 and the first set of bonding pads 112-1 of the organic substrate 110 are formed as a two-dimensional array and configured to receive terminal bumps of the first chip. The same applies to the other chips.

[0083] In the described embodiment, the interconnect layer 130 shown in FIG1 can be attached to the organic substrate 110 using a novel interconnect layer carrier structure. Hereinafter, reference will be made to... Figure 2 This describes an interconnect layer carrier structure 120 for transferring an interconnect layer onto a target substrate according to an exemplary embodiment of the present invention.

[0084] Figure 2 This illustrates a method for transferring interconnect layer 130 onto organic substrate 110 for fabrication. Figure 1A and Figure 1B A schematic diagram of the interconnect layer carrier structure of the interconnect substrate 100 shown. Figure 2 The view shown is a cross-sectional view of the interconnect layer support structure 120.

[0085] like Figure 2 As shown, the interconnect layer carrier structure 120 includes a support substrate 122; a release layer 124 formed on the support substrate 122; and an interconnect layer portion 131 formed on the release layer 124. Note that... Figure 2 The interconnect layer portion 131 shown corresponds to the interconnect layer 130 shown in FIG1 and is shown with its top and bottom surfaces relative to each other. Figure 1A The view shown is inverted.

[0086] The support substrate 122 is a rigid and stable substrate for fabricating the interconnect layer portion 131 thereon. The support substrate 122 is suitably any substrate as long as it provides sufficient rigidity and stability. In one or more embodiments, the support substrate 122 can be an inorganic substrate including glass, a semiconductor such as silicon, ceramic, and the like. In a preferred implementation, the support substrate 122 is a glass substrate, for example, since glass substrates have a transparency and a coefficient of thermal expansion (CTE) (3-12 ppm / degree Celsius) closer to that of the organic materials used to build the interconnect layer portion 131 than silicon substrates. Examples of such glass substrates can include soda lime glass, borosilicate glass, fused silica, synthetic quartz glass, to name a few.

[0087] The release layer 124 is a release coating configured to release the interconnect layer portion 131 from the support substrate 122 by suitable processing. When the support substrate 122 has transparency, UV (ultraviolet) / IR (infrared) / visible light can be irradiated from the backside of the support substrate 122 to the release layer 124 to release the interconnect layer portion 131 from the support substrate 122.

[0088] In one or more embodiments, the release layer 124 can be any known photo- sensitive release layer that allows debonding from the support substrate interface by laser irradiation in the field of wafer bonding / debonding technology. In specific embodiments, a light-to-heat conversion release coating that converts absorbed light energy into heat can be used as the release layer 124. In these specific embodiments, after the interconnect layer portion 131 is fixed to the organic base substrate 110, the lift-off layer 124 can be burned, destroyed, or decomposed by using laser irradiation to ablate the lift-off layer 124. In other embodiments, the release layer 124 can be a thermal or UV releasable adhesive layer whose adhesive properties disappear or deteriorate due to heat or UV radiation. If necessary, the residue of the release layer 124 can be cleaned after release. In still other embodiments, any known debonding method can be employed, including mechanical peeling methods, thermal slip-off methods, and solvent release methods.

[0089] As described with reference to FIG. 1, the interconnect layer portion 131 includes an organic insulating material 134; a plurality of pads 140-142 facing the support substrate 122 and embedded in the organic insulating material 134; the plurality of traces (or wires) 136a-136d embedded in the organic insulating material 134.

[0090] Although Figure 2 not shown in FIG. 1, in specific embodiments in which a thin film type adhesive is used for the adhesive 132, the interconnect layer portion 131 can further include an adhesive layer formed on top of the organic insulating material 134 and can completely cover the top surface of the organic insulating material 134.

[0091] The plurality of pads 140-142 includes side connection pads 140, first bond pads 141 for power or ground, and second bond pads 142 for signal transmission. As shown in FIG. 1, each side connection pad 140 is configured to be connected to a corresponding conductive pad 114 disposed on the organic base substrate 110 transferred onto the interconnect layer portion 131 by a solder joint 119. The plurality of pads 140-142 is divided into a plurality of groups, including a first group of pads 140-1, 141-1, 142-1 and a second group of pads 140-2, 141-2, 142-2. Each pair of side connection pads 140-1 and corresponding bond pads 142-1 are electrically coupled by a trace 136a. Each pair of bond pads 142-1 and corresponding bond pads 142-2 are electrically coupled by a trace (trace 136b is not shown in FIG. 1 for connecting the bond pads 142-1, 142-2). Figure 2

[0092] The organic insulating material 134 can be disposed on the release layer 124. In the described embodiment, the top surface of the organic insulating material 134 can be a flat and bare surface. In other embodiments, the top surface of the organic insulating material 134 can be covered by an adhesive layer. The pads 140-142 can be exposed from the organic insulating material 134 at the bottom surface and in contact with the release layer 124. In the described embodiment, each pad 140-142 includes a barrier metal layer 138 formed on the release layer 124. Each pad 140-142 can further include a seed metal layer, which can be used to deposit conductive material (e.g., the barrier metal layer 138 and the pad body) on the release layer 124 at the bottom surface of the release layer 124 (corresponding to the top surface TS) by electroplating. In preferred embodiments, each side connection pad 140 further includes a barrier metal layer 139 formed at its edge surface ES.

[0093] The organic insulating material 134 can be any of photosensitive insulating resins, such as PI (polyimide), BCB (benzocyclobutene), PBO (polybenzoxazole), or other photosensitive polymers. The use of the organic insulating material mitigates the CTE mismatch between the interconnect layer 130 and the organic base substrate 110. The conductive pattern 136 can be made of any of metal materials (e.g., Cu, Al, etc.) and other conductive materials. In particular embodiments, metallic copper can be used for the conductive pattern 136. The barrier metal layers 138, 139 can be, but are not limited to, a stack of Au / Pd / Ni or a stack of Au / Ni, where the first element (e.g., Au for both cases) is the bottom layer or the Pd layer in the stack. Figure 2

[0094] In the described embodiment, the edges El, E2 of the interconnect layer portion 131 are aligned with the edges GE1, GE2 of the support substrate 122. As shown in FIG. 1, the edge El of the interconnect layer portion 131 is aligned with the edge GE1 of the support substrate 122, and the edge E2 of the interconnect layer portion 131 is aligned with the edge GE2 of the support substrate 122. Figure 2 ​​As shown, the interconnect layer portion 131 is provided to be fabricated on the support substrate 122 in the form of a strip formed of an organic material and held by the support substrate 122 as a rigid support material. The interconnect layer carrying structure 120 can be fabricated by repeatedly performing a photolithography process with a photosensitive organic material and a suitable electroplating resistant resist material.

[0095] In the following, with reference to a series of Figures 3A-3C , Figures 4A-4C and Figures 5A-5C , a process for manufacturing an interconnect substrate 100 according to an exemplary embodiment of the present application (e.g. shown in Figure 1A ) is described. Figures 3A-3B and Figures 4A-4C show cross-sectional views of the structure obtained during the manufacturing process of the interconnect substrate 100. Figures 5A-5C shows a cross-sectional view of the structure obtained when forming the solder joints during the manufacturing process of the interconnect substrate.

[0096] As shown in Figure 3A , the manufacturing process of the interconnect substrate 100 can comprise a step of providing an organic base substrate 110 and an interconnect layer carrying structure 120. The organic base 110 prepared by this step can comprise a plurality of bond pads 112, a set of conductive pads 114 and a solder resist layer 116 provided on the organic base 110. Note that there is a defined area 110a on the organic base substrate 110 which does not have a solder resist layer.

[0097] As shown in Figure 3A , the manufacturing process can further comprise a step of applying an adhesive 132 to the organic base substrate 110 within the defined area 110a. In the described embodiment, a paste or liquid type adhesive material, which is generally able to be used as an underfill material when bonding a chip to a substrate, is used for the adhesive 132. By using a paste or liquid type adhesive, voids in the adhesive 132 can be prevented. However, in a particular embodiment where a thin film type adhesive material forms the adhesive on top of the interconnect layer portion 131, the step of applying the adhesive 132 can be omitted.

[0098] As shown in Figure 3BAs shown, the manufacturing process may include the following steps: placing the interconnect layer carrier structure 120 on the organic substrate 110 such that the edges E1, E2 of the interconnect layer portion 131 are positioned adjacent to each set of conductive pads 114, and each side-connecting pad 140 is arranged relative to a corresponding conductive pad 114 disposed on the organic substrate 110. The interconnect layer carrier structure 120 can be placed on the organic substrate 110 in an inverted manner using a bonding agent, such that the pads 140-142 face upwards and the exposed surface of the organic insulating material 134 faces downwards. The bottom of the organic insulating material 134 is attached to the top surface of the organic substrate 110 within the defined region 110a.

[0099] Since the bonding pads 141, 142 of the interconnect layer portion 131 and the bonding pads 112 on the organic substrate 110 are configured to receive bumps of the chip to be mounted, the interconnect layer carrier structure 120 is precisely positioned at the defined region 110a by using appropriate alignment marks that can be pre-formed on the organic substrate 110. The fabrication process may further include, after placing the interconnect layer carrier structure 120 on the organic substrate 110, curing the adhesive 132 to securely bond the interconnect layer portion 131 to the organic substrate 110.

[0100] Note that in other embodiments, the application of adhesive 132 may be performed after the interconnect layer carrier structure 120 has been placed, either by capillary or injection flow methods.

[0101] like Figure 3C As shown, the manufacturing process may include the step of releasing the interconnect layer portion 131 from the support substrate 122 by removing the release layer 124. In a particular embodiment, the support substrate 122 is transparent, and the release step from the support substrate 122 can be performed by irradiating and ablating the release layer 124 with a laser beam passing through the support substrate 122 while scanning the laser beam.

[0102] By performing the above steps, the interconnect layer portion 131 is transferred from the interconnect layer carrier structure 120 to the organic substrate 110 at the defined region 110a, so as to obtain the interconnect layer 130 attached to the organic substrate 110. Figure 3C The release step shown leaves an interconnect layer 130 on the organic substrate 110, such that the set of pads 140-142 faces the opposite direction to the organic substrate 110.

[0103] Although not shown in the figures, the manufacturing process can also include a step of cleaning the residue on top of the interconnect layer 130 after the step of removing the release layer 124, which can include residue of the release layer 124. The cleaning of the residue can be performed by almost any standard method including O2 plasma irradiation. In a particular embodiment, the manufacturing process can also include a step of performing etching of the surface of the pads 140-142 after the step of removing the release layer 124, which can include a seed metal layer formed on the pads 140-142 to expose the bare surface of the metal stack 138.

[0104] As shown in Figure 4A and Figure 5A , the manufacturing process can include a step of applying a surface treatment that enhances surface roughness to the exposed pad surfaces PS of the conductive pads 114 and the bond pads 112 and to a portion of the exposed substrate surfaces SS around the conductive pads 114 and the bond pads 112. It is noted that the cross-sectional views shown in Figures 5A-5C correspond to the cross-sections indicated with “Y” in the cross-sectional views of Figures 3A-3C , respectively. Examples of such surface treatment that enhances surface roughness include sandblasting (sandblasting method) and plasma treatment.

[0105] In a preferred embodiment, sandblasting is used as the surface treatment. Sandblasting can be performed by using an appropriate abrasive medium having a particle size under appropriate conditions such as the collision speed of the abrasive medium. There are various types including dry sandblasting and wet sandblasting. Wet sandblasting, in which an abrasive medium and a liquid such as water are sprayed at the workpiece, is preferred because wet sandblasting has the ability to use finer abrasive media than dry sandblasting. Sandblasting is preferred because sandblasting mechanically and physically changes the exposed surface without significantly affecting the chemical surface conditions. Furthermore, by using an appropriate abrasive grain, the roughness of the exposed surface can be controlled more precisely with a wider control range.

[0106] In a specific embodiment, plasma treatment is used as the surface treatment. The plasma treatment can use an argon (Ar) plasma, an oxygen (O2) plasma, or a mixture thereof. Plasma treatment using an Ar plasma can be preferred to use because an Ar plasma has the ability to prevent oxidation. However, O2 plasma treatment can also be considered, for example, in the case where the pads 112, 114 are protected by a noble metal layer such as an Au layer formed on top. The plasma treatment can be performed under appropriate conditions, which can include RF (radio frequency) power, acceleration voltage, gas flow rate, application time, and the like, so that sufficient enhancement of the surface roughness is obtained.

[0107] While plasma treatment is generally applied to target surfaces to remove organic residues to clean the surface and / or to functionalize the surface to chemically alter the surface properties, the plasma treatment according to exemplary embodiments differs from plasma treatment for cleaning and / or surface functionalization in terms of the target and conditions. To make the target surface sufficiently rough, the plasma treatment is applied for an extended period of time relative to the duration for cleaning and / or surface functionalization. Furthermore, the effectiveness of the plasma treatment for enhancing surface roughness persists for a relatively long time. In contrast, the effectiveness of plasma treatment for cleaning and / or surface functionalization is short-lived because a cleaned surface tends to become contaminated over time and the surface conditions change over time, thus the effectiveness decays over time. Moreover, because of the plasma treatment, particularly O2 plasma treatment, the resin surface can be made more hydrophilic due to the interaction between the active species and the surface molecules, it is preferred that the exposed surface of the solder resist layer 116 be left for a period of time after the plasma treatment until the hydrophilicity sufficiently decays.

[0108] Figure 6 A schematic of the surface treatment to enhance surface roughness according to exemplary embodiments of the present invention is described. As described illustratively in Figure 6

[0109] cosθ w = rcosθ,

[0110] where θw represents the apparent contact angle, θ represents the Young contact angle, and r represents the roughness ratio (r = 1 for a smooth surface and r > 1 for a rough surface).

[0111] When the surface irregularities are so fine that air remains at the interface and forms a chemically heterogeneous surface, the Cassie equation holds as follows:

[0112] cosθ′ c fcosθ a +(1-f)cosθ b ,

[0113] where f represents the ratio of the area of the liquid phase in contact with the solid phase, θ a represents the contact angle of component A with fractional surface area f, and θ b represents the contact angle of component B with the remaining fractional surface area (1-f). When the liquid contacts air (e.g., θ b = 180 degrees), the Cassie equation becomes as follows:​

[0114] cos θ' c = f cos θ a + 1 - f.

[0115] Thus, even if the interface between the solid and the liquid comprises air, the contact angle θ' c increases. When f = 1 and the surface returns to homogeneity, Wenzel's equation holds.

[0116] The application of the surface treatment changes the wetting properties of the exposed surfaces in the respective direction of strengthening. The substrate surface SS with low wettability (90 degrees < θ < 180 degrees) becomes more non-wettable (θw> θ). At the same time, the pad surface PS with high wettability (0 < θ < 90 degrees) becomes more wettable (θw< θ). The enhancement of the surface roughness improves the solder wettability of the exposed pad surface PS of the pad 114 with high wettability, while improving the non-wettability of the substrate surface SS with low wettability. Thereby, it is possible to prevent the bridging of adjacent side connections during soldering, and to improve the reliability of the side connections and the die bonding, even if the spacing width between the side connections and the die bonding is very fine.

[0117] Furthermore, in the described embodiment, the surface treatment for enhancing the surface roughness is performed after releasing the interconnect layer portion 131 from the support substrate 122. In this embodiment, the surfaces of the pads 140, 141, 142, including the top surface TS and possibly the edge surface ES of the side connection pad 140, and at least a portion of the top surface 130a of the interconnect layer 130 close to the pads 140, 141, 142, can also be subjected to the surface treatment. However, the surface treatment can be applied before releasing the interconnect layer portion 131 from the support substrate 122. Furthermore, while it is preferred to apply the surface treatment for enhancing the surface roughness to the substrate surface SS and the pad surface PS simultaneously, the surface treatment can be applied to the substrate surface SS and the pad surface PS separately, possibly at different locations.

[0118] As shown in Figure 4B and Figure 5B , the manufacturing process can comprise a step of applying a solder paste 117 onto the pad surfaces PS of the conductive pads 114 and the bonding pads 112 and onto the portions of the substrate surface SS which have been at least partially subjected to the surface treatment. The solder paste 117 can fill in the openings of the solder resist layer 116. It is to be noted that the cross-sectional view shown in Figure 5B corresponds to the cross-section indicated by "Y" in the cross-sectional view of Figure 4B .

[0119] As shown in Figure 4C and Figure 5CAs shown, the manufacturing process may include the step of heating solder paste 117 to form solder joint assembly 119. It should be noted that... Figure 5C The cross-sectional view shown is in Figure 4C The cross-section indicated by "Y" in the cross-sectional view corresponds to this. By heating the solder paste 117, the applied solder paste 117 becomes molten, so that it leaves the non-wettable substrate surface SS, while remaining on the separate wettable pad surfaces PS (and the surfaces of the side connection pads 140), to form solder contacts 119 on the corresponding conductive pads 114 (and the side connection pads 140). The set of solder contacts 119 is formed to mechanically and electrically connect the side connection pads 140 of the interconnect layer 130 to the corresponding conductive pads 114 disposed on the organic substrate 110, respectively. A set of pre-solder 118 can also be formed on the bonding pads 114 through this step. The paste can be applied by jet printing, stencil printing, or syringe.

[0120] In the described embodiment, the step of heating the solder paste 117 to form the solder joint group 119 is performed before chip mounting. This is suitable for situations where there is a delay until subsequent chip mounting processes. Moreover, if the subsequent chip mounting process does not use a reflow process, the formation of the solder joint 119 is preferably performed before chip mounting. However, if the subsequent chip mounting process uses a reflow process, the step of heating the solder paste 117 at this stage can be omitted, and the completion of the solder joint 119 can be delayed until the reflow process of the subsequent chip mounting process.

[0121] Although solder paste is used as the solder material in the described embodiments, other solder materials are also conceivable, as long as the solder material applied in liquid or paste form leaves a residue on the non-wettable surface while remaining on the separate wettable surfaces to form solder joints on the respective wettable surfaces. In alternative embodiments, injection fusion soldering (IMS) can be used to form the solder joint 119. IMS technology is advantageous when a larger volume of solder is preferred.

[0122] Figure 7A and Figure 7B A schematic diagram depicts solder joints expected to be formed on side connection pads 140 and conductive pads 114, without and without surface treatments that enhance surface roughness. Figure 7A As illustrated in the diagram, when the pitch width becomes narrower, some adjacent solder joints 119 will form bridges BR that cause short circuits. Conversely, by enhancing the surface roughness on the exposed pads and substrate surfaces PS, SS, even with a narrower pitch width, it is preferable to form a set of solder joints 119 that are separate from adjacent solder joints, as shown in... Figure 7BA new surface treatment is applied prior to the solder material application to prevent the resulting solder joints 119 from bridging when soldered.

[0123] The interconnect substrate 100 (comprising the organic base substrate 110, the interconnect layer 130 and the set of solder joints 119) obtained by the manufacturing process shown in the series of Figures 3A-3C , Figures 4A-4C and Figures 5A-5C can be passed to subsequent processes, such as a chip mounting process.

[0124] Referring to the series of Figures 8A-Figure 8F and Figures 9A-Figure 9B pictures, experimental results of the contact angle of a solder drop on a build-up substrate under various conditions are described.

[0125] Figures 8A-8F Pictures showing the contact angle of a solder drop on a build-up substrate measured under various conditions. The contact angle of Figures 8A-8C was measured under conditions where a stage temperature of 80 degrees Celsius was set, while the contact angle of Figures 8D-8F was measured under conditions where a stage temperature of 250 degrees Celsius was set, higher than the melting point of the lead-free solder used. Figure 8A and 8D correspond to the reference where no surface treatment was applied. Figure 8B and Figure 8E correspond to the case where the build-up substrate was rubbed with sandpaper of 2400 grit. Figure 8C and 8F correspond to the case where the build-up substrate was rubbed with sandpaper of 600 grit, which simulates a surface treatment for enhancing surface roughness. Figures 8A-8F Each picture of

[0126] As shown in Figures 8A-8F , by comparing the wettability of three different types of build-up surfaces, it was demonstrated that the rough build-up surfaces showed lower wettability, especially for the case of the surface rubbed with sandpaper of 600 grit. The measured values of the three different types of build-up surfaces are summarized in Table 1.

[0127] Table 1

[0128] Grain size of sandpaper Reference (Smooth) #2400 #600 Contact angle at 80 degrees Celsius 132 136 155 Contact angle at 250 degrees Celsius 134 138 159

[0129] Figure 9A and 9B show plots of the roughness parameters (Ra, Rq) against the surface conditions, including the reference smooth surface, the surface rubbed with sandpaper of 2400 grit and the surface rubbed with sandpaper of 600 grit. The roughness parameters (Ra, Rq) were measured by an optical interference microscope. As Figure 9A and 9BAs shown, Raand Rqof #600 are the largest. The trend of Raand Rqis consistent with the trend of the contact angle shown in Figures 8A-8F

[0130] Referring to Figures 10A-10B and Figures 11A-11C A series of results of a computational simulation of the formation of solder joints on a model structure 1000 are described. Computational fluid dynamics simulations (CFD) were performed.

[0131] Figure 10A and Figure 10B A top view and a cross-sectional view of a model structure 1000 used for computational fluid dynamics simulations are shown, respectively. The model structure 1000 includes a substrate 1002 and a resist 1004 disposed on the substrate 1002. The resist has a thickness 1010 and has a trench 1012 having a length 1014, the trench 1012 is surrounded by the resist 1004 and has a bottom surface corresponding to a top surface of the substrate 1002. There are three first pads 1006 in the trench 1012 and three second pads 1016 placed adjacent to the trench 1012 and arranged with respect to the first pads 1006. Each pad (1006, 1016) has a width 1018 and is arranged with a pitch width 1020. Each first pad 1006 has a height 1022 and is placed on the substrate 1002. The dimensions of the model structure 1000 used for the simulations are as follows: the trench length 1014 is 100 pm; the pad pitch 1020 is 110 pm; the pad width 1018 is 60 pm; the resist thickness 1010 or trench depth is 30 pm; and the pad height 1022 is 10 pm.

[0132] At the initial state of the simulation, the trench 1012 of the resist 1004 is filled with a fluid corresponding to molten solder. The transition and converged states are calculated under various conditions where the contact angle of the surface of the resin component (the surface of the resist 1004 and the surface of the substrate 1002) is set to 120 degrees, 130 degrees, and 150 degrees.

[0133] Figures 11A-11C The simulation results performed at various contact angles of the surface of the resin component in the model structure 1000 shown in FIG. 10 at the converged state are shown.

[0134] From the results of the CFD shown in Figures 11A-11C , it is demonstrated that the occurrence height of the solder bridging depends on the surface state of the resin component of the substrate 1002. As the contact angle of the resin component decreases, it is easier to occur the solder bridging. In other words, the deterioration of the wettability of the resin surface helps to prevent the solder joint bridging across adjacent pads. In addition, from the simulation results of the contact angle of the resin component of the substrate 1002, the smaller the contact angle of the pad material, the easier it is to prevent the solder bridging. ​

[0135] In the following, a schematic view of a connection structure after chip mounting according to an exemplary embodiment of the present application is described with reference to Figure 12

[0136] Figure 12 A schematic view of an electronic device 190 including an interconnect substrate 100 as an interposer is shown. Figure 12 An enlarged cross-sectional view of the electronic device 190 around the interconnect layer 130 is shown. As Figure 12 indicated, there are two chips 150-1 and 150-2 mounted as electronic components on the interconnect substrate 100. Examples of chips can include CPUs (Central Processing Units), GPUs (Graphics Processing Units), SoCs (Systems on a Chip), memory devices such as HBM (High Bandwidth Memory), etc. The first chip 150-1 and the adjacent second chip 150-2 can be used to signal each other through the interconnect layer 130 located between the first chip 150-1 and the second chip 150-2. In the described embodiment, the chips 150 are connected through the interconnect layer 130 to a power or ground line of the organic base substrate 110, which serves as a signal return current path.

[0137] As Figure 12 indicated, the electronic device 190 includes the above-described interconnect substrate 100 and first and second chips 150-1 and 150-2 mounted on the interconnect substrate 100 with their active faces facing down. Each chip 150 can be located at a position corresponding to a flip-chip region 110b on the interconnect substrate 100. The gap between the interconnect substrate 100 and the chips 150 can be filled by an underfill 168, which can be made of epoxy or urethane.

[0138] ​The first set of bond pads 112-1 and the first and second set of bond pads 141-1, 142-1 are positioned within the first flip chip area 110b-1 where the first chip 150-1 is mounted. The first chip 150-1 has a set of terminal bumps 151-1, 152-1 electrically connected with the first set of pads 141-1, 142-1 of the interconnect layer 130 by means of solder 156-1, 157-1. The first chip 150-1 further has a set of other terminals 154-1 electrically connected to the first set of bond pads 112-1 on the organic base substrate 110 by means of solder 158-1. The terminal bumps 151-1, 152-1, 154-1 can be, but are not limited to, Cu pillar bumps. The terminal bumps 151-1 can be power or ground terminals configured to be connected with power or ground lines that can serve as signal return current paths. More specifically, the terminal bumps 151-1 are connected to bond pads 141 that are connected to corresponding side connection pads 140 via wiring embedded in the organic insulating material 134 that are further connected to power or ground lines of the organic base substrate 110 by means of soldering 119. The same applies to the second flip chip area 110b-2 and the second chip 150-2.

[0139] Although not shown in Figure 12 The interconnect substrate 100 mounting the plurality of chips 150 constitutes an electronic package that can have bumps formed at the bottom of the interconnect substrate 100 and is further mounted on a motherboard by package interconnects between the bumps of the interconnect substrate 100 and pads formed on the motherboard. The final assembly product comprising the interconnect substrate 100, the chips 150 and the motherboard can also be one of the electronic devices and the connection structure after mounting the chips.

[0140] The plurality of chips 150 can communicate with each other through the interconnect layer 130 while the chips 150 are connected to the motherboard by the internal structure of the organic base substrate 110. Further in accordance with the described embodiments, the power and ground lines to the chips 150 can be routed through the interconnect layer 130 by means of the side connections implemented by the soldering 119. This allows to suppress voltage drops compared to the case of routing the wires on the organic base substrate while avoiding the area of the interconnect layer. The provision of power or ground lines that serve as signal return current paths by using the interconnect layer is advantageous for high speed signal transmission.

[0141] The interconnect structure can comprise novel side connections between the conductive pads 114 of the organic base substrate 110 and the side connection pads 140 of the interconnect layer 130. The introduction of the novel side connections increases the flexibility of the routing of the wires and the routing of the interconnect layer 130. Furthermore, it relaxes the restrictions on the terminal layout of the chips 150 using the interconnect layer 130. This interconnect structure is suitable for heterogeneous integration.

[0142] Although Figure 12Only two chips and one interconnect layer 130 through which the two chips communicate are shown. However, the number of chips in the electronic device, the number of chips per interconnect layer, and the number of interconnect layers are not limited.

[0143] Reference is made to Figures 13A-13C the manufacturing process of an electronic device that is performed subsequent to the manufacturing process of an interconnect substrate according to exemplary embodiments of the present application. Figures 13A-13C A cross-sectional view of a structure obtained during the manufacturing process of the electronic device 190 is shown.

[0144] As shown in Figure 13A , the manufacturing process of the electronic device can include a step of mounting a plurality of chips 150 onto the interconnect substrate 100 with their active faces facing down. The first chip 150-1 can be located at a position where the first set of bond pads 112 and the first set of pads 141-1, 141-2 of the interconnect layer 130 are located. The same is true for the second chip 150-2.

[0145] The chips 150 prepared for this step can include terminal bumps 151, 152, 154, each of which can be composed of a post 161, 162, or 164 and a cap 166, 167, or 168 formed thereon. In the described embodiment, the terminal bumps 151, 152, 154 are Cu post bumps. However, in other embodiments, the terminal bumps 151, 152, 154 can be any of the standard bumps, including standard flip chip bumps, fine pitch, micro bumps, Cu post bumps, Cu post bumps with Sn cap (SLID), etc. In the described embodiment, there is no solder on the bond pads 141, 142 of the interconnect substrate 100 prepared for this step, as each bond pad 141, 142 has a barrier metal layer 138 on top, which improves wettability. However, it is not precluded to apply solder onto the bond pads 141, 142 prior to chip mounting.

[0146] As shown in Figure 13B , the manufacturing process can include a step of forming solder interconnects 156, 157, 158 between the bond pads 112, 141, 142 and the posts 161, 162, 164 by a solder reflow process.

[0147] By performing the steps shown in Figure 13A and Figure 13B , the chips 150 are mounted on the interconnect substrate 100 such that the chip 150 has a terminal bump 151 that is bonded to the bond pad 141 through the bond pad 119 and is electrically connected to the conductive pad 114 disposed on the organic base substrate 110 through the side connection pad 140.

[0148] As shown in Figure 13CAs shown, the manufacturing process can include the following steps: dispensing the underfill 168 by a capillary flow underfill process to fill the gap between the interconnect substrate 100 and the chips 150, followed by curing, in order to fix the first chip 150-1 and the second chip 150-2 to the interconnect substrate 100.

[0149] In the described embodiment, the underfill 168 is described as being applied to the organic base substrate 110 after the organic base substrate 110 has been subjected to a reflow process. However, in other embodiments, a no-flow underfill can first be dispensed on the interconnect substrate 100. Then, the chips 150 are placed on the interconnect substrate 100 which has been dispensed with the underfill. Finally, the formation of the solder interconnects 156, 157, 158 and the curing of the underfill are performed simultaneously by a reflow process. In the described embodiment, a solder reflow process is used as a bonding process. However, in other embodiments, instead of a solder reflow process, a thermal compression (TC) bonding process can also be envisaged.

[0150] The connection structure according to one or more embodiments of the present application can prevent the bridging of the solder joints formed on the adjacent pads at the time of soldering. The application of the surface treatment that enhances the surface roughness improves the wettability of the pad surface of the pads and the de-wettability of the top surface of the substrate with respect to the molten solder. Thus, even if the pitch between the solder joints becomes finer, the reliability of the solder joints can be improved. Furthermore, it is possible to reduce the manufacturing cost and improve the production yield of the connection structure and the electronic device including the connection structure.

[0151] While in the above described embodiments, the target of the novel surface treatment is the solder joint for side connection and / or the solder joint for flip-chip bonding, however, the target of the novel surface treatment is not limited. Other solder joints are also envisaged, such as BGA (ball grid array), QFP (quad flat package), solder joints for wire bonding to chips, and solder joints for other surface mount devices.

[0152] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, layers, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, layers, elements, components, and / or groups thereof.

[0153] All of the apparatuses or steps plus the corresponding structural, material, acts and equivalents of the claims below are intended to include any structure, material, or acts for performing the functions described in conjunction with other claimed elements as specifically claimed below. The description of one or more aspects of the application has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the application to the forms disclosed.

[0154] Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used here has been chosen for the best reasons to best explain the principles of the embodiments, practical application, or technical improvements over technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed here.

[0155] In a preferred embodiment of the application described herein, there is provided a method of manufacturing a connection structure, comprising: providing a substrate having a top surface and including a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate, wherein the top surface of the substrate has at least a portion of the set of pads proximate a surface treatment that has applied an enhanced surface roughness, and the pad surface of each pad in the set of pads has at least a portion to which the surface treatment has been applied; and forming a set of solder joints, each solder joint disposed on a corresponding one of the set of pads. Preferably, forming the set of solder joints comprises: applying a solder material to the pad surfaces of the set of pads and the portion of the top surface of the substrate to which the surface treatment has been at least partially applied; and heating the solder material to form the set of solder joints.

Claims

1. A method for manufacturing a connecting structure, comprising: A substrate is provided having a top surface and including a set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate; as well as A surface treatment is applied to at least a portion of the top surface of the substrate near the pads and to the pad surface of each pad in the pad group, such that at least a portion of the top surface near the pads is rougher than other portions of the top surface, and the pad surface of the pads is rougher than the exposed surfaces of other conductive materials formed on the substrate.

2. The method according to claim 1, wherein, The top surface of the substrate has low wettability, and the surface of each pad has high wettability to molten solder.

3. The method according to claim 1, wherein, After the surface treatment is applied, at least a portion of the top surface of the substrate has a roughness parameter (Ra) greater than 0.4 μm and less than 2 μm.

4. The method according to claim 1, wherein, The pads comprise a metallic material, and at least a portion of the top surface adjacent to the pads comprises an organic material.

5. The method according to claim 4, wherein the portion comprising organic material is selected from an organic substrate, a dielectric layer disposed on the substrate, a solder resist layer disposed on the substrate, an adhesive disposed on the substrate, and combinations thereof.

6. The method according to claim 1, wherein, The surface treatment includes sandblasting.

7. The method according to claim 6, wherein, The sandblasting includes wet sandblasting.

8. The method according to claim 1, wherein, The surface treatment includes plasma treatment.

9. The method according to claim 8, wherein, The plasma treatment includes argon plasma.

10. The method of claim 1, further comprising forming a group of solder joints, each solder joint being disposed on a corresponding pad in the pads.

11. The method according to claim 10, wherein, Forming the group of weld points includes: Solder material is applied to at least a portion of the surface treatment applied to the surface of the pads of the pad group and the top surface of the substrate; and The solder material is heated to form the solder joint group.

12. The method according to claim 1, wherein, The substrate further includes an interconnect layer disposed on the substrate, the interconnect layer having an edge positioned adjacent to the pad group and including a side connection pad group located at the edge of the interconnect layer and exposed, each side connection pad being arranged relative to a corresponding pad among the pads disposed on the substrate.

13. The method according to claim 12, wherein, Each side connection pad has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at the edge of the interconnect layer, the edge surface facing a corresponding one of the set of pads.

14. The method of claim 12, further comprising forming a set of solder joints to connect the side connection pads of the interconnect layer to the pads disposed on the substrate, respectively.

15. A connection structure, comprising: The substrate has a top surface; as well as A set of pads for soldering, each pad having a pad surface exposed from the top surface of the substrate; The portion of the top surface of the substrate near the pad is rougher than the rest of the top surface, and the surface of each pad in the pad group is rougher than the exposed surface of other conductive materials formed on the substrate.

16. The connection structure according to claim 15, wherein, The top surface of the substrate has low wettability, and the surface of each pad has high wettability to molten solder.

17. The connection structure according to claim 15, wherein, After the surface treatment is applied, the portion of the top surface of the substrate has a roughness parameter (Ra) greater than 0.4 μm and less than 2 μm.

18. The connection structure according to claim 15, wherein, The substrate has at least a portion of the top surface to which a surface treatment for enhanced surface roughness is applied, and each of the set of pads has at least a portion of the pad surface to which the surface treatment is applied.

19. The connection structure according to claim 18, wherein, The surface treatment includes sandblasting.

20. The connection structure according to claim 18, wherein, The surface treatment includes plasma treatment.

21. An electronic device comprising a connection structure according to any one of claims 15 to 20.

22. The electronic device of claim 21, further comprising: A group of solder joints, each solder joint being set on a corresponding pad in the solder pad; as well as One or more electronic components are mounted on the substrate, each electronic component using at least one of the solder joints.

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