Method of manufacturing a semiconductor device and electronic device

Abstract

The present invention provides a method for manufacturing a semiconductor device and an electronic device. First, a hole-sealing film layer is fabricated on a carrier substrate, and the hole-sealing film layer is transferred to a first component of a device substrate through a bonding process to seal at least part of the release holes of the first component, thereby avoiding the risks of locking of the first component and entry of hole-sealing materials or developer into the interior of the semiconductor device when directly forming a hole-sealing thin film on the first component.

Description

Technical Field

[0001] The present invention relates to the technical field of module assembly of electronic products, and particularly to a method for manufacturing a semiconductor device and an electronic device. Background Art

[0002] In the manufacturing process of some existing semiconductor devices for special applications, sacrificial materials are often fabricated on a first component, and a second component is fabricated on the sacrificial materials. Then, a large number of release holes are formed in the second component to remove the sacrificial materials through the release holes. After that, a sealing film layer is formed on the second component to seal all or part of the release holes on the second component.

[0003] However, in the existing sealing process, the problem that the sealing material enters the interior of the semiconductor device easily occurs, seriously affecting the device performance.

[0004] Therefore, how to seal the release holes on the first component of the semiconductor device has become a hot issue for those skilled in the art to study. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a semiconductor device and an electronic device, which can at least seal part of the release holes on the first component, avoid the sealing material from entering the interior of the semiconductor device, and ensure the performance of the semiconductor device.

[0006] To achieve the above purpose, the present invention provides a method for manufacturing a semiconductor device, including:

[0007] Providing a device substrate, the device substrate having a first component, a second component, and a plurality of first release holes penetrating the first component;

[0008] Providing a carrier substrate, and forming a sealing film layer on the carrier substrate;

[0009] Bonding the sealing film layer to the first component to seal at least part of the first release holes;

[0010] Removing the carrier substrate.

[0011] The first component is a movable component, and the second component is a fixed component. The first component can be movable relative to the second component in the manufactured semiconductor device.

[0012] Optionally, the provided device substrate further has a first sacrificial member and a second sacrificial member. A partial region of the first component is fixedly connected to the second component through the first sacrificial member, and the remaining gap between the first component and the second component is filled with the second sacrificial member. The semiconductor device manufacturing method further includes: before bonding the hole-sealing film layer to the first component, at least removing the second sacrificial member through the first release hole and keeping the first sacrificial member maintain the fixed connection between the first component and the second component; and, after bonding the hole-sealing film layer to the first component and before or after removing the carrier substrate, removing the first sacrificial member.

[0013] Optionally, the device substrate further has a second release hole provided on the second component. Before bonding the hole-sealing film layer to the first component, the second sacrificial member is removed through the first release hole and the second release hole; after bonding the hole-sealing film layer to the first component and before or after removing the carrier substrate, at least removing the first sacrificial member through the second release hole.

[0014] Optionally, the hole-sealing film layer is a patterned film layer. After bonding the hole-sealing film layer to the first component, the hole-sealing film layer exposes a part of the first release hole; after bonding the hole-sealing film layer to the first component and before or after removing the carrier substrate, the first sacrificial member is removed through the second release hole and the first release hole exposed by the hole-sealing film layer.

[0015] Optionally, the hole-sealing film layer is a patterned film layer. A patterned hole-sealing film layer is formed on the carrier substrate by dispensing, pattern printing, or photolithography process.

[0016] Optionally, before forming the hole-sealing film layer on the carrier substrate, a temporary bonding layer or a first etch stop layer is first formed on the carrier substrate.

[0017] Optionally, the temporary bonding layer includes a thermally decomposable bonding film, a photo-decomposable bonding film, an electro-decomposable bonding film, or a chemically decomposable bonding film.

[0018] Optionally, before forming the hole-sealing film layer on the carrier substrate and after forming the temporary bonding layer or the first etch stop layer on the carrier substrate, at least a wiring for connecting to the first component is formed on the carrier substrate, and the wiring includes a single-layer structure and / or a multi-layer interconnect structure.

[0019] Optionally, after forming the temporary bonding layer or the first etch stop layer on the carrier substrate and before forming the wiring on the carrier substrate, a patterned sacrificial layer is first formed on the temporary bonding layer or the first etch stop layer.

[0020] Optionally, before forming the wiring on the patterned sacrificial layer, a second etch stop layer is formed on the patterned sacrificial layer.

[0021] Optionally, the method for manufacturing a semiconductor device further includes, after removing the carrier substrate:

[0022] Removing the first etch stop layer;

[0023] Removing the second etch stop layer exposed by the patterned sacrificial layer;

[0024] Removing the patterned sacrificial layer.

[0025] Optionally, the wiring includes a floating connection wire connecting the second component and the first component.

[0026] Optionally, the second component and the first component are flexibly connected by the floating connection wire.

[0027] Optionally, the floating connection wire is a bare wire.

[0028] Optionally, the wiring includes a pad formed on the first component and / or a pad formed on the second component.

[0029] Optionally, the wiring includes a first metal layer, and the method for manufacturing a semiconductor device further includes: after removing the carrier substrate, exposing at least a part of the surface of the first metal layer of the wiring, and electroless plating a second metal layer on the exposed surface of the first metal layer.

[0030] Optionally, the carrier substrate is removed by at least one process including debonding, mechanical grinding, and etching.

[0031] Optionally, the material of the hole-sealing film layer includes a dry film.

[0032] Optionally, after removing the carrier substrate, at least a part of the hole-sealing film layer is also exposed, and components to be assembled are assembled on the exposed hole-sealing film layer.

[0033] Optionally, the components to be assembled include active components and / or passive components.

[0034] Optionally, the active component includes an image sensor wafer.

[0035] Based on the same inventive concept, the present invention also provides an electronic device including a semiconductor device formed by the method for manufacturing a semiconductor device of the present invention.

[0036] Compared with the prior art, the technical solution of the present invention has one of the following beneficial effects:

[0037] 1. First, form a sealing film layer on the carrier substrate, and transfer the sealing film layer to the first component of the device substrate through a bonding process to seal at least part of the release holes of the first component, thereby avoiding the risk of locking the first component and the ingress of sealing material or developer into the semiconductor device when directly forming a sealing thin film on the first component.

[0038] 2. Since the sealing film layer is first formed on the carrier substrate and transferred to the first component of the device substrate by using alignment and bonding processes, it avoids the problems of locking the first component and the second component together and inaccurate or unreliable sealing on the first component when directly forming a sealing thin film on the first component.

[0039] 3. Since the wiring process including pads and / or multi-layer interconnect lines is completed on the carrier substrate before forming the sealing film layer on the carrier substrate, it is possible to avoid the process difficulty caused by directly implementing the wiring process on the device substrate, reduce costs, and also avoid the problem of difficult release of the sacrificial material between the first component and the second component when directly implementing the wiring process on the device substrate.

[0040] 4. Since the wiring process is completed on the carrier substrate before forming the sealing film layer on the carrier substrate, multi-layer metal wiring can be achieved.

[0041] 5. Since the wiring and the sealing film layer are formed on the carrier substrate and transferred to the first component simultaneously through a bonding process, it is possible to simultaneously perform wiring and release hole sealing operations on the first component.

[0042] 6. Since a temporary bonding layer is formed before forming the wiring and the sealing film layer on the carrier substrate, the carrier substrate can be reused, saving costs.

[0043] 7. Since most of the sacrificial material on the device substrate can be released before bonding the two substrates, it avoids the process difficulty caused by the need to protect the wiring when releasing the sacrificial material on the device substrate. Description of the Drawings

[0044] Figure 1 is a schematic cross-sectional structure diagram of a device in the existing semiconductor device manufacturing process.

[0045] Figure 2 is a schematic cross-sectional structure diagram of a device corresponding to a sealing technology in the existing semiconductor device manufacturing process.

[0046] Figure 3It is a schematic cross-sectional structure diagram of a device corresponding to another hole-sealing technology in the existing semiconductor device manufacturing process.

[0047] Figures 4 to 6 It is a schematic cross-sectional structure diagram of a device in a metal wiring process flow in the existing semiconductor device manufacturing process.

[0048] Figure 7 It is a schematic cross-sectional structure diagram of a device when large-sized metal wiring is arranged in the existing semiconductor device manufacturing process.

[0049] Figures 8 to 13 It is a schematic cross-sectional structure diagram of a device in the semiconductor device manufacturing method process of an embodiment of the present invention.

[0050] Figures 14 to 16 It is a schematic cross-sectional structure diagram of a device in the semiconductor device manufacturing method process of another embodiment of the present invention.

[0051] Figures 17 to 21 It is a schematic cross-sectional structure diagram of a device in the semiconductor device manufacturing method process of yet another embodiment of the present invention.

[0052] Figures 22 to 27 It is a schematic cross-sectional structure diagram of a device in the semiconductor device manufacturing method process of still another embodiment of the present invention.

[0053] Figures 28 to 29 It is a schematic cross-sectional structure diagram of a device in the semiconductor device manufacturing method process of still another embodiment of the present invention.

[0054] The reference numerals therein are as follows:

[0055] 100 - Second component, 101 - First component, 102 - Release hole, 103 - Global hole-sealing film, 104 - Patterned hole-sealing film, 105 - Sacrificial material, 106 - Bottom protective layer, 107 - Metal wire, 108 - Capping protective layer;

[0056] 200 - Second component, 200a - Second release hole, 201 - First sacrificial piece, 202 - Second sacrificial piece, 203 - First component, 204 - First release hole;

[0057] 300 - Carrier substrate, 301 - Temporary bonding layer, 302 - Hole-sealing film layer, 303 - First metal layer, 303' - Second metal layer, 304 - Intermetal dielectric layer, 305 - Upper interconnect structure, 305a - Suspended connection line, 306 - Seed layer, 307 - First etch stop layer, 308 - Patterned sacrificial layer, 309 - Second etch stop layer;

[0058] 400 - Element to be assembled. Detailed implementation manners

[0059] Taking a large-sized Micro-Electro-Mechanical System (MEMS) device as an example, the technical problems existing in the existing hole-sealing process and wiring process will be described in detail below.

[0060] In the existing hole-sealing technology during the production process of MEMS devices, there are mainly two methods: film pasting and deposition of hole-sealing materials, and it is usually divided into global hole-sealing and local hole-sealing.

[0061] Among them, please refer to Figure 1 and Figure 2 , the specific process of the global hole-sealing process includes: First, using a device wafer (not shown) and corresponding sacrificial materials to manufacture the fixed part 100 and the movable part 101 of the MEMS device. At this time, the gap between the movable part 101 and the fixed part 100 is filled with sacrificial materials (not shown, which can be referred to Figure 4 ). Further, a large number of release holes 102 can be made on the movable part 101; then, through these release holes 102, the sacrificial materials between the movable part 101 and the fixed part 100 are removed, so that the movable part 101 can move relative to the fixed part 100; after that, a global hole-sealing film 103 can be formed on the surface of the movable part 101 and its surrounding fixed part 100 by means of global film deposition or global glue coating or global film pasting, thereby closing each release hole 102 on the movable part 101, and thus forming a cavity structure between the movable part 101 and the fixed part 100.

[0062] The above-mentioned global hole-sealing process has the following defects: (1) When the release hole 102 is large and the depth-to-width ratio of the release hole 102 is small, it is difficult to achieve hole-sealing by relying on film deposition; (2) At the edge of the movable part 101 (such as the area marked by the virtual coil in Figure 2 ), the movable part 101 is fixed and locked on the fixed part 100 by the global hole-sealing film 103, so that the problem that the movable part 101 is difficult to move is caused; (3) Since the sacrificial materials have been removed before film deposition, a cavity has been formed between the movable part 101 and the fixed part 100. The channels for film deposition or glue coating are usually larger than the spacing of the release holes, and the glue coating process is often accompanied by a downward pressing action, so that the deposited film or the applied glue is easily drilled into the cavity through the release holes, which is very likely to cause damage to the internal structure of the device or the problem of the movable part moving failure; (4) The movable part is movable relative to the fixed part, resulting in the problem of low hole-sealing accuracy or unreliability; (5) In some cases, it is not suitable to achieve hole-sealing by means of global film deposition or global film pasting, for example, areas where pads need to be left on the surface of the movable part and where hole-sealing materials are not allowed to exist.

[0063] The local sealing process can meet the requirement of leaving areas such as pads on the surface of movable components where sealing materials are not allowed, and can avoid the situation where the edges of movable components are locked. Please refer to Figures 1 to 3 , and its specific process includes: first, a global sealing film is formed on the surface of the movable component 101 and its surrounding fixed component 100 by means of global film deposition, or global glue coating, or global film laminating. Then, through photolithography or a process combining photolithography and etching, the global sealing film is patterned to form a patterned sealing film 104, which can seal the release holes 102 in specific areas of the movable component 101.

[0064] The above local sealing process has the following defects: (1) Since it first uses the global sealing process, and when the aspect ratio of the release hole 102 is small, it is difficult to achieve sealing, and the sealing film material is easily drilled into the cavity through the release hole, resulting in problems such as damage to the internal structure of the device or failure of the movable component to move; (2) The movable component is movable relative to the fixed component, resulting in problems of low or unreliable sealing accuracy; (3) When the global sealing film cannot be directly photolithographed, a photoresist needs to be coated on the global sealing film. Due to the poor adhesion of the photoresist, the implementation of the photoresist coating and development processes is difficult, and it is difficult to achieve high-precision patterning. When the global sealing film is a dry film or other materials that can be directly photolithographed, the solution after dry film development is easily penetrated into the internal part of the MEMS device, further resulting in problems such as damage to the internal structure of the device or failure of the movable component to move.

[0065] In addition, in some applications, active components need to be assembled on the movable component. In this case, usually, the metal wiring process needs to be carried out before removing the sacrificial materials between the movable component and the fixed component. After the sacrificial materials are released, the metal wires laid can be used to achieve electrical connection between the fixed component and the movable component, etc. Taking the metal wiring process (such as aluminum wire) itself being intolerant to the sacrificial material (such as silicon dioxide) release process and requiring comprehensive protection of the metal wiring as an example, please refer to Figures 4 to 6, the specific process of the metal wiring process in the existing manufacturing process of a MEMS device includes: First, a device wafer (not shown) and corresponding sacrificial materials are used to manufacture the fixed component 100 and the movable component 101 of the MEMS device. At this time, the gap between the movable component 101 and the fixed component 100 is filled with the sacrificial material 105. Further, there can be a large number of release holes 102 in the movable component 101, and these release holes 102 are still filled with the sacrificial material 105; then, a patterned bottom protective layer 106 is formed on the surfaces of the sacrificial material 105, the movable component 101, and the fixed component 100, and contact holes (not shown) are formed in the bottom protective layer 106; then, a metal layer is deposited through processes such as metal sputtering deposition, and the deposited metal layer is lithographed and etched to form metal wires 107 that fill the contact holes and are electrically connected to the movable component 101 or are electrically connected to both the movable component 101 and the fixed component 100; then, a capping protective layer 108 is formed on the surface of the metal wire 107, the capping protective layer 108 covers the surface of the metal wire 107, and the corresponding sacrificial material 104 is exposed; then, the sacrificial material 105 is removed through the exposed release holes 102 of the movable component 102; after that, the exposed release holes 102 of the movable component 102 can be sealed through a global hole-sealing process or a local hole-sealing process.

[0066] The above metal wiring process has the following defects: (1) In some applications that require a flexible connection between the fixed component 100 and the movable component 101, the bottom protective layer 106 and the capping protective layer 108 will increase the adverse rigidity of the metal wire between the fixed component 100 and the movable component 101. Therefore, in the prior art, after removing the sacrificial material 104, it is also necessary to further remove the bottom protective layer 106 and the capping protective layer 108, thus increasing the complexity and cost of the process; (2) Please refer to Figure 7 , when performing the above metal wiring on the movable component 101, when there is a metal structure (such as a pad) 107' with a relatively large size, this metal structure 107' will occupy the distribution space of the release holes 102 on the movable component 101, causing difficulties in the release of the sacrificial material 105. For example, the sacrificial material 105 in the B area in Figure 7 is relatively difficult to remove compared to the A area and the C area.

[0067] Of course, some of the problems in the above process also exist in the manufacturing process of some other special application semiconductor devices other than MEMS devices.

[0068] Therefore, how to avoid sealing the release holes has become a technical problem that needs to be solved urgently by those skilled in the art, and how to simplify the metal wiring process and reduce the wiring cost has become another technical problem that needs to be solved urgently by those skilled in the art.

[0069] Based on this, in order to solve at least some of the above problems, the present invention provides a method for manufacturing a semiconductor device. First, a hole-sealing film layer is fabricated on a carrier substrate, and the hole-sealing film layer is transferred to a first component of a device substrate through a bonding process to seal at least some of the release holes of the first component, thereby avoiding the risks of locking the first component and the entry of hole-sealing materials or developer solution into the semiconductor device when directly forming a hole-sealing thin film on the first component, and ensuring the device performance.

[0070] The following will further elaborate on the technical solutions proposed by the present invention in conjunction with the Figure 8 ~ Figure 29 drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. The meaning of "and / or" herein is either one of two or both.

[0071] Please refer to Figures 8 to 13 , an embodiment of the present invention provides a method for manufacturing a semiconductor device, which specifically includes the following steps:

[0072] S1. Provide a device substrate, where the device substrate has a first component, a second component, and a plurality of first release holes penetrating through the first component;

[0073] S2. Provide a carrier substrate and form a hole-sealing film layer on the carrier substrate;

[0074] S3. Bond the hole-sealing film layer to the first component to seal at least some of the first release holes;

[0075] S4. Remove the carrier substrate.

[0076] Please refer to Figure 8 , in step S1, a device substrate is provided. The device substrate can be any suitable substrate material well-known to those skilled in the art, which has a first component 203, a second component 200, and a plurality of first release holes 204 penetrating through the first component 203.

[0077] In this embodiment, the provided device substrate is a MEMS substrate, its first component 203 is a movable component, the second component 200 is a fixed component, the device substrate further has a first sacrificial member 201 and a second sacrificial member 202. A partial area of the first component 203 is fixedly connected to the second component 200 through the first sacrificial member 201, and the remaining gap between the first component 203 and the second component 200 is filled with the second sacrificial member 202.

[0078] It should be noted that the materials of the second sacrificial member 202 and the first sacrificial member 201 are different, and different release processes are required, such as different agents, temperatures, or times required during release. Among them, the release process of the second sacrificial member 202 only requires the tolerance of the MEMS chip's own structure, while the release process of the first sacrificial member 201 also requires the tolerance of other components / parts to be integrated / installed subsequently. The structure corresponding to the first sacrificial member 201 needs to provide sufficient strength and stability. After the second sacrificial member 202 is released, the first component (i.e., the movable component) fixed by the first sacrificial member 201 has sufficient strength and stability and can be used for the integration and installation of other components / parts subsequently. As an example, the material of the second sacrificial member 202 is, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc., and the first sacrificial member 201 is, for example, amorphous carbon, polysilicon, amorphous silicon, or germanium, etc.

[0079] In addition, the first sacrificial member 201 and the second sacrificial member 202 can be realized through conventional processes such as film layer growth, patterning, planarization, and back etching. For example, the first sacrificial member 201 can be formed on the second component 200 through processes such as film layer growth and patterning, and then the second sacrificial member 202 covering the first sacrificial member 201 can be formed through processes such as film layer growth and planarization. After that, through processes such as patterning, film layer growth, and planarization, the first component 203 is formed in the second sacrificial member 202. Another example is that a sacrificial layer can be formed on the second component 200 through processes such as film layer growth and planarization first, and then the sacrificial layer is etched through patterning to form trenches, and the first sacrificial member material is filled in the trenches through film layer growth and back etched to form the first sacrificial member 201 in the sacrificial layer. After that, through processes such as film layer growth and planarization, another sacrificial layer is covered on the sacrificial layer and the first sacrificial member 201, and the two sacrificial layers constitute the second sacrificial member 202. After that, through processes such as patterning, film layer growth, and planarization, the first component 203 is formed in the second sacrificial member 202. Yet another example is that the first sacrificial member 201 can be formed on the second component 200 through processes such as film layer growth and patterning first, and then a sacrificial layer is formed through processes such as film layer growth and planarization. The sacrificial layer fills the gaps between the first sacrificial members 201 and can be flush with the surface of the first sacrificial member 201. Then, through processes such as film layer growth and patterning, the first component 203 is formed on the first sacrificial member 201, the sacrificial layer, and the second component 200. After that, through processes such as film layer growth and planarization, another sacrificial layer is formed. The other sacrificial layer and the sacrificial layer constitute the second sacrificial member 202, and the other sacrificial layer covers the surfaces of the sacrificial layer and the second component 200 exposed by the first component 203.

[0080] As an example, please refer to Figure 8 and Figure 9, in step S1, the first component 203 is formed by patterning the second sacrificial member 202 and filling it with a material. The gaps between the first components 203 serve as the first release holes 204 in the first component 203. Before bonding the device substrate to the subsequent carrier substrate, the second sacrificial member 202 can be removed (released) through the first release holes 204 and the gaps between the edges of the first component 203 and the second component 200.

[0081] As another example, please refer to Figure 8 and Figure 9 , in step S1, after the first component 203 is fabricated in the device substrate, the first component 203 can be opened by processes such as photolithography and etching to expose the surface of the underlying second sacrificial member 202, so as to form a large number of first release holes 204. Then, before bonding the device substrate to the subsequent carrier substrate, the second sacrificial member 202 can be removed (released) through the first release holes 204 and the gaps between the edges of the first component 203 and the second component 200 (which can also be regarded as a kind of first release hole).

[0082] In this embodiment, after the second sacrificial member 202 is released (removed), most of the space between the first component 203 and the second component 200 is emptied. However, due to the existence of the temporary support / connection structure of the first sacrificial member 201, the first component 203, as a movable component, can still be immovable relative to the second component 200, which is beneficial to the subsequent bonding of the carrier substrate and the precise sealing of the sealing film layer.

[0083] Please refer to Figure 10, in step S2, first, a carrier substrate 300 is provided. The material of the carrier substrate 300 can be any suitable substrate material well-known to those skilled in the art, such as a bare silicon substrate, a glass substrate, or a ceramic substrate, etc. Then, a temporary bonding layer 301 is attached to the global surface of the carrier substrate 300; next, through processes such as dispensing, coating, pattern printing, or film laminating, a sealing film layer 302 is formed on the temporary bonding layer 301. When the sealing film layer 302 is required to locally seal the first component 203, but the formed sealing film layer 302 globally covers the temporary bonding layer 301, the redundant sealing film layer can be further removed by patterning methods such as lithography to form a patterned sealing film layer 302 with bonding function in a specific area, and no sealing film material is allowed to remain in other areas, such as areas like the pad area on the first component 203 and the junction between the first component 203 and the second component 200. The sealing film layer 302 is a film structure before being bonded to the device substrate, rather than a liquid colloid, and its material is, for example, a structural adhesive or a dry film, etc. And since the sealing film layer 302 is formed on the carrier substrate 300, its upper and lower surfaces are both very flat, which is beneficial to the subsequent processes, such as facilitating the assembly of other components to be assembled on the sealing film layer 302 after step S4. Among them, the temporary bonding layer 301 includes a thermally releasable bonding film, a photo-releasable bonding film, an electro-releasable bonding film, or a chemically releasable bonding film; the thermally releasable bonding film is a film layer that can be released from the temporary bond with the carrier substrate 300 by heating, the photo-releasable bonding film is a film layer that can be released from the temporary bond with the carrier substrate 300 by light irradiation. For example, when the carrier substrate 300 is a transparent substrate (such as a glass substrate), the temporary bonding layer 301 can also be a photo-releasable bonding film such as an LTHC (light-to-heat conversion) layer or an ultraviolet double-sided tape, etc.; the electro-releasable bonding film is a film layer that can be released from the temporary bond with the carrier substrate 300 by applying electricity; the chemically releasable bonding film is a film layer that can be released from the temporary bond with the carrier substrate 300 by infiltration or immersion of a chemical liquid.

[0084] Please continue to refer to Figure 10, in step S3, the sealing film layer 302 can be bonded to the first component 203 through a conventional bonding process. The sealing film layer 302 can seal at least part of the first release holes 204 of the first component 203. During this process, due to the presence of the first sacrificial part 201, the first component 203 is immovable. Therefore, bonding based on precise positioning can be implemented, and the sealing film layer 302 is adhered to a specified area of the first component 203. Moreover, since the sealing film layer 302 is a film structure rather than a liquid colloid before being bonded to the device substrate, it will not penetrate into the interior of the device substrate during the bonding process, that is, it will not enter the cavity between the first component 203 and the second component 200 through the first release holes 204 on the first component 203.

[0085] Please refer to Figure 11 , in step S4, according to the properties of the temporary bonding layer 301, a suitable debonding process is selected to remove the temporary bonding layer 301 and the carrier substrate 300 to expose the sealing film layer 302. For example, when using a thermally debondable film as the temporary bonding layer 301, in step S4, by heating, the temporary bonding layer 301 loses its adhesiveness, and then the carrier substrate 300 can be easily peeled off. In addition, when the sealing film layer 302 is a dry film, the thermal debonding of the temporary bonding layer 301 can also cure the sealing film layer 302 to a certain extent. For another example, when using a photo-debondable film as the temporary bonding layer 301, through laser debonding, the temporary bonding layer 301 loses its adhesiveness, and then the carrier substrate 300 can be easily peeled off.

[0086] After that, please refer to Figure 12 and Figure 13 , the first sacrificial part 201 can be removed through the first release holes 204 exposed by the sealing film layer 302, and other components to be assembled 400 can be assembled on the sealing film layer 302. The components to be assembled 400 can be active components, passive components, or can have both active and passive components at the same time. Among them, the active components are, for example, image sensor wafers, etc., and the passive components are, for example, resistors, capacitors, or inductors, etc.

[0087] It should be noted that the technical solutions of the above embodiments are only specific examples of the technical solutions of the present invention, and do not indicate that the technical solutions of the present invention are only limited thereto. Those skilled in the art can increase or decrease the steps of the solution as needed, which also belongs to the technical scope protected by the technical solutions of the present invention.

[0088] For example, in the above embodiment, since local hole sealing of the first component 203 is required, the hole-sealing film layer 302 is patterned in step S2 to expose the first release holes 204 that need to be exposed on the first component 203. However, in other embodiments of the present invention, if corresponding first components 203 are formed in multiple device regions of the same device substrate, the first components 203 are spaced apart from each other (e.g., spaced apart by a scribe line), and global hole sealing needs to be performed on the first component 203 in each device region, then when simply patterning the hole-sealing film layer 302 in step S2, the hole-sealing film layer 302 is disconnected from each other at the position corresponding to the spacer region between adjacent two device regions (e.g., removing the hole-sealing film layer 302 corresponding to the scribe line region), and the hole-sealing film layer 302 corresponding to each device region can be used to completely cover the surface of the first component 203 in this device region, so that after bonding the device substrate and the carrier substrate, all the first release holes 204 on the first component 203 in each device region are sealed.

[0089] For another example, in the above embodiment, since the temporary bonding layer 301 is used in step S2, the carrier substrate 300 can be removed by releasing the temporary bonding in step S4. However, in other embodiments of the present invention, the formation of the temporary bonding layer 301 can also be omitted in step S2, and in step S4, the carrier substrate 300 is removed by processes such as mechanical grinding and / or etching. As an example, first, the back surface of the carrier substrate 300 is ground, and then wet etching is performed to remove the carrier substrate 300 and avoid damaging the hole-sealing film layer 302 to ensure the flatness of the upper surface of the hole-sealing film layer 302.

[0090] For yet another example, in the above embodiment, since only the first component 203 is provided with the first release holes 204 capable of releasing the first sacrificial member 201 and the second sacrificial member 202, and there is a gap between the edge of the first component 203 and the second component 200, the second sacrificial member 202 is removed in step S1 and the first sacrificial member 201 is removed in step S4 through the first release holes 204 on the first component 203 and the gap between the edge of the first component 203 and the second component 200 (which can be regarded as a kind of first release hole). However, in other embodiments of the present invention, as an example, please refer to Figure 28 and Figure 29, in step S1, there is a gap between the edge of the first component 203 and the second component 200. A first release hole 204 is formed on the first component 203, and a second release hole 200a is further formed on the second component 200. The second release hole 200a penetrates the second component 200 and exposes a partial surface of the second sacrificial member 202. Thus, in step S1, the second sacrificial member 202 can be removed jointly through the first release hole 204, the second release hole 200a, and the gap between the edge of the first component 203 and the second component 200 (which can be regarded as a kind of first release hole). In step S4, the first sacrificial member 201 is removed jointly through the first release hole 204, the second release hole 200a, and the gap between the edge of the first component 203 and the second component 200 (which can be regarded as a kind of first release hole). As another example, in step S1, there is a gap between the edge of the first component 203 and the second component 200 (which can be regarded as a kind of first release hole). A first release hole 204 is formed on the first component 203, and the second sacrificial member 202 is removed jointly through the first release hole 204 and the gap between the edge of the first component 203 and the second component 200. In step S3, the first component 203 is globally sealed and the gap between the edge of the first component 203 and the second component 200 (which can be regarded as a kind of first release hole) is retained. In step S4, the first sacrificial member 201 is removed only through the gap between the edge of the first component 203 and the second component 200.

[0091] In the above embodiments, since it is necessary to continue assembling other components on the first component 203 after removing the carrier substrate 300 in the subsequent step S4, the sealing film layer 302 formed in step S3 has double-sided adhesiveness. By utilizing the adhesiveness of the sealing film layer 302, other components are continued to be assembled on the sealing film layer 302 after removing the carrier substrate 300. However, in other embodiments of the present invention, when it is not necessary to continue assembling other components on the first component 203 after removing the carrier substrate 300 in the subsequent step S4, the sealing film layer 302 can be fully cured and the exposed surface has no adhesiveness.

[0092] In addition, it should be noted that in the above embodiments, it is not necessary to implement wiring on the first component 203. Therefore, only the hole-sealing film layer is fabricated on the carrier substrate 300. However, in other embodiments of the present invention, when wiring needs to be implemented on the first component 203, in step S2, before forming the hole-sealing film layer 302, the wiring required on the first component 203 can be formed on the carrier substrate 300 first, and then the wiring and the hole-sealing film layer 302 are transferred to the first component 203 together. The entire area of this wiring can be conductive, non-conductive, or a part of the wiring area can be conductive while another part of the wiring area is non-conductive. Therefore, the wiring formed on the carrier substrate 300 can include at least one of structures such as pads, connection lines between the first component and the second component, and wires for electrically leading out the first component outward. The pads include pads formed on the first component and / or pads formed on the second component.

[0093] Please refer to Figures 14 to 16 , another embodiment of the present invention provides a manufacturing method of a semiconductor device, which also includes the above steps S1 to S4. Compared with the previous embodiment, the specific processes of steps S1, S3, and S4 are basically the same. The main difference is that in step S2, after forming the temporary bonding layer 301 and before forming the hole-sealing film layer 302, wiring is formed on the temporary bonding layer 301 first.

[0094] Specifically, the specific process of this embodiment is as follows:

[0095] Please refer to Figure 15 , in step S1, according to the method of the previous embodiment, a device substrate is provided, which has a first component 203, a second component 200, a first sacrificial member 201, and a plurality of first release holes 204 penetrating through the first component 203. A partial area of the first component 203 is fixedly connected to the second component 200 through the first sacrificial member 201.

[0096] Please refer to Figure 14, in step S2, first, a temporary bonding layer 301 is formed on the provided carrier substrate 300. Then, single-layer or multi-layer wiring can be implemented on the temporary bonding layer 301, and the wiring can include at least one of structures such as pads, connection lines between the first component 203 and the second component 200, and wires for electrically leading out the first component 203 outward. The pads include pads formed on the first component 203 and / or pads formed on the second component 200. The pads or traces to be exposed in the wiring face the temporary bonding layer 301, and the part of the wiring to be used as the floating connection line 305a is directly formed on the temporary bonding layer 301. As an example, taking the formation of wiring with double-layer metal interconnects as an example, the specific process of forming wiring with multi-layer interconnects in step S2 includes:

[0097] (1), a patterned first metal layer 303 is formed on the temporary bonding layer 301 as the first layer of metal interconnects. The patterned first metal layer 303 can be a pad or a metal trace. The pads include pads formed on the first component 203 and / or pads formed on the second component 200. Among them, one method of forming the patterned first metal layer 303 is to first deposit the first metal layer 303 on the surface of the temporary bonding layer 301, and then perform photolithography and etching on the first metal layer 303 to form the patterned first metal layer 303; another method of forming the patterned first metal layer 303 is to first form a seed layer (not shown, which can be referred to Figure 17 as shown in 306 in [reference]), then form a patterned photoresist layer (not shown) on the seed layer. Next, deposit a metal material on the patterned photoresist layer and the exposed seed layer, and through a lift-off process, remove the patterned photoresist layer while removing the metal material on the photoresist layer, thereby forming the patterned first metal layer 303 in the area of the seed layer exposed by the photoresist.

[0098] (2) By means of a redistribution process or a multi-layer metal interconnection process, etc., an inter-metal dielectric layer 304, conductive plugs (not shown), and an upper-layer interconnection structure 305 are formed on the first metal layer 303 and a partial area around it. The upper-layer interconnection structure 305 may have at least one layer of metal interconnecting lines in a direction perpendicular to the surface of the carrier substrate 300. The formation process of each layer of metal interconnecting lines in the upper-layer interconnection structure 305 is specifically as follows: First, deposit the inter-metal dielectric layer 304, and etch the inter-metal dielectric layer 304 to remove the redundant inter-metal dielectric layer 304, and form a through hole (not shown) in the remaining inter-metal dielectric layer 304 to expose the surface of a partial lower-layer metal interconnecting line (for example, the first metal layer 303). Then, deposit a new metal layer and perform photolithography and etching on the new metal layer to form a new layer of patterned metal interconnecting lines. At this time, the new metal layer filled in the through hole is used as a conductive plug to realize the electrical connection between the metal interconnecting line on the upper surface of the inter-metal dielectric layer 304 and the lower-layer metal interconnecting line. In other embodiments of the present invention, when the through hole in the inter-metal dielectric layer 304 is relatively deep, a conductive plug filled in the through hole can also be formed by processes such as filling the through hole with a conductive material and planarizing, and then deposit a new metal layer on the surface of the conductive plug, the inter-metal dielectric layer 304, and the exposed area, and perform photolithography and etching on the new metal layer to form a new layer of patterned metal interconnecting lines. That is to say, in the upper-layer interconnection structure 305, the upper and lower adjacent two layers of interconnecting lines and between the upper-layer interconnection structure 305 and the first metal layer 303 are all electrically connected through corresponding conductive plugs, and the other areas between the lower adjacent two layers of interconnecting lines and between the upper-layer interconnection structure 305 and the first metal layer 303 are all insulated and isolated by corresponding inter-metal dielectric layers.

[0099] Please refer to Figure 14 , in step S2, after forming the wiring, a sealing film layer 302 can be formed on a partial area of the upper-layer interconnection structure 305 according to the method of the previous embodiment. The sealing film layer 302 exposes the part of the upper-layer interconnection structure 305 to be used as the floating connecting line 305a.

[0100] Please refer to Figure 15 , in step S3, the sealing film layer 302 can be bonded to the corresponding area of the first component 203 according to the method of the previous embodiment to seal a partial first release hole 204 of the first component 203.

[0101] Please refer to Figure 16 , in step S4, the temporary bonding layer 301 and the carrier substrate 300 are removed by a debonding method, and the first sacrificial component 201 can be further removed according to the method of the previous embodiment.

[0102] It should be noted that in this embodiment, one end of the part of the upper interconnect structure 305 in the wiring formed in step S2 that serves as the floating connection line 305a is aligned with the first component 203 and fixedly connected to the first component 203 through the corresponding sealing hole film layer 302, and the other end is aligned with the second component 200 and fixedly connected to the second component 2003 through the corresponding sealing hole film layer 302. Thus, in step S4, after removing the temporary bonding layer 301 and the carrier substrate 300, the part of the upper interconnect structure 305 that serves as the floating connection line 305a floats and is formed into the floating connection line 305a, which can realize the flexible connection between the first component 203 and the second component 200. Optionally, the floating connection line 305a is a bare wire to maximize flexibility. Further optionally, the floating connection line is a spring wire. In addition, during the above process of forming the wiring, other suitable wiring materials can be used to replace the metal to form the required wiring. Moreover, during the above wiring process, some auxiliary film layers, such as polyimide (PI), silicon oxide, silicon nitride, etc., can be applied as functional film layers such as an etching stop layer and a passivation layer. When using a thermally decomposable bonding film as the temporary bonding layer 301, all the film layers formed during the above wiring process and the related processes for treating each film layer need to be realized in a low-temperature environment within the tolerance range of the temporary bonding layer 301.

[0103] For the manufacturing method of the semiconductor device of this embodiment, on the one hand, since the wiring required on the first component is fabricated on the carrier substrate in advance, there is no need to reserve the position and area of the first release hole for the wiring on the first component. Furthermore, the first release holes can be uniformly densely arranged in a large area on the first component, reducing the release difficulty of the second sacrificial part. On the other hand, since the second sacrificial part is removed before bonding the carrier substrate and the wiring is formed on the carrier substrate, the protective film layer and its forming process implemented on the wiring surface in the prior art are cancelled, reducing the difficulty and complexity of manufacturing the semiconductor device. In addition, a floating connection line can be formed through a relatively simple process to realize the flexible connection between the second component and the first component, and avoid adding adverse rigidity to the floating connection line.

[0104] Please refer to Figures 17 to 21 , another embodiment of the present invention provides a manufacturing method of a semiconductor device, which also includes the above steps S1 to S4. Compared with the Figures 14 to 16 embodiment shown, the specific processes of steps S1 to S3 are basically the same. The main difference is that in step S4, after removing the carrier substrate 300 and the temporary bonding layer 301, at least part of the surface of the first metal layer of the wiring is exposed, and a second metal layer is electrolessly plated on the exposed surface of the first metal layer.

[0105] The specific process of the manufacturing method of the semiconductor device of this embodiment is as follows:

[0106] Please refer to Figure 19 , in step S1, according to the method of the previous embodiment, a device substrate is provided, which has a first component 203, a second component 200, a first sacrificial member 201, and a plurality of first release holes 204 penetrating through the first component 203. A partial area of the first component 203 is fixedly connected to the second component 200 through the first sacrificial member 201.

[0107] Please refer to Figure 17 and Figure 18 , in step S2, first, a temporary bonding layer 301 and a seed layer 306 are sequentially formed on the provided carrier substrate 300. The seed layer 306 may include at least one of titanium, tantalum, copper, gold, tungsten, aluminum, etc.; then, a patterned photoresist layer (not shown) is formed on the seed layer 306; then, a metal material (such as including at least one of copper, gold, tungsten, aluminum, nickel, tin, etc.) is deposited on the patterned photoresist layer and the exposed seed layer 306, and through a lift-off process, while removing the patterned photoresist layer, the metal material on the photoresist layer is removed, thereby forming a patterned first metal layer 303 on the area of the seed layer 306 exposed by the photoresist. The patterned first metal layer 303 may include pads or single-layer metal wirings. The pads include pads formed on the first component 203 and / or pads formed on the second component 200; then, using the patterned first metal layer 303 as a mask, the seed layer 306 is etched to form a patterned seed layer 306.

[0108] Please refer to Figure 18 , in step S2, after forming the patterned seed layer 306, according to the method of the previous embodiment, a hole-sealing film layer 302 may be formed on at least a partial area of the patterned first metal layer 303.

[0109] Please refer to Figure 19 , in step S3, according to the method of the previous embodiment, the hole-sealing film layer 302 may be bonded to the corresponding area of the first component 203 to seal a partial first release hole 204 of the first component 203.

[0110] Please refer to Figure 19 and Figure 20, in step S4, first, in the method of the previous embodiment, the temporary bonding layer 301 and the carrier substrate 300 can be removed by debonding to expose the seed layer 306, and the first sacrificial member 201 is further removed; then the seed layer 306 is removed by wet etching or dry etching to expose the surface of the first metal layer 303. Then, by electroless plating process, a second metal layer 303' is electrolessly plated on the exposed surface of the first metal layer 303. The material of the second metal layer 303' can be different from that of the first metal layer 303, for example, it includes nickel and / or gold. The second metal layer 303' can be a single-layer metal or a structure formed by stacking multiple layers of metals.

[0111] In this embodiment, in step S2, a patterned first metal layer is formed by a lift-off process, and the process is simple. And in step S4, after removing the carrier substrate and the temporary bonding layer, the seed layer can protect the first metal layer during the process of removing the first sacrificial member, and a second metal layer is formed on the first metal layer by electroless plating process after removing the first sacrificial member. This electroless plating process enables the second metal layer to grow only on the exposed surface of the first metal layer, avoiding affecting other parts of the device and ensuring the electrical performance of the required wiring on the first component.

[0112] Please refer to Figures 22 to 27 , another embodiment of the present invention provides a manufacturing method of a semiconductor device, which also includes the above steps S1 to S4. Compared with the Figures 14 to 16 embodiment shown, the specific processes of steps S1 and S3 are basically the same. The main difference is that in step S2, the use of the temporary bonding layer is cancelled, and before forming the hole-filling film layer, a structure formed by sequentially stacking a first etch stop layer, a patterned sacrificial layer, and a patterned second etch stop layer is formed; in step S4, after removing the carrier substrate, the first etch stop layer, at least part of the patterned sacrificial layer, and the second etch stop layer are sequentially removed.

[0113] The specific process of the manufacturing method of the semiconductor device in this embodiment is as follows:

[0114] Please refer to Figure 24 , in step S1, in the method of the previous embodiment, a device substrate is provided, which has a first component 203, a second component 200, a first sacrificial member 201, and a plurality of first release holes 204 penetrating through the first component 203. A partial area of the first component 203 is fixedly connected to the second component 200 through the first sacrificial member 201.

[0115] Please refer to Figure 22 and Figure 23, in step S2, first, a first etch stop layer 307 is sequentially formed on the provided carrier substrate 300. The first etch stop layer 307 globally covers the carrier substrate 300, and its material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Then, a patterned sacrificial layer 308 is formed on the first etch stop layer 307 through thin film deposition, photolithography, and etching. The patterned sacrificial layer 308 has openings (not shown) for defining wiring. The material of the patterned sacrificial layer 308 is different from that of the first etch stop layer 307 and the subsequent second etch stop layer to be formed, and can be any suitable material well-known to those skilled in the art, such as including at least one of amorphous carbon, polysilicon, amorphous silicon, germanium, etc. Next, a patterned second etch stop layer 309 is formed on the patterned sacrificial layer 308 through processes such as thin film deposition, photolithography, and etching. The patterned second etch stop layer 309 can be any suitable material well-known to those skilled in the art. Optionally, the material of the patterned second etch stop layer 309 is an insulating medium, and its material can be the same as or different from that of the first etch stop layer 307. In this embodiment, the pattern of the patterned second etch stop layer 309 is the same as the wiring pattern to be formed. After that, through the wiring formation method described in any of the above embodiments, single-layer wiring or multi-layer wiring is implemented on the patterned second etch stop layer 309. In this embodiment, single-layer wiring is implemented to form a patterned first metal layer 303. The patterned first metal layer 303 may include pads or single-layer metal wiring. The pads include pads formed on the first component 203 and / or pads formed on the second component 200.

[0116] Please continue to refer to Figure 23 , in step S2, after forming the patterned first metal layer 303, a hole-sealing film layer 302 can be formed on at least a part of the area of the patterned first metal layer 303 according to the method of any of the above embodiments. In this embodiment, a part of the hole-sealing film layer 302 is used for bonding with the second component 200 in the subsequent process, and a part of the hole-sealing film layer 302 is used for bonding with the first component 203 in the subsequent process, and these two parts of the hole-sealing film layer 302 are separated from each other.

[0117] Please refer to Figure 24 , in step S3, the corresponding hole-sealing film layer 302 can be bonded to the corresponding area of the first component 203 according to the method of any of the above embodiments to seal a part of the first release holes 204 of the first component 203. In this embodiment, another part of the hole-sealing film layer 302 is bonded to the second component 200. In this step, based on the precisely positioned bonding, the hole-sealing film layer 302 can be adhered to the designated area, and since the hole-sealing film layer 302 is a film structure rather than a liquid glue structure, it is not easy to penetrate into the interior of the device substrate.

[0118] Please refer to Figures 25 to 27 , in step S4, first, the carrier substrate 300 can be removed by mechanical grinding and / or back etching, such as to expose the first etch stop layer 307, as Figure 25 shown; then, the first etch stop layer 307 and the second etch stop layer 309 exposed by the patterned sacrificial layer 308 are removed by dry etching, as Figure 26 shown; then, the patterned sacrificial layer 308 is removed, as Figure 26 shown, and the first sacrificial member 201 is further removed, as Figure 27 shown.

[0119] The manufacturing method of the semiconductor device of this embodiment can also realize the sealing film layer and wiring required by the first component, and will not cause adverse effects on the device performance due to the forming process of the sealing film layer and wiring.

[0120] It should be noted that, first, in the above embodiments, the removal of the first sacrificial member is performed after the removal of the carrier substrate. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the first sacrificial member can also be removed through the second release hole on the second component and / or the first release hole exposed by the sealing film layer after bonding the sealing film layer to the first component and before removing the carrier substrate. Secondly, in the above embodiments, since the bonding surface of the sealing film layer is sticky, it can be directly bonded to the first component. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the bonding surface of the sealing film layer is not sticky, and a bonding adhesive can be further coated on the sealing film layer, and then the sealing film layer is bonded to the first component through the bonding adhesive. In this case, since the bonding adhesive is coated on the sealing film layer, the amount used is relatively small, and the sealing film layer can be accurately attached to the designated area of the first component during bonding, so the problem of the bonding adhesive entering the device substrate during bonding can also be avoided.

[0121] Please refer to Figures 8 to 29 , based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including a semiconductor device formed by the semiconductor device manufacturing method described in any of the above embodiments. The semiconductor device includes a device substrate and a sealing film layer 302. The device substrate has a first component 203, a second component 200, and a plurality of first release holes 204 penetrating through the first component 203. The sealing film layer 302 is bonded to at least the first component 203 to seal at least part of the first release holes 204. As an example, the material of the sealing film layer 302 includes dry film.

[0122] Optionally, the first component 203 is a movable component, the second component 200 is a fixed component, a gap is provided between the edge of the second component 200 and the first component 203, and the first component 203 is movable relative to the second component 200.

[0123] Optionally, the first component 203 at least partially overlaps with the second component 200, and a cavity is formed between the first component 203 and the second component 200 in the overlapping area.

[0124] Optionally, a second release hole 200a is provided on the second component 200.

[0125] Optionally, the semiconductor device further includes a wiring bonded to the first component 203, wherein the wiring may include a single-layer structure and / or an interconnect structure.

[0126] As an example, the wiring includes a suspended connection line connecting the second component 200 and the first component 203. Optionally, the second component 200 and the first component 203 are flexibly connected by the suspended connection line. As an example, the suspended connection line is a bare wire.

[0127] As another example, the wiring includes pads formed on the first component 203 and / or pads formed on the second component 200.

[0128] As yet another example, the wiring includes a first metal layer and a second metal layer formed on the surface of the first metal layer by an electroless plating process.

[0129] Optionally, the semiconductor device further includes an element 400 to be assembled mounted on the sealing hole film layer 302. As an example, the element 400 to be assembled includes an active element and / or a passive element, and the active element includes an image sensor wafer.

[0130] In addition, it should be noted that unless otherwise specified or indicated, the terms "first", "second", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between the various components, elements, steps.

[0131] It will be understood that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0132] Furthermore, it should also be understood that the present invention is not limited to the specific methods, materials, manufacturing techniques, uses and applications described herein, and they can vary. It should also be understood that the terms described herein are only used to describe specific embodiments and not to limit the scope of the present invention. It must be noted that the singular forms "a", "an", "one" and "the" used in the present application document include plural references unless the context clearly indicates the contrary. Thus, for example, a reference to "a step" means a reference to one or more steps and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of logical "or" rather than the definition of logical "exclusive or" unless the context clearly indicates the contrary. The structures described herein will be understood to also refer to functional equivalents of the structures. Language that may be interpreted as approximate should be so understood unless the context clearly indicates the contrary.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a device substrate having a first sacrificial member and a second sacrificial member, a first component, a second component, and a plurality of first release holes penetrating the first component, a partial region of the first component being fixedly connected to the second component through the first sacrificial member, and the remaining gap between the first component and the second component being filled with the second sacrificial member; Providing a carrier substrate and forming a sealing film layer on the carrier substrate; Bonding the sealing film layer to the first component to seal at least some of the first release holes; Removing the carrier substrate; The method for manufacturing the semiconductor device further includes: before bonding the sealing film layer to the first component, removing the second sacrificial member at least through the first release holes and maintaining the fixed connection between the first component and the second component by the first sacrificial member; and, before or after removing the carrier substrate after bonding the sealing film layer to the first component, removing the first sacrificial member.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The first component is a movable component, the second component is a fixed component, and the first component can be movable relative to the second component in the manufactured semiconductor device.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The device substrate further has second release holes provided on the second component. Before bonding the sealing film layer to the first component, the second sacrificial member is removed through the first release holes and the second release holes; before or after removing the carrier substrate after bonding the sealing film layer to the first component, the first sacrificial member is removed at least through the second release holes.

4. The method for manufacturing a semiconductor device according to claim 3, wherein, The sealing film layer is a patterned film layer. After bonding the sealing film layer to the first component, the sealing film layer exposes some of the first release holes; before or after removing the carrier substrate after bonding the sealing film layer to the first component, the first sacrificial member is removed through the second release holes and the first release holes exposed by the sealing film layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The sealing film layer is a patterned film layer, and a patterned sealing film layer is formed on the carrier substrate by dispensing, pattern printing, or photolithography.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming the sealing film layer on the carrier substrate, a temporary bonding layer or a first etch stop layer is first formed on the carrier substrate.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The temporary bonding layer includes a thermally decomposable bonding film, a photo-decomposable bonding film, an electro-decomposable bonding film, or a chemically decomposable bonding film.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, Before forming the sealing film layer on the carrier substrate and after forming the temporary bonding layer or the first etch stop layer on the carrier substrate, at least a wiring for connecting to the first component is formed on the carrier substrate, and the wiring includes a single-layer structure and / or a multi-layer interconnect structure.

9. The method for manufacturing a semiconductor device according to claim 8, wherein, After forming the temporary bonding layer or the first etch stop layer on the carrier substrate and before forming the wiring on the carrier substrate, a patterned sacrificial layer is first formed on the temporary bonding layer or the first etch stop layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein, Before forming the wiring on the patterned sacrificial layer, a second etch stop layer is first formed on the patterned sacrificial layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein, After removing the carrier substrate, further comprising: Remove the first etch stop layer; Remove the second etch stop layer exposed by the patterned sacrificial layer; Remove the patterned sacrificial layer.

12. The method for manufacturing a semiconductor device according to claim 8, wherein, The wiring includes a suspended connection wire connecting the second component and the first component.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The second component and the first component are flexibly connected by the suspended connection wire.

14. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The suspended connection wire is a bare wire.

15. The method for manufacturing a semiconductor device according to claim 8, wherein, The wiring includes a pad formed on the first component and / or a pad formed on the second component.

16. The method for manufacturing a semiconductor device according to claim 8, wherein, The wiring includes a first metal layer, and the semiconductor device manufacturing method further includes: after removing the carrier substrate, exposing at least a part of the surface of the first metal layer of the wiring, and electroless plating a second metal layer on the exposed surface of the first metal layer.

17. The method for manufacturing a semiconductor device according to any one of claims 1 to 16, characterized in that, Remove the carrier substrate by including at least one process of debonding, mechanical grinding, and etching.

18. The method for manufacturing a semiconductor device according to any one of claims 1 to 16, characterized in that, The material of the hole-sealing film layer includes a dry film.

19. The method for manufacturing a semiconductor device according to any one of claims 1 to 16, characterized in that, After removing the carrier substrate, at least a part of the hole-sealing film layer is also exposed, and components to be assembled are assembled on the exposed hole-sealing film layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein, The components to be assembled include active components and / or passive components.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that, The active component includes an image sensor wafer.

22. An electronic device, characterized in that, A semiconductor device formed by the semiconductor device manufacturing method according to any one of claims 1 to 21.

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